NORDMENDE SPECTRA PORTABLE 3604 (THOMSON ICC4) CHASSIS F14 (ICC4) INTERNAL VIEW.

 

The THOMSON CHASSIS ICC4 is was introducing some sophisticated features which are: Full PLL Synthesizer with Ucontroller independent from all. Matrix RGB control with Automatic Black - CutOff - Gain and White / Drive calibration circuit HA11494 (HITACHI) Analog setup value via Micro I2 Bus directly to Matrix RGB control HA11494 (HITACHI) No regulations of Deflections time base...........

The chassis ICC4 is complex and an example of how to complicate a portable TV chassis with features in circuit and technical solutions, uncommon found.

 

 (TEA2026) COLOR TV SCANNING AND POWER SUPPLY PROCESSOR TEA2026C

DEFLECTION .CERAMIC 500kHz RESONATOR F

REQUENCY REFERENCE 

.NO LINE AND FRAME OSCILLATOR ADJUSTMENT .

DUAL PLL FOR LINE DEFLECTION 

.HIGH PERFORMANCE SYNCHRONIZATION 

.SUPER SANDCASTLE OUTPUT .VIDEO IDENTIFICATION CIRCUIT 

.AUTOMATIC 50/60Hz STANDARD IDENTIFICATION 

.EXCELLENT INTERLACING CONTROL 

.SPECIAL PATENTED FRAME SYNCHRO DEVICE FOR VCR OPERATION 

.FRAME SAW-TOOTH GENERATOR 

.FRAME PHASE MODULATOR FOR THYRISTOR

 SMPS CONTROL

 .ERROR AMPLIFIER AND PHASE MODULATOR

 .SYNCHRONIZATION WITH HORIZONTAL DEFLECTION

 .SECURITY CIRCUIT AND START UP PROCESSOR 

 
GENERAL DESCRIPTION
INTRODUCTION
This integrated circuit uses l2L bipolar technology and combines analog signal processing with digital processing. Timing signals are obtained from a voltage-control- ied oscillator (VCO) operating at 500 kHz by means of a cheap ceramic resonator. This avoids the frequency adjustment normally required with line and frame oscillators. A chain of dividers and appropriate logic circuitry produce very accurately defined sampling pulses and the necessary timing signals. The principal functions implemented are :
■ Horizontal scanning processor.
■ Frame scanning processor: Two applications
are possible :
. D Class Power stage using an external thyristor.
. B Class Power stage using an external power
amplifier with fly-back generator such as the
TDA2172.
■ Line and frame synchronization separation.
■ Dual phase-locked loop horizontal scanning.
■ High performance frame and line synchronization with interlacing control.
■ Video identification circuit.
■ Super sandcastle.
■ Automatic 50-60 Hz standard identification.
■ VCR input for PLL time constant and frame
synchro switching.
■ AGC key pulse output.
■ Frame saw-tooth generator and phase modulator.
■ Switching mode regulated power supply comprising error amplifier and phase modulator.
■ Security circuit and start-up processor.
■ 500 KHz VCO
The circuit is supplied in a 28 pin DIP case.
V cc= 12 V.

SYNCHRONIZATION SEPARATOR
Line synchronization separator is clamped to black level of input video signal with synchronization pulse bottom level measurement. The synchronization pulses are divided centrally be­ tween the black level and the synchronization pulse bottom level, to improve performance on video signals in noise conditions.

FRAME SYNCHRONIZATION
Frame synchronization is fully integrated (no external capacitor required).
The frame timing identification logic permits automatic adaptation to 50 - 60 Hz standards or non-interlaced video.

An automatic synchronization window width system
provides :
■ fast frame capture (6.7 ms wide window),
■ good noise immunity (0.4 ms narrow window).
The internal generator starts the discharge of the saw-tooth generator so that it is not disturbed by line fly-back effects. Thanks to the logic control, the beginning of the charge phase does not depend on any disturbing effect of the line fly-back. A 32 ps timing is automatically applied on standardized transmissions, for perfect interlacing. In VCR mode, the discharge time is controlled by an internal monostable independent of the line frequency and gives a direct frame synchronization.

HORIZONTAL SCANNING
The horizontal scanning frequency is obtained from the 500 KHz VCO. The circuit uses two phase-locked loops (PLL) : the first one controls the frequency, the second one controls the relative phase of the synchronization and line fly-back signals.

The frequency PLL has two switched time constants
to provide :
■ capture with a short time constant,
■ good noise immunity after capture with a long time constant.
The output pulse has a constant duration of 26 ps, independent of Vcc and any delay in switching off the scanning transistor.

VIDEO IDENTIFICATION
The horizontal synchronization signal is sampled by a 2 ps pulse within the synchronization pulse. The signal is integrated by an external capacitor. The identification function provides three different levels :
■ 0 V : no video identification
• 6 V : 60 Hz video identification
■ 12 V : 50 Hz video identification

This information may be used for timing research in the case of frequency or voltage synthesizer type receivers, and for audio muting. SUPER SANDCASTLE with 3 levels : burst, line fly back, frame blanking. In the event of vertical scanning failure, the frame blanking level goes high to protect the tube.

VCR INPUT
This provides for continuous use of the short time constant of the first phase-locked loop (frequency). In VCR mode, the frame synchronization window widens out to a search window and there is no delay of frame fly-back (direct synchronization).

FRAME SCANNING
Frame saw-tooth generator: The current to charge the capacitor is automatically switched to 60 Hz operation to maintain constant amplitude. Frame phase modulator (with two differential inputs) : The output signal is a pulse at the line frequency, pulse width modulated by the voltage at the differential pre - amplifier input. This signal is used to control a thyristor which provides the scanning current to the yoke. The sawtooth output is a low impedance and can therefore be used in class B operation with a power amplifier circuit.

SWITCH MODE POWER SUPPLY (SMPS) SECONDARY REGULATION
This power supply uses a differential error amplifier with an internal reference voltage of 1.26 V and a phase modulator operating at the line frequency. The power transistor is turned off by the line fly-back. The "soft start" device imposes a very small conduc­tion angle on starting up, this angle progressively in­ creases to its nominal regulation value. The maximum conduction angle may be monitored by forcing a voltage on pin 15. This pin may also be used for current limitation.

SECURITY CIRCUIT AND START UP PROCESSOR
When the security input (pin 28) is at a voltage exceeding 1.26 V the three outputs are simultaneously cut off until this voltage drops below the 1.26 V threshold again. In this case the switch mode power supply is restarted by the "soft start" system. If this cycle is repeated three times, the three outputs are cut off definitively. To reset the safety logic circuits Vcc must be lower than 3.5 V. This circuit eliminates the risk to switch off the TV receiver in the event of a flash affecting the tube. On starting up, the horizontal and vertical scanning functions come into operation at Vcc = 6 V. The power supply then comes into operation progressively, only when c p 2 is normally locked. On shutting down, (with Vcc < 5.25 V) the three functions are inhibited simultaneously after the first line fly-back.

 APPLICATION INFORMATION ON FRAME SCANNING IN SWITCHED MODE: Fundamentals (see Figure 80) The secondary winding of EHT transformer provides the energy required by frame yoke. The frame current modulation is achieved by modulating the horizontal saw-tooth current and subsequent integration by a ”L.C” network to reject the horizontal frequency component. General Description The basic circuit is the phase comparator ”C1” which compares the horizontal saw-tooth and the output voltage of Error Amplifier ”A”. The comparator output will go ”high” when the horizontal saw-tooth voltage is higher than the ”A” output voltage. Thus, the Pin 4 output signal is switched in synchronization with the horizontal frequency and the duty cycle is modulated at frame frequency. A driver stage delivers the current required by the external power switch. The external thyristor provides for energy transfer between transformer and frame yoke. The thyristor will conduct during the last portion of horizontal trace phase and for half of the horizontal retrace. The inverse parallel-connected diode ”D” conducts during the second portion of horizontal retrace and at the beginning of horizontal trace phase. Main advantages of this system are : - Power thyristor soft ”turn-on” Once the thyristor has been triggered, the current gradually rises from 0 to IP, where IP will reach the maximumvalue at the end of horizontal trace. The slope current is determined by, the current available through the secondary winding, the yoke impedance and the ”L.C.” filter characteristics. - Power thyristor soft ”turn-off” The secondary output current begins decreasing and falls to 0 at the middle of retrace. The thyristor is thus automatically ”turned-off”. - Excellent efficiency of power stage dueto very low ”turn-on” and ”turn-off” switching losses. Frame Flyback During flyback, due to the loop time constant, the frame yoke current cannot be locked onto the reference saw-tooth. Thus the output of amplifier ”A” will remain high and the thyristor is blocked. The scanning current will begin flowing through diode ”D”. As a consequence, the capacitor ”C” starts charging upto the flyback voltage.The thyristor is triggeredas soon as the yoke current reaches the maximum positive value. - Full line synchronized derived supplyies. High engineered PCB Circuit (see) Teletext add on capability. 

 This chassis is implementing a Frame deflection technology with SSVD (Switched Synchronous Vertikal Deflection) tech, using thyristor Line deflection flyback energy switching; You can see HERE the origin of this Deflection technology were exactly was born and used.

  Switching regulator power supply device combined with the horizontal deflection circuit of a television receiver which it supplies: Step-up switching regulator power supply device comprising, connected between the poles of a rectifier circuit supplied by an isolating voltage step-down transformer and loaded by a first filter capacitor, and inductance and the collector-emitter path of a first switching transistor of NPN type, a first diode whose anode is connected to the junction of the inductance and to the collector of said transistor and whose cathode is connected to a second filter and storage capacitor supplying a voltage at its output which supplies a horizontal deflection circuit of a television receiver.

This horizontal deflection circuit which comprises in cascade a horizontal oscillator, a driver stage and an output stage, forms an integral part of the circuit controlling said first transistor and determines the repetition period of the switching, because it is started under an initial voltage slightly less than the unregulated input voltage of the device.

The switching transistor is being turned off in synchronism with the turning off of the trace switch transistor by using flyback pulses of negative polarity to bias the base thereof.

1. A power supply device with switching regulation and boosting of its DC output voltage, combined with a horizontal deflection circuit of a television receiver, supplied thereby and which comprises in cascade a horizontal oscillator, a driver stage and an output stage including a trace switch transistor and a line transformer, this device comprising an inductance and the collector-emitter path of a switching transistor connected in series between the poles of a DC input voltage source, a rectifying diode connected by its anode to the junction between the inductance and the collector of said switching transistor and by its cathode to one of the terminals of a filtering and storage capacitor whose other terminal is connected to the emitter of said transistor, so as to apply across its terminals an initial DC voltage slightly lower than said input voltage, when said switching transistor is turned off, and a regulated DC output voltage with a level higher than said input voltage, when said transistor is recurrently, alternately turned on and off, the level of said output voltage depending on the duty cycle of said switching transistor states, and a control circuit feeding the base of said switching transistor and including a regulator stage comparing an adjustable fraction of said output voltage to a fixed reference voltage and supplying a regulating current or voltage proportional to the difference between said compared voltages, a pulse-width modulator triggered by means of a recurrent signal and supplying a rectangular signal whose duty cycle varies as a function of said regulating current or voltage, another driver stage receiving the rectangular signal and controlling said switching transistor, the regulation and boosting of said output voltage being controlled by the initially independent starting up of the entire horizontal deflection circuit when supplied by said initial voltage from said power supply device as soon as a DC input voltage is applied thereto and which then delivers recurrent trigger pulses to said pulse-width modulator, one of the supply inputs of said other driver stage receiving directly a first voltage waveform whose positive alternations comprise constant-voltage plateau and whose negative alternations comprise negative-going horizontal flyback pulses provided by a first secondary winding of said line transformer, so as to control the turning off of said switching transistor substantially simultaneously with that of the trace switch transistor. 2. A power supply device as claimed in claim 1, wherein said other driver circuit comprises a third transistor whose emitter is connected to the base of said switching transistor and which is of the same type as the latter, whose collector is connected, through said supply input, to said first secondary winding of said line transformer to receive therefrom said first waveform and whose base is coupled to the output of said pulse-width modulator. 3. A power supply device as claimed in claim 2, wherein the collector of said third transistor is connected, through a resistor to the supply input and its emitter is connected, furthermore, to that of the switching transistor through another resistor so that the negative-going flyback pulses, applied to the collector of said third transistor, control the symmetric (reverse) saturation thereof so as to reversely bias the base-emitter junction of said switching transistor. 4. A power supply device as claimed in claim 2, wherein the collector of said third transistor is connected to said power supply input through a fourth diode conducting in the normal direction of its collector-emitter path, and wherein its emitter is further connected, on the one hand, through a resistor, to the emitter of the switching transistor and, on the other hand, through another resistor and a fifth diode conducting in the reverse direction to that of the base-emitter junction of the switching transistor, so as to transmit to the base thereof negative-going flyback pulses through a voltage divider formed by said two resistors in series. 5. A power supply device as claimed in claim 1, wherein said other driver circuit comprises a third transistor whose emitter is connected to the base of said switching transistor, whose collector is connected to that of this latter so as to form a so-called Darlington circuit and whose base coupled, moreover, to said pulse-width modulator is further connected, through a resistor and a diode in series, to said first secondary winding of said line transformer so as to control the simultaneous turn off of both transistors of said Darlington circuit by simultaneously reversely biasing their respective base-emitter junctions, connected in series, by means of negative-going flyback pulses. 6. A power supply device as claimed in any one of the preceding claims, wherein said pulse-width modulator, supplied at its input with a voltage waveform whose positive alternations comprise positive-going flyback pulses and whose negative alternations comprise constant negative-voltage plateaux, comprises a passive circuit which forms a simple integrator during positive alternations because one of its resistors is shunted by a diode and which is a cascaded double integrator during negative alternations of this waveform so as to deliver during the trace periods of the scan a linearly decreasing negative current which, added to the positive regulating current, supplies the base of a fourth comparator transistor, so that the turning off of this latter through equality of the negative and positive currents supplied to this base controls the beginnings of the saturation of said switching transistor in such a manner that the duration of this saturation varies inversely with variation of said output voltage. 7. A power supply device as claimed in claim 6, wherein said comparator transistor is biased, furthermore, at its base by means of a resistor which connects it to the positive pole of said input voltage source, so that it remains saturated in the absence of flyback pulses supplied by said horizontal deflection circuit so as to maintain the switching transistor in a cut off state. 8. A power supply device as claimed in any one of the preceding claims, wherein said control circuit, except for the regulator stage which is supplied by said output voltage, is supplied by said input voltage. 9. A power supply device as claimed in any one of the preceding claims 1 to 6, wherein said DC supply voltage of said control circuit, with the exception of one of the inputs of said regulator stage receiving said output voltage, is supplied by a secondary winding of said line transformer, through a rectifier circuit including a diode and a filtering capacitor.

Description:

BACKGROUND OF THE INVENTION

The present invention relates to a switching voltage regulator power supply device combined with the horizontal deflection circuit of a television receiver which it supplies with DC voltage. It relates, more particularly, to DC voltage supply devices of the type which boost or increase the voltage supplied at the output of the device in relation to the level of a DC voltage applied to its input and which regulate this level by recurrent switching of this input voltage, this switching being synchronous with the (horizontal) line frequency of the television receiver supplied by this device.

Switched step-up or boost voltage regulator devices of this type are known, particularly from the publications U.S. Pat. Nos. 3,571,697 (or 3,736,496) and they are related to switched mode power supply devices or DC-DC converters of the so-called unisolated flyback type, in which the collector-emitter path of a bipolar switching transistor is connected in series with a commutating inductance between the terminals of a DC source supplying an input voltage and a rectifying diode is connected between the junction of the inductance with the transistor and one of the plates of a filtering or storage capacitor (in parallel with the load), so that the current stored in the inductance during the conducting period of the transistor is used for charging the capacitor (and supplying the load) through the diode during its consecutive cut-off period. The use of a switched-mode power supply device of this type in television receivers for supplying, particularly, the horizontal deflection circuit thereof has been described, for example, in two articles by VAN SCHAIK entitled respectively "AN INTRODUCTION TO SWITCHED-MODE POWER SUPPLIES IN TV RECEIVERS" and "CONTROL CIRCUITS FOR SMPS IN TV RECEIVERS," appearing respectively on pages 93 to 108 of No. 3, Vol. 34, of September 1976 and on pages 162 to 180 of No. 4 of this same volume, of December 1976, in the English language Dutch review "ELECTRONIC APPLICATIONS BULLETIN" of PHILIPS', or on pages 181 to 195 of No. 135 of July 1977 and on pages 210 to 226 of No. 136 of October 1977 of the British review "MULLARD TECHNICAL COMMUNICATIONS." Since none of the switched-mode power supply devices described in these articles, isolated or not from the mains, whether they use a forward or a flyback converter, supplies at its output a DC voltage for supplying the horizontal deflection circuit before the switching transistor has been turned on (saturated or conducting) one or more times, the control circuit of this transistor must comprise an independent relaxation oscillator and must be supplied by the same DC input voltage (rectified and smoothed voltage of the AC mains) as the switching circuit comprising the inductance and the transistor in series. Synchronization of the switching with the horizontal deflection can only occur subsequently, when the horizontal oscillator and/or the horizontal deflection circuit as a whole have begun to operate, as soon as the supply voltage supplied thereto by the device which operates independently on starting up, has become sufficient. This synchronization of the switching with the horizontal deflection, advantageous for reducing or eliminating the interferences visible on the screen which are caused by high-frequency energy radiation due to abrupt transitions of power switching, particularly when the switching transistor is being cutt off, is generally carried out by means of a signal comprising flyback or retrace pulses, taken at the terminals of an auxiliary secondary winding of the line tranformer whose primary winding is generally connected between the output of the switched-mode power supply device and one of the terminals of the trace switch which is provided in the output stage. It is also possible to use for this purpose the signal provided by the horizontal oscillator (see, for example, the publication FR-A-2 040 217).

In a switched-mode supply for a television receiver described in the publication FR-A-2 261 670, the circuit for controlling the switching transistor of a forward-type converter, supplied with the rectified and smoothed voltage of the mains, comprises a bistable trigger circuit of flip-flop one of whose outputs is coupled back to one of its trigger inputs through a regulating circuit comprising a sawtooth voltage generator and a voltage comparator providing transitions which control the setting of the flip-flop, when the sawtooth voltage reaches the level of a voltage proportional to the amplitude of the flyback pulse. The other one of the two complementary outputs of this flip-flop is coupled back to its other trigger input through a so-called starting loop comprising an ascending voltage wave-form which approaches asymptotically a predetermined voltage level smaller than a predetermined fraction of the nominal level which the amplitude of the flyback pulse must reach in normal operation, and a voltage comparator providing transitions which control the recurrent resetting of the flip-flop to its initial state until the flyback pulse has reached or exceeded a threshold amplitude slightly below its nominal amplitude. When this threshold amplitude has been exceeded, resetting of the flip-flop is controlled by the flyback pulses themselves, negative-going in the present case, which supplant the starting pulses. Such an arrangement is equivalent to an astable multivibrator during the starting period, which later becomes a monostable one and triggered by the flyback pulses and whose quasi-stable state has a variable duration, depending on the amplitude of these pulses so as to obtain regulation thereof by the duty cycle. The pulse which controls the closing of the switch (saturation of the switching transistor) begins here with the leading edge of the flyback pulse and its duration or length is modulated as a function of the current drawn by the load and of the variation of the rectified and smoothed voltage, so that its end controlling the opening of the supply switch (cutting off the transistor) occurs during the trace portion of the horizontal deflection. Thus it can be seen that this switched-mode supply, like most of the known ones, effects regulation of its output voltage by varying the duty cycle as a reverse function of the level thereof.

Since the high-frequency radiation is precisely at its most intense during abrupt transitions of current in the switching inductance and of the voltage accross its terminals, the appearance of one or more vertical lines (light or dark according to the sense of the modulation of the carrier wave by the video signal) may be observed, contrasting with the normal contents of the picture, whose location on the screen depends on the duration of the pulse controlling the switching transistor. The effect of this radiation becomes particularly troublesome when the input signal of the radio-frequency stages or tuner is small, particularly when the selected channel is situated in the lower part of the VHF band, for the automatic gain-control device of the receiver acts on the gain of the high-frequency and/or intermediate-frequency input stages, so that the sensitivity (amplification) of the receiver is then maximum and this also as concerns the spurious radiated signals.

SUMMARY OF THE INVENTION

The present invention, on the one hand, avoids or at least appreciably reduces the interferences visible on the screen by controlling the cutting off of the switching transistor in synchronism with the leading edge or the flyback pulse and, on the other hand, the starting of the horizontal deflection circuit by means of a simple circuit without any special oscillator, and provides efficient protection of the switching transistor which remains cut off when the horizontal deflection circuit is not operating. This is made possible by using a step-up switching regulator supply device of the type described in the publication U.S. Pat. No. 3,571,697 and whose control circuit includes, in accordance with the invention, the horizontal deflection circuit, which it supplies.

The object of the present invention is a power supply device with boosting and regulation of its output voltage by switching, combined with a horizontal sweep circuit of a television receiver, which it supplies and which comprises a horizontal oscillator, a driver stage and an output stage including a line transformer, this device comprising an inductance and the collector-emitter path of a switching transistor connected in series between the poles of a DC input voltage source, a rectifiying diode connected by its anode to the junction between the inductance and the collector of the transistor and by its cathode to one of the terminals of a filtering capacitor whose other terminal is connected to the emitter of the transistor so as to supply between its terminals an initial output voltage, slightly lower than the input voltage, when the transistor is cut off permanently, and a regulated DC output voltage with a level higher than the input voltage, when the transistor is recurrently alternately turned on and off, the level of this output voltage depending on the duty cycle of the respective states of this transistor, and a control circuit for driving the base of the transistor and including a regulator stage comparing an adjustable fraction of the output voltage to a fixed reference voltage and supplying a regulating current or voltage proportional to the difference between these compared voltages, to a pulse-width modulator triggered by means a recurrent signal and supplying a rectangular signal whose duty cycle varies as a function of this regulating current or voltage, and another driver stage receiving the rectangular signal and controlling the switching transistor.

In accordance with the invention, the horizontal deflection forming an integral part of the circuit controlling the switching transistor, determines therefor, from the start, the repetition period of the rectangular signal controlling it, and one of the supply inputs of the other driver stage receives directly a first voltage waveform whose positive alternations, comprise DC voltage plateaux and whose negative alternations comprise negative-going flyback pulses supplied by a first secondary winding of the line transformer, so as to control the cut-off the switching transistor substantially simultaneously with that of the trace switch transistor.

DESCRIPTION OF THE DRAWINGS

The invention will be better understood and other of its objects, characteristics, features and advantages will become clear from the following description and the accompanying drawings which refer thereto, given solely by way of example, in which:

FIG. 1 is partly a block diagram and partly a schematic diagram of a power supply device combined with the horizontal deflection circuit in accordance with the invention;

FIG. 2 shows waveforms of two voltages and of a current at different points of the circuit of FIG. 1;

FIG. 3 is a block diagram of the circuit for controlling the switching transistor;

FIGS. 4 and 5 are schematic diagrams of two different embodiments of the driver circuit 20 forming the output stage of the control circuit of FIG. 3;

FIG. 6 is the block diagram of one embodiment of the pulse-width modulator 10 of the circuit of FIG. 3;

FIG. 7 shows three voltage waveforms at different points of the circuit of FIG. 6;

FIG. 8 is a schematic diagram of one embodiment of the pulse-width modulator 10 of the circuit of FIG. 3, using discrete components;

FIG. 9 shows a current waveform and two voltage waveforms at different points of the circuit of FIG. 8;

FIG. 10 is a schematic diagram of a conventional embodiment of a regulator stage 30 adapted to supply the modulation input of the modulator of FIG. 8; and

FIGS. 11 and 12 are partial respective schematic diagrams of two embodiments of a power supply device in accordance with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the schematic diagram of the power stages of the power supply device and of the horizontal deflection circuit of the television receiver, which it supplies and in block diagram form the respective circuits which control them.

The DC input voltage VE which is not regulated is supplied by a rectifier bridge R with four diodes, supplied at its input by the secondary winding of an insulating step-down transformer TS, whose primary winding is supplied by the AC mains. The output terminals of rectifier bridge R are connected respectively to the terminals of a first filtering capacitor C1 across which this input voltage VE is taken.

The positive pole P of this source of the input voltage VE is connected to one of the terminals of an energy-storage inductance L, whereas its negative pole N is connected to ground G of the receiver, which is isolated from the mains. The other terminal of inductance L is connected, on the one hand, to the collector of a first NPN bipolar switching transistor T1, whose emitter is connected to ground G and, on the other hand, to the anode of a first diode D1 whose cathode is connected to the positive terminal of a second filtering and storage capacitor C2. With the negative terminal of this second capacitor C2 connected to ground G, the output voltage VS which supplies the load is taken between its terminals.

Such a supply device BS provides both step-up or boost and regulation of its output voltage level, because the first switching transistor T1 and the first diode D1 thereof are connected so as to conduct respectively currents flowing through inductance L in the same direction, it supplies at its output formed by the terminals of the second capacitor C2, an initial DC voltage VSI as soon as the primary winding of the insulating transformer TS is connected to the mains. This initial voltage VSI which is equal to the input voltage VE less the forward voltage drop VD1 across the first diode D1, is then supplied to the load until the control circuit SC is started up, whose output 6 is connected to the base of the first transistor T1 so as to cause it to be alternately turned on and off.

When the first transistor T1 is turned on by positively biasing its base-emitter junction, its collector-emitter path connects the junction of the inductance L with the anode of the first diode D1 to ground G. Diode D1 being then reversely biased, it ceases to conduct and the inductance L connected by the first transistor T1 between the positive P and negative N poles of the source supplying the unregulated DC input voltage VE, then conducts a linearly increasing current IL so as to store the energy which increases with the square of the conduction duration of the first transistor T1, until this latter is cut off. At the instant when the first transistor T1 is cut off after the control circuit SC has brought its base-emitter voltage to zero or below, the voltage at the terminals of inductance L is reversed so that, at its junction with the collector of transistor T1 and the anode of diode D1, there appears a voltage VM greater than the input voltage VE, which results in the forward biasing of diode D1. Consequently, from the instant when transistor T1 is cut off, diode D1 conducts a linearly decreasing current until the energy stored in the form of a current IL in the inductance L, which charges the second capacitor C2 to an output voltage VS greater than the input voltage VE, disappears. The regulation of the level of the output voltage VS is here effected in a conventional way, by varying the duty cycle, i.e. the radio (quotient) between the duration of the conducting period of transistor T1 and the sum of the respective durations of two of its successive conducting and cut off periods, as a function of the desired output voltage VS (determined by comparison to a stable reference voltage).

According to the invention, a supply device BS of the above-described type is combined with the horizontal deflection circuit SH of a television receiver, which it supplies, so that this latter forms an integral part of its control circuit SC and for determining the repetition period of its operation and so that the above-mentioned regulation by varying the duty cycle maintains a stable peak-to-peak amplitude of the sawtooth scanning current and/or the very high voltage for biasing the electrodes (anode, focusing electrode and accelerating grid) of the cathode-ray tube, which are obtained by rectifying the horizontal flyback pulses supplied by a step-up secondary winding (not shown) of the line transformer TL.

The horizontal deflection circuit SH which comprises in cascade the horizontal oscillator OH whose known phase control circuit with respect to the horizontal sync signal separated from the composite video signal has not been shown here, the driver stage HD controlled by the horizontal oscillator OH and controlling the output stage OS of the horizontal deflection, is as a whole supplied by the above-described regulated power supply device BS. In fact, the positive supply input AL of the horizontal deflection circuit SH is connected by means of a fuse FS to the junction of the cathode of the first diode D1 with the positive terminal of the second capacitor C2, which forms the positive output terminal SP of the regulated power supply device BS. This supply input AL is connected directly to that of the driver circuit HD and, preferably, through a conventional Zener diode or series ballast transistor voltage regulator VR, to that of the horizontal oscillator OH, which are moreover connected to the isolated ground G.

The supply input AL of the horizontal deflection circuit SH is furthermore connected to one of the primary winding terminals B1 of the line transformer TL, whose other terminal AB is connected in parallel to the collector of another switching transistor TH, of NPN type, called trace switch transistor, to the cathode of a second so-called shunt recovery diode DR, to one of the terminals of another capacitor CR, called line-retrace capacitor, and to one of the plates of an additional capacitor CS, called trace capacitor, which supplies the horizontal deflection coils LH one terminal of which is connected to its other terminal during the trace periods of the scanning. The emitter of the scanning transistor TH, the anode of the "shunt" recovery diode DR, the other terminal of the retrace capacitor CR and the other terminal of the horizontal deflection coils LH are all connected to ground G. This assembly of components thus connected forms the output stage OS whose operation is well-known and does not form part of the invention.

As was mentioned above, as soon as the primary winding of the step-down isolating transformer TS is connected to the mains, rectifier R supplies the first filtering capacitor C1 so as to provide between its terminals P and N a unregulated low DC voltage VE. With the first transistor T1 then turned off, this input voltage is applied through the inductance L and the first diode D1 to the second capacitor C2 so as to obtain between the terminal SP and ground G an initial output voltage VSI substantially equal to VE-VD1, which is approximately equal to 60 percent of the regulated output voltage VS. This initial output voltage VSI (equal to about 0.6 VS) is sufficient to cause the generation of autonomous oscillations by the horizontal oscillator OH. This latter supplies at its output, connected to the input of driver circuit HD, pulses at an independent frequency close to the line frequency. In response to these pulses, driver circuit HD, also supplied by device BS, provides at the base of the trace switch transistor TH pulses controlling its periodical cut off at this independent frequency and its consecutive turning on after a period greater than the duration of the flyback period, so that the recovery diode DR may take the current from the deflector LH during substantially the first half of the trace portion of the scan. During flyback or retrace, with both transistor TH and diode DR cut off, the energy stored in the form of currents respectively in the inductances of deflector LH and of the primary winding B1 of the line transformer TL which are then, from the AC current point of view, connected in parallel, flow in an oscillating manner through the retrace capacitor CR which forms therewith a parallel resonant circuit whose resonance period determines the duration of the flyback period.

There then appears periodically between point AB and ground G a voltage pulse VTH having substantially a sinusoidal half-wave form, which is shown in Diagram A of FIG. 2. The average value of this voltage VTH being then equal to VSI, at start-up, and to VS, during established operation. The line transformer TL comprises, in addition to a very-high-voltage winding and other windings for supplying rectifying circuits, not shown, two secondary windings B2, B3 respectively supplying across their terminals, voltage waveforms comprising flyback pulses with zero average values and with respectively negative and positive polarities.

This means that the first secondary winding B2 supplies a voltage waveform -VTL which, between two successive flyback pulses, comprises a positive plateau whose level is equal to the average value of these pulses and which is used, in accordance with the invention, to control the turn off of the first transistor T1 so that the interferences which would otherwise be visible only occur during the line-blanking periods comprising the line-retrace periods. The second secondary winding B3 then supplies a voltage waveform +VTL which is the reverse of or complementary to the preceding one -VTL.

One of the terminals of each of these secondary windings B2, B3 is connected to ground G, whereas their other terminals are respectively connected to two inputs 2 and 1 of the control circuit SC. A third input 3 of this latter is connected to the SP output of the supply device BS and a fourth input 4 is connected to the positive pole P of the input voltage source VE. A fifth terminal 5 of the control circuit SC is connected to ground G (or negative pole N) and its output 6 is connected to the base of the first transistor T1. This control circuit SC causes, following the start up of the horizontal deflection circuit SH, a first saturation of the first transistor T1 at a time determined by a pulse-width modulator operating by conventional comparison of a sawtooth voltage waveform the elaboration of which is controlled by a first flyback pulse, with a regulating voltage, depending on the output voltage VS. During this saturation period of transistor T1 which extends as far as the leading edge of the next flyback pulse, energy is stored in inductance L.

From the instant when transistor T1 is turned off, diode D1 transfers this stored energy to the second capacitor C2, at the terminals of which it causes an increase of the voltage VS with respect to its initial value VSI, until the current in diode D1 is canceled out, when it becomes reverse biased.

The collector-emitter voltage waveforms VTH of the trace switch transistor TH and VCE of the switching transistor T1 in established operation have been shown respectively by the diagrams A and B of FIG. 2. Diagram C of FIG. 2 shows the corresponding waveform of the current IL flowing through the inductance L.

When the base of the first transistor T1 receives from the output 6 of the control circuit SC a rectangular signal which turns it on at time instant t1, its collector-emitter voltage VCE (Diagram B) becomes close to zero (V _CEsat ) and a linearly increasing current IL (Diagram C) flows through inductance L from time t1 until time t2 when transistor T1 is again turned off, which is controlled by the leading edge of the flyback pulse VTH (Diagram A). With the collector current of transistor T1 canceled at the end of the storage time of the excess minority carriers in the base, the voltage across the terminals of the inductance L inverses its polarity so as to be added to the input voltage VE, so that the collector-emitter voltage VCE (Diagram B) then reaches a level VM greater than VS (as well as VE), so as to apply forward bias to the first diode D1, which then conducts the current IL through the inductance L. This current IL, from time instant t2 when it reaches its maximum value IM, becomes linearly decreasing and it flows through the first diode D1 in the passing direction in order to recharge the second capacitor C2 and supply, in particular, the horizontal deflection circuit SH.

When the current IL passing through the first diode D1 is canceled out at time t3, the collector-emitter voltage VCE of the first transistor T1 becomes equal to the unregulated input voltage VE until the next turn on of the transistor T1, and the first diode D1 remains reversely biased until the time when this latter is cut off again.

From the above it can be easily seen that the principal advantage of this combined device resides in the fact that a single oscillator OH belonging to the horizontal deflection circuit SH is sufficient for controlling the two power switching transistors TH and T1.

Furthermore, a possible overload in the circuitry of the television receiver, such for example as a short-circuit of the trace switch transistor TH, results in overloading the diode D and the inductance L. The first transistor T1 which is consequently cut off is not subjected to this overload and is therefore protected. In order to protect the rest of the television receiver as well as inductance L and the first diode D1, a fuse FS may be connected in series in the supply line from the second capacitor C2. This fuse FS may also be inserted between pole P and inductance L.

It is moreover known that it is difficult to construct switched supplies for obtaining correct operation when it is not fully charged (for supplying, for example, a ready-state remote-control receiver). In the present case, the problem does not come up since, when the supply is in operation, there is always a minimum load formed by the horizontal deflection circuit. When this circuit is not operating, the supply circuit BS does not operate either, but it supplies an output voltage VSI of a value less than the nominal voltage VS which cannot cause damage and which may, for example, supply a ready-state receiver for television receivers having a remote control.

Finally, the control circuit SC allows transistor T1 to be cut off at the beginning of each flyback period, when the blanking circuit has extinguished the spot (s) on the cathode-ray tube. Thus, the spurious signals radiated into the receiver input circuits will cause no visible effect on the screen of the cathode-ray tube.

FIG. 3 shows in block diagram form the control circuit SC of FIG. 1.

This control circuit SC comprises a pulse-width modulator stage 10 a first input 11 of which, connected to input 1, receives flyback pulses of positive polarity +VTL from the second secondary winding B3 of the line transformer TL (see FIG. 1 and a second input 12 of which receives a so-called regulating voltage or current whose level is proportional to the difference between the actual output voltage VS and a constant reference value, delivered by the output 32 of a regulating circuit or stage 30 whose input 31 is connected through input 3 to the positive output pole SP of the supply device BS supplying the regulated voltage VS. The variation of the regulating current or voltage causes the variation of the time instant when the instantaneous amplitude of a sawtooth voltage waveform, either with substantially constant slope and amplitude, reaches the level of this regulating voltage, or with a slope variable depending of the regulating current (which is added to the current for linearly charging a capacitor), reaches the predetermined level of a fixed reference (threshold) voltage, with respect to the beginning or the end of the sawtooth waveform. Thus a two-level rectangular signal with constant periodicity is generated, whose duty cycle varies as a function of the regulating current or voltage. If it is arranged, which is possible, for a reduction of the output voltage VS with respect to its nominal value defined by the reference voltage, to cause an increase in the duty cycle and for an increase in VS to have the opposite effect, regulation of this output voltage VS is provided, which tends to be stabilized to this nominal value.

The output 14 of modulator 10 supplies a first input 21 of the driver stage 20 of the first switching transistor T1, a second input 22 of which receives the flyback pulses of negative polarity -VTL, coming from the first secondary winding B2 of the line transformer TL.

FIGS. 4 and 5 illustrate two different embodiments of the driver stage 20 of FIG. 3, providing efficient turn off of the first transistor T1.

In FIG. 4, the driver stage 20A comprises a third supply input 23 which connected to the positive pole (P) of the source of the (unregulated) input voltage VE and to one of the terminals of a first resistor R1 (1.8 kiloohms) whose other terminal is connected in parallel to the anodes of two diodes D2 and D3 (of type 1N4148). The second of these diodes D3 has its cathode connected to the base of a third NPN transistor T2 and to one of the terminals of a second resistor R2 (220 ohms). The emitter of the third transistor T2 is connected to the other terminal of the second resistor R2 and to the output 24 of stage 20A, which is connected through the output 6 of the control circuit SC to the base of the first transistor T1. The collector of the second transistor T2 is connected through a third resistor R3 (10 ohms) to the second input 22 of stage 20A receiving the signal -VTL which comprises the negative-going flyback pulses and, between them, plateaux of a constant positive level (zero average value). The base of the first transistor T1 is coupled to its emitter and to ground G, through a fourth resistor R4 (100 ohms). The third transistor T2 is thus mounted as a common collector (emitter-follower) stage.

When the output 14 of modulator 10 (FIG. 3) which is connected to the input 21 of stage 20A supplies a low state (level), i.e. a voltage close to zero, the thus positively biased diode D2 becomes conducting so that its anode will be at a voltage of a few tenths of a volt (0.7+V _CEsat ) which is less than the voltage required for making the three series PN junctions orientated in the same direction conductive, the first of which is formed by the third diode D3, the second is the base-emitter junction of a third transistor T2 and the third that of the first transistor T1, which will thus remain turned off. When, on the other hand, output 14 supplies a high state or forms an open circuit (the output stage of modulator 10 being formed by an open-collector transistor), diode D2 is cut off by its reverse bias and the voltage VE applied to the input 23 causes a current to flow through the first resistor R1, the diode D3 and the respective base-emitter junctions of transistors T2 and T1 connected in series. Under these circumstances and if, at the same time, the voltage waveform -VTL applied to the collector of transistor T3 presents its constant positive level portion, coinciding with the trace periods of the horizontal scan, transistors T2 and T1 become simultaneously saturated with the effect previously described insofar as the supply device BS of FIG. 1 is concerned. On the other hand, when the voltage waveform -VTL applied to the collector of the third transistor T2 becomes negative, during flyback periods, the current then flows between terminals 23 and 22 of driver stage 20 A, through resistor R1, diode D3, the base-collector junction of the third transistor T2 and resistor R3. The third transistor T2 then operates along its symmetrical saturation characteristics, i.e. it is inverted so that its collector becomes emitter and vice versa. It then conducts a current in the reverse direction between ground and the input 22 (negative) through the resistor R4 across the terminals of which it causes, after removal of the excess minority carriers from the base of the first transistor T1 through the third transistor T2, a voltage drop biasing said base negatively with respect to the emitter. This negative voltage applied to the base of reversely saturated transistor T3 allows a considerable reduction in the storage time and a rapid turnoff of the first transistor T1. Since the sawtooth generator of the pulse-width modulator 10 described above is controlled by positive-going flyback pulses, the rectangular signal applied by its output 14 (FIG. 14) to input 21 of stage 20A undergoes, during the flyback period following the turn off of the first transistor T1, a transition from its high state to its low state which causes diode D2 to conduct and, consequently, the third transistor T2 (reversed) to be cut off before the waveform -VTL becomes positive again and rebiases this transistor T2 the right way round.

FIG. 5 shows the schematic diagram of another embodiment of the driver circuit 20 of FIG. 3, designated by 20B, which has only been modified with respect to circuit 20A of FIG. 4 insofar as the collector circuit of the third transistor T2 and the base circuit of the first transistor T1 are concerned.

This modification is more particularly intented for the case where the negative peak amplitude of the voltage waveform -VTL applied to the base of the first transistor T1 through resistor R3 and the emitter-collector path of the reversely saturated third transistor T2, exceeds the reverse (Zener) avalanche-effect breakdown voltage of one of the base-emitter or base-collector junctions of the first transistor T1. This may occur when the first secondary winding B2 of the line transformer TL is also used for other functions in the television receiver.

To prevent the third transistor T2 from being reversely saturated (symmetrically), the circuit 20B comprises a fourth diode D4 inserted between the input 22 receiving the voltage waveform -VTL and the collector thereof, in series with the resistor R3 and connected to conduct in the same direction as its collector-emitter path. The input 22 is more over connected to the cathode of a fifth diode D5 (1N4148) whose anode is connected through a circuit formed by a fifth resistor R5 (330 ohms) and a third capacitor C3 (1nF) connected in parallel, to the base of the first transistor T1.

Diode D5 isolates the base of transistor T1 from the input 22, when the waveform -VTL is positive, and connects them together through a resistive voltage divider formed by resistors R5 and R4 in series, when it becomes negative. Capacitor C3 accelerates the turn-off by favoring the transmission to the base of T1 of abrupt transitions of the negative flybacd pulses.

FIG. 6 is a diagram, partly in block form, of a possible embodiment of the pulse-width modulator 10 of the control circuit SC of FIG. 3. Diagrams D, E and F of FIG. 7 show the voltage waveforms applied respectively to the input 11 (+VTL) and supplied by the output SI (VI) of the sawtooth generator GD and by the output 14 (VP) of circuit 10A.

Modulator 10A of FIG. 5 comprises a sawtooth generator GD formed by a conventional integrator circuit comprising a first amplifier A1 (integrated operational amplifier, for example), an integrating resistor R1 inserted in series between the input 11 receiving the voltage waveform +VTL illustrated by Diagram D of FIG. 7 and supplied by the second secondary winding B3 of the line transformer TL, and the input (inverting) of amplifier A1, as well as an interating capacitor CI connected between this input and the output SI of amplifier A1 (capacitive feedback). In response to this waveform +VTL, the output of amplifier A1 forming the output SI of sawtooth generator GD, supplies a voltage waveform VI illustrated by the diagram E of FIG. 7 which comprises, during the period between time instants t0 and t2 corresponding to the trace period TA of the scan, a voltage decreasing linearly between a maximum value (positive) and a minimum value (negative), and during the flyback intervals preceding time instant t0 and succeding to time instant t2, an increasing voltage of substantially semi-cosinusoidal shape.

Voltage VI is applied to one of the inputs (-) of an analog voltage comparator which may be formed by means of a second differential-type amplifier A2 (integrated operational amplifier), whose other input (+) connected to the input 12 of modulator 10A, receives the regulating voltage VR supplied by the regulator stage (30 of FIG. 3). This regulating voltage VR, which is obtained by comparing the output voltage VS of the supply device BS of the circuit of FIG. 1 with a reference voltage (VZ supplied by a Zener diode, for example), is a DC voltage undergoing slow variations, shown in Diagram E of FIG. 7 by a dash-dot line.

When the waveform VI applied to the inverting input (-) of comparator A2 is greater than the regulating voltage VR, which is the case during the period between time instants t0 and t1, its output connected to the output 14 of modulator 10A provides a low state. When, on the other hand, it (VI) reaches or becomes less than VR, which occurs from the time instant t1, the output 14 of modulator 10A provides a high state (which causes saturation of the first transistor T1). This high state continues until time instant t4 subsequent to the time instant t2 of the beginning of the following flyback pulse whose leading edge controls the turn-off of the first transistor T1, when the waveform VI becomes greater than the regulating voltage VR. Thus there is obtained at the output 14 of modulator 10A a rectangular signal VP shown in Diagram F of FIG. 7, formed successively of a low-level (zero or negative) beginning during the first half of the flyback period TR and ending at time instant t1, and a high level going from time instant t1 to time instant t4. Time instant t1 of the positive transition of signal VP, which determines the beginning of conduction of the first transistor T1 is then situated during the trace period of the scan TA and its position with respect to the beginning t0 or to the end t2 thereof varies as a function of the regulating voltage VR. When the regulating voltage VR is negative (as on the Diagram E of FIG. 7), a predetermined fraction of the output voltage VS is greater than the reference voltage, the duration of the high level state (t2-t1) is less than half of the trace period of the scan T1. In the opposite case, this duration (t2-t1) is greater than TA/2. The modification of this duration (t2-t1) and thus of the duty cycle is carried out in the reverse direction of the variation of the output voltage VS so as to stabilize it at a previously adjusted level, with respect to this reference voltage. The waveform -VTL may also be applied to the input 11 of modulator 10A. In this case, the input of comparator A2 must also be inverted.

To obtain suitable operating limits, while taking into consideration particularly the value of inductance L, the duty cycle or the durations (t2-t1) must vary between 0, the case where the input voltage VE is equal to the nominal output voltage VS, and about two-thirds, the case where the maximum power is supplied for a minimum voltage at the input.

The ratio between the residual alternating voltage (hum) at the output and the alternating voltage at the input must also allow an image to be obtained which is not perturbed for the eye. A value less than or equal to a hundredth for this ratio gives satisfactory results.

FIG. 8 shows the simplified diagram of a practical embodiment (by means of discrete components) of the pulse-width modulator 10 of FIG. 3. Different waveforms of a current I1 and input +VTL and output VP voltages are respectively illustrated by the Diagrams H, J and K of FIG. 9.

The input 11 of modulator 10B of FIG. 3 receives the voltage waveform +VTL which may be suppled either directly by the second secondary winding B3 of line transformer TL, or through a coupling capacitor whose one terminal is connected to the collector of the trace switch transistor TH (see FIG. 1). This input 11 supplies a passive shaping circuit, supplying negative-going (decreasing) sawtooth waveforms during the trace periods of scan T1. This passive circuit comprises a fourth coupling capacitor C4 (0.1μ) one terminal of which is connected to the input 11 and the other of which is connected to one of the terminals of a sixth resistor R6 (10 Kohms). The other terminal of this resistor R6 is connected to one of the terminals of a seventh resistor R7 (5.6 Kohms), to one of the terminals of a fifth capacitor C5 (5.6 nF) and to the anode of a sixth diode D6. The other terminal of capacitor C5 is connected to ground G. The cathode of the sixth diode D6 and the other terminal of resistor R7 are both connected to one of the terminals of an eighth resistor R8 (33 kohms), to that of a ninth resistor R9 (470 ohms), to that of a sixth capacitor C6 (4.7 nF) and to the regulation input 12 of modulator 10B, which is connected to the output 32 of the regulator stage 30 (see FIG. 3). The other terminal of capacitor C6 is connected to ground. The other terminal of resistor R8 is connected to the supply input 13 of modulator 10B receiving the input voltage VE. The other terminal of the ninth resistor R9 is connected to the base of a fourth NPN transistor T3, which forms the voltage comparator stage, whose emitter is connected to ground and whose collector (open), which forms the output 14 of modulator 10 B, is connected to the input 21 of the driver stage 20A (of FIG. 4) or 20B (of FIG. 5), formed by the cathode of the second diode D2. The value of capacitor C6 has been chosen so as to limit the maximum negative voltage applied to the base-emitter junction of transistor T3 to a value less than its reverse avalanche breakdown voltage. When the input voltage waveform +VTL is positive, as during the major portion of the flyback periods TR, diode D6 short-circuits resistor R7 and we have then a simple passive RC integrator formed by resistor R6 in series and two capacitors C5 and C6 in parallel, whose output is connected to the base of transistor T3 through resistor R9. Transistor T3 becomes conducting when its base current IB formed by the sum of currents I1 and I2 becomes positive. The current I1 shown by an arrow in FIG. 8 and on the Diagram H of FIG. 9, results from the application of the +VTL waveform of Diagram J to the above-mentionned simple integrator, during its positive alternation, and to the cascaded double integrator R6, C5, R7, C6 during its negative plateau going from t0 to t2. During this negative voltage plateau of the +VTL signal, the current I1 becomes negative and linearly decreasing. When the instantaneous negative amplitude of current I1 becomes equal to the positive current I2 shown by another arrow in FIG. 8 and by means of a reversed constant level (-I2) shown by a broken line in diagram H of FIG. 7, which occurs at time t1, the base current of transistor T3 is cancelled out and this latter is cut off. Since the current I2 is due for a large part to the regulating current IR supplied by the output of the regulator stage (30 in FIG. 3) and proportional to the error voltage, the duration of the cut-off state (t4-t1) of transistor T3 and, consequently, that (t2-t1) of the saturated state of the first transistor T1 (as well as the duty cycle) will vary reversely to the variation of this current IR. The current IE shown by an arrow in FIG. 8, which flows through the high-value resistor R8 from the input voltage source VE and which is one of the components with IR of current I2, forms a small current for maintaining transistor T3 saturated in the absence of flyback pulses and thus of horizontal deflection. The fact that resistor R8 is supplied by the unregulated input voltage VE allows another parameter to be added for acting on the duty cycle of transistor T3 as a function thereof. Diagram K of FIG. 9 illustrates the rectangular signal VP obtained at the output 14 of the modulator 10B of FIG. 8.

FIG. 10 is a schematic diagram of a conventional regulator stage 30 of the control circuit of FIG. 3. It is formed essentially by a well-known circuit called differential amplifier having two inputs, the first of which receives an adjustable fraction of the voltage to be stabilized, formed, in the present case, by the output voltage VS of the power supply device (BS, FIG. 1) and the second input of which receives a stable reference voltage which is generally generated within this stage (as in most known ballast or switched-mode voltage regulator).

The reference voltage VZ is here produced by means of a Zener diode D7 (of the BZX83C type having a stabilized Zener voltage of 7.5 V) whose cathode is connected to the input 31 receiving the output voltage VS of the device BS (FIG. 1) and whose anode is connected through an eleventh resistor R11 (10 Kohms) to ground G. The second input of the differential amplifier used here is formed by the emitter of a fifth PNP transistor T4 which is connected to the anode of the Zener diode D7. The voltage (VS-VZ) biasing this emitter is then fixed with respect to the output voltage VS. The first input of the differential amplifier is here formed by the base of transistor T4 which is biased by a voltage-divider circuit, formed from a fifteenth resistor R15 (4.7 Kohms), a potentiometer R16 (5 Kohms) and a fourteenth resistor R14 (22 Kohms) connected in series between the input terminal 31 and ground G. The base of transistor T4, connected to the slider of potentiometer R16 receives then a previously adjusted fraction of the output voltage VS supplying the horizontal deflection circuit (SH), so that it forms a constant current generator supplying a current proportional to its emitter-base voltage which is equal to the difference (error voltage) between the reference voltage VZ and the selected fraction of the output voltage VS supplied by potentiometer R16. The collector of the fourth transistor T4, connected by a tenth resistor R10 (2.2 Kohms) to the output 32, supplies then the regulating current IR to the regulating input (12, FIGS. 3 and 8) of the pulse-width modulator (10 or 10B, FIGS. 3 and 8).

It will be noted here that a feedback circuit comprising a twelfth resistor R12 (5.6 Kohms) and a seventh capacitor C7 (4.7 nF) in series connects the collector of transistor 14 to its base.

The difference between the voltage respectively provided by the potentiometer R16 and the Zener diode D7 causes more or less heavy conduction of transistor T4 which delivers the current IR.

In short, when the output voltage VS increases, the voltage (VS-VZ) at the emitter of transistor T4 increases more than that applied to its base and current IR increases. The value of I1 at which transistor T3 is cut off increases then in absolute value and this transistor T3 is turned off later, which reduces the conducting period of transistor T1. The peak current in inductance L then diminishes, which causes a reduction of the output voltage VS which comes back to its nominal value, taking into account the residual error required for controlled operation.

FIG. 11 shows the complete simplified diagram of a power supply device BS of FIG. 1 whose control circuit SCA is respectively formed by the driver circuit 20A of FIG. 4, by the modulator 10B of FIG. 8 and the regulator stage 30 of FIG. 10, except for a few variations.

The variations concern a damping resistor R17 of 1 kiloohm shunting the inductance L, resistor R8 and resistor R10 which are both connected directly to the base of transistor T3 instead of being connected to the cathode of diode D6, resistor R11 which has been omitted and a resistor R13 which shunts the slider of potentiometer R16 to ground. These details of construction have no influence at all on the operation of the circuit such as it has been described above, but simply allow easier adjustment.

Another embodiment is shown in FIG. 12. It allows more especially a television set to be supplied with power in which the horizontal deflection circuit operates from a higher DC voltage VS, of about 100 volts for example, itself obtained from an initial output voltage VSI of about 60 volts. The operation of the circuit is fundamentally the same as that of FIG. 11 and only the differences will be described below. The components playing the same role in both diagrams bear the same references. The values may however be different but their dimensioning is within the scope of a man skilled in the art. The voltage VS delivered by the power supply is used principally in the horizontal deflection circuit which is the component consuming most power in the television set. The power supply circuit components receiving permanently a voltage when the horizontal deflection circuit is not operating, but when the mains is connected, are solely those indispensable for activating the power supply, i.e. the first switching transistor T1 and the circuit for measuring the output voltage in the regulator stage 300.

To simplify the driver stage 100, instead of the single switching transistor T1, an integrated Darlington circuit T10 is used of the BU 807 type, for example. Therefore, the gain is sufficient to omit a discrete driver transistor T2 and to connect the cathode of diode D3 directly to the base input of T10. The negative -VTH pulses, coming from an intermediate tapping on coil B2 of the line output transformer, are applied directly to the base of T10 through resistor R3 which is connected in series with a diode D9 whose cathode is connected to this intermediate tapping.

Instead of the input voltage VE, the power supply input 4 of the control circuit SCB is fed by a voltage obtained by rectifying the positive half-waves (plateaux) of the -VTL voltage supplied by the first secondary winding B2, by means of a diode D8 and a capacitor C8. Thus considerably lower voltage may be obtained than that supplying the horizontal deflection circuit, of the order of 13 volts, for example. A voltage of this value allows video amplification circuits as well as other circuits of the television set to be supplied while providing for these latter a very great reliability. This voltage is applied through resistor R1 to the anodes of diodes D2 and D3 and through resistor R8 to the base of the transistor T3 of modulator 10B.

The regulator stage 300 here comprises two PNP transistors T4 and T5 connected differentially. For that, their emitters receive the voltage rectified by D8 through a resistor R18 of 1.5 kiloohms. The collector of transistor T5 is connected to ground through a resistor R20 of 3.9 kiloohms and the collector of transistor T4, which supplies the regulating current IR, is connected to the cathode of diode D6 through a resistor R10 of 4.7 kiloohms.

The reference voltage (6.2 volts) is supplied by a Zener diode D7 whose anode is connected to ground, and cathode to a resistor R19 (6.8 kiloohms) which receives the voltage rectified by D8. This reference voltage is applied to the base of transistor 14. A capacitor C9 (49 microfarads) shunts diode D7 so as to cause the reference voltage to rise gradually when the apparatus is switched on, which allows a gradual rise of the output voltage VS to be obtained.

A potentiometer R16 of 10 kiloohms connected between two stopper resistors R15 (68 kiloohms) and R14 (5.6 kiloohms) receives the voltage VS through the resistor R15 and is connected to ground through resistor R14. The sliding contact of potentiometer R16 allows a fraction of the voltage VS to be applied to the base T5. A resistor R13 (47 kiloohms) also connects this base to the common point between R15 and R16.

An anti-oscillation capacitor C10 (15 nanofarads) connects the base of the collector of transistor T5.

Thus the regulating current IR supplied by resistor R10 is directly dependent on the difference between the output voltage VS, applied to the horizontal deflection circuit, and the reference voltage determined by the Zener diode D7. The power supply BS thus stabilizes this voltage VS and at the same time the rectified voltage supplied by diode D8.

To stop this power supply, as well as that of FIG. 11 moreover, it is sufficient to stop by means of a remote control receiver, for example, the operation of the horizontal oscillator.

In this case, the input voltage VE is still present, but is considerably smaller than voltage VS. For the power supply of FIG. 12, this reduced voltage is only applied to the Darlington transistor T10 and a fraction thereof to the base of transistor T5 of the regulator stage 300. Thus the life expectation of the other components of the device BS is increased. Since the voltage supplied by diode D8 is itself regulated, it may be used for supplying a major portion of the television set, except for the horizontal deflection circuit supplied by voltage VS and the remote control receiver which must be capable of operating permanently (also in the ready state) so as to detect the turn-on control signal. The protection which was mentioned earlier on is then extended to the greatest part of the components of the television set.

It will be noted here that the three stages 10, 20 and 30 of control circuit SC (see FIGS. 1 and 3) may be formed by means of circuits different from those described and shown and which are known per se, and that it is sufficient to have a secondary winding B2 (in addition to the very-high-voltage winding) of the line transformer TL, supplying negative line-flyback pulses which may be used for generating a decreasing or increasing sawtooth voltage waveform as well as for controlling the cutting off of the first switching transistor T1.

 ICC4-TEA2026 Scanning control circuit for a television receiver, with gradual startup

This invention concerns television scanning circuits.

It involves a scanning startup circuit comprising a capacitor, and means of gradual charging or discharging, to produce a priority voltage transmitted at startup to replace a control voltage, regulating a chopped power supply circuit which is to be started up progressively. At the end of a certain period of time, the regulation control voltage takes over from the original voltage which, at startup, is at a level such that it prevents over-consumption of current in power components. The circuit is also protected against voltage surges, being halted and restarted automatically and gradually in the event of such a surge.

1. In a television receiver comprising a switched mode power supply and a scanning control circuit, said power supply circuit comprising a power switching element (T2) and a pulse-width modulator (24, 26) having an input for receiving a modulating voltage and an output for providing pulses of modulated width, wherein said scanning control circuit comprises, in view of ensuring gradual start-up of scanning:

supply terminals for receiving a low voltage supply (Vcc),

a capacitor (C3) having a first plate and a second plate which are connected to said supply terminals in such a way that upon starting up of the receiver, said first plate will follow the rising potential of one supply terminal,

a voltage limiter (38) to limit the voltage on said capacitor first plate to a predetermined value Vz,

an analogic voltage transmission device (32) having a first input connected to said capacitor first plate, a second input for receiving a control voltage which may vary between predetermined limits, and an output which is connected to the input of said pulse width modulator, said voltage transmission device being designed so that its output will transmit either the voltage on its first input or the voltage on its second input, depending on the relative magnitude of these voltages, the transmitted voltage being the one which corresponds to the narrower pulse width at the output of the pulse width modulator,

the value of Vz being such that it corresponds to a pulse width narrower than the minimum pulse width that may be produced by the modulator when said modulator receives the said control voltage from the transmission device,

means (34) for progressively altering the electrical charge of said capacitor so as to vary the potential of its first plate in a sense corresponding to an increase of the pulse width defined by this voltage.

2. A circuit as claimed in claim 1 wherein said second plate of the capacitor is directly connected to said one supply terminal. 3. A circuit as claimed in claim 1, wherein said means for progressively altering the charge of said capacitor comprises a current source controlled so as to supply current to the capacitor only when receiving fly-back pulses indicating that horizontal scanning is operating. 4. A circuit as claimed in claim 1 further comprising a threshold comparator (62) having one input receiving said low voltage supply and another input connected to a voltage reference, and an output for supplying to the pulse width modulator a disabling signal whenever said low voltage supply falls below a predetermined value (VS2). 5. A circuit as claimed in claim 3, wherein a second means for gradually altering the electrical charge of said capacitor is provided, said second means comprising a current source connected to the capacitor in such a way that it will change the voltage on the first plate in a sense corresponding to a decrease of the pulse width defined by this voltage.

Description:

This invention concerns television receivers, and more specifically circuits to control the sweep of the light spot produced on the television screen. In particular, it relates to the way in which such circuits start up when the receiver is switched on.

A television receiver usually contains a horizontal scan transformer, surrounded by several closely interconnected circuits:

stabilized supply circuit, providing a regulated DC voltage of about 100 volts, to supply the transformer;

horizontal scan control circuit supplying periodical signals to the base of a transistor mounted in series with the primary transformer winding, with a horizontal deflection coil connected to this transistor;

vertical deflection control circuit using a secondary winding of the horizontal scan transformer as source of supply, to produce a periodical voltage gradient for vertical scanning;

very high voltage circuit using a secondary winding of the transformer to create a high potential in the cathode-ray tube, for the purpose of producing and accelerating the electron beam.

In one embodiment, described in French patent application No. 81 08 337 of Apr. 27, 1981 on the present applicant's behalf, these different circuits are closely interconnected and precise provision has to be made for their startup and stoppage, taking account of their reciprocal interactions.

FIG. 1 shows the general layout of the horizontal and vertical scanning circuit, with a regulated chopped power supply circuit. This invention applies specifically to such a circuit. Further details are to be found in the aforementioned patent application, but the general structure will be described here, in order to define the purposes of this invention.

The horizontal scan transformer TL is provided with a primary winding EP, connected on one side to the collector of a transistor T1, the emitter of which is earthed, and on the other side to the output of a stabilized chopped power supply circuit, which is itself powered by the AC mains current.

A horizontal scanning control circuit 10 supplies the base of transistor T1 with periodical signals, synchronized with a synchronization signal SL, extracted by a synchronization extractor (not shown here) from the video signal reaching the receiver.

The transistor collector T1 is connected to a horizontal deflection coil 12, which produces a periodical deflection of the electronic beam of the tube at every changeover of transistor T1.

Transformer TL contains one or more secondary windings, e.g. one winding to produce a very high voltage THT, and another to activate a vertical deflection circuit. A line return signal RL, a negative pulse produced whenever the beam returns as a result of sudden blocking of transistor T1, is taken from one of these windings. This negative pulse RL is used for the horizontal scanning circuit 10, since scanning is synchronized with the syncronization signal SL by shifting the transistor T1 control signals until SL and RL are synchronized. The same pulse RL is also used to operate the chopped power supply circuit.

The vertical deflection circuit 14 is connected to a vertical deflection coil 16, and to a secondary winding of the transformer TL, and is also connected to the horizontal scanning control circuit, to ensure the necessary correspondence between line scanning and frame scanning.

The chopped power supply ciruit, comprises, following a transformer 18 powered by the mains, a rectifier bridge 20 followed by a filter capacitor C1 and inductance L1, mounted in series with the collector of a transistor T2, the emitter of which is connected to earth.

The collector of this transistor T2 is connected to the anode of a diode 22, the cathode of which is connected to a capacitor C2. The supply circuit output voltage reaches the terminals of this capacitor C2. The supply circuit functions by means of high-frequency switching (at the horizontal scan frequency) of transistor T2, by means of periodical signals (line scanning period 64 microseconds).

Capacitor C2 forms an energy accumulator, which discharges into the utilization circuit while transistor T2 is conducting, and which recharges through inductance L1 when transistor T2 is blocked; the width of the signals is automatically regulated, so that the charge lost every time transistor T2 becomes conducting is exactly counterbalanced by the charge regained during each blocking.

Regulation is obtained by taking a regulation control voltage at the supply circuit output, and comparing it with a stabilized reference voltage, the difference between them being amplified in a differential amplifier 30, and compared in a comparator 24 with a periodical sweep voltage, DSC, supplied at the line scan frequency by a generator 26, which to this effect receives signals at this frequency from the horizontal scanning circuit 10.

The comparator thereby supplies variable-width signals at this frequency, and these are amplified in an amplifier 28, and delivered to the base of transistor T2.

Finally, since transistor T2 has to block a high current every period, the strongly negative line return pulse RL from the secondary winding of transformer TL is delivered to its base. As already stated, RL is synchronized with the horizontal scanning signals from circuit 10, and therefore with returns of the sweep voltage DSC, so that a negative pulse encouraging blocking of transistor T2 appears immediately after delivery of a blocking signal from comparator 24.

The electronic control circuits are supplied with low-voltage DC current Vcc, obtainable either by rectifying a fraction of the mains AC current, or by taking a fraction of the DC voltage from the stabilized chopped power supply circuit, or even by a combination of both methods.

In conclusion, close interconnections exist among the chopped power supply circuit (operating at the horizontal scanning frequency), horizontal scanning circuit, vertical scanning circuit, and even very-high-voltage circuits. This invention is intended to perform the following functions relevant to this situation.

First, it is preferable for vertical scanning to function whenever horizontal scanning is in operation (something that involves the appearance of a very high voltage); otherwise, a motionless bright horizontal line is created on the screen, and this will ultimately burn out the photosensitive layer of the television tube.

Second, on startup of the chopped power supply circuit, when the receiver is first switched on, the regulation system will tend to make the comparator 24 generate signals of maximum length, until the supply circuit has reached its nominal output voltage. Current in transistor T2 increases in a linear way (because of inductance L1) during the period of the signal, resulting in far too high a consumption of current in the transistor during supply circuit startup, and serious overheating of the transistor, which has to cut out this high current (several amps) at high voltage (several hundred volts). In any case, the duration of these signals needs to be limited, for normal functioning of the supply circuit (e.g. by ensuring that the regulation control voltage cannot fall below a certain threshold). However, such limitation, although adequate during normal operation, does not eliminate the risk of destruction of transistor T2 during startup.

Apart from this startup problem, there is also the matter of stoppage of scanning circuits. The stabilized power supply circuit has to be switched off before horizontal scanning stops, since absence of scanning results in abnormal functioning of the power supply (removal of the sweep voltage and of the line return signal allowing transistor T2 to be properly blocked). When the supply circuit is off, scanning can be stopped, but horizontal and vertical scans have to be switched off simultaneously, and this should in fact not be done too quickly after the removal of power, since a very high voltage remains for some time, producing an electron beam which has to sweep the whole screen, so as not to risk burning a central point on it.

Finally, in exceptional cases, such as occurrence of overvoltage at a critical point, emergency switchoff of the supply circuit and scanning circuits must be possible, with automatic restarting, unless such voltage surges recur too quickly.

This invention aims to overcome such difficulties by means of a scan control circuit with a chopped power supply circuit, comprising a controlled switch (transistor T2) and a comparator or phase modulator 24, to produce control siqnals for this switch, the comparator being capable of receiving a variable regulation control voltage at one input and a sweep voltage at a second input, to produce signals of variable width, a startup circuit comprising a capacitor, means of having the potential of a first plate of the capacitor follow quickly the potential of a low voltage source Vcc, whenever this low voltage rises above zero to a value Vz, a priority transmission device, one input of which is connected to the first capacitor plate, while another input receives the regulation control voltage, and an output connected to the first comparator input, in order to ensure priority of delivery to this comparator input of whichever of the two voltages will produce narrower signals to cause the controlled switch to conduct, the value of Vz being such that when it is reached and the chopped power supply circuit is functioning, it is given priority for delivery to the comparator, to generate signals much shorter than the maximum possible length, and means of loading or unloading the capacitor gradually, in such a way that the potential of the first plate is gradually altered until it no longer has priority.

On startup, regardless of the regulation control voltage, signals making transistor T2 conduct are very short, since they widen as the capacitor discharges, until the supply circuit regulation control voltage takes over and issues signals, in accordance with normal functioning of the chopped power supply circuit.

Furthermore, control of horizontal and vertical scanning is inhibited if the low voltage is below a threshold VS1, and control of the chopped power supply circuit is inhibited until the lower voltage reaches a threshold VS2, above VS1.

The priority transmission device may, for example, comprise a pair of diodes or transistors.

Other features and benefits of the invention will emerge from the following detailed description, with reference to the accompanying figures:

FIG. 1, already described, showing the general layout of a television receiver scanning circuit, particularly suitable for use with this invention;

FIG. 2, showing the startup circuit for the invention;

FIG. 3, showing a chart of voltages during receiver startup and stoppage;

FIG. 4, showing a chart of voltages in the event of voltage surges;

FIG. 5, showing a detail of the circuit.

FIG. 2 shows a capacitor C3, the first plate of which is connected to a terminal of a circuit 31, which is itself connected to an input E1 of a priority transmission device 32, possessing another input E2, which receives a control voltage to regulate the chopped power supply circuit in FIG. 1 (voltage taken from the divider bridge at the supply circuit output and amplified by amplifier 30). The priority transmission device output S is connected to the first input of comparator 24, the other input of which receives the sweep voltage DSC.

The priority transmission device 32 delivers the higher of the two voltages entering inputs E1 and E2 at its output S. To this effect, the device may, for example, comprise two transistors T3 and T4, mounted as follower emitters. Both emitters are connected to the output S, while the base of T3 is connected to input E1 and the base of T4 to input E2.

Transistor T4 can also in fact form part of the output stage of amplifier 30. The device may also comprise two diodes, instead of the base/emitter connections.

The second plate of capacitor C3 is connected to a low-voltage source, preferably the voltage Vcc used to supply all scan control circuits in the receiver, and which may be 12 volts, for example.

This voltage Vcc is obtained by rectifying a low-voltage AC current, which may be taken from the transformer 18 in FIG. 1. In one recommended embodiment (not shown here), arrangements may be made so that, when the scanning circuit has been started up, a rectified, filtered voltage, from the line transformer, takes over from the rectified filtered voltage from transformer 18, to provide the voltage Vcc.

The first plate of capacitor C3 is also connected to a charging device (current source 34) and discharging device (current source 36), to charge and discharge the capacitor fairly slowly (a few tens or even hundreds of milliseconds). The plate is also connected to a voltage limiter (Zener diode 38 and possibly additional diodes, to adjust the limiter output voltage to 6 or 7 volts). Current source 34 functions only in the presence of the line return signal RL.

Finally, the first plate of capacitor C3 is connected to the input of a threshold comparator 40, which delivers a positive logic signal when the voltage at the plate exceeds a threshold VS4 of about 6 volts.

The comparator output is connected to one input of an AND gate 42, another input of which receives the output signal from a decoder 44 at the output from a counter 46, in such a way that the AND gate theoretically opens when threshold VS4 is exceeded, except when a predetermined content of counter 46 is reached.

The output from the AND gate 42 is connected to one input of an OR gate 48, the other input of which receives a resetting signal RAZ, for resetting input R of a bistable flipflop 50, the output of which controls incrementation of a counter 46. This counter can also be cleared by the RAZ signal from a logic circuit (not shown here), producing a logic level resetting the flipflop and counter to 0, either when Vcc falls below a low threshold VS5, of about 4 volts (i.e. when the receiver is switched on again after complete stoppage); or at the end of a given period of time.

The flipflop 50 receives a switching control signal from an AND gate 52, one input of which receives the line return signal RL from the horizontal scanning circuit, while another input receives the output signal from a threshold comparator 54, which delivers a high logic level whenever any voltage surge appears at a safety terminal 55 connected to a critical point in the receiver.

One input terminal of comparator 54 accordingly receives the voltage from this critical point, while the other input is raised to a reference potential VS3.

When this threshold VS3 is exceeded, flipflop 50 is switched over at the next line return signal RL (and therefore on condition that horizontal scanning is taking place). This switchover increments the counter and stops the horizontal and vertical scanning circuits. Here, the output of flipflop 50 is connected through an OR gate 56 to the horizontal scanning control circuit 10 and vertical scanning control circuit 14, in order to inhibit functioning of these two circuits. OR gate 56 also receives a logic signal from a threshold comparator 60, which also delivers a scanning control circuit inhibiting signal whenever supply voltage Vcc falls below a threshold VS1 of about 6 volts, significantly higher than the threshold VS5 below which the clearing signal RAZ is issued.

Finally, a last threshold comparator 62 compares Vcc with a threshold VS2 of about 9 volts, higher than VS1, and transmits, through an AND gate 64 receiving the line return signal RL and an OR gate 66, a chopped power supply circuit inhibiting signal, for example a signal inhibiting comparator 24 which establishes signals of variable width, at the first line return after voltage Vcc has fallen below threshold VS2.

Another input of OR gate 66 is connected to the output from OR gate 56.

All threshold comparators comparing Vcc with a threshold have been shown with one input at Vcc and the other at the required threshold. In practice, it is preferable to compare a voltage KVcc with a single threshold voltage common to all comparators, the coefficient K varying from one comparator to another, controled by divider bridges. The common threshold voltage may be a reference voltage of 1.26 volts, a band-gap reference that is easily generated, and which offers very good temperature stability.

The description below covers functioning of the various parts of the circuit when the receiver is switched on, switched off, and also when repeated voltage surges occur at a critical point in the receiver.

FIG. 3 shows a time chart of voltages when the receiver is switched on and switched off.

When it is switched on (at time 0), voltage Vcc quickly reaches its nominal value of 12 volts (upper graph in FIG. 3).

The capacitor C3 is initially discharged, and its first plate (connected to E1) is at a potential Ve which initially follows the potential of the other plate, i.e. Vcc, up to a value Vz of about 7 volts, depending on the Zener diode limiter 38.

Before reaching Vz, voltage Vcc passes through a phase during which it is below a threshold VS5 of about 4 volts, causing resetting to 0 of flipflop 50 and counter 46. Vcc then passes through threshold VS1 of about 6 volts, causing, by means of comparator 60, simultaneous startup of horizontal and vertical scanning (which can function with a voltage Vcc of about 6 volts).

The appearance of horizontal scanning generates a periodical signal RL at the level of the horizontal scan transformer, thereby enabling the current source 34 (the average amplitude of which is greater than that of current source 36) to function, so that capacitor C3 begins to charge, reducing potential Ve, with a time constant of a few tens of milliseconds. The decrease in Ve is approximately linear overall, but in reality it takes place in a stepped fashion, each line return signal RL causing a small drop in the capacitor load. Meanwhile, almost as soon as scanning starts, voltage Vcc has passed through threshold VS2 of about 9 volts, enabling the chopped power supply circuit to function.

Ve is therefore initially about 7 volts, i.e. much higher than the regulation control voltage delivered to the chopped power supply circuit. This control voltage tends to be at its minimum level, to produce, by comparison with the sweep voltage DSC, very wide signals. In fact, voltage Ve is transmitted with priority through transistor T3, so that narrow signals are produced. The width of the signals increases as Ve falls; the chopped power supply circuit gradually reaches normal operating conditions, and the regulation control voltage rises. The system is thus in a phase of gradual startup of the power supply circuit.

After a certain period, voltage Ve has dropped to a level below the regulation control voltage, which has risen with the supply circuit output voltage. The regulation control voltage thereupon takes over from voltage Ve in the priority transmission device 32, initiating a phase of normal regulation of the power supply circuit.

Because the chopped power supply circuit cannot begin to function until Vcc is above VS2 (9 V), whereas scanning is already in operation from VS1 (6 V), the line return signal RL is still present, as well as the sweep voltage DSC, to ensure proper functioning of the supply circuit.

When the receiver is switched off, Vcc falls gradually, for lack of mains supply. When it drops below VS2 (9 V), functioning of the chopped power supply circuit is inhibited at the next line return signal RL (comparator 62 and AND gate 64). The power supply is therefore switched off in the blocked state of transistor T2 in FIG. 1.

Vcc then falls below VS1 (6 V), stopping scanning. Meanwhile, the supply circuit output voltage has dropped, so that the very high voltage has itself fallen; the electron beam is therefore no longer so intense when scanning stops, and there is no danger of an intense motionless beam burning any point on the screen.

Occurrence of voltage surges at a critical point on the circuit is illustrated in the voltage chart in FIG. 4, showing potential Vcc from the time of switching on the receiver, and potential Ve from the time of switching on and after the appearance of three successive voltage surges, resulting, for instance, from an ionizing discharge in the cathode-ray tube at the start of its lifespan.

At switch-on (time 0), potential Vcc rises from 0 to 12 volts. Potential Ve follows it, stabilizing at Vz (about 7 volts), after which it decreases slowly, to establish the gradual startup phase of the chopped power supply circuit as already explained in connection with FIG. 3.

A voltage surge is assumed to occur at time t ₁ , causing threshold VS3 (which can be regulated as necessary, to suit the voltage surges to be detected), to be exceeded at the input to comparator 54, which therefore delivers a signal switching over flipflop 50 at the first line return signal RL after the threshold has been exceeded. Counter 46, initially reset to 0, because Vcc has passed through a level below 4 volts during switching-on of the receiver, is incremented by a unit.

Simultaneously, the flipflop output delivers a signal through OR gate 56, to inhibit horizontal and vertical scanning, and through OR gate 66, to inhibit the chopped power supply circuit.

Since there is no further horizontal scanning, current source 34 can no longer keep capacitor C3 charged, and current source 36 begins to discharge it slowly, raising potential Ve.

When Ve reaches threshold VS4, comparator 40 delivers a logic signal which resets flipflop 50, simultaneously causing restarting of scanning, and the chopped power supply circuit since Vcc has remained at 12 volts in the meantime.

Horizontal scanning causes reappearance of the periodical line return signal RL, and current source 34 can once again charge capacitor C3, causing potential Ve to fall gradually, initiating a phase of gradual startup of the supply circuit.

Further surges can occur, for example at times t ₂ and t ₃ . The same procedure prevails, unless the content of counter 46 is high enough for the decoder 44 to deliver a signal blocking AND gate 42, therefore blocking resetting of flipflop 50. If the decoder is programmed for example, to deliver a blocking signal when the contents of the counter indicate the third successive voltage surge without resetting to 0 (it should be remembered that resetting can occur either when the receiver is switched off, or after a certain period), the voltage surge occuring at time t ₃ will again cause simultaneously stoppage of scanning and of the chopped power supply circuit at the first line signal RL after appearance of the voltage surge, and therefore raising potential Ve. But decoder 44 will prevent resetting of the flipflop and therefore startup of scanning circuits and supply circuit Ve will stabilize at the level Vz determined by the limiter. No fresh startup can occur until the receiver has been switched off and on again.

The number of surges and the period for which they can occur without causing definite stoppage of scanning circuits can be selected as required.

The clock governing the period within which n succeeding surges (where n is 3, for example) must not occur can be formed of a monostable flipflop (not shown here), tripped by the first status-change in the counter, or of any other timing device. The counter and flipflop can also be cleared periodically, every 20 milliseconds, by resetting to 0 of the vertical scan.

FIG. 5 shows a constructional detail illustrating a further improvement. The circuit in FIG. 1 remains unchanged, but only the capacitor C3 and current sources 34 and 36 are shown here.

These current sources supply current of the same amplitude, but they are activated during different periodical time intervals. The time interval for control of source 34 lasts 4 microseconds on each period (provided that the line return signal RL is present); this time interval is established by a logic circuit, and is located within the duration of the RL signal. The interval controlling source 36 lasts 2 microseconds for each horizontal scanning period, and can be generated from a 500 kHz clock and a logic circuit allowing a single clock impulse to pass for each horizontal scanning period.

In the presence of RL, the average value of currents delivered means that capacitor C3 charges; in the absence of the signal, it discharges.

Provision can also be made for the lower level of voltage Ve to be limited, by a voltage from a divider bridge supplied by voltage Vcc. A diode providing a direct polarization link between the divider bridge and the first plate of capacitor C3 prevents Ve from falling below a certain level. This obviously involves absolute limitation of the width of signals which the chopped power supply circuit comparator 24 can supply.

If the scanning circuit is an integrated circuit (except for power components), capacitor C3 is kept outside this integrated circuit, as well as the divider bridge and diode, so that maximum signal width can be adjusted at will.

In the description above, the first plate of capacitor C3 has to follow potential Vcc quickly, when the receiver is switched on. For this purpose, the second plate is connected to the low-voltage source Vcc. This plate could also be earthed, and a fairly intense additional current source included, activated only when Vcc is below a threshold of 8 to 10 volts. Such a source would be parallel to source 36, and would cease to function once Vcc reached its nominal level of 12 volts. 

AN5620X  PAL System Color TV Chrominance Signal Processing Circuit

TDA4443 MULTISTANDARD VIDEO IF AMPLIFIER DESCRIPTION The TDA4443 is a Video IF amplifier with standard switch for multistandard colour or monochromeTV sets, and VTR’s. SWITCHING OFF THE IF AMPLIFIER WHEN OPERATING IN VTR MODE .DEMODULATION OF NEGATIVE OR POSITIVE IF SIGNALS. THE OUTPUT REMAINS ON THE SAME POLARITY IN EVERY CASE .IF AGC AUTOMATICALLY ADJUSTED TO THE ACTUALSTANDARD .TWO AGC POSSIBILITIES FOR B/G MODE : 1. GATED AGC 2. UNGATED AGC ON SYNC. LEVEL AND CONTROLLED DISCHARGE DEPENDENT ON THE AVERAGE SIGNAL LEVEL FOR VTR AND PERI TV APPLICATIONS FOR STANDARD L : FAST AGC ON PEAK WHITE BY CONTROLLED DISCHARGE .POSITIVE OR NEGATIVE GATING PULSE .EXTREMELY HIGH INPUT SENSITIVITY .LOW DIFFERENTIAL DISTORTION .CONSTANT INPUT IMPEDANCE .VERY HIGH SUPPLY VOLTAGE REJECTION .FEW EXTERNAL COMPONENTS .LOW IMPEDANCE VIDEO OUTPUT .SMALL TOLERANCES OF THE FIXED VIDEO SIGNALAMPLITUDE .ADJUSTABLE, DELAYED AGC FOR PNP TUNERS. GENERAL DESCRIPTION This video IF processing circuit integrates the following functional blocks : .Three symmetrical, very stable, gain controlled wideband amplifier stages - without feedback by a quasi-galvanic coupling. .Demodulator controlled by the picture carrier .Video output amplifier with high supply voltage rejection .Polarity switch for the video output signal .AGC on peak white level .GatedAGC .Discharge control .Delayed tuner AGC .At VTR Reading mode the video output signal is at ultra white level.  

TDA4445A SOUND IF AMPLIFIER .QUADRATURE INTERCARRIER DEMODULATOR .VERY HIGH INPUT SENSITIVITY .GOODSIGNALTO NOISE RATIO .FAST AVERAGINGAGC .IF AMPLIFIER CAN BE SWITCHED OFF FOR VTR MODE .GOODAM SUPPRESSION .OUTPUT SIGNAL STABILIZED AGAINST SUPPLY VOLTAGE VARIATIONS .VERY FEW EXTERNAL COMPONENTS DESCRIPTION TDA4445A: Sound IF amplifier, with FM processing for quasi parallel sound system. TDA4445B: Sound IF amplifier, with FM processing and AM demodulator, for multi-standard sound TV appliances. TDA4445Badditionnal : Bistandard applications (B/G and L) No adjustment of the AM demodulator Low AMdistortion. GENERAL DESCRIPTION This circuit includes the following functions : .Three symmetrical and gain controlled wide band amplifier stages, which are extremely stable by quasiDC coupling without feedback. .Averaging AGC with discharge control circuit .AGC voltage generator Quasi parallel sound operation : .High phase accuracy of the carrier signal processing, independentfrom AM .Linear quadrature demodulator .Sound-IF-amplifier stage with impedance converter AM-Demodulation (only TDA4445B) : .Carrier controlled demodulator .Audio frequency stage with impedance converter .Averaging low passAGC. 

 

 HA11489 (HITACHI) WIDE BAND VIDEO PROCESSOR  

DESCRIPTION The HA11494 is a serial bus-controlled videoprocessing device which integrates a complex architecture fulfilling multiple functions. .DIGITAL CONTROL OF BRIGHTNESS, SATURATION AND CONTRAST ON TV SIGNALS AND R, G, B INTERNAL OR EXTERNAL SOURCES .BUS DRIVE OF SWITCHING FUNCTIONS .DEMATRIXING OF R, G, B SIGNALS FROM Y, R-Y, B-Y, TV MODE INPUTS .MATRIXING OF R, G, B SOURCES INTO Y, R-Y, B-Y SIGNALS .AUTOMATIC DRIVE AND CUT-OFF CONTROLS BY DIGITAL PROCESSING DURING FRAME RETRACE .PEAK ANDAVERAGE BEAM CURRENT LIMITATION .ON-CHIP SWITCHING FOR R, G, B INPUT SELECTION .ON-CHIP INSERTION OF INTERNAL OR EXTERNAL R, G, B SOURCES An automatic contrast control circuit in a color television receiver for stabilizing the average DC level of the luminance information at a desired level and preventing focus blooming. The control circuitry, which is suitable for fabrication as a monolithic integrated circuit, contemplates the provision of a gain-controlled luminance amplifier stage for driving an image reproducer with luminance information having a stabilized black level. An average detector coupled to the amplifier stage output develops a control signal representative of the average DC level of the luminance information and applies it to the amplifier stage, varying its gain inversely with changes in the average luminance level. A peak limiter circuit is also provided for modifying the control signal to reduce the amplifier stage's gain whenever an AC brightness component comprising the luminance information exceeds a defined threshold level, regardless of the average DC level of the luminance information. 1. In a television receiver having a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer, said luminance signals including black level reference information, an automatic contrast control circuit comprising in combination: 2. An automatic contrast control circuit in accordance with claim 1, wherein adjustable level shifting means are interposed between said amplifier stage and said average detector means, said adjustable level shifting means providing a contrast control for manually varying the average DC level of said luminance signals. 3. An automatic contrast control circuit in accordance with claim 1, wherein said average detector means includes a capacitor having an output terminal coupled to said amplifier stage and a second terminal coupled to a plane of reference potential, said capacitor being charged by luminance signals from said amplifier stage and developing control signals representative of the average DC level of said luminance signals. 4. An automatic contrast control circuit in accordance with claim 3, wherein said control signals with respect to a plane of reference potential are equal to the potential at which black level is stabilized minus the potential drop between black level and the average DC level of said luminance information, said control signal increasing with respect to said plane of reference potential responsive to decreasing average DC levels of said luminance signals and decreasing responsive to increasing average DC levels. 5. An automatic contrast control circuit in accordance with claim 3, wherein said peak detector means includes a semi-conductor arrangement for providing said capacitor with a low impedance discharge path whenever said brightness components exceed a predetermined threshold level, the impedance of said discharge path being dependent on the amplitude of said brightness components and the discharge interval of said semiconductor arrangement being the time period during which said brightness components exceed said threshold level, said semiconductor arrangement further decreasing said control signals with respect to said plane of reference potential irrespective of the average DC level of said luminance signals. 6. An automatic contrast control circuit in accordance with claim 5, wherein said semiconductor arrangement comprises first and second transistors, said luminance signals from said amplifier stage being coupled to the input base electrode of said first transistor, said first transistor further having an emitter electrode coupled to said capacitor output terminal and a collector electrode coupled to the base electrode of said second transistor, said second transistor having a collector electrode coupled to said capacitor output terminal and an emitter electrode coupled to said plane of reference potential, said semiconductor arrangement being conductive to provide said capacitor with a low impedance discharge path whenever said brightness components exceed the base-emitter junction breakdown voltage of said first transistor. 7. An automatic contrast control circuit in accordance with claim 6, wherein said gain-controlled luminance amplifier stage includes a pair of transistors arranged in a differential amplifier configuration, the gain of which is dependent on the bias applied to the base electrodes of said transistors. 8. An automatic contrast control circuit in accordance with claim 7, wherein inverter means invert and couple said control signals to said base electrodes in said amplifier stage, the inverted control signals increasing the gain of said amplifier stage whenever the average DC level of said luminance signals decreases and decreasing the gain of said amplifier stage whenever the average DC level of said luminance information increases or whenever said brightness components exceed said threshold level. 9. An automatic contrast control circuit in accordance with claim 3, wherein said beam current limiter means provide a low impedance discharge path for said capacitor whenever the beam current exceeds a predetermined level. 10. An automatic contrast control system in accordance with claim 9, wherein said beam current limiter means monitors pulses from a voltage multiplier high-voltage system, said pulses being proportional to the beam current generated during the previous horizontal scan line. 11. An automatic contrast control circuit in accordance with claim 10, wherein said beam current limiter means comprises a transistor having a base electrode coupled to said voltage multiplier high-voltage system, an emitter electrode coupled to a plane of reference potential and a collector electrode coupled to said capacitor, said transistor providing a low impedance discharge path whenever said pulses exceed the base-emitter junction breakdown voltage of said transistor.

Description:

BACKGROUND OF THE INVENTION This invention relates in general to control circuitry for color television receivers and more particularly to an automatic contrast control circuit incorporated in the luminance processing channel. In accordance therewith, a variable DC control signal is derived from the luminance signal information as a function of the average luminance level. The DC control signal is applied to a gain-controlled amplifier stage in the luminance channel, varying its gain and thereby insuring that excessive beam currents will not be generated due to high average luminance levels. Conversely, the circuit is effective to increase the gain of the amplifier stage when under-modulated signals are received thereby providing the desired contrast level. When the white content of the instantaneous received signal exceeds a predetermined level, however, the DC control signal is modified to reflect the excessive white content even though the average luminance level may be low. Accordingly, the amplifier stage's gain is reduced to prevent defocusing. In color television receivers, the various elemental areas of differing brightness levels, or shades, in the televised image correspond to the amplitude levels of the instantaneous brightness components of the luminance signals which, together with the chrominance signal, reproduce the transmitted picture information on the image display tube. The intensity of the electron beams developed in the receiver's image display tube are varied, for the most part, according to the detected amplitude levels of the instantaneous luminance signals. Accordingly, progressively higher amplitude levels generate higher intensity electron beams and, consequently, progressively lighter shades. In addition, suitable viewer-adjustable controls are customarily provided in the television receiver whereby a particularized contrast and brightness setting may be selected according to viewer preference. It is desirable that the level of the luminance signal component corresponding to black in the televised image be maintained at the cut-off of the image reproducer. But even in those instances where there is a measure of DC coupling, the DC components of the luminance signal coupled from the video detector to the luminance channel may be degraded or otherwise restricted due to the nature of the processing circuitry as well as to other factors. Moreover, the luminance processing channel itself may well permit a degradation or undesirable shift in the desired DC characteristics. The result is that the DC level in the processed luminance signal is not properly maintained, such that, upon application to the image display tube, the black level is shifted to some undesirable reference. This leads to less than faithful half-tone reproduction on the screen of the image display tube. Gray tones can be lost simply because they are beyond the cut-off of the display tube. In other instances, blacks may appear as grays on the image display tube screen. Thus, it is desirable to make provision for the maintenance of black level in the televised image at some stabilized reference. Various systems are of course known in the art for accomplishing this objective and take various forms and configurations. For example, an arrangement commonly known as a DC restorer circuit which includes a clamping device may be employed. However, when the black level is effectively stabilized at the image reproducer's cut-off bias point, the average level of the luminance signal information may reach the point where excessive average beam currents capable of severely damaging the image reproducer are generated. In addition, the high voltage power supply during instances of high beam current may be incapable of delivering the required beam current. Such overloading reduces the power supply output voltage and results in undesirable "focus blooming." That is, there will be a loss of brightness, reduction of horizontal widths and severe defocusing of the reproduced image. The problem in this regard has been further compounded by the "new generation" high-brightness cathode-ray tubes which require higher beam currents in order to illuminate the tube to its fullest capability during high-modulation (white) scenes. In view of the added demands on the high voltage power supply and the danger of damaging the image display tube, some method for effectively limiting the beam current is required. Accordingly, automatic contrast control systems have been developed which reduce the gain of the luminance amplifier stage to prevent the generation of excessive beam currents or increase the gain when under-modulated signals are received. Most of these prior art automatic contrast control systems, however, measure only the average level of the luminance signals to derive the control signal utilized to vary the gain of the luminance amplifier. Consequently, when all or a major portion of the luminance signal's white content is of a high amplitude level and is concentrated on a very small portion of the image reproducer's screen, the control signal derived from the average luminance level is low, permitting the luminance amplifier stage to operate at nearly maximum gain. By concentrating the high-amplitude white content into a small area of the screen, the image display tube is likely to be overdriven during that period of time and "focus blooming" will result. Some automatic contrast systems, on the other hand, derive a control signal based on the peak amplitudes of the instantaneous luminance signals without regard to the average luminance level. Thus, while preventing blooming on high-amplitude white content, such systems are susceptible to luminance signals which have a dangerously high average level, but do not have any peak white signal content of a level where the system would take corrective action. OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide a color television receiver having black level stabilization with a new and improved automatic contrast control circuit which effectively overcomes the aforenoted disadvantages and deficiencies of prior circuits. A further object of the invention is to provide an improved automatic contrast control circuit which develops control signals effectively varying the gain of a luminance amplifier stage to maintain an optimum contrast, while preventing the generation of excessive beam currents in the cathode-ray tube. A more particular object of the invention is to provide an improved automatic contrast control circuit for continuously monitoring the average (DC) level of the luminance signal information and providing a control signal representative thereof to vary the gain of a luminance amplifier stage while remaining sensitive to the amplitude levels of brightness components exceeding a threshold level and modifying the control signal in accordance therewith. Another object of the invention is to provide an improved automatic contrast control circuit which increases the gain of a luminance amplifier stage during reception of undermodulated luminance signals. A further object of the present invention is to provide an automatic contrast control circuit of the foregoing type for deriving a variable DC control potential from applied luminance signals which, upon application to the luminance channel, adjusts the gain of a luminance amplifier stage in accordance with the varying luminance signal requirements. Still another object of the invention is to provide a luminance processing channel including automatic contrast control circuitry which may be fabricated as a monolithic integrated circuit to provide an output luminance signal having stabilized black level and optimum contrast without producing excessive beam currents. SUMMARY OF THE INVENTION In accordance with the present invention, an improved automatic contrast control circuit is provided for varying the gain of an amplifier stage in the luminance processing channel of a color television receiver whenever the average DC level of the input luminance information varies from a desired level, or whenever the peak amplitudes of the AC brightness components of the luminance information exceed a predetermined threshhold level. In a preferred embodiment, the automatic contrast control circuit includes a gain-controlled luminance amplifier stage in a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer. The amplified luminance signals found at the output of the amplifier stage have a stabilized black level. There are also provided detector means coupled to the amplifier output for developing control signals that are representative of the average DC level of the instantaneous luminance signals. The control signals are then applied to the gain-controlled amplifier stage to vary its gain inversely with changes in the average luminance level. Finally, peak limiter means are coupled between the amplifier output and the detector means to modify the control signals whenever the instantaneous luminance signals exceed a threshhold level. The modified control signals are similarly utilized to effect inverse gain variations in the gain-controlled amplifier stage regardless of the average level of the luminance signals. GENERAL DESCRIPTION Brief Description This integrated circuit incorporates the following features : - a synchro and two video inputs - a fixed video output - a switchable video output - normal Y, R-Y, B-Y TV mode inputs - double set of R, G, B inputs - brightness, contrast and saturation controls as wellon aR,G, B picture ason a normalTVpicture - digital control inputs by means of serial bus - peak beam current limitation - average beam current limitation - automaticdrive and cut-off controls Block Diagram Description BUS DECODER A 3 lines bus (clock, data, enable) delivered by the microcontroller of the TV-set enters the videoprocessor integrated circuit (pins 13-14-15). A control system acts in such a way that only a 9-bit word is taken intoaccount by the videoprocessor.Six of the bits carry the data, the remaining three carry the address of the subsystem. A demultiplexer directs the data towards latches which drive the appropriate control. More detailed information about serial bus operation is given in the following chapter. Video Switch The video switch has three inputs : - an internal video input (pin 39), - an external video input (pin 37), - a synchro input (pin 41), and two outputs : - an internal video output (pin 40), - a switchable video output (pin 42) The 1Vpp composite video signal applied to the internal video input is multiplied by two and then appears as a 2Vpp low impedance composite video signal at the output. This signal is used to deliver a 1Vpp/75W composite video signal to the peri-TV plug. The switchable video output canbe any of the three inputs.When the Int/Ext one active bit word is high (address number 5), the internal video input is selected. If not, either a regeneratedsynchro pulse or the external video signal is directed towards this output depending on the level of the Sync/Async one active bit word (address number 4). As this output is to be connected to the synchro integrated circuit, RGB information derived from an external source via the Peri-TV plug canbedisplayed on the screen, the synchronization of the TV-set being then made with an external video signal. When RGB information is derived from a source integrated in the TV-set, a teletext decoder for example, the synchronization can be made either on the internal video input (in case of synchronous data) or on the synchro input (in case of asynchronous data). R, G, B Inputs There are two sets of R, G, B inputs : one is to be connected to the peri-TV plug (Ext R, G, B), the second one to receive the information derived from the TV-set itself (Int R, G, B). In order to have a saturation control on a picture coming from the R, G, B inputs too, it is necessary to getR-Y, B-Y and Y signals from R, G, B information : this is performed on the first matrix that receives the three 0.9Vp (100% white) R, G, B signals and delivers the corresponding Y, R-Y, B-Y signals. These ones are multiplied by 1.4 in order to make the R-Y and B-Y signals compatible with the R-Y and B-Y TV mode inputs. The desired R, G, B inputs are selected by means of 3 switches controlled by the two fast blanking signal inputs. A high level on FB external pin selects the external RGB sources. The three selected inputs are clamped in order to give the required DC level at the output of this firstmatrix. Thethree not selected inputs are clamped on a fixed DC level. Y, R-Y, B-Y Inputs The 2Vpp composite video signal appearing at the switchable output of the video switch (pin 42) is driven through the subcarrier trap and the luminance delay line with a 6 dB attenuation to the Y input (1Vpp ; pin 12). In order to make this 1Vpp (synchro to white) Y signal compatible with the 1Vpp (black to white) Y signal delivered by the first matrix, it is necessary to multiply it by a coefficient of 1.4. Controls The four brightness, contrastand saturationcontrol functions are direct digitally controlled without using digital-to-analog converters. The contrast control of the Y channel is obtained by means of a digital potentiometer which is an attenuator including several switchable cells directly controlled by a 5 active bit word (address number 1). The brightness control is also made by a digital potentiometer (5 active bit word, address number 0). Since a + 3dB contrast capability is required, the Y signal value could be up to 0.7Vpp nominal. For both functions, the control characteristics are quasi-linear. In each R-Y and B-Y channel, a six-cell digital attenuator is directly controlled by a 6 active bit word (address number 6 and 7). The tracking needed to keep the saturation constant when changing the contrast has to be done externally by the microcontroller. Furthermore, colour can be disabledby blankingR-Y andB-Ysignals using one active bit word (address number 2) to drive the one-chip colour ON/OFF switch. Second Matrix, Clamp, Peak Clipping, Blanking The second matrix receives the Y, R-Y and B-Y signals and delivers the corresponding R, G, B signals. As it is required to have the capability of + 6dB saturation, an internal gain of 2 is applied on both R-Y and B-Y signals. A low clipping level is included in order to ensure a correct blanking during the line and frame retraces. Ahigh clipping level ensures thepeakbeamcurrent limitation. These limitations are correct only if the DC bias of the three R, G, B signals are precise enough. Therefore a clamp has been added in each channel in order to compensate for the inaccuracy of the matrix. Sandcastle Detector And Counter The three level supersandcastle is used in the circuit to deliver the burst pulse (CLP), the horizontal pulse (HP), and the composite vertical and horizontal blanking pulse (BLI). This last one is regenerated in the counter which delivers a new composite pulse (BL) in which the vertical part lasts 23 lines when the vertical part of the supersandcastle lasts more than 11 lines. The HA11489 cannot work properly if this minimum duration of 11 lines is not ensured. The counterdelivers different pulses neededcircuit and especially the line pulses 17 to 23 used in the automatic drive and cut-off control system. Automatic Drive And Cut-off Control System Cut-off and drive adjustments are no longer required with this integrated circuit as it has a sample and hold feedback loop incorporating the final stages of the TV-set. This system works in a sequentialmode. For this purpose, special pulses are inserted in G, R and B channels. During the lines 17, 18 and 19, a ”drive pulse” is inserted respectively in the green, red and blue channels. The line 20 is blanked on the three channels. During the lines 21, 22 and 23, a ”quasi cut-off pulse” is inserted respectively in the green, red and blue guns. The resulting signal is then applied to the input of a voltage controlled amplifier. In the final stages of the TV-set, the current flowing in each green, red and blue cathode is measured and sent to the videoprocessorby a current source. The three currents are added together in a resistor matrix which can be programmed to set the ratio between the three currents in order to get the appropriate colour temperature. The output of the matrix forms a high impedance voltage source which is connectedto the integratedcircuit (pin 34). Same measurement range between drive and cutoff is achieved by internally grounding an external low impedance resistor during lines 17, 18 and 19. This is due to the fact that the drive currents are about one hundred times higher than the cut-off and leakage currents. Each voltage appearing sequentially on the wire pin 34 is then a function of specific cathode current : - When a current due to a drive pulse occurs, the voltage appearing on the pin 34 is compared within the IC with an internal reference, and the result of the comparison charges or discharges an external appropriate drive capacitor which stores the value during the frame. This voltage is applied to a voltage controlled amplifier and the system works in such a waythat the pulse current drive derived from the cathode is kept constant. - During the line 20, the three guns of the picture tube are blanked. The leakagecurrent flowing out of the final stages is transformed into a voltage which is stored by an external leakage capacitor to be used later as a reference for the cut-off current measurement. - When a current due to a cut-off pulse occurs, the voltage appearing on the pin 34 is compared within the ICto the voltagepresenton the leakage memory. Anappropriate externalcapacitor is then charged or discharged in such a way that the difference between each measured current and the leakage current is kept constant, and thus the quasi cut-off current is kept constant. AverageBeam Current Limitation The total current of the three guns is integrated by means of an internal resistor and an external capacitor (pin 36) and thencompared with a programmable voltage reference(pin 38). When 70% of the maximum permitted beam current is reached, the drive gain begins to be reduced ; to do so, the amplitude of the inserted pulse is increased. In order to keep enough contrast, the maximum drive reduction is limited to 6dB. If it is not sufficient, the brightness is suppressed. SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL DATA BUS This is a bi-directional 3-wire (ENABLE, CLOCK, DATA) serial bus. The DATA line transmission is bi-directional whereas ENABLE and CLOCK lines are only microprocessor controlled. The ENABLE and CLOCK lines are only driven by the microcomputer.