NOKIA 3724 CHASSIS STANDARDMONO BG PAL 14" NN (54317550) INTERNAL VIEW

 NOKIA 3724  CHASSIS STANDARDMONO BG PAL 14" NN  is first type of monocarrier featuring the PHILIPS TDA8360 allowing a high grade integration development of a TV chassis.Was a forerunner in the market.

NOKIA 3724  CHASSIS STANDARDMONO BG PAL 14" NN (54317550)     Synchronized switch-mode power supply:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.

Description:

The invention relates to switch-mode power supplies.

Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.

To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.

Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.

It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.

It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.

A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.

 

  NOKIA 3724  CHASSIS STANDARDMONO BG PAL 14" NN (54317550)  Switch-mode power supply with burst mode standby operation:
Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.
To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of the external devices are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock. Such electrical shock may occur if the common conductor is not held floating. Furthermore, having the common conductor floating avoids an undesirable current flow, or a current loop, among the common conductors that are, as described above, connected together.
Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials at the terminals of the AC mains supply source that provides power to the receiver. Such isolation is typically achieved by a transformer, as described below. The isolated common conductor is sometimes referred to as "cold" ground conductor.
In some television receivers the AC mains supply voltage is coupled directly to a bridge rectifier for producing an unregulated direct current (DC) input voltage. The unregulated DC input voltage is applied to a SMPS having a chopper transformer that generates regulated DC voltages. The regulated DC voltages are, typically, developed, from a secondary winding of the chopper transformer, relative to the cold ground conductor. The chopper transformer conductively isolates the regulated voltages, thus causing them to be floating, relative to the potentials at terminals of the AC mains supply voltage source.
Circuit networks of the power supply that provide voltages that are not floating relative to the potentials at the AC mains supply voltage source terminals, such as voltages at the primary winding of the chopper transformer, are referenced to a common conductor that is, therefore, floating relative to the cold ground conductor and that is sometimes referred to as "hot" ground conductor.
In some television receivers, a remote control unit generates a first on/off control signal that is referenced to the "cold" ground conductor. The first on/off control signal, for example, disables a horizontal oscillator, thereby initiating a standby mode of operation. As a result, a decrease loading of circuit elements that are referenced to the "cold" ground occurs. A pulse-width modulator (PWM) controls a switching transistor of the SMPS. The switching transistor is coupled to the primary winding of the chopper transformer. The PWM, the switching transistor and the primary winding are referenced to the "hot" ground. It may be desirable to generate a second on/off control signal that is referenced to the "hot" ground via the chopper transformer to provide the required isolation between the first and second on/off control signals.
In a switch mode power supply, a first switching transistor is coupled to a primary winding of a transformer for generating pulses of a switching current. A secondary winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a control signal in the capacitor. The control signal is applied to a mains coupled chopper second transistor for generating and regulating supply voltages in accordance with pulse width modulation of the control signal. During standby operation, the first and second transistors operate in a burst mode that is repetitive at a frequency of the AC mains supply voltage such as 50 Hz. In the burst mode operation, during intervals in which pulses of the switching current occur, the pulse width and peak amplitude of the switching current pulses progressively increase in accordance with the waveform of the mains supply voltage to provide a soft start operation in the standby mode of operation within each burst group.

Description:

The invention relates to switch-mode power supplies.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of a flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce DC output supply voltages such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver and a voltage that energizes a remote control unit.

During normal operation, the DC output supply voltages are regulated by the pulse width modulator in a negative feedback manner. During standby operation, the SMPS is required to generate the DC output supply voltage that energizes the remote control unit. However, most other stages of the television receiver are inoperative and do not draw supply currents. Consequently, the average value of the duty cycle of the chopper transistor may have to be substantially lower during standby than during normal operation.

Because of, for example, storage time limitation in the chopper transistor, it may not be possible to reduce the length of the conduction interval in a given cycle below a minimum level. Thus, in order to maintain the average value of the duty cycle low, it may be desirable to operate the chopper transistor in an intermittent or burst mode, during standby. During standby, a long dead time interval occurs between consecutively occurring burst mode operation intervals. Only during the burst mode operation interval switching operation occurs in the chopper transistor. The result is that each of the conduction intervals is of a sufficient length.

In accordance with an aspect of the invention, burst mode operation intervals are initiated and occur at a rate that is determined by a repetitive signal at the frequency of the AC mains supply voltage. For example, when the mains supply voltage is at 50 Hz, each burst mode operation interval, when switching cycles occur, may last 5 milliseconds and the dead time interval when no switching cycles occur, may last during the remainder portion or 15 milliseconds. Such arrangement that is triggered by a signal at the frequency of the mains supply voltage simplifies the design of the SMPS.

The burst mode operation intervals that occur in standby operation are synchronized to the 50 Hz signal. During each such interval, pulses of current are produced in transformers and inductances of the SMPS. The pulses of current occur in clusters that are repetitive at 50 Hz. The pulses of current occur at a frequency that is equal to the switching frequency of the chopper transistor within each burst mode operation interval. Such qurrent pulses might produce an objectionable sound during power-off or standby operation. The objectionable sound might be produced due to possible parasitic mechanical vibrations as a result of the pulse currents in, for example, the inductances and transformers of the SMPS.

In accordance with another aspect of the invention, the change in the AC mains supply voltage during each period causes the length of the conduction interval in consecutively occurring switching cycle during the burst mode operation interval to increase progressively. Such operation that occurs during each burst mode operation interval may be referred to as soft start operation. The soft start operation causes, for example, gradual charging of capacitors in the SMPS. Consequently, the parasitic mechanical vibrations are substantially reduced. Also, the frequency of the switching cycles within each burst mode operation interval is maintained above the audible range for further reducing the level of such audible noise during standby operation.

A switch mode power supply, embodying an aspect of the invention, for generating an output supply voltage during both a standby-mode of operation and during a run-mode of operation includes a source of AC mains input supply voltage. A control signal at a given frequency is generated. A switching arrangement energized by the input supply voltage and responsive to the first control signal produces a switching current during both the standby-mode of operation and the run-mode operation. The output supply voltage is generated from the switching current. An arrangement coupled to the switching arrangement and responsive to a standby-mode/run-mode control signal and to a signal at a frequency that is determined by a frequency of the AC mains input supply voltage controls the switching arrangement in a burst mode manner during the standby-mode of operation. During a burst interval, a plurality of switching cycles are performed and during an alternating dead time interval no switching cycles are performed. The two intervals alternate at a frequency that is determined by the frequency of the AC mains input supply voltage.

 

NOKIA 3724  CHASSIS STANDARDMONO BG PAL 14" NN (54317550)  TEA2164G /2165 SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT


.POSITIVE AND NEGATIVE OUTPUT CURRENT
UP TO 1.2AAND – 1.7A .A TWO LEVEL COLLECTOR CURRENT LIMITATION
.COMPLETE TURN OFF AFTER LONG DURATION
OVERLOADS .UNDER AND OVER VOLTAGELOCK-OUT .SOFT START BY PROGRESSIVE CURRENT
LIMITATION .DOUBLE PULSE SUPPRESSION .BURST MODE OPERATION UNDER STANDBY
CONDITIONS
DESCRIPTION
In amaster slave architecture, the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
Located at the primary side the TEA2164 Control
IC ensures :
- the power supply start-up
- the power supply control under stand-by conditions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive of the bipolarswitching transistor
- the protection of the transistor and the power
supply under abnormal conditions.

II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Control
IC, located at the primary side of an off line
power supply achievesthe slave function ;whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
pulse transformer

In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- stand-bymode
- power supply start-up
- abnormal conditions : off load, short circuit, ...
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse widthmodulatedsignal issued from themonitoring
of the output voltage which needs the best
accuracy (in TV applications : the horizontal deflection
stagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon
commands ; and negative pulses are transistor
switching-offcommands (Figure 4). In this configuration,
only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
II.2. Stand-by Mode
In this configuration the master circuit no longer
sends PWM signals, the structure is not synchronized
; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W 3 P 3 6W (as it is
consumed in TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
output voltages.Voltage on feed-back is applied on
Pin 9.
Burst period is externally programmedby capacitor
C1.
II.3. Power Supply Start-up
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage.When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during startup.

Overvoltage Protection
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.

NOKIA 3724  CHASSIS STANDARDMONO BG PAL 14" NN (54317550)  TEA5170 SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT:
In television receivers having run and standby modes and using switched mode power supplies, an unregulated DC voltage is derived from a bridge rectifier coupled to a mains source. The unregulated DC voltage is then supplied to a primary winding of a power transformer that isolates the hot ground side of the chassis from the cold ground side. A standby regulator, such as the SGS Thomson Microelectronics TEA2162 TEA2164 TEA 2165 TEA2260 or TEA2261, is located on the hot side and controls a switching means such as a chopper transistor to apply current pulses of variable pulse width and amplitude to the primary winding. Regulated voltages are developed on secondary windings of the power transformer. The standby regulator is powered from the unregulated B+ voltage when the television receiver is first coupled to the mains, and thereafter provides the regulating action in a standby mode of operation until the apparatus is switched into the run mode, whereupon the standby regulator is controlled by a run regulator located on the hot ground side.

Loads other than the standby regulator, including the standby loads and run mode loads such as the horizontal deflection circuit, are coupled to secondary windings of the power transformer. The run mode loads are inactive in the standby mode. Run mode loads may be coupled to regulated voltages, but switched off in the standby mode by a signal from a controller such as a microprocessor responsive to a remote control. Alternatively, run mode loads may be coupled to secondary windings of the horizontal flyback transformer, and are unpowered in the standby mode because, although the flyback transformer is coupled to a regulated B+ voltage, no voltages are generated in the secondary windings of the flyback transformer in the absence of horizontal scanning.
The standby regulator operates at a stable frequency and has a pulse width modulator that regulates voltages on the secondary windings of the power transformer by adjusting the pulse width or duty cycle of the voltage pulses applied to the chopper transistor. In the standby mode, the standby regulator is made to free run at its local oscillator frequency, and regulates by sensing the voltage on a hot ground secondary winding of the power transformer. The sensed voltage is coupled to an input of an error amplifier having a second input coupled to a voltage reference. Regulation of the B+ scan supply voltage occurs indirectly, because the voltages on all the secondary windings go up or down together.

In the run mode, the standby regulator becomes the slave of a run regulator on the cold ground side. The run regulator may be, for example, the SGS Thomson Microelectronics TEA5170. The standby regulator continues to switch the chopper transistor on the primary winding of the power transformer for producing regulated voltages on the secondaries, but the standby regulator is driven in the run mode by a pulse width modulation signal generated by the run regulator. The run regulator is synchronized with the horizontal deflection by e.g. horizontal flyback pulses. The regulated B+ voltage for the horizontal deflection circuit is fed back to an error amplifier in the run regulator and compared to a reference for generating the pulse width modulation signal that is coupled back to the standby regulator. The pulse output of the run regulator is used in the run mode to supplant the output of pulse width modulation circuitry in the standby regulator.
When the feedback to whichever of the regulators that is controlling, differs from the applicable reference level, the regulator's pulse width modulation circuit changes the pulse width or duty cycle of output pulses, to vary the power through the power transformer and regulate the output voltage. In order to avoid generating too much current in the chopper transistor and power transformer, a number of safety features are built into the run and standby regulators and into the controller that switches between run and standby modes.
A current sensing resistor is coupled in series with the chopper. This resistor provides a voltage representing the current level in the chopper and in the primary winding to a shutdown circuit in the standby regulator. The shutdown circuit of the TEA2260/61 has two threshold levels. If current passes a lower threshold, the on-pulse of the pulse width modulated output is immediately terminated but is redeveloped at the next cycle of operation. If current passes a higher threshold, the standby regulator shuts down and will not restart until VCC is removed, e.g. by pulling the mains plug. 

The standby and run regulators each include other protective features and sensing circuits arranged to disable operation when their VCC power supply voltages goes above or below internally defined reference levels.
Each regulator also has circuitry to limit the maximum duty cycle of its output by substituting a fixed duty cycle output when the feedback loop attempts to drive the output duty cycle beyond a predetermined limit.
These and other protective features generally handle the load increases that occur with startup and when switching from standby to run, when the pulse width modulators would otherwise seek to increase the duty cycle of the pulse output to bring the output voltages up to their references, with possible damage to the chopper. However, it remains possible that under certain conditions, particularly in the run mode, that changes in loading can cause the duty cycle to be varied rapidly to a point where the chopper transistor is overstressed.
The maximum duty cycle of the TEA5170 run mode regulator is, for example, nominally 78%. The normal duty cycle may be relatively high when the television receiver is a high powered e.g., a large screen set operating under high load conditions, such as high picture brightness and high audio loading. The duty cycle also will be relatively high if the AC mains voltage is relatively low.

These situations may cause the duty cycle of the run regulator to occasionally reach its upper limit. Where operation is such that loading in the run mode varies, for example when the picture includes a change from very dark to very light areas, the run regulator also may increase the duty cycle to its upper limit. This could result in a potential overstressed operating condition.

Another potential problem is encountered when AC mains voltage is lost when operating in the run mode. This can occur in the event of a power outage or when the television receiver is unplugged while operating in the run mode. As the mains voltage is falling, the run regulator increases the duty cycle of the chopper in an attempt to maintain the nominal regulated B+ output voltage. The VCC sensing and maximum current protective features of the run and standby regulators may be marginal or ineffective in preventing overstress conditions in the chopper due to excessive duty cycle operation or fluctuations.

The television receiver microprocessor which generates the ON/OFF signal for switching between run and standby modes is typically supplied with a power reset circuit which detects loss of operating supplies. Once such loss is detected on, e.g., an AC line isolated supply, the microprocessor generates the OFF state of the ON/OFF signal and power to the run regulator is removed. Because power loss is sensed from a secondary winding, activation of the reset circuit may come too late to avoid overstressing the chopper transistor in an AC power loss environment.
.INTERNAL PWM SIGNAL GENERATOR .POWER SUPPLY WIDE RANGE 4.5V – 14.5V .SOFT START .REFERENCE VOLTAGE 2V ± 5% .WIDE FREQUENCY RANGE 250kHz .MINIMUM OUTPUT PULSE WIDTH 500nS
.MAXIMUM PRESET DUTY CYCLE
.SYNCHRONIZATION WINDOW
.OUTPUT SWITCH .UNDERVOLTAGELOCKOUT .FREQUENCYRANGE WITH SYNCHRONIZATION 64kHz



DESCRIPTION
The TEA5170 is designed to work in the secondary
part of an off-line SMPS, sending pulses to the
slaved TEA2260/61 which are located on the primary
side of the main transformer. An accurate
regulated voltage is obtained by duty cycle control.
The TEA5170 can be externally synchronized by
higher or lower frequency signal, then it could be
used in applications like TV set ones.



GENERAL DESCRIPTION
The TEA5170 takes place in the secondary part of
an isolated off-line SMPS. During normal mode
operation, it sends pulses to the slave circuit located
in the primary side (TEA2164, TEA2260/61)
through a pulse transformer to achieve a very
precisely regulated voltage by duty cycle control.
The main blocs of the circuit are :
- an error voltage amplifier
- an RC oscillator
- an output stage
- a VCC monitor
- a voltage reference bloc
- a pulse width modulator
- two logic blocs
- a soft start and Duty cycle limiting bloc
PRINCIPLE OF OPERATION
The TEA5170 sends pulses continuously to the
slave circuit in order to insure a proper behaviour
of the primary side.
- According to this, the output duty cycle is varying
between DON (min.) (0.05) and DON (max.) (0.75) :
then even in case of open load, pulses are still
sent to the slave circuit.

SYNCHRONIZED MODE
The TEA5170 will enter the Synchronized Mode
when it receives one pulse through Rt during Ct
discharge.
At that time Ct charging current will be multiplied
by 0.75 and period will increase up to To x 1.26.
Apulse occuring during the synchro window, commands
the Ct downloading. If none, the TEA5170
will return to normalmode at the end of the period.

STARTING
When VCC is under 4V, output pulses are not
allowed and the slave circuit keeps its own mode.
When VCC is going over 4V, output pulses are sent
via the pulse transformer (or an optical device) to
the slave circuit which is synchronizing and entering
the slaved mode. Output pulses can be shut
down only if VCC goes below 3.8 Volt.
SOFT START
Using Csf, it is possible to make a soft start sequence.
When VCC grows from 0V to 4V, voltage
on Csf equals0V.When VCC is higher than 4V, Csf
is loaded by a 3.7mA current, then TonMAX (Vcsf)
will vary linearly from Tonmin to Tonmax according
to Csfst bias.
When VCC will go low (3.8 Volt threshold), Csf will
be downloaded by an internal transistor.

NOKIA 3724  CHASSIS STANDARDMONO BG PAL 14" NN (54317550)  TEA2164G/TEA2165 EXTENDED OVERLOAD PROTECTION CIRCUIT FOR A SWITCH MODE POWER SUPPLY HAVING CYCLE DETECTOR, MEMORY AND FLIP-FLOP INHIBITION:

 

 A protection device for switch mode power supplies includes a main switch controlled by the output signals of a flip-flop. The flip-flop input receives regulation control signals. A first protection circuit supplies priority signals with respect to the regulation signals on the reset input of the flip-flop. The protection device also includes a cycle detector of the first protection circuit, a memory for accumulating at each cycle a value proportional to the duration between a signal of the detector and the set signal associated with the regulation cycle of the following cycle, and inhibiting of the flip-flop when the memory has accumulated a signal higher than a predetermined threshold.

 

 

Inventors:Maige, Philippe (Syssinet Pariset, FR) Thomson-csf (Paris, FR) 

 

 

 1. A device for protection against long duration overloading in switch mode power supplies comprising a main switch controlled by output signals from a first flip-flop, the set and reset inputs of which receive regulation control signals, a first protection circuit supplying on the reset input priority signals with respect to the regulation signals when the current in the main switch exceeds a predetermined threshold, further comprising a second protection circuit itself comprising:

means for detecting cycles for which the first protection circuit is active and interrupts the on state of the main switch prior to the arrival of the order for the off state of the regulation signal;

memorization means accumulating at each cycle a value proportional to the duration between a signal from the detection means and the set signal associated with the regulation signal of the following cycle; and

inhibition means for inhibiting the set input of the flip-flop when the memorization means has accumulated a signal higher than a predetermined threshold;

wherein the means for detecting includes a second flip-flop, a third flip-flop and an AND gate, the second flip-flop receiving at its reset input the starting output of the regulation signal, the set input of the second flip-flop receiving the output of the AND gate and the output of the second flip-flop controlling the memorization means; the third flip-flop having its set input connected to the reset input of the second flip-flop, the reset input of the third flip-flop connected to the reset regulation signal and the output of the third flip-flop connected to a first input of the AND gate; the second input of the AND gate being connected to the output of the first protection circuit.


2. A device for protection according to claim 1, wherein the memorization means comprise a capacitor permanently discharged by a discharging means and temporarily charged by a charging means only when the detection means supplies a signal.

3. A device for protection according to claim 2, wherein the charge and discharge means are current supplies and the charge current supply is connected to the capacitor through a controlled switch actuated by the output of the second flip-flop of the detection means.

4. A device for protection according to claim 1, wherein the inhibition means comprise a comparator comparing the signal accumulated by the memorization means with a reference value, the output signal of this comparator inhibiting the set input of the first flip-flop when the memorized signal becomes higher than a reference value.

5. A device for protection according to claim 4, wherein the output of said comparator is connected to the set input of a fourth flip-flop of which the output is connected to the set input of the first flip-flop through an AND gate of which the other input receives the sginal for triggering the regulation signal.

6. A device for protection according to claim 5, wherein the AND gate connected to the validation input of the first flip-flop receives other inhibition signals issuing from other switch mode power circuits, such as automatic starting control circuits.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention concerns stabilized power supplies known as "switch mode power supplies".

A switch mode supply functions in the following manner: a primary transformer winding receives a current that is, for example, issuing from a rectifying bridge receiving power from the alternating power mains. The current in the transformer is chopped by a switch (for example a power transistor) placed in series with the primary winding.

A control circuit of the transistor establishes periodic square pulses to turn on the transistor. During the square pulse period current passage is authorized; outside of this square pulse period current passage is prohibited.

On one (or several) secondary winding(s) of the transformer, an alternating voltage is thus received. This voltage is rectified and filtered in order to produce a direct voltage that is the output direct voltage of the switch mode supply.

In order to stabilize the value of this direct voltage, the duty cycle of the switch is modified, i.e. the ratio between the conduction duration and the blocking duration in a chopped period.

FIG. 1 represents by way of example a switch mode power structure manufactured by the applicant in which two integrated circuits are used. One of the circuits, CI1, acts to control the base of a power switching transistor Tp for applying thereto periodic control signals for putting under conduction and blocking control. This base control circuit CI1 is placed on the side of the primary winding EP of the transformer TA for reasons which will become apparent from the description given herein-below. The other integrated circuit, regulation circuit CI2, is on the contrary placed on the side of the secondary winding ES1 and is used to examine the output voltage Vs of the power supply in order to produce regulation signals that it transmits to the first integrated circuit through a small transformer TX. The first integrated circuit CI1 uses these regulation signals to modify the duty cycle of conduction of the switching transistor Tp and thus of adjusting the output voltage Vs of the power supply.

FIG. 1 shows the line of the public electric distribution mains under reference 10 (local supply circuit or mains at 110 or 220 volts, 50 or 60 hertz). This line is connected through a filter 12 to the input of a rectifying bridge 14, the output of which is connected on the one hand to a primary electric mass, represented throughout by a black triangle pointing downwards, and on the other hand to one end of the primary winding EP of the supply transformer TA.

A filtering capacitor 16 is placed in parallel on the outputs of the rectifying bridge 14. The other end of the primary winding is connected to the collector of the switching transistor Tp, the emitter of which is connected to the primary mass through a small current measuring resistance 18.

The transformer is provided with several secondary windings that are preferably galvanically insulated from the mains and connected for example to a secondary electric mass galvanically insulated from the primary mass.

In the present description, each of the secondary windings has one end connected to the secondary mass. The other end supplies a respective low-pass filtering capacitor through a respective rectifying diode.

Reference in the following description will be made to a single secondary winding ES1, connected by a diode 20 to a capacitor 22. The direct output voltage of the switch mode supply is the voltage Vs at the terminals of the capacitor 22; but it is well understood that other direct output voltages can be obtained at the terminals of the other filtering capacitors connected to the secondary windings. These output voltages constitute stabilized power supplies for utilization circuits (not represented). By way of example, a secondary winding ES2 supplies a stabilized power voltage of several volts for the regulation integrated circuit CI2 to which reference was made herein-above. It is thus checked that the circuit is not powered and therefore cannot supply signals as long as the switching does not function.

The same is true a priori for the base control integrated circuit CI1 of the power transistor Tp, which circuit is powered by a stabilized voltage supplied from a secondary winding ES3, from a diode 24 and from a capacitor 26 (it will be noted that this winding, although being a secondary winding is connected to the primary ground and not to the secondary mass, this for the very simple reason that the integrated circuit CI1 is necessarily galvanically connected to the primary).

However, as it is necessary to ensure starting of the chopped power supply, it has been foreseen that the power terminal 28 of the integrated circuit CI1 is also directly connected to the mains through a high resistance 30 and a diode 32; this is possible since the integrated circuit CI1 is connected to the primary ground; it is not possible for the circuit CI2 which must remain galvanically insulated from the mains. Once the switch mode power supply functions normally, the stabilized direct voltage issuing from the winding ES3 and from the diode 24 has priority over the voltage issuing from the mains and from the diode 32; this diode 32 is blocked and the direct power supply through the mains no longer intervenes after the initial starting phase.

The role of the integrated circuits CI1 and CI2 will now be defined.

The regulation circuit CI2 receives from a divider bridge 34, placed at the terminals of the capacitor 22, i.e. at the output of the stabilized power supply, data as to the value of the voltage to be stabilized Vs.

This data is compared with a desired value and applied to a pulse width modulator that establishes periodic square pulses having variable width in function of the value of the output voltage Vs; the lower is Vs the larger will be the width of the square pulses.

The square pulses are established at the switching frequency of the switch mode supply. This frequency is thus established on the side of the secondary of the circuit; it is generated either inside the circuit CI2, or outside in a circuit (not shown) in the form of a saw-tooth shaped voltage at the selected switching frequency. This saw-tooth voltage is used in a manner known per se to perform the width modulation.

The variable width square pulses, at the switching frequency, are applied to a primary winding 36 of a small transformer TX, the secondary winding, 38, of which is galvanically insulated from the primary, supplies positive and negative pulses to the rising and descending edges, respectively of the variable width square pulses.

It is these position and frequency pulses determined by the regulation circuit CI2, which constitute regulation signals applied to an input 40 of the base control circuit CI1.

The transformer TX is constituted by several coil turns wound on a ferrite rod, the turns of the primary and the turns of the secondary being sufficiently spaced apart from one another to respect the galvanic insulation standards between primary circuits and secondary circuits of the switch mode supply.

The base control integrated circuit CI1 comprises various inputs among which have been mentioned herein-above a power input 28 and a regulation signal input 40; a current measuring input 44 connected to the current measuring resistor 18; and an inhibition input allowing to check the magnetization state of a transformer. Furthermore, inputs can be provided to connect the elements (resistors, capacitors) that should form part of the integrated circuit itself but which for technological reasons (of bulk) or for practical reasons (possibilities of adjustment by the user) are externally mounted.

The integrated circuit CI1 furthermore comprises an output 46 which is intended to be connected by a direct galvanic connection to the base of the power transistor Tp. This output supplies square pulses for bringing the transistor Tp to the on or off state.

FIG. 2 represents partially the general structure of the integrated circuit CI1.

The output 46 of the circuit, intended for the base control of the transistor Tp, is the output of a push-pull amplification stage designated by the reference 48, this stage preferably comprising two separated amplifiers one of which receives square pulses which are inverted and delayed by several microseconds for to producing to the on state. Such amplifiers are well known.

The signals for switching to the on stae are issued from a logic flip-flop 50 having a set input 52 and a reset input 54. The set input triggers the on state of the power transistor. The reset input triggers the off state.

The set input 52(S) receives the pulses that pass through an AND gate 58, so that the triggering of the on state only occurs when several conditions are simultaneously satisfied; if a single condition is not satisfied, this is sufficient to inhibit the triggering of the on state.

The reset input 54(R) receives the pulses which pass through an OR gate 60, so that the interruption of the on state (after triggering of the on state) occurs once a halt signal is present on one of the inputs of this gate.

On the diagram of FIG. 2, the AND gate 58 has three inputs. One of these inputs receives periodic pulses issuing from an output 62 of a high frequency oscillator 64; the other inputs act to inhibit the transmission of these pulses.

The oscillator defines the switching period of the power supply (20 kilohertz for example). In normal operating state the oscillator 64 is synchronized by the regulation signals. In starting state it is self-oscillating at a free frequency defined by the values of a resistor Ro and of a capacitor Co outside the integrated circuit CI1 and respectively connected to an access terminal 66 and an access terminal 68. The free frequency Fo is as a rule slightly lower than the normal switching frequency.

The oscillator 64 is a relaxation oscillator that produces on an output 70 a saw-tooth, the reset to zero of which is set by the appearance of a positive pulse arriving at the terminal 40. This is the reason why the oscillator 64 is represented with an input connected to an output 72 of a separation and shaping circuit 74 that receives the regulation signals from the terminal 40 and shapes them by separating the positive pulses from the negative pulses. The shaping circuit 74 has two outputs: 72 for the positive pulses, 76 for the negative pulses (the notation of positive pulse and negative pulse will be retained in order to distinguish the triggering pulses for the on state and the triggering pulses for the off state even if the shaping circuit establishes pulses of a single sign on its two outputs 72 and 76).

The oscillator 64 has two outputs; an output 70 supplying a saw-tooth signal and an output 62 supplying a short pulse when the saw-tooth is reset to zero.

A pulse width modulator 78 is connected on the one hand to the output 70 of the oscillator and on the other hand to an adjustable reference voltage through a resistor R1 outside the integrated circuit and connected to an access terminal 80 to the circuit. The modulator 78 supplies periodic square pulses synchronized with the oscillator signals, these square pulses defining a maximal duration of the on state Tmax beyond which the off state of the power transistor must be triggered in any case as a matter of security. These square pulses of modulator 78 are applied to an input of the OR gate 60. The duration Tmax is adjustable through the external resistor R1.

The elements that have been described herein-above ensure the essential of the operating at normal condition of the integrated circuit CI1. The following elements are more specifically provided for controlling the anomalous operating or the starting of the power supply.

A very low frequency oscillator 82 is connected to an external capacitor C2 through an access terminal 86. This external capacitor adjusts the very low oscillation frequency. The frequency can be 1 hertz, for example.

The oscillator 82 is a relaxation oscillator supplying a saw-tooth signal which is applied on the one hand to a threshold comparator 88 which establishes periodic square pulses which are synchronized on the saw-tooth at a low frequency of the oscillator. These square pulses have a brief duration compared to the saw-tooth period. This duration is fixed by the threshold of the comparator 88. It can be for example of 10% of the period. It must be long with respect to the free oscillation period of the high frequency oscillator 64 so that a burst of numerous pulses of the high frequency oscillator can be emitted and utilized during this 10% of the period at very low frequency. This burst defines an attempt at starting during the first part of a starting cycle. It is followed by a pause during the remainder of the period, i.e. during the remaining 90% of the period.

The oscillator 82 only functions for the starting. It is inhibited when the regulation signals appear on the terminal 40 and indicate that the switch mode supply is functioning. This is the reason why an inhibition control of this oscillator has been represented, connected to the output 72 of the shaping circuit 74 through a flip-flop 89 which changes its condition under the effect of the pulses appearing at the output 72. It is returned to its initial condition by the output 62 of the oscillator 64 when there are no more pulses on the output 71.

The saw-tooth signals of the oscillator at very low frequency are furthermore transmitted to a circuit 90 for producing a variable threshold whose function is to establish a threshold signal (current or voltage) having a first value Vs1 in normal operating condition, and a cyclically variable threshold between the first value and a second value at starting condition.

The threshold signal established by the circuit 90 is applied to an input of a comparator 92, the other input of which is connected to the terminal 44 already mentioned, in order to receive on this input a signal that is representative of the amplitude of the current flowing through the power switching device. The output of the comparator 92 is applied to an input of the OR gate 60. It thus triggers the off state of the power transistor Tp, after an on state firing, the off state occuring, when exceeding the threshold (fixed or variable) defined by the circuit 90 has been detected.

Another threshold comparator 94 has an input connected to the current measuring terminal 44 while another input receives a signal representing a third threshold value Vs3. The third value Vs3 corresponds to a current in the switch which is higher than the first value vs1 defined by the circuit 90. The output of the comparator 94 is connected through a latch 96 to an input of the AND gate 58 whereby if the current in the power switch exceeds the third threshold value Vs3, an interruption of the on state of the transistor Tp is not triggered (this interruption is triggered by the comparator 92) but an inhibition of any firing of the transistor. This inhibition lasts until the flip-flop 96 is reset to its initial state corresponding to a normal operating.

As a rule, this return will only occur when the integrated circuit CI1 will have ceased to be normally supplied with power and will be again set under voltage. For example, the return of the latch 96 occurs through a hysteresis threshold comparator 98 which compares one fraction of the power supply voltage Vcc of the circuit (drawn off from the terminal 28) with a reference value and which resets the latch during the first passage of Vcc above this reference after a drop of Vcc below another reference value that is lower than the first one (hysteresis).

Moreover, it can be specified that the output of the flip-flop 89 (which detects the presence of regulation signals on the terminal 40 thus the normal operating of the power supply) is connected to an input of an OR gate 100 which receives on another input the output of the comparator 88 so that the output of the comparator 88 ceases to inhibit the firing of the transistor Tp (inhibition during 90% of the very low frequency cycles) once the operating of the power circuit becomes normal.

OBJECT OF THE INVENTION

Therefore, in the device previously manufactured by the applicant and described in detail herein-above, particular procedures for the starting phases and particular protective procedures in the case of functioning incidents are foreseen.

The present invention aims at further improving the operating safety by detecting operating deficiencies over a longer period of time than was the case with circuits of the prior art. Although the invention presents a novel and distinct contribution with respect to the process of the prior art, the prior device has been described in full detail herein-above in order to render apparent the numerous restrictions which are imposed during production of a novel safety device which must take into account all the possible types of operating foreseen in an already existing circuit without introducing deficiencies or blockages in the normal operating of the circuit in its differnt modes. Consequently, any novel contribution to a complex structure such as that described herein-above requires numerous selections and very numerous attempts between various solutions that could appear a priori as simple must be carried out.

SUMMARY OF THE INVENTION

Therefore, the present invention provides a device for protection against extended overloading in switch mode power supplies comprising a main switch controlled by output signals from a flip-flop of which the inputs for setting to 1 and for resetting to zero receive regulation control signals, a first protection circuit supplying on the input for resetting to zero signals which have priority with respect to the regulation signals when the current in the main switch exceeds a predetermined threshold, further comprising a second protection circuit itself comprising:

means for detecting cycles for which the first protection circuit operates and interrupts the on state of the main switch prior to the arrival of the switching off order of the regulation signal;

memorization means accumulating at each cycle a value proportional to the duration between a signal of the detection means and the setting to 1 signal associated to the regulation signal of the following cycle; and

inhibition means for inhibiting the set input of the flip-flop when the memorization means have accumulated a signal higher than a predetermined threshold.

According to one embodiment of the present invention, the detection means comprise a second flip-flop, a third flip-flop and an AND gate:

the second flip-flop receiving at its reset input the output for starting the regulation, the set input of this flip-flop receiving the output of the AND gate and the output of this flip-flop controlling the memorization means;

the third flip-flop having its set input connected to the reset input of the second flip-flop, its reset input connected to the reset signal of the regulation signal, and its output connected to a first input of the AND gate,

the second input of the AND gate being connected to the output of the first protection circuit.

According to one embodiment of the present invention, the memorization means comprise a capacitor permanently discharged by discharging means and temporarily charged by charging means only when the detection circuit supplies a signal.

According to another embodiment of the invention, the inhibition means comprise a comparator comparing the signal accumulated by the memorization means with a reference value, the output signal of this comparator inhibiting the set input of the flip-flop when the memorized signal becomes higher than a reference value.

BRIEF DESCRIPTION OF THE DRAWING

These objects, features and advantages and others of the present invention will become apparent from the following embodiment given by way of non-limitative illustration with reference to the appended drawing in which:

FIGS. 1 and 2 illustrate a switch mode power supply according to the prior art and have been described herein-above;

FIG. 3 is a simplified representation of a protection circuit against the overloading of a switch mode power supply according to the prior art;

FIG. 4 illustrates the protection circuit against overloads of long duration according to the present invention for switch mode power supplies; and

FIGS. 5-a to to 5-b are time charts intended to illustrates the functioning of the circuits represented in FIGS. 3 and 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 once again represents in a simplified manner the essential components of the circuit represented in FIG. 2 constituting a protection circuit against the excess currents in the main transistor Tp. The on state in the transistor Tp is normally controlled by a signal available on a terminal 40, resulting from a pulse width modulation circuit which controls a flip-flop 50 through a shaping circuit 74. The flip-flop 50 energizes the base of the power transistor Tp through a preamplification circuit (driver) 48 and an access terminal 46. When the current in the power transistor exceeds a given threshold, the voltage at the terminals of a resistor 18 available at the terminal 44 is compared with a threshold voltage Vs by a comparator 92 and, should this voltage exceed the threshold, the reset input R of the flip-flop 50 is energized through an OR gate 60, the other input of which receives an output signal from the shaping circuit 74.

This protection device effectively protects the switch Tp against a current overloading but does not always allow good protection of the power supply, for example in the case of long duration overloading. In fact, there is no protection against excessive heating of the transformer TA or of the rectifying diodes 20 (cf. FIG. 1) or of other components of the circuit connected to the secondary of the main transformer and it is generally necessary to over-size these components in order to take into account long duration overloadings which could occur as a result, for example, of short-circuiting on the secondary winding.

The invention which will be described herein-below with respect to FIGS. 4 and 5 concerns a device which, added to the conventional current limitation circuit described herein-above, provokes the total and definitive shut down of the power supply in the case of long duration functioning of the current limitation system. Expensive over-sizing of certain components is thus avoided and the operating safety of the power supply is as a whole increased.

The restarting of the power supply can be obtained by the momentary setting out of voltage of the system or at least of the device concerned.

As represented on FIG. 4, the present invention comprises a circuit 100 for detecting the operating of an overload circuit, comprising flip-flops FF2 and FF3 and an AND gate 101, and a circuit 102 for memorization and inhibition of the switch mode power supply. The circuit 102 operates the above described base current control flip-flop 50 through an AND gate 58.

The memorization and inhibition circuit 102 comprises a capacitor 103, a discharge system constituted by a current supply 104 functioning permanently, a system for charging this capacitor constituted by a current supply 105 controlled in all or nothing by a switch 107 receiving the output of the detection circuit 100. When the detection circuit 100 indicates that the current limitation circuit in the power switch Tp does not function, only the discharge system 104 functions and the capacitor 103 remains discharged. When the current limitation system 100 is energized, the charge system (current supply 105) is activated. The ratio between the discharge current and the charge current is selected so that overall the capacitor 103 is charged. When the voltage at the terminals of the capacitor reaches a determined value, fixed by a comparator 106, a flip-flop FF4 is triggered which definitively inhibits the on state of the switch Tp.

In the circuit 100 for detecting the functioning of the current limitation circuit, the flip-flop FF2 has its reset input R2 connected to the output 72 of the form shaping circuit 74, its set input S2 connected to the output of the AND gate 101 and its output Q2 connected to the control terminal of the switch 107 of the circuit 102. The second flip-flop FF3 has its set input S3 connected to the output 72 of the shaping circuit 74, its reset input R3 connected to the output 76 of this shaping circuit and its output Q3 connected to a first input of the AND gate 101 of which the other input is connected to the output of the comparator 92 detecting the excess currents in the power transistor Tp.

FIG. 5 indicates a time chart of the signals appearing in different points of the circuit in four particular operating cases. In FIG. 5

the line a indicates the signals present at the terminal 40 or more exactly the control signals from which result the signals at the terminal 40 following the action of the insulating transformer TX (cf. FIG. 1). Those signals correspond to more or less long square pulses according to the error signal detected;

the line b indicates the signal present at the output 76 of the shaping circuit 74, normally provoking the setting to 1 of the flip-flop 50;

the line c indicates the signal at the output 76 of the shaping circuit 74, normally controlling the reset of the flip-flop 50;

the line d indicates the signal at the output Q2 of the flip-flop FF2 controlling the switch 107;

the line e indicates the signal Q3 at the output of the flip-flop FF3;

the line f indicates the signal at the input R of the flip-flop 50, i.e. the signal at the output of the OR gate 60. This signal corresponds to the rising edge of the pulse at the output 76 of the shaping circuit 74 or at the output of the comparator 92;

the line g indicates the current in the power transistor that corresponds to the signal present on the input 44 of the comparator 92;

the line h indicates the signal at the output of the comparator.

The operating of this circuit in four possible functioning modes will now be studied.

1. Normal operating without overloading

No signal is supplied to the output of the comparator 92 and it is the outputs 72 and 76 (signals of lines b and c) that control the inputs S and R of the flip-flop 50. The circuit 102 not receiving any output signal from the circuit 100 supplies to the output Q4 of the flip-flop FF4 a high level signal and the AND gate 58 is validated thereby allowing the output signal 72 of the shaping circuit 74 to reach the input S of the flip-flop 50.

2. Functioning in lower overloading limit

As shown by line g of FIG. 5, it concerns the case where the reset pulse of the flip-flop 50 tends to bring the switch Tp at the off state prior to an overloading detection (current in Tp higher than I Max) occuring, but where an overloading occurs between the off state order and the effective off state of the power transistor. This delay is due to the blocking period or storing time ts of the switch which is not nil in particular in the case where a high voltage bipolar transistor is utilized. The current limitation comparator 92 is thus energized. However, the output signal of the comparator 92 does not reach the flip-flop FF2 to supply an output signal Q2 since the flip-flop FF3 has been previously reset by the signal 76 and blocks the AND gate 101. the flip-flop FF2 thus remains at zero and as in the preceding case, the circuit 102 is not energized and the regulation circuit continues to operate normally. It would in fact be inconvenient to shut down the operating of the chopping power supply in this particular case.

3. Operating in moderate overloading

As in the previous case, it is the output signal 72 of the shaping circuit 74 that provokes the bringing to the on state of the power transistor but, as shown by line g, the overload level of the power transistor Tp is reached prior to the normal off state signal of the transistor (line c) occuring. In this case, the comparator 92 supplies a signal which is transmitted through AND gate 101 enabled by the flip-flop FF3 to the flip-flop Q2 which is set to 1. The switch 107 of the memorization and inhibition circuit 102 is thus closed and the charge process of the capacitor 103 begins.

It will be noted that the signal Q2 (line d) remains at high level until the triggering pulse of the following cycle (bringing of the output 72 at high level). Therefore, the earlier overloading arrives in the cycle, the more the signal Q2 is present during a long period. After several functioning cycles, the voltage accumulated on the capacitor 103 will be higher than the reference voltage VRef applied to the second terminal of the comparator 106. Subsequently, the flip-flop FF4 supplies a signal at low level to its output Q4 and the AND gate 58 invalidates the input S of the flip-flop 50. This occurs only if the overloading lasts over a certain number of cycles. Thus, the functioning of the switch mode power supply is definitively brought to the off state indicating an operating failure of the device, for example a short-circuiting of a secondary winding of the transformer TA (cf. FIG. 1). To start up again the switch mode power supply, it is necessary to apply a new signal to the input R4 of the flip-flop FF4. This input can for example be connected to an initialization device when the whole of the switch mode power supply is powered.

4. Operating under strong overloading

This operating mode is illustrated on the right side of FIG. 5. It is as a whole identical to the case of a moderate overloading but it has been represented only to show the elongation of the pulses Q2 when the overloading occurs very early in an operating cycle of the switch mode power supply.

The various advantages of the present invention thus become apparent. On the one hand; the operating delay time is easily programmable by means of a single component, for example the value of the capacity of the capacitor 103. On the other hand, automatically, due to the elongation of the pulse Q2 when the overloading occurs early in a cycle, the action delay is modulated in function of the intensity of the overloading. Therefore, the greater is the overloading, the shorter is the operating delay time.

Another advantage lies in the perfect simultaneity of the triggering of the timing of the device according to the invention and of the operating of the conventional limitation of the current as described in the description of the prior art. This results in very good operating security. The risk of spurious triggering of the device close to the lower current limit is thus prevented.

On the other hand, as has been seen, the device according to the invention operates well with a power switch constituted by a bipolar transistor in which the storage time is relatively long, but this circuit is perfectly adaptable to a switch of which the off state delay tends towards zero such as a MOS power transistor.

Similarly, accordng to another advantage of the invention, this circuit is perfectly compatible with the other protection and starting assistance circuits which utilized the circuits according to the prior art. Indeed, it will be noted that the components of the circuit according to the invention are perfectly compatible with the components of the current limitation circuit described herein-above. Furthermore, the AND gate 58 that has the circuit at the off state when it is not operating bears the same reference as the AND gate 58 described in relation with FIG. 2. In fact, it can be the same gate comprising simply a supplementary input. Herein lies another advantage of the invention, i.e. it is perfectly compatible with the automatic starting circuit described in relation with FIGS. 1 and 2. In this automatic starting mode, which may be called burst mode, it is also desired to be able to detect and stop the power supply in the case of overloading. However, as mentioned herein-above in the initial burst method, the circuit operates only with a duty cycle of about 10%. In this case, the capacitor 103 risks to be insufficiently charged during this brief action period and to discharge during the 90% of non-operating. To overcome this, it is foreseen according to the present invention to inhibit the discharging of the capacitor 103 by providing a controlled switch (not represented) in series with the discharge current supply 104 and energized by a signal indicative of the fact that operating is taking place in the burst mode. Therefore, in the case of overloading in the burst method, the capacitor is charged a little at each burst and retains its voltage between the bursts. It is therefore possible to reach the voltage VRef after a certain number of burst.

 

TBA 2800
Infrared Preamplifier IC

Bipolar integrated circuit, intended as a receiver preamplifier for the MAA 2000 Central Control Unit or the infrared remotecontrol systems designed with the SAA 125O/SAA 1251 or SAA 1350/SAA 1351 integrated circuits of ITT. The TBA 2800 preamplifier IC contains four main parts: the gain-controlled amplifier I, the amplifier II, the pulse-separating amplifier Ill, and the inverter IV. as shown in Fig. 1. The ampli fier I has a wide dynamic range and thus ensures interference free operation, also at bright ambient light, XI-Hz-modulated light originating from fluorescent lamps, or at intensive infrared light, e. g. produced by infrared sound transmission. It is also possible, to approach almost directly the remote-control transmitter to the receiver without producing misfunction by overdriving the receiver. The amplifier II further amplifies the signal, and amplifier Ill separates the pulse-shaped intelligence signal from noise and other unwanted parts. The inverter IV provided additionally inverts the output signal available at pin 7 as negative pulse, and thus delivers positiie output pulses at pin 8. If an additional resistor is inserted between pin 6 and GND. the noise-immunity is increased, but the input sensitivity decreased. Pin 10 serves as test pin and must not be connected. The capacitor connected from pin 2 to ground influences the automatic gain control of amplifier I contained in the TBA 2800. A capacitance of less than 1 PF will cause misfunction in the distance range of 0.2 m to 2 m. Fig. 3 shows the dependence of the transmission range on the capacitor at pin 2. Due to tolerances of the TBA 2800 itself, the transmitter diodes’ efficiency and the receiver diode’s sensitivity. the curves of Fig. 3 must be considered with a tolerance of about f 50%. The curves have been established by simulation of the distance between transmitter and receiver by means of infrared filter glass with specified attenuation inserted between transmitter and receiver.

 

 

 

 

PHILIPS  TDA7056A 3 W BTL mono audio output amplifier with DC volume control.

GENERAL DESCRIPTION
The TDA7056A is a mono BTL output amplifier with DC volume control. It is designed for use in TV and monitors, but also suitable for battery-fed portable recorders and radios.

Missing Current Limiter (MCL)
A MCL protection circuits is built-in. The MCL circuit is activated when the difference in current between the output terminal of each amplifier exceeds 100 mA (typical 300 mA). This level of 100 mA allows for headphone applications (single-ended).

FEATURES
• DC volume control
• Few external components
• Mute mode
• Thermal protection
• Short-circuit proof
• No switch-on and off clicks
• Good overall stability
• Low power consumption
• Low HF radiation
• ESD protected on all pins.


FUNCTIONAL DESCRIPTION
The TDA7056A is a mono BTL output amplifier with DC volume control, designed for use in TV and monitor but also suitable for battery-fed portable recorders and radios. In conventional DC volume circuits the control or input stage is AC coupled to the output stage via external capacitor to keep the offset voltage low. In the TDA7056A the DC volume stage is integrated into the input stage so that coupling capacitors are not required and a low offset voltage is maintained. At the same time the minimum supply voltage remains low.

The BTL principle offers the following advantages:
• lower peak value of the supply current
• the frequency of the ripple on the supply voltage is twicethe signal frequency  

Thus, a reduced power supply and smaller capacitors can be used which results in cost savings. For portable applications there is a trend to decrease the supply voltage, resulting in a reduction of output power at conventional output stages. Using the BTL principle increases the output power. The maximum gain of the amplifier is fixed at 35.5 dB. The DC volume control stage has a logarithmic control characteristic. The total gain can be controlled from 35.5 dB to −44 dB. If the DC volume control voltage is below 0.3 V, the device switches to the mute mode. The amplifier is short-circuit proof to ground, VP and across the load. A thermal protection circuit is also implemented. If the crystal temperature rises above +150 °C the gain will be reduced, thereby reducing the output power. Special attention is given to switch-on and off clicks, low HF radiation and a good overall stability.




PHILIPS  TDA4661 Baseband delay line

GENERAL DESCRIPTION
The TDA4661 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders with colour-difference signal outputs ±(R−Y) and ±(B−Y).

FEATURES
• Two comb filters, using the switched-capacitor technique, for one line delay time (64 μs)
• Adjustment-free application
• No crosstalk between SECAM colour carriers (diaphoty)
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals (±(R−Y) and ±(B−Y))
• VCO without external components
• 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 μs line)
• Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour.


PHILIPS  TDA3653B TDA3653C Vertical deflection and guard circuit (90 ̊)

GENERAL DESCRIPTION
The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to 1.5 A peak-to-peak.

Features
• Driver
• Output stage
• Thermal protection and output stage protection
• Flyback generator
• Voltage stabilizer
• Guard circuit


FUNCTIONAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.

Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.

Flyback generator
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.

Guard circuit
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.

 

PHILIPS  TDA8361 TDA8360 Integrated PAL and PAL/NTSC TV processor
PHILIPS TDA8362 (TDA8361/60) MAIN CHARACTERISTICS
The TDA8362 television processor microcircuit contains an intermediate frequency (IF) signal processing circuit, a multi-standard demodulator of a frequency-modulated sound signal, automatically tuned notch and band-pass filters in the video signal processing channel, a luminance signal delay line, a color signal decoder in the PAL and NTSC system with automatic detection systems, TV / AV input selector, RGB signal switching scheme, horizontal and vertical scanning synchronization circuits.
Variant TDA8362A also contains automatic white balance circuits. Thus, the TDA8362/60 includes all the basic low signal circuits needed to build a color television receiver.
The minimum number of elements connected to external circuits and only one element requiring adjustment (reference circuit of the IF signal demodulator) creates an exceptional usability of the TDA8362. As a result, the TDA8362 processor has become one of the most widely used chips in modern television technology.
The main characteristics of TDA8362 are given in table. 1.

Parameter	Value
Supply voltage	8 ± 0.8
Current consumption, mA	80
Power consumption	0.7
Sensitivity of the IFI, μV	70
Sensitivity UPCHZ, mV	1
Sound signal from an external input, mVeff	350
Video signal from external input, Vp_p	1
Signals at the inputs in RGB, Bn n	0.7
Demodulated PTsTS, Vp-p	2,4
Tuner AGC control current, mA	0 ... 5
The range of voltage changes AFCG, V	6
Audio output signal (vyv. 50), mV	700
Output signals in RGB, Bn_n	4
Horizontal line output current, mA	10
Framing output current, mA	1
Control voltage range, V	0 ... 5

Table 1. Key Features of the TDA8362 Processor

The construction, pinout and basic parameters of all modifications of the TDA8362 microcircuits (with the exception of the TDA8362A variant) are the same. Features of their application will be discussed below.
 

DESCRIPTION OF STRUCTURAL SCHEME

Table 2 gives the pin assignment of TDA8362, and also shows the difference in pinout of the TDA8362 and TDA8362A options.
The latter contains a circuit for automatic white balance, the measuring signal at the input of which comes from pin 14 of TDA8362.

TDA8362	TDA8362A	Pin assignment
1	1	Pre-emphasis correction of sound signal and switching to positive modulation
2	2	IF signal demodulator reference circuit
3	3	IF signal demodulator reference circuit
4	4	Video identification circuit output, sound switch input
5	5	IF signal input and volume control
6	6	Audio input from external connectors
7	7	PCTS output
8	8	Decoupling capacitor of the power supply circuit of the digital part
9	41	Earth 1 (common)
10	10	Power input
eleven	eleven	Earth 2 (common)
12	12	Decoupling capacitor filter settings
thirteen	thirteen	Internal video input
14	14	RF correction circuit adjustment input (sharpness)
fifteen	fifteen	External video input
16	16	Chroma input
17	17	Brightness adjustment
18	18	Exit to
19	19	Output G
20	20	Output R
21	21	RGB switch and blanking output
22	22	Signal output R (from external sources)
23	23	Signal output G (from external sources)
24	24	Signal output B (from external sources)
25	25	Contrast adjustment
26	26	Saturation Adjustment
27	27	Color tone adjustment (or color signal output)
28	28	CV input BY (from delay line)
29th	29th	RRS input RY (from delay line)
thirty	thirty	RCS RY output (to delay line)
31	31	TsRS BY output (to the delay line)
32	32	4.43 MHz reference signal output on TDA8395
33	33	Phase detector filter
34	34	Conclusion connection of a quartz resonator of 3.58 MHz
35	35	4.43 MHz quartz resonator connection terminal
36	36	Power output to trigger horizontal scanning
37	37	Horizontal scan trigger output
38	38	Horizontal Flyback Pulse Input / Gating Pulse Output (SSC)
39	39	Phase Detector Filter 2
40	40	Phase Detector Filter 1
41	42	Frame Reverse Pulse Input
42	43	Conclusion conclusion of an RC chain of ZG frame scan
43	44	Firing trigger pulses output
44	9	AFC output
45	45	IF signal input 1
46	46	IF signal input 2
47	47	AGC circuit output
48	48	A conclusion of the connection of the decoupling capacitor of the AGC circuit
49	49	Tuner AGC adjustment input
fifty	fifty	Sound output
51	51	Conclusion connection output decoupling capacitor demodulator sound
52	52	Decoupling capacitor of the power control circuit

Table 2. TDA8362 Processor Pin Assignment

IF SIGNAL PROCESSING CIRCUIT
The IF image signal amplifier (IFI) is a three-stage differential amplifier with an adjustable gain and a symmetrical differential input (vyv. 45 and 46 TDA8362). The gain variation range is at least 64 dB. The sensitivity of the IFI (70 μV) is comparable to the parameters of modern specialized TDA8362 IFI.
Maximum input signal up to 100 mV eff. The IF signal is demodulated using a reference carrier frequency generated by passive regeneration of the carrier image. The reference circuit of the demodulator is connected to pin 2 and 3 of the TDA8362. It is the only item that needs to be configured. The demodulator provides the ability to process IF signals with both negative and positive modulation. The automatic frequency control circuit (AFC) generates a signal at pin 44 of TDA8362, which provides tuning of the tuner local oscillator frequency with an error of no more than 50 kHz.
The circuit uses the same reference signal as for the demodulator.
The built-in sampling-storage circuit ensures the protection of the AFC circuit from the penetration of a video signal. A storage capacitor is built into the TDA8362. The steepness of the characteristics of the AFC circuit (33 mV / kHz) directly depends on the quality factor of the reference circuit. To reduce the steepness, a resistor is connected to pin 44 of the TDA8362. The output voltage range is 6 V (at a nominal frequency of 3.5 V). The characteristic of the AFC for the TDA8362-N5 modification is optimized for the European IF standard. The automatic gain control (AGC) circuit generates the control voltage of the amplifier and the tuner (vv. 47 TDA8362), ensuring a constant amplitude of the signals at the input of the amplifier and at the output of the video amplifier.
To exclude the influence of the AGC circuit on the tuner at low levels of the input signal, an AGC response delay is introduced. The delay value is regulated by applying a control voltage to pin 49 of the TDA8362. The voltage variation range is 0.5 ... 4.5 V. The minimum and maximum signal levels at pin 49, at which the tuner AGC is triggered, are 0.2 mV eff and 150 mV eff, respectively.
The AGC detector monitors the amplitude of the clock pulses with negative modulation of the IF signal and white peaks with positive modulation. To ensure noise immunity, the gating of the detector is used. Gating is disabled for the duration of the reverse frame scan. This allows you to avoid changing the amplitude of the video signal in the playback mode from the VCR due to phase shifts that occur during the switching of video heads. A capacitor (usually 2.2 μF) is connected to pin 48 of the TDA8362, which sets the time constant of the AGC circuit.

The external connection of this capacitor provides the flexibility of using the TDA8362. The permissible leakage current of the capacitor is 10 μA for negative and 200 nA for positive modulation. An increase in leakage current degrades the characteristics of the AGC circuit and leads to a change in the amplitude of the video signal during the field. The voltage at the output of the AGC circuit (vyv. 47) is at maximum gain (U pit +1) V and at minimum gain (saturation voltage) - 0.3 V.
Switching the demodulator and the AGC circuit to the IF signal processing mode with positive modulation is carried out by supplying voltage (U pit -1) V to pin 1 of TDA8362. The video signal identification circuit works independently of the synchronization circuit, which ensures that the setting is saved to the received television channel during translation TV to monitor mode.
The circuit generates the following signals at the output (pin 4 of TDA8362):

• voltage no more than 0.5 V in the absence of a video signal (in this case, the sound detector is turned off);
• voltage of 6 V when receiving a signal with a frequency of a subcarrier of color of 3.58 MHz;
• voltage of 8 V when receiving a signal with a frequency of a subcarrier of color 4.43 MHz.

In the modification of TDA8362-N5, an identification mode is provided for tuner detuning. To do this, when the signal is weak, the gating of the tuner AGC circuitry for the time of receiving horizontal synchronization pulses is disabled, which prevents erroneous identification of color subcarrier outbreaks by signals. The video amplifier provides amplification of the detected video signal, matching with the load and limiting noise emissions in the video signal.
The signal amplitude at the output (pin 7 of TDA8362) is 2.4 V. The output impedance of the amplifier is not more than 50 Ohms, the load current is not more than 5 mA. The bandwidth of the video amplifier (at the level of -3 dB) is up to 9 MHz, which makes it possible to use TDA8362 in all broadcasting standards. The emission control scheme provides the inversion of white peaks exceeding 4.8 V, noise emissions having a level below 1.4 V (the tops of the clock pulses have a level of 2 V), and their introduction into the video signal at 3.2 V and 2.6 V , respectively. At the same time, the noise emission inversion circuit only works during the reception of a large signal, since with a weak signal it negatively affects the operation of the audio signal processing channel.
In the modification of TDA8362-N4, an ultra-white peaks binding scheme is used in the video signal. The TDA8362-N5 modification does not use a white peak limiting scheme, since when there are a large number of white peaks, inverting and introducing them at 3.2 V results in the image becoming gray.

SOUND PROCESSING CHAIN

The sound signal to the second PC sound extracted from the full television signal is fed to pin 5 of the television processor (TDA8362). To the same output, a control voltage is supplied through the resistor to adjust the volume. The control voltage range is 0 ... 5 V.
The IF signal of the sound is limited and fed to the demodulator, made in the form of a phase locked loop (PLL). The PLL system is automatically tuned to the input frequency and does not require adjustments. The PLL system capture range is 4.2 ... 6.8 MHz.
The preliminary amplifier (PU) provides amplification of the detected sound signal to a level of 350 mV eff. This signal, which is not adjustable in magnitude, is fed to pin 1 of the TDA8362, to which an external capacitor is connected to correct the distortion of the sound signal, and to the switching and volume control circuitry. PU also provides mute when there is no identification of the video signal.
The signal from pin 1 of the TDA8362 is used to output to external connectors (for example, SCART). The sound signal from external connectors is fed to pin 6 of the TDA8362, its magnitude is 350 mV eff. The switching circuit, controlled by the voltage supplied to pin 16 of the TDA8362, provides for the output of pin 50 of the TDA8362 sound output signal, which then goes to the low-frequency amplifier.
The value of the output signal, which is -6 dB from the maximum is 700 mB eff, when adjusting the volume changes in the range of 80 dB. DC voltage at the terminal 50 TDA8362 3.3 V (when turning off the sound 10 ... 50 mB). The TDA8362-N5 modification provides click protection in the speakers when the sound is turned on, while using the previous TDA8362 modifications, a 290 kOhm resistor was needed between pin 1 of the TDA8362 and the +8 B bus to solve this problem.
Switching the TDA8362 to the signal processing mode with positive modulation is carried out by supplying at least 1 (U pit - 1) V to pin 1 of the TDA8362.

SYNCHRONIZATION CHAIN

The selection of clock pulses (SI) from the video signal arriving at vyv.13 or 15 TDA8362 is carried out by a selector containing an amplifier, an amplitude selector and a circuit for the selection of lowercase and frame SI.
Lower case SIs are supplied to the first phase detector (PD1) and a coincidence detector, which identifies the presence of a video signal and controls the synchronization of the master oscillator (ZG) of horizontal scanning. In the absence of synchronization, the voltage at pin 14 of the TDA8362 becomes low, which can be used to identify the presence of a video signal. PD1, together with a low-pass filter (LPF) connected to pin 40 of TDA8362, and a horizontal scan line generator form a PLL that provides frequency and phase adjustment of the pulse pulses to lower case SI parameters.
The time constant ФД1 is automatically switched (by switching internal resistance) according to the signals from the noise detector and from the coincidence detector. With an increase in the noise level in the video signal at pin 13 of TDA8362, the PD1 time constant increases (the output current is 30 μA). In the absence of a video signal, the time constant increases even more (output current 6 μA), which ensures synchronization in the on-screen display (OSD) mode.
When a normal signal is received, as well as when processing a signal fed to pin 15 of the TDA8362, the time constant decreases (output current 180 μA) to expand the capture band and increase the noise immunity of the synchronization circuit.
To ensure quick compensation of the phase error that occurs in the signal from the VCR when switching the video heads, the time constant is further reduced by about 1.5 times for the reverse scan time of the vertical scan (output current 270 μA). Thus, good synchronization circuit characteristics are achieved both in the case of receiving a weak signal and in the case of signal processing from a VCR.
The video signal span on pin 13 of the TDA8362 (including sync pulses) must be at least 2 V when a normal signal is received. Otherwise, the noise detector will switch the time constant at a lower IF signal level (switching occurs at a signal-to-noise ratio of 20 dB), which will lead to a “jitter” phase of the horizontal scanning signal.
To ensure the independence of the image phase from the horizontal frequency (15.625 or 15.734 kHz), the PD1 static characteristic has a very high slope. Horizontal scanning operates at a double horizontal scanning frequency. Its frequency is automatically calibrated using the tuning circuit by comparing it with the frequency of the generator with quartz stabilization of the color decoder. As a result, the frequency of free oscillations of the GB has a deviation of no more than 2% of the central value. At startup, calibration is always performed with 4.43 MHz quartz, unless the 3.58 MHz quartz forced mode is selected.
The second phase detector (FD2) ensures the formation of horizontal line triggering pulses on pin 37 of the TDA8362 and maintaining the phase of these pulses relative to 3G pulses in the capture mode in PD1. PD2 together with the low-pass filter connected to pin 39 of the TDA8362 and the 3G form a PLL. The initial phase of the image is set by changing the external load connected to pin 39 of TDA8362. The shift range is ± 2 μs when the control current changes within ± 6 μA. The horizontal flyback pulses necessary for the operation of PD2 are received at pin 38 of TDA8362.
At the same output, combined strobe pulses are formed, which are necessary for operation of integrated delay line microcircuits (TDA4661 or TDA4665) and SECAM decoder (TDA 8395).
Gating pulses have the following parameters:

• binding voltage during the reverse pulse: 3 ± 0.4 V;
• voltage during the quenching pulse: 2 ± 0.2 V;
• voltage during the color subcarrier flash: 5.3 ± 0.5 V;
• field blanking pulse width: 14 lines;
• flash highlight pulse width: 3.5 ± 0.2 μs.

When using the TDA8362 in question, X-ray protection can be implemented. For this, the external detector must provide switching of a constant voltage (at least 6 V) on pin 39 of TDA8362. In this case, the formation of horizontal line triggering pulses stops, and the voltage at pin 37 of the TDA8362 becomes approximately equal to the supply voltage. If the voltage on pin 39 returns to its normal level, then trigger pulses reappear on pin 37.
Parameters of pulses of start of horizontal scanning:

• lower level of output voltage: 0.3 V;
• maximum level: U pit;
• pulse duty cycle: 2;
• maximum permissible output current: 10 mA.

The launch of the horizontal scanning line is carried out by applying a voltage of 8 V to terminal 36 of the TDA8362 (minimum starting current of 6.5 mA). It should be noted that it is possible to start when the current is 5.5 mA. At the same time, calibration of the ZG is not carried out and its frequency will be higher than the nominal (maximum frequency deviation is 75%).
 In TDA8362-N5, the maximum trigger pulse frequency is limited to 20 kHz. When the voltage on pin 36 of TDA8362 decreases to 5.8, the formation of start pulses immediately stops. If the pre-start mode of the ЗГ is not used, then pin 36 and 10 of the TDA8362 are connected to the 8 V power bus. With separate power supply, the voltage at pin 36 must always be greater than or equal to the voltage at pin 10 of the TDA8362.

The control pulses for the HR horizontal scan, which is a sawtooth voltage generator, are obtained by dividing the frequency of the horizontal horizontal scan.
The frequency divider has two operating modes.
The “large window” mode is activated when there is no synchronization or when a non-standard signal is received (the number of lines in a half-frame is from 311 to 314 in 50 Hz mode and from 261 to 264 in 60 Hz mode). In this case, the divider is in search mode and switches from a frequency of 45 Hz to a frequency of 64.5 Hz.
The narrow window mode is activated when more than 15 consecutive frame sync pulses are detected.
This is the standard mode of operation. In the absence of clock pulses, the reverse motion of Zr turns on at the end of the half-frame (window), which ensures minimal image distortion.
The divider switches back to search mode if there are no frame sync pulses for 6 consecutive periods of frame scan. To pin 42 of TDA8362 is connected an external RC chain of a 3G frame scan.
The amplitude of the sawtooth voltage at pin 42 is 1.5 ... 1.8 V. At pin 41 of the TDA8362, reverse-frequency pulses of a vertical sweep (from the output stage) are applied to ensure the linearity of the output voltage.
The constant voltage on pin 41 is 2.5 ± 0.5 V, the alternating voltage is 1 V. In the TDA8362, the kinescope is protected against burn-through in the event of a frame scan failure, which dampens the rays when the direct voltage on pin 41 of the TDA8362 increases or decreases by 1 5 in (relative to the above). Framing control pulses are formed on pin 43 of TDA8362. The maximum and minimum voltage are respectively 4 and 0.3 V.
The maximum permissible output current is 1 mA. The delay in turning on the vertical scan at power-on is 140 ms, and the output voltage is high. When you start the HR frame scan is turned on at a frequency of 60 Hz.
In the TDA8362-N5 modification, the launch is carried out at a frequency of 50 Hz, which is used for the on-screen display. The voltage at pin 43 of the TDA8362 when turned on is low, which makes it easier to start the frame sweep.
TDA8362 synchronization circuit The TDA8362 provides reliable horizontal and frame synchronization of the image when processing a signal from a VCR, both in the case of phase displacement of the clock pulses (with a stretched tape), and in the case of playing back video tapes with copy protection.

TDA8362 VIDEO PROCESSING CIRCUIT
The full color television signal allocated on pin 7 of the TDA8362 passes notch filters to suppress the second intermediate frequency of the sound and goes to pin 13 of the TDA8362 (internal signal). On pin 15 of the TDA8362, a signal is supplied from external inputs (external signal).
The signal swing at pin 13 (including sync pulses) is 2 ... 2.8 V, and at pin 15 is TDA8362 1 ... 1.4 V. Switching the input video signal is carried out by a switching circuit controlled by voltage level on pin 16 of TDA8362 (U 16). At U 16 <0.5B, internal video and audio signals are processed (a notch filter that suppresses the color signal is turned on). With 3 <U16 <5V, external video and audio signals in the S-VHS standard are processed. In this case, a color signal is supplied to pin 16 of the TDA8362, and a brightness signal to pin 15. The notch filter is disabled in this mode. At U16> 7.5 V, external video and audio signals are processed (notch filter on).
The TDA8362 contains notch and bandpass filters to separate color and luminance signals.
The filter tuning scheme provides automatic adjustment of the filters in accordance with the frequency of the crystal oscillator included in the decoder. A pin 12 of the TDA8362 is connected to a decoupling capacitor of the tuning circuit.

In modification TDA8362-N5, the resonant frequency of the notch filter during signal processing in the SECAM system is reduced to 4.2 MHz to provide better suppression of the DR and DB subcarriers in the luminance signal. Filters are calibrated during the reverse frame scan. The luminance signal enters the delay line (480 ns) and the RF correction circuit, which provides an increase in the frequency response in the high-frequency region, and then to the matrixing circuit. pin 14 TDA8362 is used to control the RF correction circuit (image sharpness). The control voltage range is 0 ... 5 V. When a voltage of 7 V is applied to pin 14, the correction circuit is switched off (nominal mode). In the absence of a video signal, the current consumed by TDA8362 according to pin 14 increases to 1 mA (in versions N3 and N4 - up to 200 μA). The voltage on pin 14 is reduced. This information can be used to identify the video signal.

 The color signal is fed to a band-pass filter and an amplifier with AGC, and then to a decoder, which includes a generator with quartz frequency stabilization, a color difference signal demodulator (CRS), and a color off circuit.
The generator generating the signal of the reference subcarrier, the PD, and the low-pass filter connected to pin 33 of the TDA8362 form a PLL system that provides synchronization in frequency and phase of the signals of the reference subcarrier with a color burst signal (SCC). Quartz resonators are connected to pin 34 and 35 of the TDA8362, while a resonator with a frequency of 4.43 MHz is connected to pin 35. This frequency is used for calibrating 3G horizontal scanning, and to pin 34 - a resonator with a frequency of 3.58 MHz.
When using one quartz or connecting two quartz to one pin (usually to pin 34) and using an external switching circuit, pin 35, the TDA8362 is connected to the power bus through a 47 kOhm resistor. This ensures the forced inclusion of the generator.

When using modifications N4 and N5 TDA8362, the value of the resistor is reduced to 8.2 kOhm. This is essential to enable 3G line scan calibration. The system's automatic detection circuitry provides recognition of color signals in PAL and NTSC systems and switching of signal processing circuits.
To process the color signal in the SECAM system, a TDA8395 decoder is used, to which a 4.43 MHz reference signal is supplied from pin 32 of the TDA8362. The amplitude of the reference signal is 0.25 ± 0.5 V. In the case of identifying a color signal in a PAL or NTSC system, the voltage at pin 32 of the TDA8362 is 1.5 V. If there is no identification, the color scheme disables the outputs of the demodulator central circuit (pin 30 and 31) , and the voltage on pin 32 of the TDA8362 increases to 5 V. This voltage blocks the TDA8395 color shutdown circuit in m / s and connects its outputs to the central control system.

The current consumed by TDA8395 with pin 32 of TDA8362 when identifying a color signal in the SECAM system is 150 μA. Increasing the current to this value forces the TDA8362 to SECAM mode. In this case, the system automatic detection circuit does not search for color signals in PAL and SECAM systems. Forcing the TDA8362 to NTSC mode is not possible.

The color signal for the TDA8395 can be obtained on pin 27 of the TDA8362 by connecting this output to the power bus via a 4.7 ... 12 kΩ resistor. The signal span is 330 mV. This combination of chips can only be used as a PAL / SECAM decoder. In the case of color signals processing, PAL / SECAM / NTSC systems use an external color signal extraction circuit for TDA8395.

It should be noted that when using modifications N4 and N5 of TDA8362, to prevent erroneous identification of the signal from the video recorder in the SECAM system as NTSC, it is necessary to provide a voltage at the terminal 27 of TDA8362 of at least 6 V.

FEATURES
Available in TDA8360, TDA836

1
and TDA8362
· Vision IF amplifier with high
sensitivity and good differential
gain and phase
· Multistandard FM sound
demodulator (4.5 MHz to 6.5 MHz)
· Integrated chrominance trap and
bandpass filters (automatically
calibrated)
· Integrated luminance delay line
· RGB control circuit with linear RGB
inputs and fast blanking
· Horizontal synchronization with two
control loops and alignment-free
horizontal oscillator without
external components
· Vertical count-down circuit
(50/60 Hz) and vertical preamplifier
· Low dissipation (700 mW)
· Small amount of peripheral
components compared with
competition ICs
· Only one adjustment (vision IF
demodulator)
· The supply voltage for the ICs is
8 V. They are mounted in a shrink
DIL envelope with 52 pins and are
pin compatible.
Additional features
TDA8360
· Alignment-free PAL colour decoder
for all PAL standards, including
PAL-N and PAL-M.
TDA8361
· PAL/NTSC colour decoder with
automatic search system
· Source selection for external
audio/video (A/V) inputs (separate
Y/C signals can also be applied).
TDA8362
· Multistandard vision IF circuit
(positive and negative modulation)
· PAL/NTSC colour decoder with
automatic search system
· Source selection for external
A/V inputs (separate Y/C signals
can also be applied)
· Easy interfacing with the TDA8395
(SECAM decoder) for
multistandard applications.
GENERAL DESCR

IPTION
The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
deflection.
Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.
The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
possible).
The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.
For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.

TDA8361
The TDA8361 has the following
differences to the pinning:
Pin 1: only audio de-emphasis
Pin 27: only hue control
Pin 32: 4.43 MHz output for TDA8395
is not connected.
FUNCTIONAL DESCRIPTION
Video IF amplifier
The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.
The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.
In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.
The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.
The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.
The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.
To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.
The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependen

t on the frequency of the
incoming chrominance signal.

Sound circuit
The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.
The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of -6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.
The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.
Synchronization circuit
The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
amplitude.
The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.
The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
typical value.
The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.
X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.
The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8

V supply line.
The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.
Integrated video filters
The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
decoder.
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.
When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
applications.
The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.
Colour decoder
The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.
TDA8360
This IC contains only a PAL decoder.
Depending on the frequency of the
crystals which are connected to the IC
the decoder can demodulate all PAL
standards. Because the horizontal
oscillator is calibrated by using the
crystal frequency as a reference the
4.4 MHz crystal must be connected to
pin 35 and the 3.5 MHz crystal to
pin 34. When only one crystal is
connected to the IC the other crystal
pin must be connected to the positive
supply rail via a 47 kW resistor. For
applications with two 3.5 MHz
crystals both must be connected to
pin 34 and the switching between the
crystals must be made externally.
Switching of the crystals is only
allowed directly after the vertical
retrace. The circuit will indicate
whether a PAL signal has been
identified by the colour decoder via
the saturation control pin.
When two crystals are connected to
the IC the output voltage of the video
identification circuit indicates the
frequency of the incoming
chrominance signal.

The conditions are:
· Signal identified at
fosc = 3.6 MHz; VO = 6 V
· Signal identified at
fosc = 4.4 MHz (or no colour);
VO = 8 V.
This information can be used to
switch the sound bandpass filter and
trap filter.
TDA8361
This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5 kW or 10 kW resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.
TDA8362
In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
decoder TDA8395.
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 mA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R-Y and B-Y outputs
and increase the voltage level on
pin 32.
This voltage will switch off the
colour-killer in the TDA8395 and
switch on the R-Y and B-Y outputs of
the TDA8395. Forcing the system to
the SECAM standard can be
achieved by loading

pin 32 with a
current of 150 mA. Then the system
manager in the TDA8362 will not
search for PAL or NTSC signals.
Forcing to NTSC is not possible.
For PAL/SECAM applications the
input signal for the TDA8395 can be
obtained from pin 27 (hue control)
when this pin is connected to the
positive supply rail via the 5 kW or
10 kW resistor. An external source
selector is required by the
TDA8395/TDA8362 combination for
PAL/SECAM/NTSC applications.
RGB output circuit
The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.
The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.

 

THOMSON TEA5101A - RGB HIGH VOLTAGE AMPLIFIER BASIC OPERATION AND APPLICATIONS:

GENERAL
The control of state-of-the-art color cathode ray
tubes requires high performance video amplifiers
which must satisfy both tube and video processor
characteristics.
When considering tube characteristics (see Fig-
ures 13 and 14),we note that a 130V cutoff voltage
is necessary to ensure a 5mA peak current.How-
ever 150V is a more appropriate value if the satu-
ration effect of the amplifier is to be taken into
account. As the dispersion range of the three guns
is ± 12%, the cutoff voltage should be adjustable
from 130V to 170V. The G2 voltage, from 700 to
1500V allows overall adjustment of the cutoff volt-
age for similar tube types.
A 200V supply voltage of the video amplifier is
necessary to achieve a correct blanking operation.
In addition, the video amplifier should have an
output saturation voltage drop lower than 15V, as
a drive voltage of 130V (resp. 115V) is necessary
to obtain a beam current of 4 mA for a gun which
has a cutoff point of 170V (resp. 130V).
Note : For all the calculations discussed above, the
G1 voltage is assumed to be 0V.
The video processor characteristics must also be
considered. As it generally delivers an output volt-
age of 2 to 3V, the video amplifier must provide a
closed loop DC gain of approximately 40.
The video amplifier dynamic performances must
also meet the requirements of good definition even
with RGB input signals (teletext,home computer...),
e.g. 1mm resolution on a 54cm CRT width scanned
in 52µs. Consequently, a slew rate better than
2000V/µs, i.e. rise and fall times lower than 50ns,
is needed. In addition, transition times must be the
same for the three channels so as to avoid coloured
transitions when displaying white characters. The
bandwidth of a video amplifier satisfying all these
requirements must be at least 7MHz for high level
signals and 10MHz for small signals.
One major feature of a video amplifier is its capa-
bility to monitor the beam current of the tube. This
function is necessary with modern video proces-
sors:
- for automatic adjustment of cutoff and also, where
required,video gain in order to improve the long
term performances by compensation for aging
effects through the life of the CRT. This adjust-
ment can be done either sequentially (gun after
gun) or in a parallel mode.
- for limiting the average beam current
A video amplifier must also be flashover protected
and provide high crosstalk performances. Cros-
stalk effects are mainly caused by parasitic capaci-
tors and thus increase with the signal frequency. A
crosstalk level of -20dB at 5MHz is generally ac-
ceptable.

Table 1 summarizes the main features of a high
performance video amplifier.
Table 1 :
Main Features of a High Performance
Video Amplifier
Maximum Supply Voltage
220V
Output voltage swing "Average"
100V
Output voltage swing "Peak"
130V
Low level saturation (refered to VG1)
15V
Closed loop gain
40
Transition time
50ns
Large signal bandwidth
7MHz
Small signal bandwidth
10MHz
Beam current monitoring
Flash over protection
Crosstalk at 5MHz
-20dB
The SGS-THOMSON Microelectronics TEA5101A
is a high performance and large bandwidth 3 chan-
nel video amplifier which fulfills all the criteria dis-
cussed above. Designed in a 250V DMOS bipolar
technology, it operates with a 200V power supply
and can deliver 100V peak-to-peak output signals
with rise and fall times equal to 50ns.
The 5101A features a large signal bandwidth of
8MHz, which can be extended to 10MHz for small
signals (50 Vpp).
Each channel incorporates a PMOS transistor to
monitor the beam current. The circuit provides
internal protection against electrostatic discharges
and high voltage CRT discharges.
The best utilization of the TEA 5101A high perform-
ance features such as dynamic characteristics,
crosstalk,or flashover protection requires opti-
mized application implementation. This aspect will
be discussed in the fourth part of this document.

I.1 - Input Stage
The differential input stage consists of the transistor
T1 and T2 and the resistors R4,R5 and R6.
This stage is biased by a voltage source T3,R1,R2
and R3.
VB(T1) = (1 + R2
R3) x VB(T3) ≅ 3.8V
Each amplifier is biased by a separate voltage
source in order to reduce internal crosstalk. The
load of the input stage is composed of the transistor
T4 (cascode configuration) and the resistor R7. The
cascode configuration has been chosen so as to
reduce the Miller input capacitance. The voltage
gain of the input stage is fixed by R7 and the emitter
degeneration resistors R5,R6,and the T1,T2 internal
emitter resistances. The voltage gain is approxi-
mately 50dB.
Using a bipolar transistor T4 and a polysilicon re-
sistor R7 gives rise to a very low parasitic capaci-
tance at the output of this stage (about 1.5pF).
Hence the rise and fall times are about 50ns for a
100V peak-to-peak signal (between 50V and
150V).
I.2 - Output Stage
The output stage is a quasi-complementary class
B push-pull stage. This design ensures a symetrical
load of the first stage for both rising and falling
signals. The positive output stage is made of the
DMOS transistor T5,and the negative output stage
is made of the transistors PMOS T6 and DMOS T7.
The compound configuration T6-T7 is equivalent to
a single PMOS. A single PMOS transistor capable
of sinking the total current would have been too
large.
By virtue of the symetrical drive properties of the
output stage the rise and fall times are equal (50ns
for 100V DC output voltage).

 I.3 - Beam Current Monitoring
This function is performed by the PMOS transistor
T8 in source follower configuration. The voltage on
the source (cathode output) follows the gate volt-
age (feedback output). The beam current is ab-
sorbed via T8 . On the drain of T8, this current will
be monitored by the videoprocessor.
I.4 - Protection Circuits
I.4.1 - MOS protection
Four zener diodes DZ(1-4) are connected between
gate and source of each MOS in order to prevent
the voltage from reaching the breakdown volt-
age.Hence the VGS voltage is internally limited to
± 15V.
I.4.2 - Protection against electrostatic dis-
charges
All the input/output pins of the TEA5101A are pro-
tected by the diodes D1-D7 which limit the overvol-
tage due to ESD.
I.4.3 - Flashover Protection
A high voltage and high current diode D5 is con-
nected between each output and the high voltage
power supply. During a flash, most of the current is
generally absorbed by the spark gap connected to
the CRT socket. The remaining current is absorbed
by the high voltage decoupling capacitor through
the diode D5. Hence the cathode voltage is
clamped to the supply voltage and the output volt-
age does not exceed this value.

 I.1 - Voltage Amplifier
II.1.1 - Bias conditions Vin = Vref
The bias point is fixed by the feedback resistor
Rf,the bias resistor Rp, and by the internal refer-
ence voltage when Vin = Vref.
If VO is the output voltage (pin 9) :
VO = (1 + Rf
Rp) x Vref (1)
In this state T1 and T2 are conducting. A current
flows in R7 and T4 soT5 is on. The T5 drain current
is fed to the amplifier input through the feedback
resistor. The current in R7 is:
I(R7) = VDD − VO − VGS(T5)
R7
≅ VDD − VO
R7
and the current in T5 and Rf is :
I(T5) = VO − Vref
Rf
≅ VO
Rf
Thus the total current absorbed by each channel of
the TEA5101A is :
VDD
R7 + VO x (1
Rf − 1
R7)
The cathode (pin 7) output voltage is:
VO + VGS(T8) = VO
The beam current is absorbed by T8 and Rm. The
voltage developed across Rm by this current is fed
to the videoprocessor in order to monitor the beam
current.
II.1.2 - Dynamic operation
The TEA5101A operates as a closed loop amplifier,
with its voltage gain fixed by the resistors Rf and
Re.
Since the open loop gain A is not infinite, the resistor
Rp and the input impedance Rin must be consid-
ered.Hence the voltage gain is
G = − Rf
Re x
1
1 + 1
A (1 +
Rf
Rp ⁄ ⁄ Re ⁄ ⁄ Rin)
(2)
II.1.2.1 - Input voltage Vin < Vref (black picture)
In this case the current flowing in R7 and T1 de-
creases whilst the collector voltage of T4 and the
output voltage both increase. In the extreme case,
I(T1) = I(R7) = 0 and VO= VDD-VGS(T5)
In order to charge the tube capacitor the voltage is
fed to the cathode output in two ways:
- through the PMOS (with a VGS difference) for the
low frequency part
- through the capacitor C for the high frequency
part (output signal leading edge)
To correctly transmit the rising edge, the value of
the capacitor C must be high compared to CL.
With the current values used (C = 1nF,CL = 10pF),
the attenuation is very small (0.99)
II.1.2.2 - Input voltage Vin > Vref (white picture)
In this case,the current in R7 and T1 increases with
an accompanying drop of T4’s collector voltage until
T1 and T4 are saturated. At this point:
VO ≅ VC(T4) ≅ VCC
During a high to low transition (i.e. black-white
picture), the beam current is absorbed in two ways:
- through the capacitor C and the compound
PMOS T6-T7 for the high frequency part (falling
edge)
- through the PMOS T8 and the resistor Rm for the
low frequency part.
II.2 - Beam Current Monitoring
II.2.1 - Stationary state
The beam current monitoring is performed by the
PMOS T8 and the resistor Rm. When measuring low
currents (leakage, quasi cutoff),the Rm value is
generally high. When measuring high currents
(drive, average or peak beam current),Rm is gen-
erally bypassed by a lower impedance.
It should be noted that the current supplied by the
three guns flows through this resistor.Hence,with
too large a value for the resistor Rm,the cathode
voltage of the tubes will become too high for the
required operating current values.This is a funda-
mental difference between the TEA5101A and dis-
crete video amps. In discrete video amps, the
current monitoring transistor is a high voltage PNP
bipolar which may saturate. In this case the beam
current can flow through the transistor base and it
is no longer monitored by the video processor. This
effect does not occur with the TEA 5101A.
II.2.2 - Transient phase : low current measure-
ments
The cut-off adjustment sequence is generally as
follows:
In a first step, the cathode is set to a high voltage
(180V) in order to blank the CRT and to measure
the leakage current. In a second step, the tube is
slighly switched on to measure a very low current
(quasi cut-off current). This operation is performed
by setting the cathode voltage to about 150V and
adjusting it until the proper current is obtained. The
maximum time available to do this operation is
generally about 52µs.
Figure 3 shows the simplified diagram of the
TEA5101A output, the voltages during the different
steps,and the stationary state the system must
reach for correct adjustment.
I.1 - Voltage Amplifier
II.1.1 - Bias conditions Vin = Vref
The bias point is fixed by the feedback resistor
Rf,the bias resistor Rp, and by the internal refer-
ence voltage when Vin = Vref.
If VO is the output voltage (pin 9) :
VO = (1 + Rf
Rp) x Vref (1)
In this state T1 and T2 are conducting. A current
flows in R7 and T4 soT5 is on. The T5 drain current
is fed to the amplifier input through the feedback
resistor. The current in R7 is:
I(R7) = VDD − VO − VGS(T5)
R7
≅ VDD − VO
R7
and the current in T5 and Rf is :
I(T5) = VO − Vref
Rf
≅ VO
Rf
Thus the total current absorbed by each channel of
the TEA5101A is :
VDD
R7 + VO x (1
Rf − 1
R7)
The cathode (pin 7) output voltage is:
VO + VGS(T8) = VO
The beam current is absorbed by T8 and Rm. The
voltage developed across Rm by this current is fed
to the videoprocessor in order to monitor the beam
current.
II.1.2 - Dynamic operation
The TEA5101A operates as a closed loop amplifier,
with its voltage gain fixed by the resistors Rf and
Re.
Since the open loop gain A is not infinite, the resistor
Rp and the input impedance Rin must be consid-
ered.Hence the voltage gain is
G = − Rf
Re x
1
1 + 1
A (1 +
Rf
Rp ⁄ ⁄ Re ⁄ ⁄ Rin)
(2)
II.1.2.1 - Input voltage Vin < Vref (black picture)
In this case the current flowing in R7 and T1 de-
creases whilst the collector voltage of T4 and the
output voltage both increase. In the extreme case,
I(T1) = I(R7) = 0 and VO= VDD-VGS(T5)
In order to charge the tube capacitor the voltage is
fed to the cathode output in two ways:
- through the PMOS (with a VGS difference) for the
low frequency part
- through the capacitor C for the high frequency
part (output signal leading edge)
To correctly transmit the rising edge, the value of
the capacitor C must be high compared to CL.
With the current values used (C = 1nF,CL = 10pF),
the attenuation is very small (0.99)
II.1.2.2 - Input voltage Vin > Vref (white picture)
In this case,the current in R7 and T1 increases with
an accompanying drop of T4’s collector voltage until
T1 and T4 are saturated. At this point:
VO ≅ VC(T4) ≅ VCC
During a high to low transition (i.e. black-white
picture), the beam current is absorbed in two ways:
- through the capacitor C and the compound
PMOS T6-T7 for the high frequency part (falling
edge)
- through the PMOS T8 and the resistor Rm for the
low frequency part.
II.2 - Beam Current Monitoring
II.2.1 - Stationary state
The beam current monitoring is performed by the
PMOS T8 and the resistor Rm. When measuring low
currents (leakage, quasi cutoff),the Rm value is
generally high. When measuring high currents
(drive, average or peak beam current),Rm is gen-
erally bypassed by a lower impedance.
It should be noted that the current supplied by the
three guns flows through this resistor.Hence,with
too large a value for the resistor Rm,the cathode
voltage of the tubes will become too high for the
required operating current values.This is a funda-
mental difference between the TEA5101A and dis-
crete video amps. In discrete video amps, the
current monitoring transistor is a high voltage PNP
bipolar which may saturate. In this case the beam
current can flow through the transistor base and it
is no longer monitored by the video processor. This
effect does not occur with the TEA 5101A.
II.2.2 - Transient phase : low current measure-
ments
The cut-off adjustment sequence is generally as
follows:
In a first step, the cathode is set to a high voltage
(180V) in order to blank the CRT and to measure
the leakage current. In a second step, the tube is
slighly switched on to measure a very low current
(quasi cut-off current). This operation is performed
by setting the cathode voltage to about 150V and
adjusting it until the proper current is obtained. The
maximum time available to do this operation is
generally about 52µs.
Figure 3 shows the simplified diagram of the
TEA5101A output, the voltages during the different
steps,and the stationary state the system must
reach for correct adjustment.

I.1 - Voltage Amplifier
II.1.1 - Bias conditions Vin = Vref
The bias point is fixed by the feedback resistor
Rf,the bias resistor Rp, and by the internal refer-
ence voltage when Vin = Vref.
If VO is the output voltage (pin 9) :
VO = (1 + Rf
Rp) x Vref (1)
In this state T1 and T2 are conducting. A current
flows in R7 and T4 soT5 is on. The T5 drain current
is fed to the amplifier input through the feedback
resistor. The current in R7 is:
I(R7) = VDD − VO − VGS(T5)
R7
≅ VDD − VO
R7
and the current in T5 and Rf is :
I(T5) = VO − Vref
Rf
≅ VO
Rf
Thus the total current absorbed by each channel of
the TEA5101A is :
VDD
R7 + VO x (1
Rf − 1
R7)
The cathode (pin 7) output voltage is:
VO + VGS(T8) = VO
The beam current is absorbed by T8 and Rm. The
voltage developed across Rm by this current is fed
to the videoprocessor in order to monitor the beam
current.
II.1.2 - Dynamic operation
The TEA5101A operates as a closed loop amplifier,
with its voltage gain fixed by the resistors Rf and
Re.
Since the open loop gain A is not infinite, the resistor
Rp and the input impedance Rin must be consid-
ered.Hence the voltage gain is
G = − Rf
Re x
1
1 + 1
A (1 +
Rf
Rp ⁄ ⁄ Re ⁄ ⁄ Rin)
(2)
II.1.2.1 - Input voltage Vin < Vref (black picture)
In this case the current flowing in R7 and T1 de-
creases whilst the collector voltage of T4 and the
output voltage both increase. In the extreme case,
I(T1) = I(R7) = 0 and VO= VDD-VGS(T5)
In order to charge the tube capacitor the voltage is
fed to the cathode output in two ways:
- through the PMOS (with a VGS difference) for the
low frequency part
- through the capacitor C for the high frequency
part (output signal leading edge)
To correctly transmit the rising edge, the value of
the capacitor C must be high compared to CL.
With the current values used (C = 1nF,CL = 10pF),
the attenuation is very small (0.99)
II.1.2.2 - Input voltage Vin > Vref (white picture)
In this case,the current in R7 and T1 increases with
an accompanying drop of T4’s collector voltage until
T1 and T4 are saturated. At this point:
VO ≅ VC(T4) ≅ VCC
During a high to low transition (i.e. black-white
picture), the beam current is absorbed in two ways:
- through the capacitor C and the compound
PMOS T6-T7 for the high frequency part (falling
edge)
- through the PMOS T8 and the resistor Rm for the
low frequency part.
II.2 - Beam Current Monitoring
II.2.1 - Stationary state
The beam current monitoring is performed by the
PMOS T8 and the resistor Rm. When measuring low
currents (leakage, quasi cutoff),the Rm value is
generally high. When measuring high currents
(drive, average or peak beam current),Rm is gen-
erally bypassed by a lower impedance.
It should be noted that the current supplied by the
three guns flows through this resistor.Hence,with
too large a value for the resistor Rm,the cathode
voltage of the tubes will become too high for the
required operating current values.This is a funda-
mental difference between the TEA5101A and dis-
crete video amps. In discrete video amps, the
current monitoring transistor is a high voltage PNP
bipolar which may saturate. In this case the beam
current can flow through the transistor base and it
is no longer monitored by the video processor. This
effect does not occur with the TEA 5101A.
II.2.2 - Transient phase : low current measure-
ments
The cut-off adjustment sequence is generally as
follows:
In a first step, the cathode is set to a high voltage
(180V) in order to blank the CRT and to measure
the leakage current. In a second step, the tube is
slighly switched on to measure a very low current
(quasi cut-off current). This operation is performed
by setting the cathode voltage to about 150V and
adjusting it until the proper current is obtained. The
maximum time available to do this operation is
generally about 52µs.
Figure 3 shows the simplified diagram of the
TEA5101A output, the voltages during the different
steps,and the stationary state the system must
reach for correct adjustment.

During the blanking phase, the tube is switched off,
the PMOS is switched off and its VGS voltage is
equal to the pinch-off voltage (about 1.5V). The
voltages at the different nodes are shown in figure
3 (V(9) = 180V, V(k) = 181.5V). The falling edge of
the cutoff pulse is instantaneously transmitted by
the capacitor C. When the stationary state is
reached, the cathode voltage will be 152.5V if the
voltage on pin 9 is 150V, as the VGS voltage of the
conducting PMOS is about 2.5V.
We can see that the voltage

on C must increase by
an amount of ∆Vc = 1V. This charge is furnished by
the tube capacitor which is discharged by an
amount of ∆VCL = 29V with a time constant equal
to R x CL (10 ns). By considering the energy
balance, we can calculate the maximum charge
∆Vmax that CL can furnished to C
∆Vmax = √CL
C x ∆VCL ≅ 3V
Since this voltage is greater than ∆VC, the capacitor
C can be charged and the stationary state is
reached without any contribution being required
from the tube current,i.e. the whole tube current
can flow through the PMOS and the adjustment can
be performed correctly.
Considering higher voltage and beam current
swings, the margin is greater because:
- the voltage swing across the tube capacitor is
greater
- the tube current is higher and the picture is not
disturbed even if part of the beam current is used
to charge the capacitor C.