NORDMENDE COLOR 3035 CHASSIS F15-01 (THOMSON ICC5 / ICC5100M) INTERNAL VIEW.

  NORDMENDE COLOR 3035  CHASSIS F15-01 (THOMSON ICC5)  :

The early production run of the mono - colour TV-sets started with the chassis F 15-01 (110°CRT) and F 16-01 (90°CRT). During production run the chassis changed to the variables F 15-02 and F 16-02. The differences will be noticed in the change of the p.c.b. lay-out (producing of the voltage U 4’ 13 V). The models Spectra 3201 and Spectra 3205 have been fitted with the chassis variable 02 from production start on. The chassis variables F 15-03 and F 16-03 have been fitted only with a new chroma-video-module. Since all other components and parts re- main identical only the new chroma-video-module will be added in this service manual. Please pay attention to the fact of the different chassis variables when ordering spare parts or when filing the service manuals. Investigate the variantes on the p.c.b. printed side near the antenna socket. The following markings may be found: “Chassis 01” with F 15 01/F 16-01, “Chassis 02” with F 15-02/F 16-02 and “Chassis 03” with F 15-03/F 16-03.


Operating
(Channel Instructions storage) 1. Series fitted “Single-Standard” sets The mono-CTV-sets fitted with the chassis F 15 and F 16 are capable of receiving the following TV-standards: PAL-B/G (e.g. Federal Republic of Germany, Switzerland, Austria, Italy). SECAM-B/G (e.g. DDR) Standard switch-over is carried out automatically. The channels can either be set by automatic search (button —*e) or direct channel- selection. For channel-selection press button «C» until -- is being displayed. In case, only a C— is being displayed then the set is a model with “Multi- Standard” (see point 2). When the -- appears set the channel number with the buttons «1...10». (Set the zero with button number «10». Set a zero with button «10» in front of each channel-number 2...9 and then the channel-number). For storage of the desired channel press the program-button until the displayed dot stops to blink. Sample; select channel 32 on program-place 1: «C, 3, 2, 1». Each command has to be carried out within 4 seconds! If not, the complete input has to be repeated. For selection of “Cable-Channels” it is re- quired, to press button «C» (-— must be indicated) and «C» be pressed again so (CC is indicated). Followed by the selection of the cable- channel number. Sample; Cable-channel S 2 on program no. 3: «C, C, 10, 2, 3». It is possible to store up to 39 channels. The program-places 11. . .39 are being selected as follows: e.g. program 11: button 10, 1 program 23: button 10, 10, 3 program 39: button 10, 10, 10, 9 The program places 10, 20 and 30 are reserved for AV-playback with a video-recorder. Only in this channels will the time-constant be switched on for video-playback. 2.Sets with “Multi-Standard” The mono-CTV-sets containing the chassis F 15 and F 16 can be extended to “Multi-Standard” function (additionally NTSC and SECAML standard). With these sets the different TV-standards are being selected during direct channel selection (not with automatic channel search). Press the button «C» until the display shows C-.In case -- is being displayed, then the set is a model having “Single-Standard” or the set has not been programmed for “Multi Standard” (see section “Service-Mode”). If C- is dis- played, then select the standard with one of the buttons «1...5» (see table on page 4).

Afterwards select the channel-numbers. For storage of the channel press the desired program button until dot stops blinking. Sample PAL, channel 42 onto program-place 2 «C,1, 4, 2, 2». Each command has to be carried out within 4 seconds, otherwise the complete input has to be repeated. For selection of the cable-channels S1...S20 the button «C» has to be pressed again after standard selection. Sample SECAM L, channel $12 onto program place 8: «C, 2, C, 1, 2, 8».

 Service-Mode The “Service-Mode” is an operational feature of the set, in which the technician has the possibility to change the program of the microprocessor of the operating unit in a few operations: a) After replacement of the IC MDA 2061, position IR 73 (EEPROM), b) For programming of the set from “Single- Standard” to “Multi-Standard”, c) To switch-over the display characters from German to international (English) characters. In order to switch the set into “Service-Mode’ it is necessary to switch the set off with the mains-switch. Then press both local volume buttons «+» and «—» on the set simultaneously and additional switch the set on again with the mains-switch and keep the volume buttons depressed until the display is active. Let loose the volume buttons. After 8 seconds the display indicates -- . If not, repeat the foregoing procedure. If -- is being displayed, then the following functions can be switched over. Single segments of the display show the corresponding function condition:

 Replacement of the IC MDA 2061, in position IR 73 (EEPROM) After replacement of the MDA 2061, the set will react as follows: a) The display shows German function symbols. b) The program storages have all stored Ch OO. c) PAL B/G, and SECAM B/G (DDR) can be received in “Single-Standard”, not NTSC and SECAM L (France) = Multi-Standard. Thus, it is necessary that all transmitters are being stored newly again. With all sets which have been modified to Multi standard or to SECAM L (France) it is required to switch - during “Service-Mode” - over to Multi-Standard (see section “Service-Mode’”). These sets can be recognized by the sub-module AM/FM 5101 (fig. 1) which is soldered onto the sound module. When the function symbols should be dis- played international (English), then the switch- over has to be carried out in the “Service - Mode”.

The ICC5 got a bad press but they were an advanced design and unusual for the time for a European chassis in that they didn't make widespread use of Philips techniques or components.B&O sets have used it like the MX3000, MX4500 and MX5000. B&O had also used the previous ICC3 in the MX2000 and the M20, so they weren't much of a culture shock - the removal of the big mains transformer that the ICC3 had was clearly the key design goal.I found the chassis to be reasonably reliable after reworking and well laid out in general maybe a bit too compact, there were a few quirks without a doubt , the E-W stage once sorted with modified coil etc. wasn't so unreliable after all. The PCB layout was one of the most complex design almost like a computer board. It was only when they aged you started to get some real weird faults. The ICC7/8 were a lot more conventional circuitry wise, and posed few real problems. The ICC9 and IDC2 were not very reliable at all, possibly the least reliable of the lot, the IKC2 was a close second! Personally i disliked the IKC2.This models series are the last featuring the THOMSON CHASSIS ICC5, replaced with THOMSON ICC7, ICC8 SERIES.

 Function description:
 
 Power supply

 For all colour television sets with the chassis F 15/F 16, the power supply is located on the main chassis, for technical reasons related to manufacture. In the present case, a reverse- converter switch mode power supply synchronised at the horizontal scanning frequency and provided with secondary regulation as well as a separate stand-by power supply is employed. Special features of the design are the follow- ing: — All output voltages are stabilized. - Shielding of the switching power supply transformer is not necessary. - Excellent stability of the operating voltage for the horizontal deflection stage is achieved by secondary regulation. - The operating safety and reliability are enhanced by the separate stand-by power supply. - The power consumption during stand-by operation is very low (about 3W). — The control range extends from 180 to 264V. 1.1 Stand-by power supply The power supply is illustrated in figure 1 (page 10). In order to permit the television set to be switched on by remote control, the infrared detector, the control-panel microcomputer, and the switching power supply must be switched to the stand-by mode. After actuation of the main power switch, the stand-by transformer, LP 03, supplies about 7.5V through the bridge rectifier to the series transistor, TP 45. DP 45 li- mits its emitter voltage to 7.5V. The filter capacitor, CP 46, smooths the direct voltage. TP 44, a further series transistor, supplies the 5-V stand-by operating voltage - stabilised by DP 44 - at the emitter. During start of operation with the set, the control-panel microcomputer switches the transistors, TR 26 and TP 48, through RR 27. The power processor, TEA 2029, thus receives its operating voltage at pin 8; however, this voltage can be derived from the stand-by power supply only during the process of switching on.

 In the steady operating state, the diode split transformer yields the 13-V power processor operating voltage through DP 47. The switching power supply receives its stand-by voltage necessary for starting from the centre tap of LP 03. DP 08 and DP 09 operate as rectifying diodes. CP 26 serves as a filter for the 100-Hz starting voltage. 1.2 Switching power supply By means of the control-panel microcomputer, TR 26, TP 48, a switch-on command activates the power processor, IL 14. During the starting phase, the power processor delivers initially narrow and gradually expanding pulses at the scanning frequency to LP 32. The pulse trans- former, LP 32, provides for isolation from the power mains and transmits the triggering signal at a ratio of 3:1. TP 11 delivers this signal in inverted form to the driving stage, a push-pull emitter follower consisting of TP 19 and TP 16, which supplies the base current for the switch- ing transistor, TP 24. The bootstrap circuit com- prising DP 21 and CP 19 increases the efficiency of the driving stage. It ensures a sufficient- ly high base current in TP 16 during the con- ducting phase of the switching transistor, TP 24. When TP 16 blocks, TP 24 blocks too, while TP 11 and TP 19 conduct. During the conducting phase of TP 24, the positive base current at TP 24 charges CP 24. The charging voltage is limited to 2.1 V by the three diodes, DP 17, DP 18, and DP 19. After TP 24 has switched off, this serves as a negative blocking voltage. During the switch-on process, the inductance coil, LP 24, allows the base current in TP 24 to increase in accordance with an exponential function to about 1.2 A.s and thus decreases the power loss. Moreover, an adaptation to the breaking characteristic of TP 24 is effected by LP 24. By means of this measure, the breaking loss is reduced to a minimum. lf TP 24 is switched on, an augmenting, saw- tooth-shaped current flows from the bridge rectifier through the storage coil, LP 04, (terminals 3/6), TP 24, RP 25, and RP 21 to the chassis earth (figure 2, a to d). As a result of the control signal at the base, TP 24 blocks once again. The collector voltage at TP 24 is given by the sum of the mains voltage of about 300V and that induced by the secondary current flow. During this phase, the energy transfer proceeds from the primary to the secondary circuit of LP 04 . An important contribution to the reduction of breaking losses is provided by the attenuation network comprising DP 23, CP 23, RP 23, and RP 28. As a result of recharging at CP 23, the rise of the collector voltage is decreased, and thus the power peak is smaller. 1.3 Regulation The system voltage U 2 present secondarily at CP 41 serves to supply the horizontal deflection - stage. It is decreased to about 1.3 V by the vol- tage divider comprising RL 10, PL15, and RL 15, and supplied to pin 9 of IL 74. The pulse width modulator present in IL 14 de- rives the pulse width at the output, pin 7, from the voltage difference between the internally preset voltage of 1.3V and that prevailing at pin 9. In the event that the system voltage deviates from its set value, IL 14 delivers pulses of differing width at pin 7. An excessive rise of the voltage is counteract- ed by temporarily shortened closing pulses for TP 24. Since less energy is accepted during a shorter conducting period, the energy dissipation in the secondary circuit is likewise lower, as a consequence. Thus, the system voltage stabilizes to its set value. If the system voltage drops as a result of increasing load, the pulse width modulator in IL 14 yields progressively broader pulses at the scanning frequency. TP 24 remains conductive for a longer time. The energy storage coil, LP 04, now absorbs more energy. During the blocking phase of TP 24, the energy transfer proceeds to the secondary circuit of LP 04. Thus, the voltage remains stable even for increasing load on U 2.
 
 Protective circuit 

The protective circuit responds only in the case of extreme overload. In the event of failure, it ultimately switches off. This operational state is signalised with high level (7 V) at pin 15 of IL 14. 1.4.1 Dynamic control limiting Besides the static limiting by the power processor, IL 14 (maximal pulse width * 28 ps), dynamic control limiting is also provided by the components RP 20, DP 25, DP 24, and RP 18 in the switching power supply. If the mains voltage drops below the permissible lower limit, this leg of the protective circuit prevents overloading of the transistor, TP 24, by switching it off. While a discharge current — originating from LP 04 — is flowing, the voltages on the secondary windings of the power supply circuits are positive. During this time, the transistor, TP 11, re- mains switched on through DP 25, DP 24, and RP 18.Thus, TP 24 remains blocked until the secondary.charging current has ceased to flow. This also applies to the case where the closing signal is present at the power processor out- put, pin 7, because of the control circuit. If the mains voltage falls below about 80 V, the control panel microcomputer discontinues the operation of the set. 1.4.2 Short circuit of LP 04 or of a rectifier diode in the secondary circuit With increasing load, the time of current flow in TP 24 increases.The voltage due to the current through RP 25 and RP 21 increases until TP 15 switches on. Together with TP 14, this transistor constitutes a monostable mono vibrator stage. As governed by the time constant of RP 14 and CP 04, it remains in its astable state for about 100 ms. During this period, TP 19 is conductive, and the power supply is therefore not operative. Consequently, all secondary operating voltages decrease. The drop of U 4 (+13V) is used for blocking the transistor, TL 17, through DL 23 by means of the negative voltage jump arising across CL 33. Through RL 36 and RL 19, the positive voltage across CL 36 is now present at the protective circuit input, pin 28, of IL 14 (TEA 2029). In this manner, the switch-off information is transmitted through the power mains isolation from the primary to the secondary circuit of the power supply. After 2 to 3 s, the switching power supply res- tarts. The renewed soft start with initially narrow and progressively broader pulses is con- trolled by the discharging of CL 21 at pin 15 of IL 14. A total of two soft starts are effected. Ifa defect is present in the circuit, IL 14 blocks the triggering signals for the switching power sup- ply, as well as the horizontal and vertical deflection stages. The set remains in the protective switching mode until a “reset” operation is effected internally in the IC by renewed switching the set off and on by means of the main power switch. 1.4.3 Prolonged overloading of the system voltage U 2 or of the audio module voltage supply Us In such cases of malfunction, a permanent transformer coupling prevents correct operation of the power supply. If, for example, the voltage supplied to the driver circuit is not sufficient, TP 24 is no longer switched with certainty. The operating voltages do not attain the re- quired values. Nevertheless, the integrated cir- cuit, IL 14, continues to deliver a triggering sig- nal at the horizontal scanning frequency from pin 7. As a result, a positive voltage arises at CL 36 by way of DL 38 and RL 38.Since, however, the voltage U 4 (+13V) is now no longer building up, TL 17 remains blocked. The positive voltage on CL 36 activates the protective circuit through RL 36, RL 19, and pin 28 of IL 14. After two unsuccessful attempts to start, IL 14 remains in the protective. switching mode. In the event of momentary overload or picture- tube arc-over, the set would resume normal operation after a single protective switching operation.
 
 Prolonged overloading of the U1 (7 V) or U4 (13V) voltage source The supply to these circuits proceeds from comparatively loosely coupled transformer windings; hence, the protective switching process previously described is not effective in this case: Because of the excessively high current, a negative voltage is present at the common base resistor, RP 37 (resistance wire bridge). By way of RP 38, DP 38, and DP 36, this voltage reaches TP 17 and causes it to block. The voltage prevailing across CL 36 now activates the protective circuit input, pin 28 of IL 14.
 
Over voltage protection An excessive increase of all operating voltages, for example, as a result of a malfunction in the control circuit or failure of the vertical deflection circuit (such as the absence of a triggering signal at DL 21), is prevented by monitoring of U 5 (21V) through DL 18, RL 20, and DL 19. 2.

IR remote control By means of the infrared remote control, a remote-control design characterised by convenient serviceability and operational reliability is employed with the colour television sets with the chassis F 15F 16. The technical specifications on the remote control include: - IR remote control for 35 commands; - command transmission with the use of 11-bit data words; - toggle bits for unambiguous command re- cognition; - clock-oscillator at 400 kHz; - especially low power consumption (active current: about 2 mA, stand-by current: about 2 pA); — wide supply voltage range (4 to 7V), — low-power “flashed” pulse transmission. The entire electronic system of the IR remote control comprises only two active and eight passive components; thus, a high degree of operational reliability is ensured in advance.
A mechanical push-button matrix completes the circuitry. Upon pressing of a key on the 7x7 matrix, a sensor input is set to “low”, and an interrogation cycle is initiated. In the quiescent state, the driver outputs, pins 13 to 19, of the IC, IB 01, are at low level with their “open drain” outputs. The “pull-up” sensor inputs are thus set to “high” (pins 2 to 8). During the push-button matrix interrogation, only a single driver output is switched to low resistance in each case. If the actuation of a key is recognised by the IC, the oscillator is starting. The oscillator comprises essentially an inverter, which is externally coupled for feed-back with a ceramic oscillator. CB 01 and CB 02 en- sure a brief oscillation-build-up time over a wide range of supply voltage. The oscillator signal is fed to a divider, whose output signal serves for timing the counter connected downstream. The respective status of the counter is decoded, fed to the driving stage, and is then available at the outputs, pins 13 to 18 for interrogation of the push-button matrix.A key actuation recognised in the sensor decoder (pins 2 to 8) is accepted in the data memory. These data are fed to the modulation counter by means of a data multiplexer. The modulation counter generates an 11-bit data word in pulse interval modulation. By means of an amplifier, the data word is decoupled and made available at the output, pin 1.

The following driving stage with TA 13 performs three functions: It serves as driving stage, peak- value rectifier, and control voltage gain for the automatic gain control. The time constant of RA 16 and CA 14 is less than 5 ms, and thus shorter than the shortest pulse interval for the infrared transmitter. This peak-value rectification ensures that interfering signals below the useful signal amplitude are not transmitted. In combination with RA 14, the capacitor, CA 19, constitutes a low-pass filter which limits interfering, transient pulse peaks. A further time- constant component comprising RA 19 and CA 19 serves the purpose of broadening the output pulses to about 20 us, in order to ensure reliable “interrupt” triggering in the microcomputer by means of the switching transistor, TA 22. The automatic gain control has been designed in such a way that TA 08 in the final amplification stage is not over modulated. The AGC is transmitted from CA 14 through RA 16 and RA 17 directly to the amplifier, TA 07, by way of the control stage with TA 06. The control time constant is determined by CA 14, RA 16, and RA 17. An even faster control branch involving DA 09 is connected in parallel to the large con- trol time constant. Its purpose is to immediately control very strong signals, thus preventing them from overloading the amplifier, TA 12, or the peak-value rectifier comprising TA 13, RA 16, and CA 14, before the intrinsic control function becomes effective. This control branch is effective only for very strong signals. The RC network consisting of RA 24 and CA 24 serves as a Coarse filter for the operating vol- tage. RA 10 and CA 03 provide additional smoothing of the operating voltages for the first amplifier stages.


Electronic control unit with microcomputer 

 

The single-chip microcomputer, Thom 06, situated on the main chassis, operates at a clock frequency of 4 MHz and features an 8-kbyte ROM and a 256-byte RAM. It offers high processing speed for the extraordinarily versatile program. The data specific to the model, as well as the values selected by the operator for channel tuning, brightness, volume, etc., and the data from the service mode for the diverse standards, combination lock, and child-safe feature, are stored for an unlimited time in an EEPROM MDA 2061 (IR 73). The internal structure is evident from the block circuit diagram. The 5-V stand-by potential is present at pin 27. It is supplied to the clock oscillator, the power-mains flip-flop, and the re- set circuit, as well as the remote-control decoder and a portion of the RAM.

Through the rise of the 5-V stand-by potential, the reset circuit generates an internal RESET pulse. Subsequently, the mains FF is also set. The unit switches on with low level at pin 5. After starting of the set, a 5-V stabilised potential due to IR 81 is present at pin 40 for supplying the remaining stages in the microcomputer. This voltage is derived from the 13-V supply circuit; after the horizontal deflection stage has started operation, this is obtained from the high-voltage transformer, LL 53. From the detailed circuit diagram, it is evident the TR 83 becomes conductive simultaneously with the rise of the 13-V potential and holds pin 4 at L-level. TR 81 switches to the conductive state, and TR 83 blocks, only after CR 80 (100 pF) has been charged to about 7V through RR 77 and DR 78. 5V is now present at the reset input, pin 4, and releases the micro- computer. This process ensures that the ope- rating voltage and the clock frequency are correct during start of operation by the microcomputer. Simultaneously with IR 01, the EEPROM, IR 73, is reset at pins 6 and 12. The microcomputer first checks to determine the manner in which the switch-on command is effected. If no remote control signal has been received, and if the mains FF has not been set externally, a power mains interruption has occurred. This can also be the result of switching off and on by means of the mains power switch. By interrogation of the corresponding memory cell in the EEPROM, the microcomputer now checks whether the set was in the stand-by or “ON” mode prior to the mains interruption. In the latter case, it remains switched on at pro- gramme setting “1”; in the former case, the microcomputer switches back to the stand-by mode. The storage of the “ON” or stand-by mode in- formation is effected after setting of the mains FF in a byte under a specified address in the EEPROM. Only a single bit of the byte is re- quired for this information. Through the application of bit rotation, the “lifetime” of the EE- PROM is prolonged from 10000 to 8x10000 switching cycles, which can be viewed as equivalent to entry cycles. As already mentioned, the switching operation, “stand-by - set ON”, can be effected by means of the remote control or by an L-level externally supplied to the mains FF through pin 5. Resetting of the mains FF is feasible only with the use of the remote control. The externally supplied L-level must exhibit a minimal duration of 20 us. This possibility is utilised for the following purposes: 1. Switching on with the use of the program advancement key on the near control panel, by means of TR 23 and TR 24. 2. Switching on with the use of a video recorder in play-back operation, which thereby delivers the switching voltage, AV + 12V to plug 8 of the Scart jack. A positive pulse is thereby transmitted through CR 23 to the base of TR 24, which is thus rendered conductive momentarily. The clock oscillator operates at 4 MHz with the quartz crystal, QR 27, connected to pin 1. The clock frequency divided by the factor 4096 is delivered from pin 3 to the EEPROM MDA 2061 (IR 73). This close association of the clock pulses can lead to a total loss of memory in the EEPROM if, for example, the oscillator is loaded with less than 350 kQ at pin 1 as a result of measurements. Even a capacitance exceeding 20 pF can result in failure of the oscillator. This condition can be recognised by random flashing of the display segments. If the set is not switched off immediately in such a case, the contents of the EEPROM memory may be deleted after a brief period. The picture screen is then blanked. If the key +1 is pressed for a duration exceeding 4 s, the EEPROM accepts the analogue average values contained in the ROM of the CCU. Image noise now appears, and the channel data can be restored in the program settings. However, the model-specific manufacturing features are no longer present; they can be restored only by exchanging of the EEPROM during repair service.

For this reason, the measurement for functional testing on the CCU should not be per- — formed on the clock oscillator; instead, the pulses at the IM bus (port 4), such as pin 8 = CLOCK, should be measured. Pulses are always present at pins 9 (ident) and 7 (data), too, since an exchange of data is constantly in progress through the bidirectional DATA transmission line, at least for the digital audio signal processing.

The manner in which the CCU transmits or receives data on the DATA transmission line for specified addresses can be seen from figure 5. The other two lines are unidirectional from the CCU to the receiver EEPROM or audio section. The beginning of a new transmission is identified by L-level on the “ident” and “clock” links. Subsequently, the CCU transmits an 8-bit address beginning with LSB. With the following positive flanks on the clock line, the H- or L-levels are accepted by the modules connected the- reto. “Ident” now shifts to H-level, and the address is consequently evaluated there. The module intended by the address switches to READ or WRITE. Since the CCU “knows” where the data are to go or where they have originated, it transmits 8 or 16 further clock pulses. Data are thus transferred to the specified address or received from that address. In this case, too, the acceptance of data by the CCU proceeds with the positive flank of the clock signal, whereas the IC which has been addressed transmits the digital information with the negative flank. The termination of the data transfer is identified by a short negative pulse on the ident line, which causes the corresponding interface to store the data. The minimal clock period is 6 ys; that is, the maximal clock frequency is about 170 kHz. The 8-bit processor (CPU) with the program memory (ROM) and the working memory for the actual operating values (volume, brightness, automatic search, etc.), the RAM, is shown in the block circuit diagram . All operator controls and equipment features for the entire series of television sets are stored in the ROM. Which of these can in fact be called is governed by the values stored in the EEPROM. The 8-kbyte memory capacity is thereby nearly exhausted. The operating values stored in the RAM are lost if the set is completely switched off. If the personal values are to be retained, they can be entered into the EEPROM by pressing of the “S” key of the remote control for more than 4s, and retrieved by means of the software after the set has been switched on. Port 3 is devoted entirely to segment control for the display, whereas the digits are con- trolled through pins 23 to 26 of port 2. Pin 36 of port 2 yields an “enable” pulse which forms the Thomson bus and the PLL bus in conjunction with the clock and DATA signals of the IM bus.

The module which is addressed (PLL or video) recognizes whether or not it has been addressed from the number of clock pulses: 9 for video and 18 for PLL. By means of the Thomson bus, the microcomputer, Thom 06, controls the video analogue values, as well as a possibly, built-in BTX module. With the 18 bits of the PLL bus, it controls the divider ratio for the PLL as well as band in- formation, as already Known from the chassis F 14. Port 1, pin 33 (CL) and pin 35 (D) constitute the l2C bus for control of the teletext module.

Intermediate-frequency amplifier The IF amplifier consists of the emitter follower, TI 27, which serves the purpose of decoupling, the preamplifier, Tl 33, with a surface-wave fil- ter, Fl 29, connected downstream, and the Eu- ro-IF-IC, Il 36. For sets with AM sound, the audio IF signal is drawn from the emitter of TI 27. Because of its physical and electrical proper- ties, the surface-wave filter replaces conventional LC networks for IF signal' processing. It offers the following advantages:
— no necessity of alignment,
- temperature stability,
— no ageing problems,
- mechanical stability, and
- compact dimensions.
At the output, the picture carrier at 38.9 MHz and the sound carrier at 33.4 MHz are available selectively for the audio signal processing. Terminals 4 and 5 decouple the intermediate-frequency picture signal symmetrically to the IF- IC, 11 36. A three-stage, regulated, broad-band amplifier feeds the IF signal to the demodulator controlled by the picture carrier. The external resonant circuit, LI 41, of the demodulator is aligned to 38.9 MHz. The video signal is decoupled through a video post amplifier with low-pass characteristic to pin 11 of the IC for further video and audio signal processing. The scanning pulse for the control voltage generation is provided by the power processor at pin 7 of the IF-IC. The extent of intermediate- frequency control amounts to 60 dB. The high- frequency input stages in the tuner strips, adjustable with the use of PI 36, receive the de- layed AGC from pin 5 of the IF-IC.
Because of the synthesiser tuning system, an AFC is not re- quired. The AV operating state is signalised to the IF-IC with 5V at pin 2. The intermediate-frequency signal is blocked, and ultra white level is established at the video output, pin 11. In addition to standard B/G, which is employed in the Federal Republic of Germany, the IF-IC can also process standard L (such as French SECAM signals). For standard L, the control- panel microcomputer supplies about 6.5V to pin 2 of the IF-IC. As a result of this switching voltage, the video signal is fed in inverted form to the video output, pin 11. For this operating state, peak-white-level control is employed. The video signal now present at the output, pin 11, is of the same polarity as for standard B/G. Processing of the intermediate-frequency sound signal is performed by the IC, Il 71. Here, the picture and sound carriers are combined by means of the quasi parallel sound process. The intermediate-frequency sound signal is available at pin 12 for further audio signal processing at 5.5 MHz, and for stereo at 5.74 MHz.

PLL The circuit design employed here comprises a single-chip PLL with integrated pre divider and four band-switching outputs (band I, band Ill, hyperband, UHF). For a tuning process, the control-panel micro- computer furnishes the divider and band data by way of a data bus to the 18-bit shift register of the PLLIC, IT 20. If the “enable” pulse at pin 2 is at high level, the 18-bit data word can be entered into the shift register at pin 3 and into the downstream memory, with 18 clock pulses at pin 4. This process occurs anew for every channel selection call, but only once in each case.

The four bits of highest value contain the band information. This information is transmitted to the tuner by way of the transistors, TT 06, TT 07, and TT 08. Fourteen further bits signalize to the programmable dividers the dividing ratio with which the already pre divided tuner oscillator frequency at pin 15 is to be divided once again. For an engaged frequency-control loop, the result for the phase and frequency comparator stage amounts to 7812.5 Hz for each receiving channel. This value corresponds exactly to the reference frequency from the 4-MHz oscillator (pin 6/7) divided by 512 with a 9-bit counter. From the divided oscillator signal and the divided quartz reference signal, a signal is formed for comparison during tuning (pin 9). The transistor, TT 12, functions as a switch and operates as a controllable load resistor for the 30-V tuning voltage present at DT 14. Thus, a tuning voltage from 0.5 to 30V is available for the tuners. If the frequency at the output of the programmable divider alters as a result of a tuning process, the tuner oscillator is automatically adjust- ed by means of the tuning voltage until the oscillator and quartz frequencies are again identical. The smallest tuning step is 62.5 kHz. Thus, the 7-MHz bandwidth of the VHF standard raster can be covered by means of 112 fine-tuning steps.

 Video-chroma module 

In contrast to the previous series of television sets, the video and colour signal processing are performed on a common printed circuit board, the video-chroma module, in the present chassis design.
 
 Chroma signal processing In the present design, all active stages of the multistandard colour decoder are accommodated in a single integrated circuit, 1C 01. Signals corresponding to different standards, such as PAL or SECAM, are recognised and appropriately decoded without manual switching. A minimum of external switching ensures high operating reliability. From TV 49, the FBAS signal is supplied at low resistance to the chroma filters. Since a special cross-over network is necessary for each standard, IC 01 activates the PAL signal path with high level at pin 28 after recognition of the standard. The chroma filter, consisting of CC 24, LC 28, CC 28, RC 23, and CC 25, provides the required 4.43-MHz band-pass characteristic. TC 34 decouples the chroma signal through CC 34 to pin 15 of IC 01. The SECAM signal path is activated with high level at pin 27. The bell filter, CC 23/LC 23, characteristic for SECAM, is situated in the signal path. TC 29 operates as switchable emitter follower. The colour signal supplied capacitively to pin 15 of IC 01 first passes through a controlled amplifier stage. This measure is necessary for always maintaining the colour difference signals in a specified relationship to the Y-signal for differing intermediate-frequency transmission curves or mis tuning of the receiver. As actual value for control, the burst amplitude is em- ployed for the PAL signal, and the entire signal is employed for the frequency-modulated SE- CAM signal. CC 11 at pin 16 serves as filter for the control voltage. Direct-voltage negative feedback has been provided for stabilizing the operating point of the chromaticity signal control stage. CC 09 separates the negative feed- back signal from alternating voltage components. With the burst component, the controlled coJour signal is made available for standard identification. For this purpose, the signals are analised at the back porch, since the individual signals are characterized and mutually distinguished here. The identifying circuit in the decoder IC comprises three subassemblies: a. phase discriminator for comparing the burst phases of PAL and NTSC signals with the reference signal; b. frequency discriminator for deriving the H/2 signal during SECAM broadcasts; c. H/2 demodulator for PAL and SECAM signals, with logic circuit for the identification itself. The controlled burst signal is fed to the phase discriminator for PAL and NTSC signals, together with the colour signal. For phase comparison, the phase detector employs the colour difference signals as reference. The phase discriminator supplies the demodulated burst signals required for identification. The derivation of the H/2 signal from the frequency-modulated SECAM signal proceeds by means of a frequency discriminator which ope- rates as a quadrature demodulator and consists of an internal phase discriminator as well as an external phase-shift network, the so- called SECAM identification reference circuit, connected to pin 22 of IC 01. For forming the arithmetical average, the output signals from the PAL-SECAM discriminator are integrated in the external capacitor, CC 13, connected to pin 21 after the H/2 demodulation. The voltage arising here constitutes the actual identifying signal from which the control signals for pins 25 to 28 are derived in a subsequent comparator and logic circuit.

 The internal standard-identifying circuit checks whether the colour signal being fed to the decoder is decoded in conformance with the standard which is switched on. If a different standard prevails, the next standard interrogation is effected within 80 ms. For a black-and- white signal, the search operation proceeds continuously in a cyclical manner. Since the colour-synchronised demodulators are blocked during this period, no colour is displayed on the picture screen. If the interrogat- ed standard concurs with that of the incoming colour signal, the colour difference signals are switched through to the outputs, pins 1 and 3, after a brief colour switching delay. First, however, the switching voltage corresponding to the standard detected and prevailing at one of the terminals, 25 to 28, is increased to about 6 V; during the searching process, it is equal to about 2.5V. All other switching voltages remain at a level below 0.5V. From this point, the co- lour signal input filters and, for NTSC, the crystals of the reference oscillator as well as the co- lour sub carrier traps are switched on. For SECAM signals, a distinction must be made between an H-identification, in which the fo signals are evaluated at the back porch, and a V-identification, in which special, identifying signals are transmitted in the field blanking interval, are employed for evaluation. The original process was the V-identification. It is more reliable than the H-identification because of the longer V-identifying signals and the larger frequency deviation (Fig = 3.9 MHz; fir = 4.756 MHz). For the H-identification, only the normal fo- signal at the end of the back porch of the scanning pulse is available for evaluation. Since, however, space in the field blanking interval must often be reserved for other information (e.g. TELETEXT), the H-identification is employed preferentially. Besides the iC-internal, automatic H- or V-identification switch-ov- er (pin 23 open), the identification can also proceed forcibly. If pin 23 is connected to chassis earth, H-identification occurs; if pin 23 is connected to Up, V-identification is selected.
 
PLL circuit for generation of the reference signals For demodulating the quadrature-modulated PAL and NTSC colour signals, the reference signals, Ref. (R-Y) and Ref. (B-Y), are required, and are derived from the burst. A PLL circuit, consisting of a VCO, 2:1-divider, and phase discriminator, is employed for the purpose. In the present version, the oscillator operates at twice the frequency of the colour subcarrier. It offers the advantage that both reference signals are available with a phase difference of exactly 90° at the output of the divider circuit, without an external phase shifter and without balancing. In the phase discriminator of the PLL circuit, the (R-Y) reference signal is compared with the burst for PAL and NTSC decoding. The burst signal and the colour signal are supplied together from the output of the colour signal control stage directly to the phase discriminator in the case of PAL decoding, and through the intermediary of a hue-adjustment stage in the case of NTSC decoding. The tint correction is accomplished by means of DC control (2 to 4V) at pin 17. During the burst signal, the phase discriminator is activated by scanning pulses and provides a fine-tuning voltage to the VCO as a function of the phase difference between the burst and reference signals. This voltage is filtered externally by means of @ low-pass component at pin 18. The 8.86-MHz crystal of the reference oscillator is connected to pin 19. For frequency alignment of the reference oscillator, pin 17 must be connected to the chassis earth. The alignment is effected b y adjusting of CC 12, which is connected in series with the crystal, with simultaneous observation of the continuous colour sweep on the picture screen. The synchronisation o! the PLL circuit can thereby be switched off byth € burst. If12V is impressed on pin 17, Ug, the colour is forcibly switched on.


For PAL decoding, the burst signal is first blanked from the colour signal arriving from the control stage, in order to prevent the occurrence of interference from this source. The splitting of the colour signal into the two components, Fr-y and Fp-y, at the subcarrier frequency is effected in a transit-time decoder, which consists of the delay line, VC 11, and a matrix circuit. The colour signal, which has been separated from the burst, is amplified by 18 dB in an IC- internal amplifying and driving stage before driving the delay line, which is terminated at the in- put and output sides. The phasing alignment is effected with LC 17. This inductance has the function of compensating for the input and out- put capacitance of the delay line. The potentiometer, PC 18, is connected to the output of the delay line and is employed for performing the amplitude balancing of the transit-time decoder. The delayed signal is drawn from the slider of PC 18 and fed through pin 10 to the iC-internal matrix. Here, the non delayed signal is added to and subtracted from the delayed signal for deriving the two components, Fp-y and Fr-y, at the carrier frequency. In the (R-Y) demodulator, the PAL switch is connected upstream from the demodulator stage itself. This switch serves to cancel the phase position of the carrier-frequency colour signal component, Fr-y, which alternates at the horizontal scanning frequency. The colour signal demodulators are synchronous demodulators of the usual kind. The colour difference signals thus derived are blanked during the horizontal blanking intervals, in order to ensure the availability of pure achromatic values as clamping reference values in the colour difference channels, pins 1 and 3. The NTSC decoding is effected in the same manner. However, the PAL delay line is not present in this case; that is, only the direct (non delayed) signal is processed. The PAL switch is thereby inoperative. For the reception of sequential SECAM signals, a parallel intermediate switch, the so-called permutator, is included upstream from the demodulator. Thus, the non delayed colour signal and that delayed by means of VC 11 are alternately fed to the two synchronous demodulator stages in reversed sequence from line to line. A limiting stage is connected downstream from the permutator in each colour channel for eliminating the amplitude modulation of the frequency-modulated SECAM colour signals. Quadrature demodulators are employed for frequency demodulation of these signals. Each consists of an external phase-shifting circuit at pins 4 and 5, or pins 7 and 8, respectively, as well as a multiplying stage. The SECAM reference circuits rotate the phase of the corresponding colour signal at the respective achromatic frequency by 90° hence, the signal voltage vanishes at the demodulator output. Moreover, two deemphasis components, CC 08 at pin 2 and CC 07 at pin 6, are included for SECAM decoding. 8.4 Video signal processing For the purpose of sound carrier suppression, the video signal from the intermediate-frequency section is fed through a 5.5-MHz trap to pin 38 of the video processor IV 21 at about 2V, peak-to-peak. The video signal is amplified to about 3V peak-to-peak by the IC and is avail- able at the output, pins 39 and 41. The !C-inter- nal video switches, 1 and 2, are capable of transmitting signals from three different input sources: 1. internal video input, pin 38, 2. external video input, pin 36, and 3. external synchronous input, pin 40. The video signal from pin 39 leads to the teletext decoder or to the Scart jack. The peak-to-peak video signal at about 3V present at pin 41 is fed through TV 49 and the Y delay line (0.4 ps) to the Y-signal input, pin 13, at about 1V, peak-to-peak. A 4.43-MHz trap has been integrated into VV 53. For matching this Y-signal to the Y-signal to the level of matrix, it is amplified by a factor of 1.4.


The Y-signal reaches matrix 2 through video switch 3 as well as the contrast and brightness controls. The colour difference signals are provided by IC 01 at pins 11 and 12. They are clamped and likewise fed to matrix 2 at controlled amplitude. The RGB signals are present at its output. Two mutually independent RGB signals can be coupled into the signal path by means of the IC inputs, 3 to 8: 1. teletext signals for the built-in teletext decoder, and 2. external RGB signals from the Scart jack. In order to permit adjustment of the colour saturation for these RGB signals, too, they are converted to colour difference signals by matrix 1 and supplied to matrix 2, likewise at con- trolled amplitude. By means of the control-panel microcomputer, a 9-bit data word from the remote control is fed to pin 15 of the video processor and controls the video switches, 6, 8, 9, and 10. These switches determine which RGB input signal is to be processed further. The corresponding RGB source must provide a gate voltage in the form of a high level, at pin 10 for teletext, and at pin 9 for external RGB. This high level closes the switches 3 to 5 and opens the path for signals from matrix 1. If, for example, the VT key is actuated on the remote control, switches 7 to 10 assume the setting indicated; switch 6 closes upward. {f a teletext decoder has not been installed in the set, the high level is absent from pin 10, and switches 3 to 5 remain at the setting indicated. If the set is equipped with a teletext decoder, it supplies a high level to pin 10. Switches 3 to 5 change their setting and conduct the teletext signal through the adjusting stages to matrix 2. Besides the gating high level at pin 9, the horizontal and vertical synchronising signal at pin 40 must be combined with the RGB signal from the Scart jack. The synchronising pulses reach the pulse separation stage of IL 14 through the switches, 2 and 1, pin 4, as well as TV 49. By means of a data bus, the following commands are transmitted from the control-panel microcomputer to the video processor: - contrast adjustment, - brightness adjustment, - colour saturation adjustment, - video internal / external, - RGB inputs, internal /external, and - input switch, TV/ RGB. Every control command is transmitted as a 9- bit word through the DATA line to pin 15. A clock pulse (pin 14) is associated with each data bit. The “enable” line (pin 16) must assume low level prior to the first positive flank of the clock pulse, until all nine data bits have been entered with the clock pulses.

An IC-internal control system ensures that only 9-bit words are accepted. Three bits transmit the address, and six bits transmit the command. An evaluation of the signals is not feasible with- out the use of a storage oscilloscope. Matrix 2 furnishes the RGB signals, which are limited and clamped at a well-defined level for achieving correct gating during the horizontal and frame retrace times. The upper level limits the peak current.
Since the DC operating point must be defined exactly for the RGB signals, clamping is necessary in each channel. The capacitors, CV 31, CV 32, and CV 33 maintain the DC level of the clamping stages until the next scanning pulse. The horizontal and vertical fly-back blanking is effected with the aid of super sandcastle pulses in the video processor. 8.5 Automatic white- and black-level alignment Each vertical pulse on pin 31 (IC-IV 21) starts an \C-internal line counter which controls several functional stages for ensuring automatic white- and black-level alignment. An external black- and white-level alignment is no longer necessary with the present chassis design. The control system compensates for the drift of all video stages, including the final video stages. The control circuit operates sequentially during the frame alternation; this process is invisible to the viewer. The RGB signals are supplied to the picture tube circuit board from pins 24, 27, and 30. For the major portion of the modulation range for the picture tube, the transistors, TV 51, TV 61, and TV 71, are in the saturation range. In the proximity of the picture-tube blocking point, the picture-tube cathode current, amounting to 30 pA per system, is so low that the transistors operate in the active range. The automatic white- and blocking-point alignment is effected even before termination of the vertical retrace; this encompasses 23 line pulses at 64 ps each.

With the vertical component in the super sandcastle pulse, the beginning of the frame alternation is signalised to the video processor. A counter records 23 sandcastle line pulses and blanks the picture screen during this period. Exceptions are the lines 17, 18, and 19. Since they are not visible to the viewer of the picture screen, the video processor controls the picture-tube cathodes sequentially with a pulse corresponding to the white level. In the final RGB stage, the current flowing in each of the three RGB channels is conducted in succession through the PNP transistors, TV 51, TV 61, and TV 71. The resulting voltage drops at the collectors are fed through DV 55, DV 65, DV 75, and DV 95 on the cut-off line to pin 33 of the video processor and are stored in the capacitors CV 38, CV 36, and CV 34. For the duration of the measurement, pin 32 is connected to chassis earth through an electronic switch. From the ratio of the RGB beam cur- rents, a matrix element determines the optimal colour temperature for the white level.

For the lines 20, 21, 22, and 23, quasi white-level pulses are supplied to the final video stage. The picture-tube cathode current resulting therefore and amounting to about 30 pA for lines 21, 22, and 23, is very low. By way of PV 50, RV 65, and PV 70, the three voltage drops reach the cut-off line. In order to make measurable voltage drops available at pin 33, pin 32 is disconnected from chassis earth for the duration of the quasi black level measurement. For line 20, all three picture-tube systems are blanked. The leakage current of the final stage is stored as a voltage drop in CV 43. For lines 21, 22, and 23, three comparators in the video processor compare the respective RGB voltage drop at pin 33 with the charge on CV 43. The difference voltages are stored in the capacitors, CV 35, CV 37, and CV 39. In correspondence with the level of these voltages, the video processor sets the grey level, individually matched to the picture tube. The amplitude of the RGB output signals governs the white level, and its underlying direct voltage is decisive for the grey level. 8.6 Beam-current limiting The integrating capacitor required for beam- current limiting is connected to pin 35 (IC-IV 21), while the set value for limiting is supplied to pin 37. By means of the small time constant of RV 42 and CV 42, the transistor, TV 41, which normally blocks, is rendered conductive by the voltage jump on the cut-off line in rapidly from the 12-V operating voltage and causes the beam cur- rent to be limited. TV 50 serves the purpose of luminous-spot suppression. At the moment of switching off, the IC output voltages decay very rapidly. Thus, the picture tube would flash brightly. This is prevented by CV 50, which renders TV 50 conductive at the instant of switching off. The high level reaches the base of TV 81 and causes it to block for a few ms. After this time has elapsed, the high voltage has decayed sufficiently that a luminous spot can no longer arise. 9. Final RGB stages The positive RGB output signals delivered by the IC (IV 21) must be amplified and inverted in the final RGB stage for driving the picture tube. Since all three final video stages are of identical structure, the final blue stage is considered for explanation. For the middle setting of contrast and brightness, the output voltage of the RGB signals from the IC (IV 21) amounts to about 2.5Vpp, For this operating state, the picture tube re- quires a peak-to-peak cathode driving voltage of about 60V. For ensuring good constancy of the amplification factor and of the operating point, a sufficiently high amplification by the final stage over the entire video-frequency range without negative feed-back is necessary. For this reason, the present final AB stage has been selected. The transistor, TV 72, amplifies the video signal to about 60 Vpp. Rising signal flanks are there- by supplied through TV 70, DV 70, and RV 74 to the cathode, whereas falling signal flanks drive the picture tube through DV 71, FV.71, and RV 74. This circuit design permits fast recharging of the picture-tube cathode capacitance and improves the frequency response in the high- frequency range. The transistor, TV 81, is connected as emitter follower and serves as common low-resistance base point for the final RGB stage. Since CV 81 and CV 50 continue to maintain the base voltage of TV 81 for a brief period through TV 50 when the set is switched off, TV 81 blocks and thus prevents flashing of the picture screen. The transistors, TV 51, TV 61, and TV 71, deter- mine the cut-off voltages for the video proces- sor. The functional sequence has already been explained in section 8 for the video chroma module.

 Horizontal deflection stage
The signals for triggering the horizontal deflection stage are prepared in the power processor IC, IL 14. The core of the IC is a PLL circuit and comprises a VCO which oscillates at 500 kHz and whose output signal is decreased by a fac- tor of '/42 to the scanning frequency in a divider. A phase comparator compares this frequency with that of the line-synchronising pulses from the amplitude filter. If the VCO exhibits a deviation in phase or frequency, a control voltage readjusts the VCO until both signals concur exactly in frequency and phase. A 500-kHz ceramic oscillator operates externally in series resonance between pins 18 and 19. The PLL phase-shift circuit is connected to pin 17. This new circuit technology renders a scanning frequency adjustment superfluous. The RC network at pin 22 smooths the oscillator frequency which has been divided by 32. The control time constant is adjusted by means of a charging and discharging current con- trolled by the IC. The unit is switched to AV operation at: — low level at pin 23, - absence of a video signal, and - noisy signal (for the purpose of obtaining a larger capture range). For a good signal-to-noise ratio, the system switches to a large control time constant. Within the IC, the scanning pulses already synchronised at the transmitting station are transferred to four switching stages: - for processing of the horizontal component in the sandcastle puise; - for deriving the control voltage in the phase comparator for the phase shifter, phi, where- by a scanning pulse derived from the diode- splitting transformer is supplied to pin 12 of IL 14 as a reference for the phase comparison, thus defining the line beginning or horizontal position; - for line sawtooth preparation; - for driving the pulse-shaper phase shifter, * phi, which together with the line sawtooth controls the time slot and pulse width of the output signal at pin 10. During the switch-on phase, the charging of CL 16 results in a slowly progressing pulse broadening of the driving signal at the scanning frequency at pin 10. Thus modified, the signal prevents overloading of TL 31 during the start- ing phase. For the steady state, the scanning pulse width amounts to 26 us, regardless of the operating voltage and of any switch-off delay of the deflection transistor. The horizontal driving transistor, TL 25, amplifies the scanning-frequency signal coming from pin 10, in order to generate the required base saturation current at TL 31 by means of the driver transformer, LL 32. The RC network consisting of RL 29 and CL 29 attenuates the voltage peaks which arise when TL 25 is switched off. For starting operation, TL 25 receives its starting voltage from the switching power supply through LP 04, terminal 20. During steady-state operation, this function is assumed by U 5 from the diode-split transformer. The transistor, TL 31, operates as a switch, which is connected in parallel with the diodes, DL 46 and DL 41. Inverse operation of the transistor is thus prevented. Moreover, the diodes constitute a part of the E/W diode modulator. The functional principle of the horizontal deflection circuit in the steady state is explained on the basis of the chassis diagram.

The most important components are designated as follows:
BL 46: deflection coil CL 44: forward-sweep and tangent capacitor CL 48: horizontal fly-back capacitor TL 31: switching transistor DL 46: switching diode The fly-back capacitor, which is effective during the blocking phase of TL 31, is a series net- work consisting of CL 48 and CL 44. The voltage and current curves during the time period of one line are shown in figure 14. The following sequence is thereby evident: At the end of the forward sweep time, ty, TL 31 is blocked by a corresponding base driving signal. The energy stored in the deflection coil and in the diode split transformer gives rise to rapid charging of CL 48. At the end of the first half of the horizontal fly-back at time tg, the charging attains its maximum. The current passes through zero and changes direction during the second half of the fly-back phase. CL 48 now discharges and transfers the energy back to the deflection coil (resonant circuit principle). At the end of the horizontal fly-back, tg, the voltage passes through zero and assumes negative values. At this time, DL 46 becomes conductive. Thus, CL 48 is short-circuited, and the forward sweep phase begins. The energy of the circuit is now present in the deflection coil. Consequently, current flows from the deflection coil to the forward-sweep capacitor, CL 44, and charges it during the first half of the for- ward-sweep phase. This process is completed at the middle of the frame, tq. The current again passes through zero, changes direction, and flows from C 44 through TL 31 back to the deflection coil. A prerequisite, however, is that TL 31 be driven correspondingly at the base. For switching off in a well-defined manner at the end of the forward sweep, ts, the base of TL 31 receives a negative pulse from the driving stage; this pulse is somewhat advanced in time. During this period, the charge carriers must be removed very rapidly from the base zone of TL 31. This process is supported by the RC net- work connected to the base. Otherwise, the power loss at TL 31 would be larger than is permissible.

Practical design of the circuit A portion of the deflection current flows through the bridge coil, LG 11, and CL 42 from the deflection coil through the linearity coil, LL 46, to the chassis earth. Because of the ope- ration of the E/W diode modulator, portions of the deflection current also flow through CL 44, DL 46, and DL 41 to the chassis earth (refer to the description of the E/W modulator). An attenuation circuit is connected in parallel with CL 42. RL 43, DL 42, and CL 43 attenuate the inherent forward-sweep resonance in the event of sudden load changes, which could result in undesirable horizontal phase modulation in the image. The interference suppressor, consisting of LL 56, RL 56, and CL 56, attenuates the harmonics which arise in the deflection circuit. The energy required for the deflection process is furnished by LL 53 at winding tap 9/10. When TL 31 is switched on, current flows from U 2 through the transformer winding 10/9, thus supplying the necessary magnetic field energy. In the secondary circuits, the secondary ope- rating voltages are obtained from the scanning pulses with the use of rectifying diodes.

East-west correction circuit 

The 110° picture tube employed for the present chassis design requires an east-west correction circuit which modulates the horizontal deflection current parabolical by about 7 per cent at the vertical frequency. An east -west correction is not required for chassis F 16, fitted with a 90° degree picture tube. However the east-west control stage and also the diode-modulator remain in the chassis for the purpose of horizontal width adjustment. Accordingly, the existing circuit differences between the two chassis F 15 and F 16 are very small: e.g. pin 1 and pin 2 of IG are not controlled and the parabolic- and the trapezoidal waveform adjustment is not required and the potentiometer RG 68 for east-west adjustment has been replaced by the fixed resistor RG 24.

 East-west driving circuit The preparation of the east-west driving signal is effected in the IC, IG 01. From the difference between the input currents at pin 1 (vertical sawtooth) and pin 2 (adjustable direct voltage), a parabola is formed at the output of the multi- plier. If the arithmetical average of the saw- tooth current at pin 1 is equal to the current at pin 2,a symmetrical parabola results at the output of the multiplier (figure 15). Hence, an east- west trapezoidal correction can be performed with PG 02.
 
 The output current from the multiplier allows a voltage to arise in proportion to the current at the externally connected impedance. It is com- pared with a linear sawtooth voltage at the horizontal frequency in the comparator connected downstream. The direct voltage position of the sawtooth voltage can be adjusted with the use of PG 12. It influences the picture width. The pulse-width-modulated signal from the comparator controls the final stage operating in the D-mode. An IC-internal diode returns the excess energy drawn from the final horizontal scanning stage to U 5. The integration of the output signal at pin 5, which is switched at the horizontal scanning frequency, is performed by the coupling coil, LG 11.
 The vertical-frequency parabola is now present at the east-west diode connecting point (refer to the detailed circuit diagram). The pulse- width-modulated output signal is linked through PG 08 and RG 11 with CG 06 as negative feedback, which is also utilised for the east- west amplitude adjustment. The parabolic voltage thus arising is added to the signal from the multiplier (pin 7). For static and dynamic picture-width stabilisation, a control signal proportional to the beam current is fed through RG 06 to pin 7. It is derived from the base point of the high-voltage winding, terminal 5. 11.2E£/W diode modulator A diode modulator is employed for modulating the horizontal deflection current. In spite of the amplitude modulation of the deflection cur- rent, the circuit design in the form of a bridge network prevents reaction with the magnetisation current in the primary winding of the diode-split transformer. Hence, undesirable modulation cannot occur in the high-voltage winding. The bridge consists of two parallel-resonant circuits connected in series.
 
 For providing a better understanding, the possible extreme conditions, switch S in IG 01 open and closed, are explained first. \f the switch is open, the capacitor, CG 11, is charged to the open-circuit voltage, Um. It corresponds to the integrated feedback voltage on CL 41 during a scanning period of 64 us. The circuit is aligned in such a way that the pulse voltage drop due to the deflection cur- rent in the bridge coil, LG 11, is of the same magnitude as the voltage prevailing at the diode connecting point during fly-back. The bridge condition is thus fulfilled. No current flows through the coupling coil, LG 11. If the switch S is open, the entire deflection current flows exclusively through the bridge coil, LG 11, and CL 42 to chassis earth during the forward sweep. If a controlled direct voltage source is connect- ed to pin 5 of IG 01 with the switch S open, the two limiting cases can be simulated as follows for the diode modulator: 1. 24V at the diode connecting point, = switch open; 2. OV at the diode connecting point, * switch closed. As governed by the direct voltage prevailing at the diode connecting point, a differing distribution results for the horizontal fly-back pulse voltage from the diode-split transformer. In the first limiting case, as already mentioned, the deflection current flows only through the bridge coil and CL 42 to chassis earth during the forward sweep phase (picture width too small, and east-west cushion error). In the second limiting case, the deflection current circuit closes during the forward sweep directly through CL 44 and DL 46, or TL 31, without alternate routing (CG 11 cannot charge). In correspondence with the dc-level set at the coupling coil, a differing current distribution is established through CL 44 and the bridge coil, LG 11. If a parabolic voltage at the vertical frequency, resulting by integration of the output signal from IG 01, pin 5 through the coupling coil, is impressed, the horizontal deflection current is modulated parabolically. The desired east- west correction is thus achieved.
 
 Vertical deflection stage The circuit technology employed here is nearly identical to that for the chassis F 11B and F 14. Signal-processing stages, such as the vertical oscillator, differential amplifier, and modulator, are integrated into the power processor IC, IL 14. Only the final vertical stage is connected externally. The signal processing is explained first: The capacitor, CF 01, connected to pin 5 of IL 14, is charged through RF 22 and RF 01 with a nearly constant current originating from U 7. This charging process is visible in the rising saw- tooth form at terminal 5. Discharging of CF 01 is effected within the IC by each vertical synchronising pulse. For 60-Hz operation, an additional current source is connected in parallel with the external charging resistor for CF 01. This ensures that the vertical amplitude remains constant during 60-Hz operation, too. An |C-internal standard-recognition circuit controls this process. For 50 Hz, 12V is present at pin 24, for 60 Hz, 6V, and without any signal, OV. At the same time, this output signal serves as muting contro! for a few set versions for export. The vertical sawtooth present at pin 5 is transferred at low resistance to pin 3, and by way of RF 11 to pin 2 of the IC.
 
Vertical blanking protective circuit The vertical sawtooth voltage fed to pin 2 is supplied through the differential amplifier al- ready mentioned to an IC-internal switching transistor not explicitly shown in the circuit dia- gramme. This transistor is conductive for each vertical fly-back. If no vertical fly-back is recognised, or if the fly-back is of duration longer than the blanking time, the protective circuit responds. Consequently, the lower level of the super sandcastle pulse at pin 11 remains at about 3V (figure 23). Thus, the picture tube is effectively protected against damage during vertical failure, by means of the video processor, which decreases the beam current.

 Vertical output stage
As can be seen from the circuit diagram, the final vertical stage includes only a single active component, the silicon control rectifier, DL 21. The deflection coil, BL 55, is connected as a bridge from the operating voltage source, U 5, 21V, and the diode split transformer winding, 4/ 11, the inherent generator. It is thus direct-current coupled. The diode-split transformer furnishes all of the energy for vertical deflection. The generator winding supplies horizontal scanning pulses at about 240V, peak-to-peak. It is alternately connected unilaterally to chassis earth by the diode, DL 22, during the horizontal fly-back phase, and by the silicon control rectifier, DL 21, during the forward sweep phase. Two extreme states serve to illustrate how a bipolar current arises in the deflection coil. - 1. The silicon control rectifier does not trigger. - 2. The silicon control rectifier always triggers. In the first case, a normal clamping circuit would be involved. Terminal 4 of the diode-split transformer winding would be clamped to chassis earth during the fly-back phase. The voltage curve presented in figure 24 a would be measured at terminal 11 of the winding. The low-pass filter comprising LL 32 and CL 54 would allow a high positive voltage to arise on CL 54. Hence, a high current could flow from CL 54 through the deflection coil and RF 17 to U 5. This case does in fact occur during the vertical fly-back, in order to deflect the electron beam to the starting position for the next frame as fast as possible. In the second case, the winding is always connected to chassis earth with terminal 4. The direct voltage of OV which thereby arises at terminal 11 is shown..

In this operating state, a current would now flow in the opposite direction, from U 5 through RF 17 and the deflection coil to CL 54. Both limiting cases illustrated indicate that this circuit is capable of allowing current to flow through the deflection coil in both directions. For reasons of linearity, the driving range has been utilised only minimally. Hence, maximal voltages of 23 + 20V are established at CL 54. (23 to 43 V correspond to the upper half of the picture; 23 to 3V correspond to the lower half [figure 25].) Residual components at the horizontal frequency are negligible, since the reactive component for the vertical deflection coil is very large at this frequency and allows practically no cur- rent to flow. How does a vertical sawtooth arise from horizontal scanning pulses? At the beginning of the picture at the upper edge of the frame, the modulator supplies narrow pulses at the scanning frequency to the gate of the silicon control rectifier. These make it possible for the diode, DL 22, to clamp the voltage in the integrating network, LL 32 and CL 54, at about 43.5V. With every further line which is scanned, the gate triggering signal is broadened; the clamping time for DL 22 there- by becomes shorter. The clamping voltage arising in the integrating network continually decreases in proportion thereto. Vertical saw- tooth components are thus generated for driving the current through the deflection system. Extinction of the triggered silicon control rectifier is effected with each scanning pulse from the winding, 4/11.
Operating-point stabilization and tangential correction The negative feedback signal results from the voltage drop over the reference resistor, RF 17, and is supplied through RF 15, PF 14, and RF 16 to pin 2 of the IC, IL 14. Among other purposes, it serves to stabilise the picture amplitude. PF 14 in the negative feedback path determines the vertical amplitude. The tangential correction is performed by DF 17, DF 18, RF 13, and RF 18. In the vertical mid- frame zone, the voltage drop across the reference resistor, RF 17, is so small that no current flows through the diodes. In the upper and lower fourths of the picture, the threshold values are exceeded. The diodes now conduct and increase the negative feedback. The deflection current decreases. RF 18 increases the corrective current during the conductive phase of DF 17 and DF 18; the temperature drift is thereby reduced. A slight nonlinearity of the sawtooth is compensated by RF 13, which allows a non symmetrical current to flow between the upper and lower edges of the picture. A dc -level adjustable with the use of PF 02 provides the vertical position correction through pin 1 of the IC.

   COLOR TV SCANNING AND POWER SUPPLY PROCESSOR TEA2029C

DESCRIPTION
The TEA2029C is a complete (horizontal and vertical)
deflection processor with secondary to primary
SMPS control for color TV sets.

DEFLECTION .CERAMIC 500kHz RESONATOR FREQUENCY
REFERENCE .NO LINE AND FRAME OSCILLATOR ADJUSTMENT
.DUAL PLL FOR LINE DEFLECTION .HIGH PERFORMANCE SYNCHRONIZATION .SUPER SANDCASTLE OUTPUT .VIDEO IDENTIFICATION CIRCUIT .AUTOMATIC 50/60Hz STANDARD IDENTIFICATION
.EXCELLENT INTERLACING CONTROL .SPECIALPATENTED FRAME SYNCHRO DEVICE
FOR VCR OPERATION .FRAME SAW-TOOTH GENERATOR .FRAME PHASE MODULATOR FOR THYRISTOR
SMPS CONTROL .ERROR AMPLIFIER AND PHASE MODULATOR
.SYNCHRONIZATION WITH HORIZONTAL
DEFLECTION .SECURITY CIRCUIT AND START UP PROCESSOR.

GENERAL DESCRIPTION
This integrated circuit uses I2L bipolar technology
and combines analog signal processing with digital
processing.
Timing signals are obtainedfrom a voltage-controlled
oscillator (VCO) operatingat 500KHzby means
of a cheap ceramic resonator. This avoids the
frequency adjustment normally required with line
and frame oscillators.
A chain of dividers and appropriate logic circuitry
produce very accurately defined sampling pulses
and the necessary timing signals.
The principal functions implemented are :
- Horizontal scanning processor.
- Frame scanning processor. Two applications are
possible :
- D Class : Power stage using an external
thyristor.
- B Class : Powerstageusing an externalpower
amplifier with fly-back generator
such as the TDA8170.
- Secondary switch mode power regulation.
The SMPS output synchronize a primary I.C.
(TEA2260/61)at the mains part.
This concept allows ACTIVE STANDBY facilities.
- Dual phase-locked loop horizontal scanning.
- High performance frameand line synchronization
with interlacing control.
- Video identification circuit.
- Super sandcastle.
- AGC key pulse output.
- Automatic 50-60Hz standard identification.
- VCR input for PLL time constant and frame synchro
switching.
- Frame saw-tooth generator and phase modulator.
- Switchingmode regulated power supplycomprising
error amplifier and phase modulator.
- Security circuit and start-up processor.
- 500kHzVCO
The circuit is supplied in a 28 pin DIP case.
VCC = 12V.
Synchronization Separator
Line synchronization separator is clamped to
black level of input video signal with synchronization
pulse bottom level measurement.
The synchronization pulses are divided centrally
between the black level and the synchronization
pulse bottom level, to improve performance on
video signals in noise conditions.
Frame Synchronization
Frame synchronization is fully integrated (no external
capacitor required).
The frame timing identification logic permits automatic
adaptation to 50 - 60Hz standards or non-interlaced
video.
An automatic synchronization window width system
provides :
- fast frame capture (6.7ms wide window),
- good noise immunity (0.4ms narrow window).
The internal generator starts the discharge of the
saw-tooth generator capacitor so that it is not disturbed
by line fly back effects.
Thanks to the logic control, the beginning of the
charge phase does not depend on any disturbing
effect of the line fly-back.
A 32ms timing is automatically applied on standardized
transmissions, for perfect interlacing.
In VCR mode, the discharge time is controlled by
an internal monostable independent of the line
frequency and gives a direct frame synchronization.
Horizontal Scanning
The horizontalscanningfrequencyis obtainedfrom
the 500kHz VCO.
The circuit uses two phase-locked loops (PLL) :
the first one controls the frequency, the second one
controls the relative phase of the synchronization
and line fly-back signals.
The frequency PLL has two switched time constants
to provide :
- capture with a short time constant,
- good noise immunity after capture with a long
time constant.
The output pulse has a constant duration of 26ms,
independent of VCC and any delay in switching off
the scanning transistor.
Video Identification
The horizontal synchronization signal is sampled
by a 2ms pulse within the synchronization pulse.
The signal is integrated by an external capacitor.
The identification function provides three different
levels :
- 0V : no video identification
- 6V : 60Hz video identification
- 12V : 50Hz video identification
This information may be used for timing research
in the case of frequency or voltage synthetizer type
receivers, and for audio muting.
Super Sandcastle with 3 levels : burst, line flyback,
frame blanking
In the event of vertical scanning failure, the frame
blanking level goes high to protect the tube.
Frame blanking time (start with reset of Frame
divider) is 24 lines.
VCR Input
This provides for continuous use of the short time
constant of the first phase-locked loop (frequency).
In VCR mode, the frame synchronization window widens out to a search window and there is no
delay of frame fly-back (direct synchronization).
Frame Scanning
FRAME SAW-TOOTH GENERATOR. The current
to charge the capacitoris automatically switched to
60Hz operation to maintain constant amplitude.
FRAME PHASE MODULATOR (WITH TWO DIFFERENTIAL
INPUTS). The output signal is a pulse
at the line frequency, pulse width modulatedby the
voltage at the differential pre-amplifier input.
This signal is used to control a thyristor which
provides the scanning current to the yoke. The
saw-tooth output is a low impedance,however, and
can therefore be used in class B operation with a
power amplifier circuit.
Switch Mode Power Supply (SMPS) Secondary
to Primary Regulation
This power supply uses a differential error amplifier
with an internal reference voltage of 1.26V and a
phase modulator operating at the line frequency.
The powertransistor is turnedoff bythe falling edge
of the horizontal saw-tooth.
The ”soft start” device imposes a very small conduction
angle on starting up, this angle progressively
increases to its nominal regulation value.
The maximum conductionangle may be monitored
by forcing a voltage on pin 15. This pin may also
be used for current limitation.
The outputpulse is sent to the primaryS.M.P.S. I.C.
(TEA2261) via a low cost synchro transformer.
Security Circuit and Start Up Processor
When the security input (pin 28) is at a voltage
exceeding 1.26V the three outputs are simultaneously
cut off until this voltagedrops below the 1.26V
threshold again. In this case the switch mode
power supply is restarted by the ”soft start” system.
If this cycle is repeated three times, the three
outputs are cut off definitively. To reset the safety
logic circuits, VCC must be zero volt.
This circuit eliminates the risk to switch off the TV
receiver in the event of a flash affecting the tube.
On starting up, the horizontal and vertical scanning
functions come into operation at VCC = 6V. The
power supply then comes into operation progressively.
On shutting down, the three functions are interrupted
simultaneously after the first line fly-back.




APPLICATION INFORMATION ON FRAME
SCANNING IN SWITCHED MODE:


Fundamentals (see Figure 80)
The secondary winding of EHT transformer provides
the energy required by frame yoke.
The frame current modulation is achieved by
modulating the horizontal saw-tooth current and
subsequent integration by a ”L.C” network to reject
the horizontal frequency component.

General Description
The basic circuit is the phase comparator ”C1”
which compares the horizontal saw-tooth and the
output voltage of Error Amplifier ”A”.
The comparator output will go ”high” when the
horizontal saw-tooth voltage is higher than the ”A”
output voltage. Thus, the Pin 4 output signal is
switched in synchronization with the horizontal frequency
and the duty cycle is modulated at frame
frequency.
A driver stage delivers the current required by the
external power switch.
The external thyristor provides for energy transfer
between transformer and frame yoke.
The thyristor will conduct during the last portion of
horizontal trace phase and for half of the horizontal
retrace.
The inverse parallel-connected diode ”D” conducts
during the second portion of horizontal retrace and
at the beginning of horizontal trace phase.
Main advantages of this system are :
- Power thyristor soft ”turn-on”
Once the thyristor has been triggered, the current
gradually rises from 0 to IP, where IP will reach
the maximumvalue at the end of horizontal trace.
The slope current is determined by, the current
available through the secondary winding, the
yoke impedance and the ”L.C.” filter characteristics.
- Power thyristor soft ”turn-off”
The secondary output current begins decreasing
and falls to 0 at the middle of retrace. The thyristor
is thus automatically ”turned-off”.
- Excellent efficiency of power stage dueto very
low ”turn-on” and ”turn-off” switching losses.

Frame Flyback
During flyback, due to the loop time constant, the
frame yoke current cannot be locked onto the
reference saw-tooth. Thus the output of amplifier
”A” will remain high and the thyristor is blocked.
The scanning current will begin flowing through
diode ”D”. As a consequence, the capacitor ”C”
starts charging upto the flyback voltage.The thyristor
is triggeredas soon as the yoke current reaches
the maximum positive value.

CHASSIS ICC5 Switched mode power supply transformer


A switched mode power supply transformer, particularly for a television receiver, including a primary winding and a secondary winding with the primary winding and the secondary winding each being subdivided into a plurality of respective partial windings. The partial windings of the primary lie in a first group of chambers and the partial windings of the secondary lie in a second group of chambers of a chamber coil body, and the chambers of both groups are nested or interleaved with one another.







1. A switched mode power supply transformer, particularly for a television receiver, comprising in combination:
a primary winding and a secondary winding, with said primary winding being subdivided into three partial windings and said secondary winding being subdivided into two partial windings;
a chamber coil body having a plurality of chambers;
said partial windings of said primary winding being disposed only in a first group of said chambers, and said partial windings of said secondary winding being disposed only in a second group of said chambers, with each of said partial windings being disposed in a respective one of said chambers;
said chambers of said first group being interleaved with said chambers of said second group such that they alternate in sequence with said primary partial windings and said secondary partial windings being alternatingly disposed in five successive said chambers, so as to generate the major operating voltage at said secondary winding;
an additional secondary winding for generating a further operating voltage, said additional secondary winding likewise being subdivided into a plurality of partial windings; and,
said partial windings of said additional secondary winding are disposed only in respective said chambers of said second group below any of said partial windings of said secondary winding.


2. A transformer as defined in claim 1 wherein the total number of said chambers is six.

3. A transformer as defined in claim 1 wherein the width of the narrowest of said chambers is approximately 1 mm.

4. A transformer as defined in claim 1 or 2 wherein the widths of said chambers are different.

5. A transformer as defined in claim 1 or 2 wherein the total width of all of said chambers is only approximately 20 mm, whereby a flat and optimally coupled transformer is realized.

6. A transformer as defined in claim 1 wherein said additional secondary winding provides an operating voltage for a load which has a fluctuating current input.

7. A transformer as defined in claim 1 wherein said partial windings of said additional secondary winding are connected in parallel.

8. A transformer as defined in claim 1 wherein said partial windings of said primary winding are connected in series.

9. A transformer as defined in claim 1 or 8 wherein said partial windings of said secondary winding are connected in series.

10. A transformer as defined in claim 1 further comprising a plurality of auxiliary primary windings disposed in one chamber of said first group which is disposed in approximately the center of said first group and above the said partial winding of said primary winding disposed in said one chamber of said first group.

11. A transformer as defined in claim 1 wherein all of said partial winding disposed in said chambers of both said groups are wound with wire having the same diameter.

12. A switched mode power supply transformer as defined in claim 1 or 10 wherein: said coil body has six of of said chambers; said additional secondary winding is subdivided into three said partial windings; and two of said partial windings of said additional secondary winding are disposed below respective ones of said partial windings of said secondary winding and the third said partial winding of said additional secondary winding is disposed in the sixth said chamber.

13. A switched mode power supply transformer as defined in claim 10 further comprising at least one further secondary winding disposed in one of said chambers of said second group above any partial secondary winding present in said one of said chambers.

14. A switched mode power supply transformer, particularly for a television receiver, comprising in combination:
a primary winding and a secondary winding, with said primary winding and said secondary winding each being subdivided into a plurality of partial windings;
a chamber coil body having a plurality of chambers;
said partial windings of said primary winding being disposed only in a first group of said chambers, and said partial windings of said secondary winding being disposed only in a second group of said chambers with each of said partial windings being disposed in a respective one of said chambers;
said chambers of said first group being interleaved with said chambers of said second group such that said primary partial windings and said secondary partial windings are alternatingly disposed in successive said chambers, so as to generate the major operating voltage at said secondary winding;
an additional secondary winding for generating a further operating voltage, said additional secondary winding likewise being subdivided into a plurality of partial windings, and said partial windings of said additional secondary winding are disposed only in respective said chambers of said second group below any of said partial windings of said secondary winding.


15. A switched mode power supply transformer as defined in claim 1 or 14 wherein each of said partial windings of said primary winding contains the same number of turns and each of said partial windings of said secondary winding contains the same number of turns.

Description:

BACKGROUND OF THE INVENTION
The present invention relates to a switched mode power supply transformer, particularly for a television receiver.
In communications transmissions devices, particularly in television receivers, it is known to effect the desired dc decoupling from the mains by means of so-called switched mode power supply transformers. Such switched mode power supply transformers are substantially smaller and lighter in weight than a mains transformer for the same power operating at 50 Hz, because they operate at a significantly higher frequency of about 20-30 kHz. Such a switched mode power supply transformer (hereinafter called SMPS transformer) generally includes a primary side with a primary winding serving as the operating winding for the switch and further additional auxiliary windings, as well as a secondary side with a secondary winding for generating the essential operating voltage and possibly further additional windings for generating further operating voltages of different magnitude and polarity. The secondary and primary are insulated from one another as prescribed by VDE and have the necessary dielectric strength so that there is no danger of contact between voltage carrying parts on the secondary. A switched mode power supply (SMPS) circuit for a tv-receiver is described in U.S. Pat. No. 3,967,182, issued June 29, 1976.
A further requirement placed on such an SMPS transformer is that the stray inductance at least of the primary winding and of the secondary winding should be as small as possible. With too high a stray inductance, a transient behavior may develop during the switching operation which would not assure optimum switch operation of the switching transistor connected to the primary winding and would endanger this transistor by taking on too much power. Moreover, an increased stray inductance undesirably increases the internal resistance of the voltage sources for the individual operating voltages.
It is known to design the windings for such transformers as layered windings. Such layered windings, however, contain feathered intermediate foil layers and, after manufacture, generally require that the coil or the complete transformer be encased in order to insure VDE safety. Use as a chamber winding in television receivers presently does not take place because of the problems to be discussed below. A chamber winding would have the particular advantage that it could be wound more easily and economically by automatic machines. when using a chamber winding for a switched mode power supply, the detailed insulation between the primary and the secondary would be realized initially by two chambers with one of these chambers being filled only with the windings of the primary and the other of these chambers being filled only with the windings of the secondary. However, with such an arrangement there would exist only slight coupling between the primary and the secondary and thus an undesirably high stray inductance. If, on the other hand, the number of chambers were selected to be substantially larger, the transformer becomes more expensive and unnecessarily large. Moreover, a larger core would be required. Consequently, in the past, no television receiver has been introduced that included an SMPS transformer.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide an SMPS transformer designed in the chamber wound technique which permits economical automatic winding, i.e. can be wound with but a single type of wire, has a structure which is spatially narrow and as flat as possible, provides the required insulation between the primary and secondary windings, and has a low stray inductance. The transformer should not be encased or saturated and nevertheless should produce no interfering noise during operation. The transformer should be able to be held in a circuit board without mechanical aids merely by its connecting terminals which are soldered to the circuit board.
The above object is basically achieved according to the present invention in that the transformer for a switched mode power supply, particularly for a television receiver, comprises: a primary winding and a secondary winding with the primary and secondary windings each being subdivided into a plurality of partial windings; and a chamber coil body with a plurality of chambers; and wherein the partial windings of the primary winding are disposed in a first group of chambers of the coil body, the partial windings of the secondary winding are disposed in a second group of chambers of the coil body, and the chambers of the first and second groups are interleaved.
Due to the fact that the individual windings or partial windings of the primary are disposed only in chambers of the first group and the windings or partial windings of the secondary are disposed only in chambers of the second group, i.e. primary and secondary are distributed to separate chambers, the necessary dielectric strength between primary and secondary is assured. By dividing each of the primary and secondary windings to a respective plurality or group of chambers and, due to the interleaved or nested arrangement of the chambers of the primary and the secondary, the desired fixed coupling between primary and secondary, and thus the desired low stray inductance at the primary and secondary, are realized. It has been found that a total number of chambers in the order of magnitude of six constitutes an economically favorable solution. With a smaller number of chambers, the coupling between primary and secondary is reduced. With a larger number of chambers, however, either the individual chambers become too small or the entire transformer, and particularly the core, become too large.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram for a preferred embodiment of a switched mode power supply transformer according to the invention.
FIG. 2 is a schematic partial sectional view showing the distribution of the individual windings of FIG. 1 to different chambers according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a transformer intended for a switched mode power supply for a television receiver with a power output between 40 and 150 watts. The transformer includes a primary side P and a secondary side S which, while maintaining the required dielectric strength of, for example, 10,000 V, are galvanically decoupled or separated from one another. The primary side P includes a primary winding 1 which, as the operating winding, will lie in the collector circuit of a switching transistor switched at about 20-30 kHz. The primary winding 1 is divided into three partial windings 1a, 1b and 1c which are connected in series. When utilized in a television receiver, the beginning of partial winding 1a and the end of partial winding 1c are connected into the collector circuit of the switching transistor, while the taps between the partial windings 1a-1b and 1b-1c are not utilized, but rather form supporting points for the connection of the terminals of the partial windings. The primary side P also includes an additional winding 3 which feeds the feedback path with which the primary winding 1a-1c is designed as a self-resonant circuit. Moreover, the primary side P includes an additional winding 4 for regulating the moment of current flow in the switching transistor in the sense of stabilizing the amplitude of the output voltages on the secondary side S.
The secondary side S initially includes the secondary winding 2 from which is obtained, via a rectifier circuit (not shown), the main operating voltage U1. The secondary winding 2 is divided into two series connected partial windings 2a and 2b. Additionally, the secondary winding S includes a winding 5 for generating an operating voltage for the video amplifier and a further winding 6 for generating the operating voltage for the vertical deflection stage of a television receiver. Moreover, an additional secondary winding 7 is provided from which, after rectification, the operating voltage or the audio output stage of the receiver is obtained. Winding 7 comprises three partial windings 7a, 7b, 7c which are connected in parallel. The audio output stage of a television receiver has a greatly fluctuating current input between 50 mA and 1000 mA so that the load of the secondary side S varies considerably. This variation in load may effect an undesirable change in the operating voltage U1 which also influences the horizontal deflection amplitude. This undesirable dependency can be reduced in that the coupling between winding 7 and winding 4 is dimensioned greater, for regulating purposes, than the coupling between winding 2 and winding 4. This solution is described in greater detail in Federal Republic of Germany Offenlegungsschrift (laid open application) DE-OS No. 2,749,847 of May 10, 1979. This increased coupling between windings 7 and 4 is realized in the present case by the three parallel connected windings 7a, 7b, 7c. Finally, the secondary S includes a further winding 8 which serves to generate, after rectification, a negative operating voltage of -30 V.
FIG. 2 shows one half of the chamber coil body 9 for the individual windings of FIG. 1, with the body 9 including a total of six chambers 10. The size and particularly the widths of the individual chambers 10 can vary with respect to one another and the widths may all be different. Preferably, the width of the narrowest chamber 10 is about 1 mm and the total width of all six chambers is only approximately 20 mm so as to realize a flat and optimally coupled transformer.
As shown, one third of the primary winding 1, in the form of respective partial windings 1a, 1b and 1c, is distributed to each of the first, third and fifth chambers 10 of the coil body 9. The additional primary windings 3 and 4 are disposed in the third chamber 10 above the partial winding 1b. One half of the secondary winding 2, in the form of respective partial windings 2a, 2b, is distributed to each of the second and fourth chambers 10 of the coil body 9. The three partial windings 7a, 7b and 7c of the additional secondary winding 7 for the audio output stage are distributed to the second, fourth and sixth chambers 10, respectively, with the partial windings 7a-7c being disposed closest to the longitudinal axis of the coil body 9 and thus below any partial secondary winding 2a, 2b or other secondary winding which may be located in the same chamber. That is, the partial windings 7a and 7b are disposed below the partial windings 2a and 2b, respectively, in the respective second and fourth chambers 10, and below the additional secondary windings 5 and 8 in the sixth chamber 10. Further winding 6 is disposed above partial secondary winding 2b.
As can be seen in FIG. 2, the chambers 10 contain alternatingly only windings or partial windings of the primary side P or of the secondary side S. The illustrated nesting or interleaving of the windings, i.e. the alternating arrangement of windings of the primary side P and of the secondary side S in successive chambers 10, assures the desired close coupling between the primary side P and the secondary side S. The arrangement of the windings 3, 4 in approximately the center of the coil body 9 above partial winding 1b assures the desired close coupling between the windings 3, 4 with the other windings.
In an embodiment of the transformer shown in FIGS. 1 and 2 which was successfully tested in practice, the individual windings were all wound with the same diameter wire and contained the following numbers of turns:

______________________________________

Winding No. Number of Turns

______________________________________

1a 22 1b 22 1c 22 2a 30 2b 30 3 3 4 10 5 25 6 1 7a 11 7b 11 7c 11 8 16

______________________________________

The diameter of the wire of the windings 1-8 may be about 0.40 or 0.45 mm. Also, each winding may exist of two parallel shunted wires each of 0.3 mm diameter. The width of the six chambers 10--seen from the left to the right in FIG. 2--may be 0.95/1.95/1.75/1.95/0.95/2.75 mm and the thickness of the walls forming the chambers 0.65 mm.
It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

 

TDA4443 MULTISTANDARD VIDEO IF AMPLIFIER  DESCRIPTION
The TDA4443 is a Video IF amplifier with standard
switch for multistandard colour or monochromeTV
sets, and VTR’s.

SWITCHING OFF THE IF AMPLIFIER WHEN
OPERATING IN VTR MODE .DEMODULATION OF NEGATIVE OR POSITIVE
IF SIGNALS. THE OUTPUT REMAINS
ON THE SAME POLARITY IN EVERY CASE .IF AGC AUTOMATICALLY ADJUSTED TO
THE ACTUALSTANDARD .TWO AGC POSSIBILITIES FOR B/G MODE :
1. GATED AGC
2. UNGATED AGC ON SYNC. LEVEL AND
CONTROLLED DISCHARGE DEPENDENT
ON THE AVERAGE SIGNAL LEVEL FOR VTR
AND PERI TV APPLICATIONS
FOR STANDARD L : FAST AGC ON PEAK
WHITE BY CONTROLLED DISCHARGE .POSITIVE OR NEGATIVE GATING PULSE .EXTREMELY HIGH INPUT SENSITIVITY .LOW DIFFERENTIAL DISTORTION .CONSTANT INPUT IMPEDANCE .VERY HIGH SUPPLY VOLTAGE REJECTION .FEW EXTERNAL COMPONENTS .LOW IMPEDANCE VIDEO OUTPUT .SMALL TOLERANCES OF THE FIXED VIDEO
SIGNALAMPLITUDE .ADJUSTABLE, DELAYED AGC FOR PNP
TUNERS.

GENERAL DESCRIPTION
This video IF processing circuit integrates the following
functional blocks : .Three symmetrical, very stable, gain controlled
wideband amplifier stages - without feedback
by a quasi-galvanic coupling. .Demodulator controlled by the picture carrier .Video output amplifier with high supply voltage
rejection .Polarity switch for the video output signal .AGC on peak white level .GatedAGC .Discharge control .Delayed tuner AGC .At VTR Reading mode the video output signal
is at ultra white level.



TDA4445A SOUND IF AMPLIFIER


.QUADRATURE INTERCARRIER DEMODULATOR
.VERY HIGH INPUT SENSITIVITY .GOODSIGNALTO NOISE RATIO .FAST AVERAGINGAGC .IF AMPLIFIER CAN BE SWITCHED OFF FOR
VTR MODE .GOODAM SUPPRESSION .OUTPUT SIGNAL STABILIZED AGAINST
SUPPLY VOLTAGE VARIATIONS .VERY FEW EXTERNAL COMPONENTS
DESCRIPTION
TDA4445A:
Sound IF amplifier, with FM processing for quasi
parallel sound system.
TDA4445B:
Sound IF amplifier, with FM processing and AM
demodulator, for multi-standard sound TV appliances.
TDA4445Badditionnal :
Bistandard applications (B/G and L)
No adjustment of the AM demodulator
Low AMdistortion.


GENERAL DESCRIPTION
This circuit includes the following functions : .Three symmetrical and gain controlled wide
band amplifier stages, which are extremely stable
by quasiDC coupling without feedback. .Averaging AGC with discharge control circuit .AGC voltage generator
Quasi parallel sound operation : .High phase accuracy of the carrier signal processing,
independentfrom AM .Linear quadrature demodulator .Sound-IF-amplifier stage with impedance converter
AM-Demodulation (only TDA4445B) : .Carrier controlled demodulator .Audio frequency stage with impedance converter
.Averaging low passAGC.

 THOMSON ICC5 Color television standard identification circuit:

A PAL-NTSC color television standard identification circuit, comprising a first demodulation circuit (7) for a reference component and a second demodulation circuit (11) for a possible color identification component of a color synchronizing signal, can perform a reliable identification by means of a digital decoding circuit (81) for the output signals of the demodulation circuits if the second demodulation circuit (11) is adapted (41, 45, 49) to demodulate along an axis slightly differing from the axis of the color identification component (FIG. 1).



1. A color television standard identification circuit for distinguishing at least a PAL and an NTSC color television signal, said identification circuit comprising a first demodulation circuit for demodulating a reference component (R) of a color synchronizing signal occurring in both PAL and NTSC, a second demodulation circuit for demodulating a color identification component of the color synchronizing signal occurring only in PAL, and a decoding circuit having an input coupled to respective outputs of said first and second demodulation circuits for determining whether the color synchronizing signal is a PAL or an NTSC color synchronizing signal, wherein said identification circuit further comprises a sign determination circuit coupled between the outputs of said first and second demodulation circuits and the input of said decoding circuit, said sign determination circuit comprising a comparison circuit having a comparison level, at which the level of an output signal of said comparison circuit changes, which is substantially equal to a reference level of said first and second demodulation circuits, and a sampling circuit having a input coupled to an output of said comparison circuit, an input of said sign determination circuit being coupled to an input of said comparison circuit and an output of said sign determination circuit being coupled to an output of said sampling circuit, wherein said second demodulation circuit is arranged to demodulate the color synchronizing signal at an axis slightly differing from the axis of the color identification component, whereby said sign determination circuit may accurately determine the correct sign of the output signal from said second demodulation circuit during demodulation of an NTSC color synchronizing signal by said second demodulation circuit. . 2. A color television standard identification circuit as claimed in claim 1, wherein said first demodulation circuit comprises a first synchronous demodulator having an input and an output coupled, respectively, to an input and the output of said first demodulation circuit; and said second demodulation circuit comprises a second synchronous demodulator having an input coupled to an input of said second demodulation circuit, and an adder circuit having a first input coupled to the output of said first synchronous demodulator and a second input coupled to an output of said second synchronous demodulator, an output of said adder circuit being coupled to the output of said second demodulation circuit, and wherein said identification circuit further comprises an oscillator for supplying reference signals to reference signal inputs of said first and second synchronous demodulators, said oscillator having a control input coupled to the output of said second synchronous demodulator thereby forming a phase-locked loop for controlling the phase of said oscillator. 3. A color television standard identification circuit as claimed in claim 1 or 2, wherein a change-over switch is coupled between the input of said sign determination circuit and the outputs of said first and second demodulation circuits, respectively, said change-over switch having a switching signal input coupled to an output of said decoding circuit.

Description:

The invention relates to a color television standard identification circuit for distinguishing at least a PAL and an NTSC color television signal, said circuit comprising a first demodulation circuit for demodulating a reference component of a color synchronizing signal occurring in both PAL and NTSC and a second demodulation circuit for demodulating a color identification component of the color synchronizing signal occurring only in PAL, and a decoding circuit for determining by means of output signals of the first and the second demodulation circuit whether the color synchronizing signal is a PAL or an NTSC color synchronizing signal.
A color television standard identification circuit of the type described above is known from IEEE Transactions on Consumer Electronics, Vol. CE 31, No. 3, August 1985, pp. 147-155. The greater part of this circuit is incorporated in an integrated circuit to which two capacitors performing a memory function in the decoding circuit must be connected.
It is an object of the invention to obviate as much as possible the use of capacitors to be connected externally.
According to the invention, a color television standard identification circuit of the type described in the opening paragraph is therefore characterized in that a sign determination circuit is arranged between an output of the demodulation circuits and an input of the decoding circuit, said sign determination circuit comprising a comparison circuit whose sign reversal level is substantially equal to the rest level of the demodulation circuits and further comprising a sampling circuit, the second demodulation circuit being adapted to demodulate the color synchronizing signal at an axis slightly differing from the axis of the color identification component in such a way that the sign determination circuit cannot determine an incorrect sign during demodulation of an NTSC color synchronizing signal.
It is to be noted that the use of a sign determination circuit with a comparison circuit and a sampling circuit for obtaining a decoding circuit no longer requiring capacitors is known from French Patent Application FR-A 2,575,353 for identifying a color difference signal associated with a given line period in a SECAM receiver.
It has been found that it is insufficient to incorporate a sign determination circuit, for example, after the demodulation circuits of a color television standard identification circuit.
To obtain a reliable standard identification, it is necessary that the second demodulation circuit supplies a signal from which the sign determination circuit can obtain such a signal that the decoding circuit can make a distinction between noise and the presence of an NTSC color synchronizing signal.
If the second demodulation circuit had a demodulation axis which would completely coincide with the phase of the PAL color identification component, it would supply an output signal which would be equal to the rest level of the second demodulation circuit in the case of demodulation of an NTSC color synchronizing signal. With a slight internal shift of its comparison level, its own noise could then cause the sign determination circuit to supply a signal which would not correspond to the sign desired for the rest level of the second demodulation circuit. This is prevented by slightly modifying the demodulation axis of the second demodulation circuit.
The invention will now be described in greater detail, by way of example, with reference to the accompanying drawing in which
FIG. 1 is a block diagram of a color television standard identification circuit according to the invention,
FIG. 2 is a phasor diagram of the demodulation of the components of a PAL color synchronizing signal by means of a circuit according to FIG. 1, and
FIG. 3 is a phasor diagram of the demodulation of the components of an NTSC color synchronizing signal by means of a circuit according to FIG. 1.
In FIG. 1 a chrominance signal is applied to an input 1, from which signal a gating circuit 3 selects the color synchronizing signal and passes it on to an input 5 of a first demodulation circuit 7 and to an input 9 of a second demodulation circuit 11.
The first demodulation circuit 7 is a first synchronous demodulator which receives a reference signal at a reference signal input 13 from an output 15 of a 90° phase-shifting network 17, which reference signal has a phase which is 90° shifted with respect to the phase of a reference signal occurring at an input 19 thereof and originating from an output 21 of an oscillator 23.
The input 9 of the second demodulation circuit 11 is also an input of a second synchronous demodulator 25, a reference signal input 27 of which is connected to the output 21 of the oscillator 23 and an output 29 of which applies, via a low-pass filter 31, a control signal to a control signal input 33 of the oscillator 23.
The oscillator 23, the second synchronous demodulator 25 and the low-pass filter 31 constitute a phase-locked loop controlling the phase of the reference signal at the reference signal input 27 of the second synchronous demodulator 25 in such a way that it differs ninety degrees from that of the reference component of the color synchronizing signal. As a result, the demodulated color identification component of the color synchronizing signal occurs at the output 29 of the second synchronous demodulator 25 in the case of synchronous demodulation of a PAL color synchronizing signal, whilst the phase-locked loop will control said output 29 substantially at its rest level in the case of synchronous demodulation of an NTSC color synchronizing signal.
The demodulation axis of the second synchronous demodulator 25 is the ninety-degree axis in FIGS. 2 and 3, and the demodulation axis of the first synchronous demodulator 7 is the zero axis. The reference component of the color synchronizing signal is denoted by R in the two Figures and has a phase of one hundred and eighty degrees. The PAL color synchronizing signal is denoted by B and B' in FIG. 2, dependent on the line period in which it occurs.
In FIG. 1 an output 35 of the first synchronous demodulator 7 applies the demodulated reference component R of the color synchronizing signal, which has a negative polarity, to an input 37 of a change-over switch 39 and via an attenuator 41 to an input 43 of an adder circuit 45, an output 47 of which is also the output of the second demodulation circuit 11.
The output 29 of the second synchronous demodulator 25 applies the demodulated color identification component via a further attenuator 49 to a further input 51 of the adder circuit 45. The output 47 of the second demodulation circuit 11 now applies a demodulated color synchronizing signal to a further input 53 of the change-over switch 39, which signal is demodulated in accordance with an axis which is denoted by D in FIGS. 2 and 3 and which differs slightly from the ninety-degree axis. This difference is determined by the ratio of the attenuations of the attenuators 41 and 49.
FIGS. 2 and 3 show that in the case of PAL a slightly asymmetrical demodulation of the color identification component is effected with an amplitude A in the one line period and an amplitude A' in the next period, whilst in the case of NTSC a small negative amplitude C is demodulated by the second demodulation circuit 11.
In FIG. 1 an output 55 of the change-over switch 39 is connected to an input 57 of a sign determination circuit 59 via a low-pass filter 56 having an integration time of approximately half a microsecond. The input 57 is also an input of a comparison circuit 61, a reference level input 63 of which receives the rest level of the first and the second demodulation circuits 7, 11, which is symbolically indicated by a connection between this input 63 and a rest level output 65, 67 of the first and the second synchronous demodulator 7, 25, respectively.
An output 69 of the comparison circuit 61 is connected to a D input 71 of a D flip-flop 73 operating as a sampling circuit, a clock signal input 75 of which receives a pulse each time at the end of the occurrence of a color synchronizing signal. As a result, a logic value of one is obtained at an output 77 of the D flip-flop 73, which output is also the output of the sign determination circuit 59, if the signal at the input 57 of the sign determination circuit 59 was positive with respect to the reference level at the reference level input 63 of the comparison circuit 61, and a logic value of zero if the signal at the input 57 was negative with respect to this reference level.
The output 77 of the sign determination circuit 59 applies this logic one or logic zero signal to an input 79 of a decoding circuit 81 which supplies at an output 83 a switching signal of half the line frequency and the correct phase for switching the demodulation axis of a (R-Y) demodulator when a PAL signal is received, at an output combination 85 a signal combination which can bring a color television receiver comprising the color identification circuit to a PAL or NTSC receiving state, and at an output 87 a switching signal which can cause the change-over switch 39 to successively take up its two positions in a given receiving state of the receiver and which to this end is applied to a switching signal input 89 of the change-over switch 39.
The decoding circuit 81 compares the pattern of logic levels at its input 79 with a pattern to be expected in a given receiving state and a given state of the change-over switch 39, and with reference to the number of differences per period of time, for example, per field period it determines whether the receiving state of the receiver is the desired state, or whether no color information is received. This is effected by means of a counter which may be in the form of, for example a pseudo-random counter in order to obtain a small number of components.
The demodulation axis D, which is different from ninety degrees, of the second demodulation circuit 11 can now give a clear distinction between the pattern of logic levels occurring at the output 77 of the sign determination circuit due to a noise signal or due to an NTSC color synchronizing signal which occurs at the input 9 of the second demodulation circuit 11 when the change-over switch 39 is in the state not shown.
In the presence of an NTSC color synchronizing signal the negative amplitude C of the demodulated color synchronizing signal will cause the input 57 to be negative during the occurrence of the signal with respect to the rest level at the rest level input 63 so that the output 77 of the sign determination circuit always remains logic zero. In the presence of a noise signal, thus in the absence of a color synchronizing signal, the output 77 will, at an average, assume a logic zero level approximately as frequently as a logic one level.
If the demodulation axis of the second demodulation circuit 11 had been at ninety degrees, no distinction could be made because the own noise of the comparison circuit 61 could then cause the same logic signal pattern at the input 79 of the decoding circuit 81 in the presence of a noise signal as well as in the presence of an NTSC color synchronizing signal at the input 9 of the second demodulation circuit 11.
As can be seen in FIG. 2, a small difference from ninety degrees will cause a small asymmetry in a demodulated color identification component, which does not, however, introduce any change in the logic signal pattern at the input 79 of the decoding circuit 81.
If desired, the circuit may be extended by a section for identification of a SECAM color television signal, for example, by applying a frequency-demodulated SECAM color synchronizing signal to a third input of the change-over switch 39.
Capacitors are no longer required for the identification function, because this identification is now carried out in a digital signal processing section.
Instead of combining the output signals of the first and the second synchronous demodulator by means of the adder circuit 45, a third synchronous demodulator whose reference signal would have the desired phase D could be used in the second demodulation circuit 11.
The first and the second synchronous demodulators 7, 25 may also be used as color difference signal demodulators if the gating circuit 3 is omitted and if the demodulated color synchronizing signals are obtained from the output signals of the synchronous demodulators by means of gating circuits.
If desired, a sign determination circuit may be incorporated after each demodulation circuit and the change-over switch 39 may be omitted if the decoding circuit 81 is adapted to simultaneously process the output signals of the sign determination circuits.
Instead of using attenuators 41 and 49, the demodulators 7 and 25 may be formed in such a manner, for example, by choosing a certain ratio of currents supplied by current sources of multipliers in the form of synchronous demodulators, that the adder circuit 45 receives the correct amplitude ratio in the non-shown state of the change-over switch 39.

TDA4556 Multistandard decoder


GENERAL DESCRIPTION
The TDA4555 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.




NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)   U4647 - TEA5040 (TELEFUNKEN) WIDE BAND VIDEO PROCESSOR

DESCRIPTION
The U4647 - TEA5040S is a serial bus-controlled videoprocessing
device which integrates a complex architecture
fulfilling multiple functions.


.DIGITAL CONTROL OF BRIGHTNESS,
SATURATION AND CONTRAST ON TV SIGNALS
AND R, G, B INTERNAL OR EXTERNAL
SOURCES .BUS DRIVE OF SWITCHING FUNCTIONS .DEMATRIXING OF R, G, B SIGNALS FROM
Y, R-Y, B-Y, TV MODE INPUTS .MATRIXING OF R, G, B SOURCES INTO
Y, R-Y, B-Y SIGNALS .AUTOMATIC DRIVE AND CUT-OFF CONTROLS
BY DIGITAL PROCESSING DURING
FRAME RETRACE .PEAK ANDAVERAGE BEAM CURRENT LIMITATION
.ON-CHIP SWITCHING FOR R, G, B INPUT
SELECTION .ON-CHIP INSERTION OF INTERNAL OR EXTERNAL
R, G, B SOURCES


An automatic contrast control circuit in a color television receiver for stabilizing the average DC level of the luminance information at a desired level and preventing focus blooming. The control circuitry, which is suitable for fabrication as a monolithic integrated circuit, contemplates the provision of a gain-controlled luminance amplifier stage for driving an image reproducer with luminance information having a stabilized black level. An average detector coupled to the amplifier stage output develops a control signal representative of the average DC level of the luminance information and applies it to the amplifier stage, varying its gain inversely with changes in the average luminance level. A peak limiter circuit is also provided for modifying the control signal to reduce the amplifier stage's gain whenever an AC brightness component comprising the luminance information exceeds a defined threshold level, regardless of the average DC level of the luminance information.

1. In a television receiver having a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer, said luminance signals including black level reference information, an automatic contrast control circuit comprising in combination:

2. An automatic contrast control circuit in accordance with claim 1, wherein adjustable level shifting means are interposed between said amplifier stage and said average detector means, said adjustable level shifting means providing a contrast control for manually varying the average DC level of said luminance signals.

3. An automatic contrast control circuit in accordance with claim 1, wherein said average detector means includes a capacitor having an output terminal coupled to said amplifier stage and a second terminal coupled to a plane of reference potential, said capacitor being charged by luminance signals from said amplifier stage and developing control signals representative of the average DC level of said luminance signals.

4. An automatic contrast control circuit in accordance with claim 3, wherein said control signals with respect to a plane of reference potential are equal to the potential at which black level is stabilized minus the potential drop between black level and the average DC level of said luminance information, said control signal increasing with respect to said plane of reference potential responsive to decreasing average DC levels of said luminance signals and decreasing responsive to increasing average DC levels.

5. An automatic contrast control circuit in accordance with claim 3, wherein said peak detector means includes a semi-conductor arrangement for providing said capacitor with a low impedance discharge path whenever said brightness components exceed a predetermined threshold level, the impedance of said discharge path being dependent on the amplitude of said brightness components and the discharge interval of said semiconductor arrangement being the time period during which said brightness components exceed said threshold level, said semiconductor arrangement further decreasing said control signals with respect to said plane of reference potential irrespective of the average DC level of said luminance signals.

6. An automatic contrast control circuit in accordance with claim 5, wherein said semiconductor arrangement comprises first and second transistors, said luminance signals from said amplifier stage being coupled to the input base electrode of said first transistor, said first transistor further having an emitter electrode coupled to said capacitor output terminal and a collector electrode coupled to the base electrode of said second transistor, said second transistor having a collector electrode coupled to said capacitor output terminal and an emitter electrode coupled to said plane of reference potential, said semiconductor arrangement being conductive to provide said capacitor with a low impedance discharge path whenever said brightness components exceed the base-emitter junction breakdown voltage of said first transistor.

7. An automatic contrast control circuit in accordance with claim 6, wherein said gain-controlled luminance amplifier stage includes a pair of transistors arranged in a differential amplifier configuration, the gain of which is dependent on the bias applied to the base electrodes of said transistors.

8. An automatic contrast control circuit in accordance with claim 7, wherein inverter means invert and couple said control signals to said base electrodes in said amplifier stage, the inverted control signals increasing the gain of said amplifier stage whenever the average DC level of said luminance signals decreases and decreasing the gain of said amplifier stage whenever the average DC level of said luminance information increases or whenever said brightness components exceed said threshold level.

9. An automatic contrast control circuit in accordance with claim 3, wherein said beam current limiter means provide a low impedance discharge path for said capacitor whenever the beam current exceeds a predetermined level.

10. An automatic contrast control system in accordance with claim 9, wherein said beam current limiter means monitors pulses from a voltage multiplier high-voltage system, said pulses being proportional to the beam current generated during the previous horizontal scan line.

11. An automatic contrast control circuit in accordance with claim 10, wherein said beam current limiter means comprises a transistor having a base electrode coupled to said voltage multiplier high-voltage system, an emitter electrode coupled to a plane of reference potential and a collector electrode coupled to said capacitor, said transistor providing a low impedance discharge path whenever said pulses exceed the base-emitter junction breakdown voltage of said transistor.

Description:

BACKGROUND OF THE INVENTION

This invention relates in general to control circuitry for color television receivers and more particularly to an automatic contrast control circuit incorporated in the luminance processing channel. In accordance therewith, a variable DC control signal is derived from the luminance signal information as a function of the average luminance level. The DC control signal is applied to a gain-controlled amplifier stage in the luminance channel, varying its gain and thereby insuring that excessive beam currents will not be generated due to high average luminance levels. Conversely, the circuit is effective to increase the gain of the amplifier stage when under-modulated signals are received thereby providing the desired contrast level. When the white content of the instantaneous received signal exceeds a predetermined level, however, the DC control signal is modified to reflect the excessive white content even though the average luminance level may be low. Accordingly, the amplifier stage's gain is reduced to prevent defocusing.

In color television receivers, the various elemental areas of differing brightness levels, or shades, in the televised image correspond to the amplitude levels of the instantaneous brightness components of the luminance signals which, together with the chrominance signal, reproduce the transmitted picture information on the image display tube. The intensity of the electron beams developed in the receiver's image display tube are varied, for the most part, according to the detected amplitude levels of the instantaneous luminance signals. Accordingly, progressively higher amplitude levels generate higher intensity electron beams and, consequently, progressively lighter shades. In addition, suitable viewer-adjustable controls are customarily provided in the television receiver whereby a particularized contrast and brightness setting may be selected according to viewer preference.

It is desirable that the level of the luminance signal component corresponding to black in the televised image be maintained at the cut-off of the image reproducer. But even in those instances where there is a measure of DC coupling, the DC components of the luminance signal coupled from the video detector to the luminance channel may be degraded or otherwise restricted due to the nature of the processing circuitry as well as to other factors. Moreover, the luminance processing channel itself may well permit a degradation or undesirable shift in the desired DC characteristics. The result is that the DC level in the processed luminance signal is not properly maintained, such that, upon application to the image display tube, the black level is shifted to some undesirable reference. This leads to less than faithful half-tone reproduction on the screen of the image display tube. Gray tones can be lost simply because they are beyond the cut-off of the display tube. In other instances, blacks may appear as grays on the image display tube screen.

Thus, it is desirable to make provision for the maintenance of black level in the televised image at some stabilized reference. Various systems are of course known in the art for accomplishing this objective and take various forms and configurations. For example, an arrangement commonly known as a DC restorer circuit which includes a clamping device may be employed. However, when the black level is effectively stabilized at the image reproducer's cut-off bias point, the average level of the luminance signal information may reach the point where excessive average beam currents capable of severely damaging the image reproducer are generated. In addition, the high voltage power supply during instances of high beam current may be incapable of delivering the required beam current. Such overloading reduces the power supply output voltage and results in undesirable "focus blooming." That is, there will be a loss of brightness, reduction of horizontal widths and severe defocusing of the reproduced image. The problem in this regard has been further compounded by the "new generation" high-brightness cathode-ray tubes which require higher beam currents in order to illuminate the tube to its fullest capability during high-modulation (white) scenes. In view of the added demands on the high voltage power supply and the danger of damaging the image display tube, some method for effectively limiting the beam current is required.

Accordingly, automatic contrast control systems have been developed which reduce the gain of the luminance amplifier stage to prevent the generation of excessive beam currents or increase the gain when under-modulated signals are received. Most of these prior art automatic contrast control systems, however, measure only the average level of the luminance signals to derive the control signal utilized to vary the gain of the luminance amplifier. Consequently, when all or a major portion of the luminance signal's white content is of a high amplitude level and is concentrated on a very small portion of the image reproducer's screen, the control signal derived from the average luminance level is low, permitting the luminance amplifier stage to operate at nearly maximum gain. By concentrating the high-amplitude white content into a small area of the screen, the image display tube is likely to be overdriven during that period of time and "focus blooming" will result. Some automatic contrast systems, on the other hand, derive a control signal based on the peak amplitudes of the instantaneous luminance signals without regard to the average luminance level. Thus, while preventing blooming on high-amplitude white content, such systems are susceptible to luminance signals which have a dangerously high average level, but do not have any peak white signal content of a level where the system would take corrective action.

OBJECTS OF THE INVENTION

Accordingly, it is an object of the present invention to provide a color television receiver having black level stabilization with a new and improved automatic contrast control circuit which effectively overcomes the aforenoted disadvantages and deficiencies of prior circuits.

A further object of the invention is to provide an improved automatic contrast control circuit which develops control signals effectively varying the gain of a luminance amplifier stage to maintain an optimum contrast, while preventing the generation of excessive beam currents in the cathode-ray tube.

A more particular object of the invention is to provide an improved automatic contrast control circuit for continuously monitoring the average (DC) level of the luminance signal information and providing a control signal representative thereof to vary the gain of a luminance amplifier stage while remaining sensitive to the amplitude levels of brightness components exceeding a threshold level and modifying the control signal in accordance therewith.

Another object of the invention is to provide an improved automatic contrast control circuit which increases the gain of a luminance amplifier stage during reception of undermodulated luminance signals.

A further object of the present invention is to provide an automatic contrast control circuit of the foregoing type for deriving a variable DC control potential from applied luminance signals which, upon application to the luminance channel, adjusts the gain of a luminance amplifier stage in accordance with the varying luminance signal requirements.

Still another object of the invention is to provide a luminance processing channel including automatic contrast control circuitry which may be fabricated as a monolithic integrated circuit to provide an output luminance signal having stabilized black level and optimum contrast without producing excessive beam currents.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved automatic contrast control circuit is provided for varying the gain of an amplifier stage in the luminance processing channel of a color television receiver whenever the average DC level of the input luminance information varies from a desired level, or whenever the peak amplitudes of the AC brightness components of the luminance information exceed a predetermined threshhold level. In a preferred embodiment, the automatic contrast control circuit includes a gain-controlled luminance amplifier stage in a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer. The amplified luminance signals found at the output of the amplifier stage have a stabilized black level. There are also provided detector means coupled to the amplifier output for developing control signals that are representative of the average DC level of the instantaneous luminance signals. The control signals are then applied to the gain-controlled amplifier stage to vary its gain inversely with changes in the average luminance level. Finally, peak limiter means are coupled between the amplifier output and the detector means to modify the control signals whenever the instantaneous luminance signals exceed a threshhold level. The modified control signals are similarly utilized to effect inverse gain variations in the gain-controlled amplifier stage regardless of the average level of the luminance signals.

GENERAL DESCRIPTION
Brief Description
This integrated circuit incorporates the following
features :
- a synchro and two video inputs
- a fixed video output
- a switchable video output
- normal Y, R-Y, B-Y TV mode inputs
- double set of R, G, B inputs
- brightness, contrast and saturation controls as
wellon aR,G, B picture ason a normalTVpicture
- digital control inputs by means of serial bus
- peak beam current limitation
- average beam current limitation
- automaticdrive and cut-off controls
Block Diagram Description
BUS DECODER
A 3 lines bus (clock, data, enable) delivered by the
microcontroller of the TV-set enters the videoprocessor
integrated circuit (pins 13-14-15). A control
system acts in such a way that only a 9-bit word is
taken intoaccount by the videoprocessor.Six of the
bits carry the data, the remaining three carry the
address of the subsystem.


A demultiplexer directs the data towards latches
which drive the appropriate control. More detailed
information about serial bus operation is given in
the following chapter.
Video Switch
The video switch has three inputs :
- an internal video input (pin 39),
- an external video input (pin 37),
- a synchro input (pin 41),
and two outputs :
- an internal video output (pin 40),
- a switchable video output (pin 42)
The 1Vpp composite video signal applied to the
internal video input is multiplied by two and then
appears as a 2Vpp low impedance composite
video signal at the output. This signal is used to
deliver a 1Vpp/75W composite video signal to the
peri-TV plug.
The switchable video output canbe any of the three
inputs.When the Int/Ext one active bit word is high
(address number 5), the internal video input is
selected. If not, either a regeneratedsynchro pulse
or the external video signal is directed towards this
output depending on the level of the Sync/Async
one active bit word (address number 4). As this
output is to be connected to the synchro integrated
circuit, RGB information derived from an external
source via the Peri-TV plug canbedisplayed on the
screen, the synchronization of the TV-set being
then made with an external video signal.
When RGB information is derived from a source
integrated in the TV-set, a teletext decoder for
example, the synchronization can be made either
on the internal video input (in case of synchronous
data) or on the synchro input (in case of asynchronous
data).
R, G, B Inputs
There are two sets of R, G, B inputs : one is to be
connected to the peri-TV plug (Ext R, G, B), the
second one to receive the information derived from
the TV-set itself (Int R, G, B).
In order to have a saturation control on a picture
coming from the R, G, B inputs too, it is necessary
to getR-Y, B-Y and Y signals from R, G, B information
: this is performed on the first matrix that
receives the three 0.9Vp (100% white) R, G, B
signals and delivers the corresponding Y, R-Y, B-Y
signals. These ones are multiplied by 1.4 in order
to make the R-Y and B-Y signals compatible with
the R-Y and B-Y TV mode inputs. The desired R,
G, B inputs are selected by means of 3 switches
controlled by the two fast blanking signal inputs. A
high level on FB external pin selects the external
RGB sources. The three selected inputs are
clamped in order to give the required DC level at
the output of this firstmatrix. Thethree not selected
inputs are clamped on a fixed DC level.
Y, R-Y, B-Y Inputs
The 2Vpp composite video signal appearing at the
switchable output of the video switch (pin 42) is
driven through the subcarrier trap and the luminance
delay line with a 6 dB attenuation to the Y
input (1Vpp ; pin 12). In order to make this 1Vpp
(synchro to white) Y signal compatible with the
1Vpp (black to white) Y signal delivered by the first
matrix, it is necessary to multiply it by a coefficient
of 1.4.

Controls
The four brightness, contrastand saturationcontrol
functions are direct digitally controlled without using
digital-to-analog converters.
The contrast control of the Y channel is obtained
by means of a digital potentiometer which is an
attenuator including several switchable cells directly
controlled by a 5 active bit word (address
number 1). The brightness control is also made by
a digital potentiometer (5 active bit word, address
number 0). Since a + 3dB contrast capability is
required, the Y signal value could be up to 0.7Vpp
nominal. For both functions, the control characteristics
are quasi-linear.
In each R-Y and B-Y channel, a six-cell digital
attenuator is directly controlled by a 6 active bit
word (address number 6 and 7). The tracking
needed to keep the saturation constant when
changing the contrast has to be done externally by
the microcontroller. Furthermore, colour can be
disabledby blankingR-Y andB-Ysignals using one
active bit word (address number 2) to drive the
one-chip colour ON/OFF switch.
Second Matrix, Clamp, Peak Clipping, Blanking
The second matrix receives the Y, R-Y and B-Y
signals and delivers the corresponding R, G, B
signals. As it is required to have the capability of +
6dB saturation, an internal gain of 2 is applied on
both R-Y and B-Y signals.
A low clipping level is included in order to ensure a
correct blanking during the line and frame retraces.
Ahigh clipping level ensures thepeakbeamcurrent
limitation. These limitations are correct only if the
DC bias of the three R, G, B signals are precise
enough. Therefore a clamp has been added in
each channel in order to compensate for the inaccuracy
of the matrix.
Sandcastle Detector And Counter
The three level supersandcastle is used in the
circuit to deliver the burst pulse (CLP), the horizontal
pulse (HP), and the composite vertical and
horizontal blanking pulse (BLI). This last one is
regenerated in the counter which delivers a new
composite pulse (BL) in which the vertical part lasts
23 lines when the vertical part of the supersandcastle
lasts more than 11 lines.
The TEA5040S cannot work properly if this minimum
duration of 11 lines is not ensured.
The counterdelivers different pulses neededcircuit
and especially the line pulses 17 to 23 used in the
automatic drive and cut-off control system.
Automatic Drive And Cut-off Control System
Cut-off and drive adjustments are no longer required
with this integrated circuit as it has a sample
and hold feedback loop incorporating the final
stages of the TV-set. This system works in a sequentialmode.
For this purpose, special pulses are
inserted in G, R and B channels. During the lines
17, 18 and 19, a ”drive pulse” is inserted respectively
in the green, red and blue channels. The line
20 is blanked on the three channels. During the
lines 21, 22 and 23, a ”quasi cut-off pulse” is
inserted respectively in the green, red and blue
guns.
The resulting signal is then applied to the input of
a voltage controlled amplifier. In the final stages of
the TV-set, the current flowing in each green, red
and blue cathode is measured and sent to the
videoprocessorby a current source.
The three currents are added together in a resistor
matrix which can be programmed to set the ratio
between the three currents in order to get the
appropriate colour temperature. The output of the
matrix forms a high impedance voltage source
which is connectedto the integratedcircuit (pin 34).
Same measurement range between drive and cutoff
is achieved by internally grounding an external
low impedance resistor during lines 17, 18 and 19.
This is due to the fact that the drive currents are
about one hundred times higher than the cut-off
and leakage currents.
Each voltage appearing sequentially on the wire
pin 34 is then a function of specific cathode current
:
- When a current due to a drive pulse occurs, the
voltage appearing on the pin 34 is compared
within the IC with an internal reference, and the
result of the comparison charges or discharges
an external appropriate drive capacitor which
stores the value during the frame. This voltage is
applied to a voltage controlled amplifier and the
system works in such a waythat the pulse current
drive derived from the cathode is kept constant.
- During the line 20, the three guns of the picture
tube are blanked. The leakagecurrent flowing out
of the final stages is transformed into a voltage which is stored by an external leakage capacitor
to be used later as a reference for the cut-off
current measurement.
- When a current due to a cut-off pulse occurs, the
voltage appearing on the pin 34 is compared
within the ICto the voltagepresenton the leakage
memory. Anappropriate externalcapacitor is then
charged or discharged in such a way that the
difference between each measured current and

the leakage current is kept constant, and thus the
quasi cut-off current is kept constant.
AverageBeam Current Limitation
The total current of the three guns is integrated by
means of an internal resistor and an external capacitor
(pin 36) and thencompared with a programmable
voltage reference(pin 38). When 70% of the
maximum permitted beam current is reached, the
drive gain begins to be reduced ; to do so, the
amplitude of the inserted pulse is increased.
In order to keep enough contrast, the maximum
drive reduction is limited to 6dB. If it is not sufficient,
the brightness is suppressed.
SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL
DATA BUS
This is a bi-directional 3-wire (ENABLE, CLOCK,
DATA) serial bus. The DATA line transmission is
bi-directional whereas ENABLE and CLOCK lines
are only microprocessor controlled. The ENABLE
and CLOCK lines are only driven by the microcomputer.

 

 

THOMSON CHASSIS ICC5 REPAIRING / SERVICING NOTES:

icc5 (110deg) lg11 faulty cg11(1nf)
icc intermittent controls- replace membrane .
icc5 1 sec eht then stby try s/c pin5 micro pro to earth .
icc5 3 lines of scan at top of pic only il14 tea2029.
icc5 3 trips then off dl55(ba157)+cl58(47uf100v)+rv82(10r).
icc5 330nf s-correction cap, check j134 22v .
icc5 3trips/dead tda2030 .
icc5 3trips/dead ,test pin 4/11 to earth if < 700r loptx.
icc5 3trips/dead dl55 ba157,cl58 47uf100v rv82 (10r, on crt base pcb) .
icc5 3trips/dead l25, zpd10 zener diode.
icc5 3trips/dead tl17 bc548b in trip cct.
icc5 3trips/dead, cp24 47uf,100v from choptr base tp24.
icc5 bent sides ew coil,tda4950,dl41(byw76),dl46(by228),rl44(66+120r).
icc5 bent sides tda4950 ew ig01 dl42(ba157) 18k across it.
icc5 blank bright raster. 10r on crt base.
icc5 blank raster dots hot smell dl21/dl22.
icc5 blank raster no snd tda2541
icc5 blank raster no snd, osd & scart ok,tda2451-2.
icc5 blank raster,line across top, dl21(esm740g).
icc5 child lock “press red green blue then hold yellow 10 secs” .
icc5 cl44(0.44uf250v).
icc5 cl48(12n4f)+tda4950+tl17.
icc5 clicking on nicam add 47k between pins 13 & 16 ic1580 nicam pcb
icc5 cold hiss ds03(bb809).
icc5 cold top lines/foldover cl52 from pin 3 loptx.
icc5 cold tripping il14(tea2029c),
icc5 color cast/bright text tv41(1k).
icc5 dead lg11,cl44(300nf).
icc5 dead rp23+1n4148 dl28.
icc5 dead “88” showing, rp42 1r2 in psu,
icc5 dead 1a6t+cap next to 1r4w resistors in mains filter unit.
icc5 dead 330nf400v lg11 tda4950+fusible jl34(22r) .
icc5 dead bu508at.
icc5 dead choptr(tp24) dp37 tl31 rl10(115k).
icc5 dead cl44 300nf250v .
icc5 dead cl48 12.4nf +tda4950 + bc548b tl17.
icc5 dead cl48.choptr(bu508a),cp23.
icc5 dead coil,lg11, tda4950 tda4950 rl44, cl48 10.5nf cl44 300nf.
icc5 dead cp02(10nf250v) blue disc.
icc5 dead cp37(1000uf) 8v line.
icc5 dead dl55(ba157).
icc5 dead eht surge cp26(470uf16v) loc241
icc5 dead fp05 rp01 rp02 rp01 on scan coils.
icc5 dead front digits ok,line scan coil plug
icc5 dead fuse blown check degauss ptc.
icc5 dead fuse cp02 10nf blue disc cap.
icc5 dead led flash once cp26(470uf25v).
icc5 dead led flash, rr30 pins.
icc5 dead led flicks once,lg11+tda4950+cl44+rl46(1k)+rl44(56r+120r)+j134(22r).
icc5 dead lg11 cl44(33pf) rl44 ig01(tda4950) add 22r in place of ji34.
icc5 dead lg11 coil+rl44(56+120r)+tda4950+cl48(10n5)+cl44(300nf).
icc5 dead lo start volts at il14 ,dp45(zpd9v1).
icc5 dead loptr 2000a3 cl48
icc5 dead loptr cause loptx try discon pins 6/8/9/10 to prove.
icc5 dead loptr cause scan coils leak to field /ew raster coil.
icc5 dead loptr s2000af bend the corners of the heatsink away from choptx.
icc5 dead loptr+cl48 11nf(51k7) loptx rl10
icc5 dead loptr,cl42(360nf250v)
icc5 dead loptr= ew trans=lg11 ig01 rl44 120r+56r.
icc5 dead loptx, choptr bu508a, field thy, jungle chip, fucus/a1 unit
icc5 dead pulse of power at switch off cl44(330nf250v).
icc5 dead rl23 1r
icc5 dead rp23 w/wound,no line drive dl29(1n4148)
icc5 dead s2000a3+4*by255+pins+mains plug.
icc5 dead stby programme up button on tv front for 6 seconds.
icc5 dead stby ir73(mda2062).
icc5 dead stby lg11 ig01 tda4950 cl44 rl46 rrl44 j134 22r
icc5 dead stby tp45=4v(should be 11.5v) stby tx lp03 .
icc5 dead switching stby/on qr27.
icc5 dead throbbing lo ht 50v, 220uf385v mains cap.
icc5 dead tl17 bc548 il14
icc5 dead tl17(bc548)
icc5 dead tp15(bc548b).
icc5 dead tp45 11.5vn, the stby transformer lp03
icc5 dead tp45(bc649).
icc5 dead trip is41(tda2030)
icc5 dead tripping dl18(zpd36),tl31(bu508a),rp43.
icc5 dead/dark blank raster, cp37 4700uf25v
icc5 degauss posistor+1r0+1.6at.
icc5 disable trip by shorting tl17 collector to emitter.
icc5 eht stays up 10 secs/no digits.
icc5 eht stby, ic904(sl486)try reset use remote or hold ch up.”
icc5 eht surge only, try disconnect pin 4 loptx, field collapse
icc5 eht/htrs ok no brill,unplug field scan coils (scr to earth)
icc5 ew (tda4950) cause lg11 flashover.
icc5 ew bowing (59p7).dg 10 6.8 zener
icc5 ew bowing tda4950
icc5 ew coil 1r+6.5r
icc5 ew coil on 110 crt,cl44 330nf,rl44,56+120r,j134 22r,tda4950.cg11 inf
icc5 ew distortion rl44(120r+56r) cl 44 0.3uf tda4950 ig010 ew coil lg11,
icc5 ew j134(22r)+tda4950 dl42(ba159)+18k, ig01
icc5 ew lg11 110deg tubes cl44 330nf; rl44 56r+120r fusible; j134 22r, ig01 tda4950 ew
icc5 ew raster ,tda4950,cg11(1nf),dg13(1n4148),dl41(byw76),lg11,rg08(22r).
icc5 ew raster ig8,rg41(10r),tg62(bc547b).
icc5 ew raster lg11 dl46+dl41+lg11+rl44+cg11+ig01+cl41+cl44+j134(72r),ig01.
icc5 excess blue iv50 .
icc5 excess brill rv82(10r) crt base.
icc5 faint pic snd ok cv90,cp37
icc5 field cl22+rl22+cl52 1000uf.
icc5 field collapse (wavy line) scan coil plug
icc5 field collapse ,line nr top, rl33(3m3),il14.
icc5 field collapse cf01, 470nf,il14,rf01(3m)/rl33, scan coil pins.
icc5 field collapse dp47, bg22,bg36,cf01, scan coil pins.
icc5 field collapse rf01(3m).
icc5 field collapse rf21(820r),rl50(1r), loptx pins.
icc5 field collapse. rf01(3m).
icc5 field top cramp,cl22 rl22,cl52 1,000uf, 23v line.
icc5 field top foldover rf(1k).
icc5 flyback lines, tv50(bf422), dl22,cl22,rl22(1k5),tv81.
icc5 front leds pulsing rp42 (1r) o/c+dp41 o/c pins.
icc5 ha11498 changed to u4647/b1-tea5040
icc5 hot hum bar/field collapse. dp47
icc5 hot snd cracks (51k5), two screen cans on nicam pcb; pin 24 of main edge.
icc5 hot snow it20(tda6316ap).
icc5 hum/hissy snd pc1253 pins cs36 qs05.
icc5 inch of pic lhs, iv02(saa5243) on t/text.
icc5 int blue pic flyback pin 11 of crt base.
icc5 int color when setting pic geometry, mod change dv11 to 100pf.
icc5 int colour,dv21(1n4148)
icc5 int field collapse. dp47
icc5 int interference/lines tda4443
icc5 int line flashes across it20(u6316).
icc5 int nicam pc1253-001.is01 ta8662 is08 adc2300 pins
icc5 int nicam ta8662+adc2300 pins.
icc5 int no color dv21(1n4148).
icc5 int no pic, tuner
icc5 int no snd,headphone socket
icc5 int no start, earth pin28 il14 for tripped test.
icc5 int pic cv57(22nf).
icc5 int sides ew, loptx pins .
icc5 int snd cr56 .
icc5 int snd headphone socket pins.
icc5 int start lines at top,1.5k rl22 4.7nf cl22.cl52 1000uf.
icc5 int stby choptr tp24
icc5 int stby,choptr tp24. pins
icc5 int ticking snd/int mute, earth spkr grill.
icc5 int trip degauss positor .
icc5 int trips ,rl48(4k7).
icc5 int trips led flashing 6 times rl18 4k7 sm.
icc5 int trips,degaussing posistor.
icc5 interference pic ,tda4443
icc5 just osd tda2451-2
icc5 just snow c109(1nf).
icc5 led flashing 6 times,rl18(4k7sm)
icc5 line collapse 2″ dl41, ll46,rl46.
icc5 lineop disconnect ,dummy load tween dp41 cathode, chassis
icc5 lines across screen, pf14(100r) field cct.
icc5 lines flashing , tuner unit,it20(u6316). pll
icc5 low blue tea5040+mod kit.
icc5 low height il14(tea2029c), ty01(bf422).
icc5 low ht(158vn), rl10(115k).
icc5 low tuning voltage ci05(1nf).
icc5 low width cl44(300nf400v)+rl44(120r+56r)
icc5 low width cl54 680nf
icc5 low width, dg10,ig01(tda4950).,dl41(byw76).
icc5 low width/ew ,0.33uf250+td4950+4r7(rf14).
icc5 lop transistor getting hot ,bend h/sink corner away from choptx.
icc5 loptr running hot cause loptx magnetic field hitting heatsink, add shield.
icc5 loptr scancoils lg11/tda4950+,,,.
icc5 loptr(s2000af)
icc5 loptx arcing dst85b172/401416, hr6260
icc5 loptx dst85b243/473197_00= hr6373
icc5 loptx+bu508a choptr (chopper transistor).
icc5 loptx=hr6373/hr6067 dst85b243 473 197_00.
icc5 mod ha11498 changed to u4647/b1-tea5040
icc5 nicam (nasty) resolder earths on nicam pcb screen
icc5 nicam clicking , earth speaker .
icc5 nicam crackles ii71(tda4445b) is09 .
icc5 nicam=nasty inconsistant companded audio muckup
icc5 no 5v cp44(22nf)leaks.
icc5 no blue rv73(47k)
icc5 no blue tea5040 iv21. mod kit wve
icc5 no channel change. ic ir01.
icc5 no channel store ir01 .
icc5 no color chv5700 as panel.
icc5 no eht,loptx.
icc5 no ew correction. j134(22r),ig01(tda4950)
icc5 no fastext ir01.
icc5 no green tv62.
icc5 no line sync ql07 from pin 18 il14.
icc5 no luma/dark screen chroma subpanel.
icc5 no nicam pc1253 qs03(16m384hz).
icc5 no nicam snd poor mono snd c176 10uf inside if can
icc5 no osd rv02(47r) tv05(mps2369a).
icc5 no osd tv07,4v3 zener on text board
icc5 no osd/ttext, tv67(bc547c)
icc5 no osd/ttext. dv05 zener (zpd10) on text pcb.
icc5 no picture bc558b decoder
icc5 no picture dl21
icc5 no picture tv50 on decoder pcb
icc5 no pic/snd lt13 dt21(in4150).
icc5 no pic/snd. cp37(4700uf) .
icc5 no pic/snd/led digits, micropro ir01(ferg07)
icc5 no raster dl22(ba157) il14,rp42(1r).
icc5 no raster/snd cp37(4u700f)
icc5 no remote ,ir receiver remove c950(10uf) add link.
icc5 no remote ir rx (mod c950 with wire)
icc5 no remote ir73/ ir01.
icc5 no scart sound tba120t.
icc5 no sound even on scart tba120t
icc5 no sound just hiss. tda4453 in if can.
icc5 no sound rs13(4r7) tr57(bc558b) ts04 is08(adc2300).
icc5 no sound tba120t sound det chip
icc5 no sound tr57(bc558b), rs13(4r7), headphone socket.
icc5 no start.rp42 on main pcb – low volts to ic il14
icc5 no text cv05 rv43 rv44(0r22).
icc5 no text dv03(zpd4v3)/dvo5(zpd10v) .
icc5 no text/osd iv05 tv67(bc547c) dv05(zpd10)dv03(zpd4v3)
icc5 no text/osd. tv67 (bc547c)
icc5 no ttext/osd. dv05 zener (zpd10) on text pcb.dv03 zener zpd4v3
icc5 no tuning it20 (tda6316ap) no volts to tuner.
icc5 no tuning it20(tda6316ap).
icc5 no video text ok rv74 2r7
icc5 no video tv50.
icc5 no video,nicam pcb 3 connect pins, luma output (top);luma input (bottom).
icc5 no/int color dv21, r35.
icc5 ns raster rg42(1r5).
icc5 odd field coloured lines(1k5) nr thyristor
icc5 odd lines on pic , scart ok,u6316 pll chip it20
icc5 osd sync rv36(22k).
icc5 osg ir01 ir01 tr84(bc238-40).
icc5 picture flutter check cp37(4700uf).
icc5 pic ripple. tr107 l120.
icc5 poor ew,ew coil+tda4950 ,dl41(byw76), dl46(by228),rl44(66+120r)
icc5 poor focus loptx faulty
icc5 poor pic lo emission rv73 47kr 1w,
icc5 poor scart picture,add 6n8f63v across rs26.
icc5 poor sound cs05(22nf/100nf).
icc5 poor start+top lines rl22(1k5) cl22(4u7f)+cl52(1000uf).
icc5 pulsing sound = nicam unit.
icc5 pulsing. dl55 (ba157)
icc5 ragged verticals dv68 on text pcb
icc5 remote control, ir receiver sl466 ic
icc5 rhs crackling is10.
icc5 ripple on picture, tr107+l120.
icc5 rolling lines, dl22(ba157).
icc5 scart poor pic. add 6n8f63v across rs26.
icc5 set trips 3 times tl29(bc639), rl30(1r ).
icc5 slow start dp51(1n4002) 12v bridge.
icc5 smeary picture iv50(u4647b).
icc5 sound hiss, tda4453 in can.
icc5 sound popping add 47k between pins 13 & 16 of is08 on pc1253
icc5 sound stutter front of spk & mid spk mounting
icc5 sound int rhs front mounted headphone socket.
icc5 sparking from res nr coil in corner lg11
icc5 stby programme up button on tv front for 6 seconds.
icc5 stby cp46, dl52(ba157),rp46dp44(zpd5v6),mda2062).
icc5 stby eht surge ic904(sl486) .
icc5 stby loptr s2000a3 tl31,cl48 10.5nf
icc5 stby press prog up front for 6 seconds.
icc5 stby rp42
icc5 stby s2000a3 +cl48(10n5f)
icc5 stby s2000a3 loptr tl31+cl48(10n5)
icc5 telefunken 617 3trips loptx.
icc5 test discon loptx 8+10, bulb 100w pin8 to earth lites 3 times if ok.
icc5 text dropout iv28 dvt5403 ir01.
icc5 text line tearing dv68(zdp6v2).
icc5 text no osg tv07.
icc5 top 3 colored flyback lines dl21 thyristor
icc5 top cramp rf12(1k),il14.
icc5 tripped cp37 4,700uf was .
icc5 tripped rl10
icc5 tripping cl48(11nf).+loptx
icc5 tripping cp29(47nf).
icc5 tripping dl51(by397)/cg05.
icc5 tripping focus arcing.
icc5 tripping ir01(micropro).
icc5 tripping ir81(mc7805).
icc5 tripping lg11 tda 4950 +s2000af .
icc5 tripping loptr+cl48.
icc5 tripping loptx s/c pins 11/3.
icc5 tripping loptx+dp37(byw72).
icc5 trips (0u33f250v)+tda4950 .
icc5 trips (22uf250v)+rl23(1r) .
icc5 trips 3 times dead cp24 47uf100v drive coupler to tr24.
icc5 trips 3 times cp24(47uf100v) drive coupler to tr24 .
icc5 trips 3 times dead dl55 ba157 cl58 47uf100v rv82 10r .
icc5 trips 3 times dl25(zpd10).
icc5 trips 3 times dl55(ba157),cl58(47uf100v),rv82(10r)
icc5 trips cl16(3n3f) il14,dl51.
icc5 trips cp37(4700uf).
icc5 trips disable tl17 c/e. dl25 zpd10 zener 13v line monitor.
icc5 trips dl25(zpd10 zenner.
icc5 trips once stby rl44 56r hold mains sw for 3-4secs
icc5 trips quietly 0u33f 250v nr loptx, e/w coil tda4950
icc5 trips tp16(bc368).
icc5 tuning bad qt16(4mhz).
icc5 tuning no 33v voltage ,tt12 bc547
icc5 vcr flag waving ,use channels end in zero. ie 10, 20 etc.
icc5 warm no ew correction pg02 2k2
icc5 warm trips cl33(10uf25v)+cp23(2n2)
icc5 white raster check rv82.
icc5 white raster rv82.
icc5 width 1″ on lhs text ic iv02.