MAGNADYNE TV17P "ZEUSI" CHASSIS T-202 INTERNAL VIEW.

The CHASSIS T-202 is a modular chassis type so easy to understand.

The tuning circuits has a large knob potentiometers tuning system which use voltage controlled capacitances such as varactor diodes as the frequency determining elements.

Therefore a stable AFC circuit is developed:

A superheterodyne receiver having an automatic intermediate frequency control circuit with means to prevent the faulty regulation thereof. The receiver has means for receiving a radio frequency signal and mixing the same with the output of a superheterodyne oscillator. This produces an intermediate frequency signal which is coupled to a frequency or phase discriminator to produce an error signal for controlling the frequency of the superheterodyne oscillator. A regulation circuit is provided having an electronic switch to interrupt the feedback circuit when only unwanted frequencies tend to produce faulty regulation of the superheterodyne oscillator.


Power supply is realized with mains transformer and Linear transistorized power supply stabilizer, A DC power supply apparatus includes a rectifier circuit which rectifies an input commercial AC voltage. The rectifier output voltage is smoothed in a smoothing capacitor. Voltage stabilization is provided in the stabilizing circuits by the use of Zener diode circuits to provide biasing to control the collector-emitter paths of respective transistors.A linear regulator circuit according to an embodiment of the present invention has an input node receiving an unregulated voltage and an output node providing a regulated voltage. The linear regulator circuit includes a voltage regulator, a bias circuit, and a current control device.

In one embodiment, the current control device is implemented as an NPN bipolar junction transistor (BJT) having a collector electrode forming the input node of the linear regulator circuit, an emitter electrode coupled to the input of the voltage regulator, and a base electrode coupled to the second terminal of the bias circuit. A first capacitor may be coupled between the input and reference terminals of the voltage regulator and a second capacitor may be coupled between the output and reference terminals of the voltage regulator. The voltage regulator may be implemented as known to those skilled in the art, such as an LDO or non-LDO 3-terminal regulator or the like.
The bias circuit may include a bias device and a current source. The bias device has a first terminal coupled to the output terminal of the voltage regulator and a second terminal coupled to the control electrode of the current control device. The current source has an input coupled to the first current electrode of the current control device and an output coupled to the second terminal of the bias device. A capacitor may be coupled between the first and second terminals of the bias device.
In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
A circuit is disclosed for improving operation of a linear regulator, having an input terminal, an output terminal, and a reference terminal. The circuit includes an input node, a transistor, a bias circuit, and first and second capacitors. The transistor has a first current electrode coupled to the input node, a second current electrode for coupling to the input terminal of the linear regulator, and a control electrode. The bias circuit has a first terminal for coupling to the output terminal of the linear regulator and a second terminal coupled to the control electrode of the transistor. The first capacitor is for coupling between the input and reference terminals of the linear regulator, and the second capacitor is for coupling between the output and reference terminals of the linear regulator. The bias circuit develops a voltage sufficient to drive the control terminal of the transistor and to operate the linear regulator. The bias circuit may be a battery, a bias device and a current source, a floating power supply, a charge pump, or any combination thereof. The transistor may be implemented as a BJT or FET or any other suitable current controlled device.




TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUITGENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)

The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.



TBA920 line oscillator combination
DESCRIPTION
The line oscillator combination TBA920 is a monolithic
integrated circuit intended for the horizontal deflection of the black and white
and colour TV sets
picture tube.

FEATURES:
SYNC-PULSE SEPARATION
OPTIONAL NOISE INVERSION
GENERATION OF A LINE FREQUENCY VOL-
TAGE BY MEANS OF AN OSCILLATOR
PHASE COMPARISON BETWEEN SYNC-
PULSE AND THE OSCILLATOR WAVEFORM

PHASE COMPARISON BETWEEN THE OS-
CILLATOR WAVEFORM AND THE MIDDLE OF
THE LINE FLY-BACK PULSE
AUTOMATIC SWITCHING OF THE VARIABLE
TRANSCONDUCTANCE AND THE VARIABLE
TIME CONSTANT TO ACHIEVE NOISE SUP-
PRESSION AND, BY SWITCHING OFF, POS-
SIBILITY OF TAPE-VIDEO-REGISTERED RE-
PRODUCTION
SHAPING AND AMPLIFICATION OF THE OS-
CILLATOR WAVEFORM TO OBTAIN PULSES
FOR THE CONTROL OF DRIVING STAGES IN
HORIZONTAL, DEFLECTION CIRCUITS
USING EITHER TRANSISTORS OR THYRISTORS


 THE TBA920 SYNC/TIMEBASE IC It has been quite common for some time for sync separation to be carried out in an i.c. but until 1971 this was as far as i.c.s had gone in television receiver timebase circuitry. With the recent introduction of the delta featured 110°  colour series however i.c.s have gone a step farther since this chassis uses a TBA920 as sync separator and line generator. A block diagram of this PHILIPS /Mullard  i.c. is shown in Fig. 1.
The video signal at about 2-7V peak -peak is fed to the sync separator section at pin 8, the composite sync waveform appearing at pin 7.
The noise gate switches off the sync separator when a positive -going input pulse is fed in at pin 9, an external noise limiter circuit being required .
The line sync pulses are shaped by R1 /C1 /C2/R2 and fed in to the oscillator phase detector section at pin 6.
The line oscillator waveform is fed internally to the oscillator phase detector circuit which produces at pin 12 a d.c. potential which is used to lock the line oscillator to the sync pulse frequency, the control potential being fed in at pin 15. The oscillator itself is a CR type whose waveform is produced by the charge and discharge of the external capacitor (C7) connected to pin 14. The oscillator frequency is set basically by C7 and R6 and can be varied by the control potential appearing at pin 15 from pin 12 and the external line hold control. Internally the line oscillator feeds a triangular waveform to the oscillator and flyback phase detector sections and the pulse width control section. The coincidence detector section is used to set the time constant of the oscillator phase detector circuit. It is fed internally with sync pulses from the sync separator section, and with line flyback pulses via pin 5. When the flyback pulses are out of phase with the sync pulses the impedance looking into pin 11 is high (21(Q). When the pulses are coincident the impedance falls to about 150Q and the oscillator phase detector circuit is then slow acting. The effect of this is to give fast pull -in when the pulses are out of sync and good noise immunity when they are in sync. The coincidence detector is controlled by the voltage on pin 10. When the sync and flyback pulses are in sync C3 is charged: when they are out of sync C3 discharges via R3. VTR use has been taken into consideration here. With a video recorder it is necessary to be able to follow the sync pulse phase variations that occur as a result of wow and flutter in the tape transport system, while noise is much less of a problem. For use with a VTR therefore the network on pin 10 can simply be left out so that the oscillator phase detector circuit is always fast acting. A second control loop is used to adjust the timing of the pulse output obtained from pin 2 to take into account the delay in the line output stage. The fly back phase detector compares the frequency of the flyback pulses fed in at pin 5 with the oscillator signal which has already been synchronised to the sync pulse frequency.
Any phase difference results in an output from pin 4 which is integrated and fed into the pulse width control section at pin 3. The potential at pin 3 sets the width of the output pulse obtained at pin 2: with a high positive voltage (via R11 and R12) at pin 3 a 1:1 mark -space ratio out- put pulse (32/us on, 32/us off) will be produced while a low potential at pin 3 (negative output at pin 4) will give a 16us output pulse at  the same frequency. The action of this control loop continues until the fly- back pulses are in phase with a fixed point on the oscillator waveform: the flyback pulses are then in phase with the sync pulses and delays in the line output stage are compensated. The output obtained at pin 2 is of low impedance and is suitable for driving valves, transistors or thyristors: R9 is necessary to provide current limiting.


TDA1190 & TDA1190Z:
ONE CHIP tv SOUND SYSTEM
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The TDA1190 and TDA1190Z are silicon monolithic
integrated circuits in 12-pin plastic power packages.
They perform all the functions needed for TV sound systems, including IF limiter-amplifier, FM detector, AF preamplifier and power output stage.

The TDA1190 is specified for 5.5 MHz (PAL) sound systems and the TDA1190Z is specified for 4.5 MHZ (NTSC) sound systems. They are constructed using the Fairchild Planar‘ epitaxial process.
They provide an output power of 4.2 W into a 16 S2 load at V+ = 24 V, or 1.5 W into an
8.0 Q load at V+ = I2 V. This performance, together with the FM-IF section characteristics of high sensitivity, high AM rejection and low distortion, enables them to be used in almost every type of television receiver. No external shielding is needed.

The basic differences between the TDA1190 and TDA1190Z are:

The TDA1190Z is designed for a larger volume control potentiometer
The TDA1190 includes one of the gain adjust resistors on the chip, while in the TDA119OZ
both are required in the external circuitry.