GRUNDIG SUPER COLOR B7681/96 SERIE M4022 SUPER SOUND CHASSIS CUC740 INTERNAL VIEW.

The CUC series was replacing all earlier Grundig TV chassis types known as thyristors deflection based

- A completely NEW design of chassis and  power supply was developed By GRUNDIG when designing the CUC720 CUC740 CHASSIS SERIES.

Based on TDA4600 (SIEMENS) was Universally used for very long time since the design Of the CHASSIS CUC720 is the father of all chassis design from 1981 to the end of GRUNDIG productions, employing a varyiety of versions type of the control IC (TDA460X) except for CHASSIS CUC2201 and CUC3400 and CUC3410 and CUC3510 which they're based on other technology.

The low cost, simplicity of design and intrinsic efficiency of flyback transformers have made them a popular solution for power supply designs of below 100W to 150W. Other advantages of the flyback transformer over circuits with similar topology include isolation between primary and secondary and the ability to provide multiple outputs and a choice of positive or negative voltage for the output.

GRUNDIG SUPER COLOR B7681/96  SERIE M4022  SUPER SOUND  CHASSIS CUC740  Power supply Description based on TDA4601d (SIEMENS)

TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.

Description:

The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:

FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and

FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.

Referring now to the drawing and, first, particularly to FIG. 1 thereof, there is shown a rectifier circuit G in the form of a bridge current, which is acted upon by a line input represented by two supply terminals 1' and 2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path of an NPN power transistor T1 i.e. the series connection of the so-called first bipolar transistor referred to hereinbefore with a primary winding I of a transformer Tr. Together with the inductance of the transformer Tr, the capacitance C1 determines the frequency and limits the opening voltages of the switch embodied by the first transistor T1. A capacitance C2, provided between the base of the first transistor T1 and the control output 7,8 of a control circuit RS, separates the d-c potentials of the control or regulating circuit RS and the switching transistor T1 and serves for addressing this switching transistor T1 with pulses. A resistor R1 provided at the control output 7,8 of the control circuit RS is the negative-feedback resistor of both output stages of the control circuit RS. It determines the maximally possible output pulse current of the control circuit RS. A secondary winding II of the transformer Tr takes over the power supply of the control circuit, in steady state operation, via the diode D1. To this end, the cathode of this diode D1 is directly connected to a power supply input 9 of the control circuit RS, while the anode thereof is connected to one terminal of the secondary winding II. The other terminal of the secondary winding II is connected to the emitter of the power switching transistor T1.

The cathode of the diode D1 and, therewith, the power supply terminal 9 of the control circuits RS are furthermore connected to one pole of a capacitor C3, the other pole of which is connected to the output 3' of the rectifier G. The capacitance of this capacitor C3 thereby smoothes the positive half-wave pulses and serves simultaneously as an energy storage device during the starting period. Another secondary winding III of the transformer Tr is connected by one of the leads thereof likewise to the emitter of the first transistor T1, and by the other lead thereof via a resistor R2, to one of the poles of a further capacitor C4, the other pole of which is connected to the first-mentioned lead of the other secondary winding III. This second pole of the capacitor C4 is simultaneously connected to the output 3' of the rectifier circuit G and, thereby, via the capacitor C3, to the cathode of the diode D1 driven by the secondary winding II of the transformer Tr as well as to the power supply input 9 of the control circuit RS and, via a resistor R9, to the cathode of a second diode D4. The second pole of the capacitor C4 is simultaneously connected directly to the terminal 6 of the control circuit RS and, via a further capacitor C 6, to the terminal 4 of the control circuit RS as well as, additionally, via the resistor R6, to the other output 4' of the rectifier circuit G. The other of the poles of the capacitor C4 acted upon by the secondary winding II is connected via a further capacitor C5 to a node, which is connected on one side thereof, via a variable resistor R4, to the terminals 1 and 3 of the control circuit RS, with the intermediary of a fixed resistor R5 in the case of the terminal 1. On the other side of the node, the latter and, therefore, the capacitor C5 are connected to the anode of a third diode D2, the cathode of which is connected on the one hand, to the resistor R2 mentioned hereinbefore and leads to the secondary winding III of the transformer Tr and, on the other hand, via a resistor R3 to the terminal 2 of the control circuit RS.

The nine terminals of the control circuit RS have the following purposes or functions:

Terminal 1 supplies the internally generated reference voltage to ground i.e. the nominal or reference value required for the control or regulating process;

Terminal 2 serves as input for the oscillations provided by the secondary winding III, at the zero point of which, the pulse start of the driving pulse takes place;

Terminal 3 is the control input, at which the existing actual value is communicated to the control circuit RS, that actual value being generated by the rectified oscillations at the secondary winding III;

Terminal 4 is responsive to the occurrence of a maximum excursion i.e. when the largest current flows through the first transistor T1 ;

Terminal 5 is a protective input which responds if the rectified line voltage drops too sharply; Terminal 6 serves for the power supply of the control process and, indeed, as ground terminal;

Terminal 7 supplies the d-c component required for charging the coupling capacitor C2 leading to the base of the first transistor T1 ;

Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and

Terminal 9 serves as the first terminal of the power supply of the control circuit RS.

Further details of the control circuit RS are described hereinbelow.

The capacity C3 smoothes the positive half-wave pulses which are provided by the secondary winding II, and simultaneously serves as an energy storage device during the starting time. The secondary winding III generates the control voltage and is simultaneously used as feedback. The time delay stage R2 /C4 keeps harmonics and fast interference spikes away from the control circuit RS. The resistor R3 is provided as a voltage divider for the second terminal of the control circuit RS. The diode D2 rectifies the control pulses delivered by the secondary winding III. The capacity C5 smoothes the control voltage. A reference voltage Uref, which is referred to ground i.e. the potential of terminal 6 is present at the terminal 1 of the control circuit RS. The resistors R4 and R5 form a voltage divider of the input-difference control amplifier at the terminal 3. The desired secondary voltage can be set manually via the variable resistor R4. A time-delay stage R6 /C6 forms a sawtooth rise which corresponds to the collector current rise of the first bipolar transistor T1 via the primary winding I of the transformer Tr. The sawtooth present at the terminal 4 of the control circuit RS is limited there between the reference voltage 2 V and 4 V. The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the control circuit RS the enabling voltage for the drive pulse at the output 8 of the control circuit RS.

The diode D4, together with the resistor R9 in cooperation with the diode D1 and the secondary winding II, forms the starting circuit provided, in accordance with the invention. The operation thereof is as follows:

After the switching power supply is switched on, d-c voltages build up at the collector of the switching transistor T1 and at the input 4 of the control circuit RS, as a function in time of the predetermined time constants. The positive sinusoidal half-waves charge the capacitor C3 via the starting diode D4 and the starting resistor R9 in dependence upon the time constant R9.C3. Via the protective input terminal 5 and the resistor R11 not previously mentioned and forming the connection between the resistor R9 and the diode D1, on the one hand, and the terminal 5 of the control circuit RS, on the other hand, the control circuit RS is biased ready for switching-on, and the capacitor C2 is charged via the output 7. When a predetermined voltage value at the capacitor C3 or the power supply input 9 of the control circuit RS, respectively, is reached, the reference voltage i.e. the nominal value for the operation of the control voltage RS, is abruptly formed, which supplies all stages of the control circuit and appears at the output 1 thereof. Simultaneously, the switching transistor T1 is switched into conduction via the output 8. The switching of the transistor T1 at the primary winding T of the transformer Tr is transformed to the second secondary winding II, the capacity C3 being thereby charged up again via the diode D1. If sufficient energy is stored in the capacitor C3 and if the re-charge via the diode D1 is sufficient so that the voltage at a supply input 9 does not fall below the given minimum operating voltage, the switching power supply then remains connected, so that the starting process is completed. Otherwise, the starting process described is repeated several times.

In FIG. 2, there is shown a further embodiment of the circuit for a blocking oscillator type switching power supply, according to the invention, as shown in FIG. 1. Essential for this circuit of FIG. 2 is the presence of a second bipolar transistor T2 of the type of the first bipolar transistor T1 (i.e. in the embodiments of the invention, an npn-transistor), which forms a further component of the starting circuit and is connected with the collector-emitter path thereof between the resistor R9 of the starting circuit and the current supply input 9 of the control circuit RS. The base of this second transistor T2 is connected to a node which leads, on the one hand, via a resistor R10 to one electrode of a capacitor C7, the other electrode of which is connected to the anode of the diode D4 of the starting circuit and, accordingly, to the terminal 1' of the supply input of the switching power supply G. On the other hand, the last-mentioned node and, therefore, the base of the second transistor T2 are connected to the cathode of a Zener diode D3, the anode of which is connected to the output 3' of the rectifier G and, whereby, to one pole of the capacitor C3, the second pole of which is connected to the power supply input 9 of the control circuit RS as well as to the cathode of the diode D1 and to the emitter of the second transistor T2. In other respects, the circuit according to FIG. 2 corresponds to the circuit according to FIG. 1 except for the resistor R11 which is not necessary in the embodiment of FIG. 2, and the missing connection between the resistor R9 and the cathode of the diode D1, respectively, and the protective input 5 of the control circuit RS.

Regarding the operation of the starting circuit according to FIG. 2, it can be stated that the positive sinusoidal half-wave of the line voltage, delayed by the time delay stage C7, R10 drives the base of the transistor T2 in the starting circuit. The amplitude is limited by the diode D3 which is provided for overvoltage protection of the control circuit RS and which is preferably incorporated as a Zener diode. The second transistor T2 is switched into conduction. The capacity C3 is charged, via the serially connected diode D4 and the resistor R9 and the collector-emitter path of the transistor T2, as soon as the voltage between the terminal 9 and the terminal 6 of the control circuit RS i.e. the voltage U9, meets the condition U9 <[UDs -UBE (T2)].

Because of the time constant R9.C3, several positive half-waves are necessary in order to increase the voltage U9 at the supply terminal 9 of the control circuit RS to such an extent that the control circuit RS is energized. During the negative sine half-wave, a partial energy chargeback takes place from the capacitor C3 via the emitter-base path of the transistor T2 of the starting circuit and via the resistor R10 and the capacitor C7, respectively, into the supply network. At approximately 2/3 of the voltage U9, which is limited by the diode D3, the control circuit RS is switched on. At the terminal 1 thereof, the reference voltage Uref then appears. In addition, the voltage divider R5 /R4 becomes effective. At the terminal 3, the control amplifier receives the voltage forming the actual value, while the first bipolar transistor T1 of the blocking-oscillator type switching power supply is addressed pulsewise via the terminal 8.

Because the capacitor C6 is charged via the resistor R6, a higher voltage than Uref is present at the terminal 4 if the control circuit RS is activated. The control voltage then discharges the capacitor C6 via the terminal 4 to half the value of the reference voltage Uref, and immediately cuts off the addressing input 8 of the control circuit RS. The first driving pulse of the switching transistor T1 is thereby limited to a minimum of time. The power for switching-on the control circuit RS and for driving the transistor T1 is supplied by the capacitor C3. The voltage U9 at the capacitor C3 then drops. If the voltage U9 drops below the switching-off voltage value of the control circuit RS, the latter is then inactivated. The next positive sine half-wave would initiate the starting process again.

By switching the transistor T1, a voltage is transformed in the secondary winding II of the transformer Tr. The positive component is rectified by the diode D1, recharing of the capacitor C3 being thereby provided. The voltage U9 at the output 9 does not, therefore, drop below the minimum value required for the operation of the control circuit RS, so that the control circuit RS remains activated. The power supply continues to operate in the rhythm of the existing conditions. In operation, the voltage U9 at the supply terminal 9 of the control circuit RS has a value which meets the condition U9 >[UDs -UBE (T2)], so that the transistor T2 of the starting circuit remains cut off.

For the internal layout of the control circuit RS, the construction shown, in particular, from FIG. 3 is advisable. This construction is realized, for example, in the commercially available type TDA 4600 (Siemens AG).

The block diagram of the control circuit according to FIG. 3 shows the power supply thereof via the terminal 9, the output stage being supplied directly whereas all other stages are supplied via Uref. In the starting circuit, the individual subassemblies are supplied with power sequentially. The d-c output voltage potential of the base current gain i.e. the voltage for the terminal 8 of the control circuit RS, and the charging of the capacitor C2 via the terminal 7 are formed even before the reference voltage Uref appears. Variations of the supply voltage U9 at terminal 9 and the power fluctuations at the terminal 8/terminal 7 and at the terminal 1 of the control circuit RS are leveled or smoothed out by the voltage control. The temperature sensitivity of the control circuit RS and, in particular, the uneven heating of the output and input stages and input stages on the semiconductor chip containing the control circuit in monolithically integrated form are intercepted by the temperature compensation provided. The output values are constant in a specific temperature range. The message for blocking the output stage, if the supply voltage at the terminal 9 is too low, is given also by this subassembly to a provided control logic.

The outer voltage divider of the terminal 1 via the resistors R5 and R4 to the control tap U forms, via terminal 3, the variable side of the bridge for the control amplifier formed as a differential amplifier. The fixed bridge side is formed by the reference voltage Uref via an internal voltage divider. Similarly formed are circuit portions serving for the detection of an overload short circuit and circuit portions serving for the "standby" no-load detection, which can be operated likewise via terminal 3.

Within a provided trigger circuit, the driving pulse length is determined as a function of the sawtooth rise at the terminal 4, and is transmitted to the control logic. In the control logic, the commands of the trigger circuit are processed. Through the zero-crossing identification at input 2 in the control circuit RS, the control logic is enabled to start the control input only at the zero point of the frequency oscillation. If the voltages at the terminal 5 and at the terminal 9 are too low, the control logic blocks the output amplifier at the terminal 8. The output amplifier at the terminal 7 which is responsible for the base charge in the capacitor C2, is not touched thereby.

The base current gain for the transistor T1 i.e. for the first transistor in accordance with the definition of the invention, is formed by two amplifiers which mutually operate on the capacitor C2. The roof inclination of the base driving current for the transistor T1 is impressed by the collector current simulation at the terminal 4 to the amplifier at the terminal 8. The control pulse for the transistor T1 at the terminal 8 is always built up to the potential present at the terminal 7. The amplifier working into the terminal 7 ensures that each new switching pulse at the terminal 8 finds the required base level at terminal 7.

Supplementing the comments regarding FIG. 1, it should also be mentioned that the cathode of the diode D1 connected by the anode thereof to the one end of the secondary winding II of the transformer Tr is connected via a resistor R11 to the protective input 5 of the control circuit RS whereas, in the circuit according to FIG. 2, the protective input 5 of the control circuit RS is supplied via a voltage divider R8, R7 directly from the output 3', 4' of the rectifier G delivering the rectified line a-c voltage, and which obtains the voltage required for executing its function. It is evident that the first possible manner of driving the protective input 5 can be used also in the circuit according to FIG. 2, and the second possibility also in a circuit in accordance with FIG. 1.

The control circuit RS which is shown in FIG. 3 and is realized in detail by the building block TDA 4600 and which is particularly well suited in conjunction with the blocking oscillator type switching power supply according to the invention has 9 terminals 1-9, which have the following characteristics, as has been explained in essence hereinabove:

Terminal 1 delivers a reference voltage Uref which serves as the constant-current source of a voltage divider R5.R4 which supplies the required d-c voltages for the differential amplifiers provided for the functions control, overload detection, short-circuit detection and "standby"-no load detection. The dividing point of the voltage divider R5 -R4 is connected to the terminal 3 of the control circuit RS. The terminal 3 provided as the control input of RS is controlled in the manner described hereinabove as input for the actual value of the voltage to be controlled or regulated by the secondary winding III of the transformer Tr. With this input, the lengths of the control pulses for the switching transistor T1 are determined.

Via the input provided by the terminal 2 of the control circuit RS, the zero-point identification in the control circuit is addressed for detecting the zero-point of the oscillations respectively applied to the terminal 2. If this oscillation changes over to the positive part, then the addressing pulse controlling the switching transistor T1 via the terminal 8 is released in the control logic provided in the control circuit.

A sawtooth-shaped voltage, the rise of which corresponds to the collector current of the switching transistor T1, is present at the terminal 4 and is minimally and maximally limited by two reference voltages. The sawtooth voltage serves, on the one hand as a comparator for the pulse length while, on the other hand, the slope or rise thereof is used to obtain in the base current amplification for the switching transistor T1, via the terminal 8, a base drive of this switching transistor T1 which is proportional to the collector current.

The terminal 7 of the control circuit RS as explained hereinbefore, determines the voltage potential for the addressing pulses of the transistor T2. The base of the switching transistor T1 is pulse-controlled via the terminal 8, as described hereinbefore. Terminal 9 is connected as the power supply input of the control circuit RS. If a voltage level falls below a given value, the terminal 8 is blocked. If a given positive value of the voltage level is exceeded, the control circuit is activated. The terminal 5 releases the terminal 8 only if a given voltage potential is present.

Foreign References:
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.

Inventors:

Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)

 GRUNDIG Simplified horizontal /  line deflection circuit.

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This GRUNDIG CHASSIS Series was featuring a Simplified BU208A  Based horizontal deflection section replacing all Thyristor horizontal timebase based circuits.
A flyback transformer (FBT), also called a line output transformer (LOPT), is a special transformer, which is used for conversion of energy (current and voltage) in electronic circuits. It was initially designed to generate high current sawtooth signals at a relatively high frequency. In modern applications is used extensively in switched-mode power supplies for both low (3V) and high voltage (over 10 kV) supplies.
Flyback Transformer

It was invented as a means to control the horizontal movement of the electron beam in a cathode ray tube (CRT). Unlike conventional transformers, a flyback transformer is not fed with a signal of the same waveshape
as the intended output current. A convenient side effect of such a transformer is the considerable energy that is available in its magnetic circuit. This can be exploited using extra windings that can be used to provide power to operate other parts of the equipment. In particular, very high voltages are easily obtained using relatively few turns of winding which, once rectified, can provide the very high accelerating voltage for a CRT. Many more recent applications of such a transformer dispense with the need to produce high currents and just use the device as a relatively efficient means of producing a wide range of lower voltages using a transformer much smaller than a conventional mains transformer would be.

A horizontal deflection circuit makes a sawtooth
current flow through a deflection coil. The current
will have equal amounts of positive and negative
current. The horizontal switch transistor conducts
for the right hand side of the picture. The damper
diode conducts for the left side of the picture.
Current only flows through the fly back capacitor
during retrace time.



For time 1 the transistor is turned on. Current
ramps up in the yoke. The beam is moved from the
center of the picture to the right edge. Energy is
stored on the inductance of the yoke.
E=I2L/2


For time 2 the transistor is turned off. Energy
transfers from the yoke to the flyback capacitor. At
the end of time two all the energy from the yoke is
placed on the flyback capacitor. There is zero
current in the yoke and a large voltage on the
capacitor. The beam is quickly moved from the
right edge back to the middle of the picture.









During time 3 the energy on the capacitor flows
back into the yoke. The voltage on the flyback
capacitor decreases while the current in the yoke
builds until there is no voltage on the capacitor. By
the end of time 3 the yoke current is at it's
maximum amount but in the negative direction.
The beam is quickly deflected form the center to the
left edge.






Time 4 represents the left hand half of the picture.
Yoke current is negative and ramping down. The
beam moves from the left to the center of the
picture.












The current that flows when the horizontal switch is
closed is approximately:
Ipk ≅ Vcc T / Ldy
Ipk = collector current
T = 1/2 trace time
Ldy = total inductance (yoke + lin coil + size coil)
note:The lin coil inductance varies with current.
______
Tr ≅ 3.14 √ L C
The current that flows during retrace is produced by
the C and L oscillation. The retrace time is 1/2 the
oscillation frequency of the L and C.
I2L /2 ≅ V2C /2 or I2L = V2C As stated earlier the energy in the yoke moves to the
flyback capacitor during time 2.
V= the amount of the flyback pulse that is above the
supply voltage.


D.C. annualizes is inductors are considered
shores, capacitors are open and generally
semiconductors are removed. The voltage at the
point “B+” is the supply voltage. The collector
voltage of Q1 is also at the supply voltage. The
voltage across C2 is equal to the supply voltage.
When we A.C. annualize this circuit we will find
that the collector of Q1 has a voltage that ranges
from slightly negative to 1000 volts positive. The
average voltage must remain the same as the D.C.
value.
In the A.C. annualizes of the circuit, the
inductance of the yoke (DY) and the inductance of
the flyback transformer are in parallel. The
inductance of T2 is much larger than that if the
DY. This results is a total system inductance of
about 10% to 20% less than that of the DY it’s
self.
The voltage across the Q1 is a half sinusoid pulse during the flyback or retrace period and close to zero at
all other times. It is not possible or safe to observe this point on an oscilloscope without a proper high
frequency high voltage probe. Normally use a 100:1 probe suitable for 2,000V peak. The probe must have
been high frequency calibrated recently.


HORIZONTAL SIZE /  E/W AMPLITUDE - CORRECTION CIRCUIT:

There are several different methods of adjusting horizontal size.



SIZE COIL
Add a variable coil to the yoke current path
causes the total inductance to vary with the coils
setting.
The yoke current is related to supply voltage,
trace time and total inductance. This method
has a limited range!
The horizontal section uses a PWM to set the
horizontal size. One DAC sets the horizontal
size and another DAC sets the pincushion and
trap.
The Raster Centering (D.C. centering) is
controlled by a DAC.
On small monitors the retrace time is fixed. On
large monitors or wide frequency range monitors
two different retrace times are available. The flyback time is set by the micro computer by selecting two
different flyback capacitors. At slow frequencies the longer retrace time is selected.
Different S corrector capacitor values are selected by the micro computer. At the highest frequency the
smallest capacitor is selected.



SPLIT DIODE MODULATOR
This horizontal circuit consists of two parts. D1, C1, C2 and DY are the components as described above.
D2, C3, C4 and L1 are a second “dummy” horizontal section that does not cause deflection current. By the
D.C. analyzing this circuit the voltage across C2 + C4 must equal the supply voltage (B+). Deflection
current in the DY is related to the supply voltage minus the voltage across C4. For a maximum horizontal
size the control point must be held at ground. This causes the dummy section to not operate and the DY
section will get full supply voltage. If the control point is at 1/3 supply then the DY section will be
operating at 2/3 supply.
Note: The impedance of (D1,C1,C2 and DY) and (D2,C3,C4 and L1) makes a voltage divider. If the
control point is not connected then there is some natural voltage on C4. Most split diode monitors are built
to pull power from the dummy section through L2 to ground. A single power transistor shunts from the
control point to ground. It is true that power can be supplied from some other supply through L2 to rise the voltage on C4. For maximum range a bi-directional power amplifier can drive the control point.
The most exciting feature if the split diode modulator is that the flyback pulse, as seen by the flyback
transformer, is the same size at all horizontal size settings.


HORIZONTAL SWITCH/DAMPER DIODE
On the right hand side of the screen, the H. switch transistor conducts current through the deflection yoke.
This current comes from the S correction capacitors, which have a charge equal to the effective supply
voltage. The damper diode allows current for the left hand side of the screen to flow back through the
deflection yoke to the S capacitors.
FLYBACK CAPACITOR
The flyback capacitor connects the hot side of the yoke to ground. This component determines the size and
length of the flyback pulse. ‘Tuning the flyback capacitor’ is done to match the timing of the flyback pulse
to the video blanking time of the video signal. The peak flyback voltage on the horizontal switch must be
set to less that 80% if the Vces specification. The two conditions of time and voltage can be set by three
variables (supply voltage, retrace capacitor and yoke inductance) .
S CAPACITOR
The S capacitors corrects outside versus center linearity in the horizontal scan. The voltage on the S cap
has a parabola plus the DC horizontal supply. Reducing the value of S cap increases this parabola thus
reducing the size of the outside characters and increasing the size of the center characters.
S Capacitor value: Too low: picture will be squashed towards edges.
Too high: picture will be stretched towards edges.

By simply putting a capacitor in series with each coil, the sawtooth waveform is
modified into a slightly sine-wave shape. This reduces the scanning speed near the
edges where the yoke is more sensitive. Generally the deflection angle of the electron
beam and the yoke current are closely related. The problem is the deflection angle
verses the distance of movement on the CRT screen does not have a linear effect.

BASE DRIVE CURRENT
The base drive resistor determines the amount of
base drive. If the transistor is over driven the Vsat
looks very good, but the current fall time is poor.
If the base current is too small the current fall time is very fast. The problem is that the transistor will have many volts across C-E when closed.
The best condition is found by placing the transistor in the heaviest load condition. Adjust the base resistor for the least power consumption then increase the base drive a small amount. This will slightly over drive the base.

BU208(A)

Silicon NPN
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.

DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.

APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.

ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C


Testing Flyback Transformer:

Nowadays, more and more monitor comes in with flyback transformers problems.
Testing flyback transformer are not difficult if you carefully follow the
instruction. In many cases, the flyback transformer can become short
circuit after using not more than 2 years. This is partly due to bad design
and low quality materials used during manufactures flyback transformer.
The question is what kind of problems can be found in a flyback transformer
and how to test and when to replace it. Here is an explanation that will help
you to identify many flyback transformer problems.
There are nine common problems can be found in a flyback transformer.
a) A shorted turned in the primary winding.
b) An open or shorted internal capacitor in secondary section.
c) Flyback Transformer becomes bulged or cracked.
d) External arcing to ground.
e) Internal arcing between windings.
f) Shorted internal high voltage diode in secondary winding.
g) Breakdown in focus / screen voltage divider causing blur display.
h) Flyback Transformer breakdown at full operating voltage (breakdown when under load).
i) Short circuit between primary and secondary winding.

Testing flyback transformer will be base on (a) and (b) since problem
(c) is visible while problem (d) and (e) can be detected by hearing the arcing
sound generated by the flyback transformer. Problem (f) can be checked with multimeter
set to the highest range measured from anode to ABL pin while (g) can be solved by
adding a new monitor blur buster (For 14' & 15' monitor only.) Problem (h) can only be
tested by substituting a known good similar Flyback Transformer. Different monitor have
different type of flyback transformer design. Problem (i) can be checked using an
ohm meter measuring between primary and secondary winding. A shorted turned or open
in secondary winding is very uncommon.

What type of symptoms will appear if there is a shorted turned in primary winding?
a) No display (No high voltage).
b) Power blink.
c) B+ voltage drop.
d) Horizontal output transistor will get very hot and later become shorted.
e) Along B+ line components will spoilt. Example:- secondary diode UF5404 and B+ FET IRF630.
f) Sometimes it will cause the power section to blow.

What type of symptoms will appear if a capacitor is open or shorted in a flyback transformer?

Capacitor shorted

a. No display (No high voltage).
b. B+ voltage drop.
c. Secondary diode (UF5404) will burned or shorted.
d. Horizontal output transistor will get shorted.
e. Power blink.
f. Sometimes power section will blow, for example: Raffles 15 inch monitor.
g. Power section shut down for example: Compaq V55, Samtron 4bi monitor.
h. Sometimes the automatic brightness limiter (ABL) circuitry components will get burned.
This circuit is usually located beside the flyback transformer. For example: LG520si

Capacitor open

a. High voltage shut down.
b. Monitor will have ‘tic - tic’ sound. Sometimes the capacitor may measure O.K. but
break down when under full operating voltage.
c. Horizontal output transistor will blow in a few hours or days after you have replaced it.
d. Sometimes it will cause intermittent "no display".
e. Distorted display i.e., the display will go in and out.
f. It will cause horizontal output transistor to become shorted and blow the power section.

How to check if a primary winding is good or bad in a Flyback Transformer?
a) By using a flyback/LOPT tester, this instrument identifies faults in primary winding by
doing a ‘ring’ test.
b) It can test the winding even with only one shorted turned.
c) This meter is handy and easy to use.
d) Just simply connect the probe to primary winding.
e) The readout is a clear ‘bar graph’ display which show you if the flyback transformer
primary winding is good or shorted.
f) The LOPT Tester also can be used to check the CRT YOKE coil, B+ coil and switch mode power transformer winding.

NOTE: Measuring the resistance winding of a flyback transformer, yoke coil, B+ coil and
SMPS winding using a multimeter can MISLEAD a technician into believing that a shorted
winding is good. This can waste his precious time and time is money.

How to diagnose if the internal capacitor is open or shorted?
By using a normal analog multimeter and a digital capacitance meter. A good capacitor have the range from 1.5 nanofarad to 3 nanofarad.*
1) First set your multimeter to X10K range.
2) Place your probe to anode and cold ground.
3) You must remove the anode cap in order to get a precise reading.
4) Cold ground means the monitor chassis ground.
5) If the needle of the multimeter shows a low ohms reading, this mean the internal capacitor
is shorted.
6) If the needle does not move at all, this doesn’t mean that the capacitor is O.K.
7) You have to confirm this by using a digital capacitance meter which you can easily get one
from local distributor.
8) If the reading from the digital capacitance meter shows 2.7nf, this mean the capacitor is
within range (O.K.).
9) And if the reading showed 0.3nf, this mean the capacitor is open.
10) You have three options if the capacitor is open or shorted.
- Install a new flyback transformer or
- Send the flyback transformer for refurbishing or
- Send the monitor back to customers after spending many hours and much effort on it.

* However certain monitors may have the value of 4.5nf, 6nf and 7.2nf.
Note: Sometimes the internal capacitor pin is connected to circuits (feedback) instead of ground.
Tv rca flyback transformer circuits usually do not have a internal capacitor in it.
If you have a flyback diagram and circuits which you can get it from the net, that would be an advantage to easily understand how to check them.


----------------------------------------------------------------------------------


Note on the upper right chassis the Ensemble / Stereo bandwidth enhancer unit.


GRUNDIG SUPER COLOR B7681/96  SERIE M4022  SUPER SOUND  CHASSIS CUC740 This version Incorporates a Stereo band expansion Unit fitted on the right bottom side of the cabinet.

It combines circuits to feature the Stereo sound expansion:29502.006.01
A system and method for enhancing the stereo sound effect produced by speaker systems having two or more speakers fed by two or more channels or audio, respectively. Second-order high pass filtering is applied to first and second audio signals of a stereo signal. A phase shift of approximately 180 degrees is applied to the resulting signals. A mixer mixes the processed first audio signal with the original second audio signal and mixes the processed second audio signal with the original first audio signal, whereby an expanded stereo sound field effect is created.

Stereo separation is the ability of an audio system to reproduce the spatial location information of sound sources in an audio recording. During stereo recording, two or more microphones, in different locations, are typically used to record an acoustic source. The time delays and pressure differences between the audio signals from the microphones provide spatial information. The spatial information allows the listener to interpolate the location of the various sound sources in the recording. By contrast, a monophonic sound recording may contain the same detail of the recorded source, but will not contain the spatial information of stereophonic sound.

Various design factors may have a negative affect on stereo separation. For example, audio systems which have the right and left stereo speaker drivers in close proximity to each other can suffer from poor channel separation, which reduces the stereo sound field effect, yielding a sound that is more monophonic than stereophonic. Other factors that can negatively affect stereo separation include, but are not limited to, the physical design of the speaker enclosure, speaker placement within the enclosure, and sound processing techniques, including bass enhancement circuits or algorithms.

In audio systems that include two speaker drivers and a subwoofer, driving the speakers out of phase with respect to each other can be used to enhance the stereo sound field effect. This technique is generally disadvantageous, however, particularly in audio systems containing two speaker drivers without a subwoofer, because it can cause phase-related distortion of the low-frequency content due to the generally monophonic nature of such content; because the low-frequency signal is substantially the same in both the left and right channels, running the left and right speakers out of phase causes cancellation of desirable low frequencies.

Various electrical circuits have been provided for enhancing the stereo sound field, but these typically utilize complex circuitry and speaker driver configurations to create the effect. For example, U.S. Pat. No. 5,870,484 to Greenberger teaches a sound reproduction system having an array of loudspeaker transducer elements that operate in combination with signal processing circuitry to control the radiation pattern of sound radiating from the system. Signals fed to the system are manipulated by the signal processing circuitry so that the signals are each radiated in their desired directions, thereby improving spatial separation. Such approaches, however, are complex and expensive to implement, and are inappropriate for stereo systems containing a small number of loudspeaker transducer elements.

It is therefore an object of the invention to provide an improved system and method for enhancing the stereo sound field in speaker systems.

It is one object of the invention to provide a system and method for providing enhanced stereo sound field which overcomes one or more of the limitations of the prior art.

It is a further object of the invention to provide an enhanced stereo sound effect in audio systems that include two or more speaker drivers but which do not include a subwoofer.

It is a further object of the invention to provide a system and method for enhancing the stereo sound effect without sacrificing low frequency content.

In one embodiment, the invention provides a system and method for enhancing the stereo sound effect produced by speaker systems having two or more speakers fed by two or more channels or audio, respectively. Second-order high pass filtering is applied to first and second audio signals of a stereo signal. A phase shift of approximately 180 degrees is applied to the resulting signals. A mixer mixes the processed first audio signal with the original second audio signal and mixes the processed second audio signal with the original first audio signal, whereby an expanded stereo sound field effect is created.

The disclosed system and method can be used in any audio system and is particularly useful when the audio system contains two or more speaker drivers without a subwoofer. The system and method improves the stereo field without sacrificing low frequency content.

TDA3561A (PHILIPS)

Luminance+Chrominance+RGB MATRIX

PAL decoder TDA3561A

GENERAL DESCRIPTION



The TDA3561A is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals.

Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages.
The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:

· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded.
The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt transitions from colour to white signals.

· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.

· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.

· Non-synchronized external RGB signals do not disturb the black level of the internal signals.

· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.

· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.

· High current capability of the RGB outputs and the chrominance output.





























































TUNING SYSTEM 96 PROGR. (ABSTIMMUNG BAUSTEIN 29504- 003.04)

96 Programs frequency synthesized tuning system based on SIEMENS uController and SIEMENS
synthesizer and memory.

- SDA2010 A013 uController

- SDA2112-3 (Uc controlled frequency systhesizer)

- SDA2006 (Memory x 3)






















- TDA2594 (PHILIPS) Synch Separator + H-OSC

- TDA2653 (PHILIPS) FRAME Deflection Output + V-OSC

Vertical deflection circuit TDA2653A

DESCRIPTION

The TDA2653A is a monolithic integrated circuit for vertical deflection in large screen colour television receivers.

The circuit incorporates the following functions:

· Oscillator; switch capability for 50 Hz/60 Hz operation
· Synchronization circuit
· Blanking pulse generator with guard circuit
· Sawtooth generator with buffer stage
· Preamplifier with fed-out inputs
· Output stage with thermal and short-circuit protection
· Flyback generator
· Voltage stabilizers

QUICK REFERENCE DATA
Note
1. for 45 AX systems
PACKAGE OUTLINE
13-lead SIL; plastic power (SOT141RGA); SOT141-6; 1996 November 19.

Supply voltage (pin 9) V9-8= VS typ. 26 V
Supply current (pin 5 + pin 9) (1) I5 + I9 = IS typ. 325 mA
Output current (peak-to-peak value) (1) I6(p-p) typ. 1,7 A
Maximum output current (peak-to-peak value) I6(p-p) max. 2,6 A
Picture frequency f 50 Hz/60 Hz
Sync input pulse (peak-to-peak value) V2-8(p-p) ³ 1 V
Thermal resistance from junction to mounting base Rth j-mb £ 5 K/W





TDA2030 14W Hi-Fi AUDIO AMPLIFIER

DESCRIPTION
The TDA2030 is a monolithic integrated circuit in
Pentawatt[ package, intended for use as a low
frequency class AB amplifier. Typically it provides
14W output power (d = 0.5%) at 14V/4W; at ± 14V
or 28V, the guaranteed output power is 12W on a
4W load and 8W on a 8W (DIN45500).
TheTDA2030 provideshigh outputcurrentand has
very low harmonic and cross-over distortion.
Further the device incorporates an original (and
patented) short circuit protection system comprising
an arrangement for automatically limiting the
dissipated power so as to keep the working point
of the output transistors within their safe operating
area.A conventional thermal shut-down system is
also included.

SHORT CIRCUIT PROTECTION
TheTDA2030hasan original circuit whichlimits the
current of the output transistors. Fig. 18 shows that
the maximum output current is a function of the
collector emitter voltage; hence the output transistors
work within their safe operating area (Fig. 2).
This function can thereforebe consideredas being
peak power limiting rather than simple current limiting.
It reduces the possibility that the device gets damaged
during an accidental short circuit from AC
output to ground.

THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the
following advantages:
1. An overload on the output (even if it is permanent),
or an abovelimit ambienttemperaturecan
be easily supported since the Tj cannot be
higher than 150°C.
2. The heatsink can have a smaller factor of safety
compared with that of a conventional circuit.
There is no possibility of device damage due to
high junction temperature.If for any reason, the
junction temperatureincreasesup to 150°C, the
thermal shut-down simply reduces the power
dissipation at the current consumption.
The maximum allowable power dissipation depends
upon the size of the external heatsink (i.e. its
thermal resistance); fig. 22 shows this dissipable
power as a function of ambient temperature for
different thermal resistance.



- Stereo Sound Decoder 29504-002.001 TDA2795 + TDA1195 + TDA4942.

- Sound Amplifier unit 29504-004.12 TDA2030 (see above)






















GRUNDIG SUPER COLOR B7681/96  SERIE M4022  SUPER SOUND  CHASSIS CUC740 Remote control television with external data bus connection,
Remote Control With MOS IC's For TV Sets: THE GRUNDIG AV FEATURE CONNECTOR TECHNOLOGY:A television receiver is provided for use as a picture display terminal for electronic peripheral equipment, where a control system with a data-bus is built into the television receiver for multitude of commands and in which the television receiver is intended to be used in addition to the normal direct reception of televised pictures for other possible applications. The television receiver can serve as a monitor for a picture tape recorder, which is equipped for recording independently of the television receiver. A complete television receiving set is provided with automatic transmitter seeking mechanism and electronic channel storage.


1. A system for the use of a television receiver for external control of electronic peripheral devices, said television being of the type including a built-in integrated circuit remote control receiver, said remote control receiver being divided into two sections, one section being allocated to the remote control of the receiving and reproduction sections of the television receiver and the other section being allocated to a databus having nothing to do with the television receiver receiving and reproduction sections; an output terminal of said databus comprising an adaptor connector between said television receiver and an external peripheral device; a peripheral device external to the television receiver; cable means connecting the output of said databus with said peripheral device; and a decoder interposed between said databus output terminal and peripheral device for converting data from said databus into a form suitable for controlling functions of said peripheral device.

2. A television receiver as a picture terminal according to claim 1, in which said external coupling includes a connecting cable between the external connections of the television set and the peripheral device forming a unitary unit together with a decoder which transforms the data from the data collector into a code which directly controls the functions of the peripheral device.

3. A television receiver as a picture terminal according to claim 1 or 2, in which the peripheral device is a picture taping device which operates for recording independently from the television set which acts as a monitor.

4. A television receiver as a picture terminal according to claim 1, in which the functions controlled by said first commands include the on-off switching, picture, sound and channel selection of the television receiver and the functions controlled by said second commands include electronic program storage and changeover functions.

Description:

BACKGROUND OF THE INVENTION
Integrated circuits are presently known in the art for the convenient operation of television receivers, whereby the functions of on-off switching, channel selection, picture (video) and sound (audio) can be remotely controlled by the received telecontrol signal. In particular, the following function can be operated by such a system: Switching on and off of the equipment, calling for different program channels, variations and basic adjustments of sound level, brightness and color saturation, silencing of the sound as well as inserting of time references. With a known and presently available operating system up to 16 channels can be installed, so that it is possible, to select directly that number of programs and to tune the receiver to the appropriate channel.
Television receivers available today in many designs provide for up to 30 remotely controlled channels or channels controlled by the received signal (tele-signal) to properly operate. Additionally, infrared control is also becoming popular. These controls provide commands by means of a databus so that the operation of the various functions is possible with the provision of additional commands.
It is further known to equip peripheral equipment such as video tape recorders with a so-called electronic-tap-key rather than keys with a long throw so that all parts which are susceptable to mechanical wear are eliminated and replaced by digital controls.
It has become of interest to connect the peripheral equipment such as the video tape recorder to the television receiver so that both can be conveniently operated. With the development of new concepts simplification of design becomes critical for ease of operation and reduction of expense.
SUMMARY OF THE INVENTION
A television receiver as a picture display terminal for electronic peripheral devices wherein a remote control system with a data collector is installed for receiving a plurality of commands and in which only a portion of the commands is used for the remote control functions of the receiving and display portions of the television set, while another portion of the commands is used for adjusting the functions of an electronic peripheral device which may be coupled with a television set, and that the data collector is electrically coupled by means of an external coupling of the television set with the corresponding stages of the peripheral device.
BRIEF DESCRIPTION OF THE DRAWING
The FIGURE is a diagrammatic showing of a television receiver and electronic periphery device incorporating the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A television receiver and electronic peripheral device incorporating the invention are shown in the FIGURE. The television receiver 10 can be used as a picture display terminal for peripheral device 12. This provides the advantage, that by means of a single tele-control signal, the control of functions of the receiving and displaying sections of the television receiver can be accomplished as well as the control functions of the peripheral equipment 12, which is connected to the receiver. The peripheral device does not require a separate tele-control system since that which is already installed in the television receiver can be used. To accomplish this, portion A of the available commands A, B of the tele-control system 11 are used for the function of the television receiver 10. The remaining portion B of the available commands A, B, which is made available at databus or data collector 14 is used for the control of functions of the peripheral equipment. The databus, which is coordinated with the peripheral equipment, and which is built into the tele-control system of the television receiver, is connected electrically to external terminal 16 of the television receiver. The external terminals at television receivers and peripheral equipment are relatively inexpensive.
The primary expenses result from the necessary cable connections between the external terminals of the television receiver and the peripheral equipment, as well as the auxiliary apparatus, such as decoder 18, which decodes the data from the databus 14 and prepares it for the peripheral equipment. These expenses are reduced by simplified design, in which the connecting cables 20 and 22 together with the auxiliary apparatus or decoder 18 are combined in one component or building block. This building block can be offered as an accessory to the user of television receivers with peripheral equipment.
The invention can be used with especial advantage in connecting a television receiver with a picture tape recorder as a peripheral equipment. The picture tape recorder is equipped preferably for recording independently from the television receiver, so that the latter serves as a monitor only. With such a switching combination it is possible, for example, to accomplish this with a single control system, and by the help of a tele-control system, which is built into the television receiver, to operate the channel selection and drive mechanism control, the control for an electronic switch clock and programming of the switch commands of the picture tape recorder as well as the control of the function of the receiving and displaying unit of the receiver. In this way it is possible to use the tele-control of a television receiver additionally for the tele-control of the picture tape recorder without substantial higher expenses.

 GRUNDIG SUPER COLOR B7681/96  SERIE M4022  SUPER SOUND  CHASSIS CUC740 Television receiver including a teletext decoder circuit :

In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.

1. A receiver for television signal s including a teletext decoder circuit for decoding teletext signals constituted by character codes which are transmitted in the television signal, and comprising:
a video input circuit receiving the television signal and converting it into a serial data flow;
an acquisition circuit for receiving the serial data flow supplied by the video input circuit and selecting that part therefrom which corresponds to the teletext page described by the viewer;
a character generator comprising:
a memory medium addressed by the character codes which together represent the teletext page desired by the user and which in response to each character code successively supply m₂ series of m₁ simultaneously occurring character picture element codes each indicating wether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m₁ simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m₁ character picture element codes of a series one after the other and at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed;
characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m₁ clock pulse to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m₁ character picture element codes.
2. A character generator for use in a receiver teletext claim 1, comprising:
a memory medium which is addressable by character codes and successively applies m₂ series of m₁ simultaneously occurring character picture element codes in response to a character code applied as an address thereto, each character picture element code indicating whether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m₁ simultaneously occurring character picture element codes and the display clock pulses for supplying the m₁ character picture element codes of the series one after the other at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed; characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m₁ clock pulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m₁ character picture element codes.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.
2. Description of the Prior Art
As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.
Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.
A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.
For the purpose of display each character is considered as a matrix of m ₁ ×m ₂ picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m ₁ qμsec, each line has a length of 40 m ₁ μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m ₁ =6 have been chosen.
The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m ₁ ×m ₂ memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m ₁ memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m ₁ substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m ₁ character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).
The frequency f _d at which the display clock pulses occur directly determines the length of a picture element and hence the character width. In the above-mentioned case in which m ₁ =6 and in which a character width of 1 μsec is chosen, this means that f _d =6 MHz. A change in the rate of the display clock pulses involves a change in the length of a line of the page to be displayed (now 40 μsec). In practice a small deviation of, for example, not more than 5% appears to be acceptable. For generating the display clock pulses the generator circuit receives reference clock pulses. In the decoder circuit described in Reference 1 these reference clock pulses are also supplied at a rate of 6 MHz, more specifically by an oscillator specially provided for this purpose.
OBJECT AND SUMMARY OF THE INVENTION
A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.
According to the invention,
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m ₁ clockpulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m ₁ character picture element codes.
The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m ₁ picture elements, m ₁ reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m ₁ character picture element codes.
REFERENCES
1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.
3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.
4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;
FIG. 2 shows different matrices of picture elements constituting a character;
FIG. 3 shows diagrammatically the general structure of a character generator;
FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 5 shows some time diagrams to explain its operation;
FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 7 shows some time diagrams to explain its operation;
FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.
EXPLANATION OF THE INVENTION
General structure of a TV receiver
FIG. 1 shows diagrammatically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2 receiving a television signal modulated on a high-frequency carrier, which signal is processed in a plurality of processing circuits. More particularly, it is applied to a tuning circuit 23 (tuner or channel selector). This circuit receives a band selection voltage V _B in order to enable the receiver to be tuned to a frequency within one of the frequency bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning voltage V _T with which the receiver is tuned to the desired frequency within the selected frequency band.
This tuning circuit 3 supplies an oscillator signal having a frequency of f _OSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.
The signal CVBS thus obtained is also applied to a colour decoder circuit 5. this circuit supplies the three primary colour signals R', G' and B' which in their turn are applied via an amplifier circuit 6 to a display device 7 in the form of a display tube for the display of broadcasts on a display screen 8. In the colour decoder circuit 5 colour saturation, contrast and brightness are influenced by means of control signals ANL. The circuit also receives an additional set of primary colour signals R, G and B and a switching signal BLK (blanking) with which the primary colour signals R', G' and B' can be replaced by the signals R, G and B of the additional set of primary colour signals. A Philips IC of the TDA 356X family described in Reference 3 can be used for this circuit 5.
The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency f _o from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.
The Philips IC SAA 5030 may be used as video input circuits 91, the Philips IC SAA 5040 may be used as teletext acquisition and control circuit, a 1K8 RAM may be used as page memory, a modified version of the Philips IC SAA 5050 may be used as character generator 94 and a modified version of the Philips IC SAA 5020 may be used as control circuit 95, the obvious modification being a result of the fact that this IC is originally intended to receive reference clock pulses at a rate of 6 MHz for which 13.5 MHz has now been taken.
The acquisition and control circuit 92 is also connected to a bus system 11. A control circuit 12 in the form of a microcomputer, an interface circuit 13 and a non-volatile memory medium 14 are also connected to this system. The interface circuit 13 supplies the said band selection voltage V _B , the tuning voltage V _T and the control signals ANL for controlling the analog functions of contrast, brightness and colour saturation. It receives an oscillator signal at the frequency f' _OSC which is derived by means of a frequency divider 15, a dividing factor of which is 256, from the oscillator signal at the frequency f _OSC which is supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 13 combined constitute a frequency synthesis circuit. The Philips IC SAB 3035 known under the name of CITAC (Computer Interface for Tuning and Analog Control) and described in Reference 4 can be used as interface circuit 13. A specimen from the MAB 84XX family, manufactured by Philips, can be used as a microcomputer.
The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage V _B and a given tuning voltage V _T so that the receiver is tuned to the desired transmitter.
For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.
The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receives operating instructions and activates, via the bus system 11, one of the circuits connected thereto. It is to be noted that an operating instruction may be a single instruction, that is to say, it is complete after depressing only one key. It may also be multiple, that is to say, it is not complete until two or more keys have been depressed. This situation occurs, for example, when the receiver is operating in the teletext mode. Operation of figure keys then only yields a complete operating instruction when, for example, three figure keys have been depressed. As is known, such a combination results in the page number of the desired teletext page.
The character generator
As already stated, a character is a matrix comprising m ₂ rows of m ₁ picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m ₁ =6 and m ₂ =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.
FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m ₁ ×m ₂ memory elements each comprising a character picture element code. Each m ₁ ×m ₂ character picture element code corresponds to a picture element of the character and defines, as already stated, whether the relevation picture element must be displayed in the so-called foreground colour or in the so-called background colour. Such a character picture element code has the logic value "0" or "1". A "0" means that the corresponding picture element must be displayed in the background colour (for example, white). The "1" means that the corresponding picture element must be displayed in the foreground colour (for example, black or blue). At C in FIG. 2 there is indicated, the contents of the sub-memory for the character shown at B in FIG. 2.
The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.
The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.
The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f ₀ . In the character generator described in Reference 2, page 391, f ₀ is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.
When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f ₀ is not a rational multiple of 6 MHz, for example, if f ₀ =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.
FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec.
An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding network 9442 each time supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse in a group of fourteen reference clock pulses. More particularly the display clock pulse, which is obtained each time in response to the first reference clock pulse of a group, is applied to the output line 9443, whilst the other display clock pulses are applied to the output line 9444. Thus, the pulse series shown at B and C in FIG. 5 occur at these output lines 9443 and 9444, respectively.
The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.
This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register elements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422.
Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.
The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.
The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.
As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner.
In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6 by ensuring that two consecutive picture elements partly overlap each other. This is realized in the converter circuit shown in FIG. 4 by means of a rounding circuit 9427 which receives the character picture element codes occurring at the output of the shift register circuit 9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D flip-flop 9427(2). The T input of this flip-flop receives the clock pulses shown at E in FIG. 5, which pulses are derived from the reference clock pulses TR by means of a delay circuit 9427(3). This circuit has a delay time t ₀ for which a value in the time diagram indicated at E in FIG. 5 is chosen which corresponds to half a clock pulse period of the reference cock pulses. The character picture element codes supplied by the shift register circuit 9420 are now applied directly and via the D flip-flop 9427(2) to the OR gate which thereby supplies the six character picture element codes CH(.) in the time intervals as indicated at F in FIG. 5. The result of this measure for the display of the character with the letter A is shown at F in FIG. 2.
The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providing it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 have the same reference numerals. The converter circuit 942 shown in FIG. 8 differs from the circuit shown in FIG. 6 in that the said rounding circuit denoted by the reference numeral 9428 is incorporated between the pulse widening circuit 9426 and the AND gate circuits 9424(.). More particularly this rounding circuit is a pluriform version of the rounding circuit 9427 shown in FIG. 4 and is constituted by six D flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the respective control signals S(1) to S(6) directly and via the D flip-flops. The T inputs of these D flip-flops again receive the version of the reference clock pulses delayed over half a reference clock pulse period by means of the delay circuit 94210. This rounding circuit thus supplies the control signals S'(.) shown in FIG. 7.

Other References:

Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5030 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.



GRUNDIG SUPER COLOR B7681/96  SERIE M4022  SUPER SOUND  CHASSIS CUC740   Teletext / Videotext Error correction circuit using character probability :

An error correction circuit in a television receiver for receiving, for example, Teletext information, Viewdata information or information of comparable systems. The codes representing symbol information received by the receiver are classified into one out of two or more classes in dependence on the frequency of their occurrence, this classification being an indication of the extent to which it is probable that a received code is correctly received.
In FIG. 1, a picture text television receiver has a receiving section, audio and video amplifiers 4 and 9 and a picture tube 10, 11. A text decoder 21 receives symbol information which is stored in a store 25 for display. An error detector circuit 40 including a comparison circuit 43 and two parity circuits 41 and 42, and checks for parity between newly received and already stored symbol information. A reliability circuit 60 is also included.

1. An error correction circuit for a receiving device for receiving digitally transmitted symbol information, the transmission of this information being repeated one or more times, the receiving device having a decoding circuit for decoding the received information, an information store coupled to said decoding circuit for storing the information, a circuit for generating synchronizing signals and a video converter circuit coupled to said information store and said generating circuit for converting information and synchronizing signals into a composite video signal for application to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of video lines greater than one, the error correction circuit being coupled to said decoding circuit and said information store and including means coupled between said decoding circuit and said information store for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, a write-switch having one input coupled to said decoding circuit and an output coupled to said information store, and a write-setting circuit, coupled to another input of said write-switch, which determines whether the newly received information is written or not written into the information store, said write-setting circit having an input coupled to said checking means whereby the results of said checking are a factor in the setting of said write-switch by said write-setting circuit, characterized in that the error correction circuit further comprises a classification circuit coupled to the output of said decoding circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, the input of the classification circuit being coupled to another input of the write-setting circuit. 2. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the write-setting circuit includes a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to the information store for accessing the additional storage elements, for determining, from the additional storage element corresponding with the symbol address position of newly received symbol information, a new reliability bit, an output of the reliability circuit being coupled back to the information store for writing this new reliability bit into the corresponding additional storage element when the reliability bit for this symbol address changes its value. 3. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the checking means comprises a comparison circuit for bit-wise comparing a newly received and decoded symbol with a symbol read from an address of the information store, this address corresponding with the symbol location, a comparison output of the comparison circuit being coupled to a further input of the reliability circuit. 4. An error correction circuit for a receiving device as claimed in any one of the preceding claims, characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store. 5. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the reliability circuit comprises a reliability flipflop and a reliability read circuit for this flipflop, an output of which also constitutes the output of the reliability circuit. 6. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the error correction circuit comprises a second classification circuit, coupled between said other classification circuit and said write-setting circuit and having inputs coupled to said information store, for classifying a symbol read from the information store. 7. An error correction circuit for a receiving device as claimed in claim 1 characterized in that the information store comprises, for each symbol address in the information store, at least one further storage element for storing the classification associated with the symbol for that symbol address.

Description:

BACKGROUND OF THE INVENTION
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking.
Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity.
For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 ⁸ ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European languages, in so far they are written in latin characters, have all sorts of "extra" characters, for example Umlaut letters, accent letters, etc. When all these extra characters are totalled, including Icelandic, Maltese and Turkish, then it appears that a total of approximately 220 symbols is required, namely the 128 known symbols plus further symbols for these "extra" characters.
Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds.
As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the symbols for one text line of 40 characters in one video line, whereas on the other hand the average transmission rate decreases if more video lines are needed for the information transmission. This solution is generally considered to be unacceptable, also because the compatibility with existing receivers would be fully lost.
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.
SUMMARY OF THE INVENTION
It is the object of the invention to provide an error correction circuit of the type referred to for a receiving device for Teletext and comparable systems, which offers such a solution for the problem outlined above that also for an 8-bit code without a parity bit substantially all errors, if any, can be corrected in the second transmission cycle which is received.
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A _x will never be received as another A-symbol A _y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839.
For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be considered to be somewhat suspect. This also applies to each B-symbol recorded in the first cycle, which may lead to a further improvement when a decision is taken.
Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
When the transmitter successively transmits an A-symbol for a certain symbol and location and symbols ABA are successively received, then the A-symbol may be recorded as being "non-suspect" after the first cycle, indicated by an R (reliable) hereinafter. An R' after the second (A), the brackets indicating that the information is retained (not written into the information store) indicates the assumed non-reliability of this retained (A)-symbol, and an A and an R in the third cycle indicates the reliability of the correctly received A-symbol. The A-symbol in the information store is now again assumed to be reliable for this symbol sequence.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used.
As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.
It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:

TABLE I

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Modified Class Symbol (n+1) Parity symbol (n+1) Parity

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A xxxxxxx 1 1 xxxxxxx 1 1 A xxxxxxx 0 1 xxxxxxx 1 0 B xxxxxxx 1 0 xxxxxxx 0 1 B xxxxxxx 0 0 xxxxxxx 0 0

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In this case only one 8-bit parity circuit is needed.
It is of course alternatively possible to realize the second classification circuit virtually by using the first classification circuit twice on a time-sharing basis, first as the first and then as the second classification circuit. This requires some additional control logic and some additional time, so that the provision of a second classification circuit will be preferred, especially in the case where a simple parity check is performed.
The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A receiving section 1 having an aerial input 2 comprises the high-frequency receiving section, the intermediate-frequency amplifier section, the detection and the synchronizing circuits of the receiver. An audio output 3 is coupled to one or more loudspeakers 5 via an audio amplifier 4. Via control switches 7 and 8 a video output 6 is coupled for normal television reception to a video amplifier 9 for a picture tube 10 comprising the picture screen 11. Via a control switch 13 a synchronizing output 12 is coupled during normal television reception to a time-base circuit 14 which supplies the deflection voltages for the picture tube 10 via an output 15.
However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.
The decision whether the content of the buffer register 23 must be transferred or not transferred to the storage register 24 is taken by an error correction circuit, which would, in the known Teletext system, consist of a parity check circuit.
The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having two inputs and an output. An input 45-i of each of the write switches is always connected to a corresponding output 46-i of the buffer register 23, these outputs also being connected respectively to inputs 47-1 to 47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7 inclusive, of the comparison circuit 43.
The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK _R =CLK, obtained from the clock signal generator 29. J _R =R/WR _G +(R/W)'EP (I) K _R =R/WR _G +(R/W)'EB (II)
in which R _G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2.
Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S _x in consecutive cycles 0 to 7, inclusive, indicated as S _x ,0 to S _x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S ₀ to S _x -1, inclusive, and S _x +1 to S ₉₅₉ , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R _G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R _G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R _G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.

TABLE II

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Decision Read Write SR EP EB R G 23➝24 Written S R K R

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1 0 0 0 1 0 0 x 2 1 0 0 1 1 1 x 3 1 1 0 1 1 1 x 5 1 1 1 0 1 x 1 6 1 0 1 0 0 x 0 7 0 0 1 0 0 x 0 (4) 1 0 0 1 0 0 x

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The states, indicated by an x, of J _R and K _R are irrelevant for the position of the flipflop. The equations I and II have been chosen thus that the required values "0" and "1" for J _R and K _R are produced.
FIG. 2 shows the states and EP, EB and R in the line sections 112, 113 and 105, respectively, by means of an example which shows an unprobable burst of received errors, such that each one of the decisions occurs at least once.
When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R _G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R _G remains "0" because J _R =0, K _R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R _G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.
In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1" at the output "odd parity".
This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R _G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:

TABLE III

______________________________________

Read Write Written Decision EP R G 23-24 R G

______________________________________

1A 1 0 1 1 2A 1 1 1 1 3A 0 0 1 0 4A 0 1 0 0

______________________________________

Again this embodiment can be easily realized by one normally skilled in the art, using what has been described herein.
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.

GRUNDIG SUPER COLOR B7681/96  SERIE M4022  SUPER SOUND  CHASSIS CUC740  Frequency synthesizer tuning system for television receivers:

SHOWING SIEMENS SDA2010 / SDA2010 A013 uController - SDA2112-3 (Uc controlled frequency systhesizer)
- SDA2006 (Memory x 3)



" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"

A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The tuning consists of three discrete time periods. First, a settling time to allow channel change transients to settle; second, a short period of forced search at a relatively rapid rate to insure proper tuning; and third, a slower rate of step-by-step correction to accomodate for station drift and the like during reception. This third time period is initiated either by the passage of a fixed length of time following the start of the forced search period or by sensing a preestablished number of changes of state in the output of the frequency discriminator during the forced/search period.


1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.

Description:

BACKGROUND OF THE INVENTION
Both of the above mentioned patents are directed to frequency synthesizer tuning systems for use with television receivers to enable operation of the receivers with minimal viewer fine tuning adjustments. By the utilization of the frequency synthesizer tuning systems of these patents, the fine tuning adjustment which is necessary with conventional types of television receiver tuning systems has been substantially eliminated. The system employed in the '953 patent permits utilization of a frequency synthesizer tuning system which correctly tunes to a desired television station or channel even if the transmitted signals from that station are not precisely maintained at the proper frequencies. The '535 patent is directed to a signal seek tuning system adaptation of the frequency synthesizer tuning system of the '953 patent which still permits implementation of all of the desired wide-band pull in range of the frequency synthesizer system of the '953 patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.

It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.

The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Most of the circuitry of this receiver is conventional, and for that reason it has not been shown in FIG. 1. Added to the conventional television receiver circuitry of FIG. 1, however, is a frequency synthesizer tuning system, in accordance with a preferred embodiment of the invention, which is capable of automatically changing the reference frequency when a frequency offset exists in the received signal for a particular channel.
Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circuit for producing an output in response to the presence of vertical synchronizatin pulses, a picture carrier detection circuit, and an automatic gain control (AGC) amplifier. Outputs representative of these sensor components are shown as being coupled over a group of lead 20 to sensory circuitry 22, which in turn couples outputs representative of the operation of these various sensor circuits to a microprocessor unit 23 for controlling the operation of the microprocessor unit.
The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.

The microprocessor SIEMENS SDA2010 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.

The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of the interface between the keyboard 25, the microprocessor unit 23, and the circuitry used in the frequency synthesizer portions of the system. A commercially available microprocessor which has been used for the microprocessor 23, and which forms the basis for the diagramatic representation of the microprocessor in FIG. 2, is the Matsushita Electronics Corporation MN1402 four-bit single-chip microcomputer. This microcomputer has two, four-bit parallel input ports labeled "A" and "B". In addition, three output ports, a five-bit output port "C" and two four-bit output ports "D" and "E" are provided. The internal configuration of the microcomputer 23 includes an arithmetic logic unit (ALU), a read only memory (ROM) for storing instructions and constants, and a random access memory (RAM) used for data memory, arranged into four files, each file containing 16 four-bit words. These words are selected by X and Y registers and this memory is used, for example, for timers, counters, etc., and also is used to hold intermediate results. To facilitate an understanding of the operation of the system, a portion of this memory is shown in FIG. 2 as a clock 81 and a reversible counter 82 connected between the "B" input port and the "D" output port. The microcomputer 23 is programmed to permit it to operate in conjunction with the remainder of the circuits shown in FIG. 2. The programming techniques are standard, and the microcomputer 23 itself is a standard commercially available circuit component.
There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.

The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port.
From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The system shown in the drawings has a capability of correcting for frequency offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2 MHz on channels 6 and 13. The remainder of the channels have a range between these two values.
If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.

Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.

The comparator 61 simply is a conventional comparator for determining whether or not the output of the frequency discriminator is positive or negative, as indicated in the upper waveform of FIG. 5. The comparators 62 and 63 are each adjusted with appropriate reference input levels to provide a narrow window centered about the center tuning frequency (fc) of the receiver. If the tuning of the receiver, as indicated by the output of the frequency discriminator 60, is outside this window on either side of the central axis shown in FIG. 5, one output condition is indicated on the input terminal B11 of the microcomputer. Only when the tuning frequency is within the tuning window, indicative of a properly tuned receiver, is the appropriate input applied to the microcomputer input terminal B11. This input overrides any other input that may be present on the input terminal B12 and is indicative of a properly tuned receiver. The input from the frequency discriminator 60, as applied to the microcomputer on its input port B12, is used to determine the direction of operation of the counter 82 of the microcomputer for the localized search count signals applied to the latch circuits 49 and 50 to change the count of the reference programmable divider counter 35 on a step-by-step basis.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in the first example considered for frequency f1; so that the counter 82 of the microprocessor 23 operates to change the count in the reference counter 35 in a manner to cause the local oscillator frequency to go higher toward a frequency f3 +Δf, as shown in FIG. 5.
A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.

The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the microcomputer 23 causes a signal to be applied through the outputs of the E output port to the decoder circuit 52 indicative of the completion of this time interval. The decoder 52 then applies a pulse on an output lead connected to the B13 input of the B input port of the microcomputer 23. This pulse is sensed by the microcomputer 23 and is applied to the clock 81 to change the clock rate to a much slower rate, approximately one-third (1/3) or one-fourth (1/4) the rate used previously during the forced search mode of operation. This then permits the system to accomodate station drifts which normally occur at a very slow rate during the transmission and reception of a television signal. As a consequence, it is possible to use more filtering in the filter 39 on the tuning line (FIG. 1) and employ a smaller frequency window for the channel verification sensed by the circuitry shown in FIG. 3.

The result is a more precise tuning from the receiver than is otherwise possible if only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output signal to the SNS1 sensory input of the microcomputer 23 only when vertical synchronizing signal components are present.
In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
For a system that does not use signal seek operation, only the frequency discriminator sensory input is required for proper operation. The discriminator 60 is used for both fine tuning direction information and to produce a frequency window to indicate the presence of a correctly tuned station (channel verification). Initially, after a channel change, there is a 250 millisecond settling time, the same as the operation described above with compatible seek. After that, however, comes a period of time where a forced localized search is produced by the microcomputer 23. The forced search is needed to insure that the system will correctly tune to stations that initially may be tuned to the undesired zero voltage crossover in the right half of the upper curve of FIG. 5. Such signals may be within the frequency window of the discriminator 60; and if a search is not forced, this system will not correctly tune. The compatible seek system described previously correctly tunes the local oscillator without a forced search, because the picture carrier detector and vertical detector do not give an output for this situation and the system automatically goes into its search mode of operation. However, the non-seek system does not have a picture carrier sensor input and must be forced to search for an initial period of time sufficient to allow the system to tune up to its maximum frequency and then reset (loop) back to a frequency of 2 Δf lower. Then it is tuned to the positive left half portion of the discriminator curve (FIG. 5) and the frequency window created by the discriminator 60 is sufficient to insure proper tuning. If the discriminator output produced by the desired incoming signal created an initial situation that produces the correct tuning direction information, i.e., in the left half of the curve of FIG. 5, or in the right half portion that gives the correct direction and

frequency window information, the forced search would not be needed. However, the forced search will produce a correct tuning situation anyway. In these cases, the tuning either is correct to begin with or correct tuning is reached quickly. Then, even though the forced search is active, it simply alternates up and down through the correct tuning point because each time the receiver is tuned a little high in frequency, it produces a negative output from the discriminator 60; and the tuning direction signal causes the system to tune down in frequency.

Then, a positive discriminator output is produced, and the system tunes up in frequency. This continues until the forced search is removed by time-out of the microcomputer 23 (a fraction of a second). At such time, the receiver is correctly tuned by the frequency window of the discriminator to be very near fc. The system cannot tune to the undesired discriminator crossover shown in the right half portion of FIG. 5 because the polarity of the tuning direction signal always causes it to tune away from that point.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.

Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the inventi

on, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.

LIST OF COMMON FAULTS / TROUBLESHOOTING  OF GRUNDIG CHASSIS  CUC740:

Grundig CUC740 Chopper tr blows instantly R633 27R o/c in base cct - also blew lop tr
Grundig CUC740 Dead - chopper tr blows instantly at sw on R633 27R o/c in base cct - also blew LOPTr
Grundig CUC740 dead - comes on briefly when tapped dry joints chopper tr and surroundings

Grundig CUC740 Dead - S1644 1.25A fuse blown T654 BU208A s/c - check for arcing at C634
Grundig CUC740 Excess width D572 SKE4G2/06
Grundig CUC740 INT CUTOUT , GOING TO SBY OR DEAD D671 5v SUPPLY
Grundig CUC740 Int Dead D671 BY299 in 5v supply int o/c
Grundig CUC740 Int dead or int st/by C633 100µ 25v
Grundig CUC740 Int sound Check if +G supply missing - if so check relay contacts
Grundig CUC740 lines across screen - no sound adj R2741 on Ablenkung pcb
Grundig CUC740 No adj of vol,col,contrast etc IC2335 MC144111 inside IF/Tuner can
Grundig CUC740 Pulling/Rolling - weak sync 2 x 1µ & 1 10µ cap in IF module
Grundig CUC740 Pulling/rolling with weak sync replace 2 x 1µ caps & 1 x 10µ cap in IF module
Grundig CUC740 Sound couldn't be reduced &"88" in display MC144111 IC2335 on tuning pcb