TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 Power supply is realized with mains transformer and Linear transistorized power supply stabilizer, A DC power supply apparatus includes a rectifier circuit which rectifies an input commercial AC voltage. The rectifier output voltage is smoothed in a smoothing capacitor. Voltage stabilization is provided in the stabilizing circuits by the use of Zener diode circuits to provide biasing to control the collector-emitter paths of respective transistors.A linear regulator circuit according to an embodiment of the present invention has an input node receiving an unregulated voltage and an output node providing a regulated voltage. The linear regulator circuit includes a voltage regulator, a bias circuit, and a current control device.
In one embodiment, the current control device is implemented as an NPN bipolar junction transistor (BJT) having a collector electrode forming the input node of the linear regulator circuit, an emitter electrode coupled to the input of the voltage regulator, and a base electrode coupled to the second terminal of the bias circuit. A first capacitor may be coupled between the input and reference terminals of the voltage regulator and a second capacitor may be coupled between the output and reference terminals of the voltage regulator. The voltage regulator may be implemented as known to those skilled in the art, such as an LDO or non-LDO 3-terminal regulator or the like.
The bias circuit may include a bias device and a current source. The bias device has a first terminal coupled to the output terminal of the voltage regulator and a second terminal coupled to the control electrode of the current control device. The current source has an input coupled to the first current electrode of the current control device and an output coupled to the second terminal of the bias device. A capacitor may be coupled between the first and second terminals of the bias device.
In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 Vertical deflection circuit
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit.
2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal.
3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit.
4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit.
5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit and the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means.
Description:
BACKGROUND OF THE INVENTION
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
One of the major causes for variation of the vertical flyback pulse width is interference by horizontal flyback pulses from the horizontal deflection circuit, in which case sufficient interlaced scanning can not be performed.
In order to avoid these inconveniences, the vertical flyback pulse width must be controlled at a constant width. However, by the reason as will be described with reference to FIG. 1, a prior art vertical deflection circuit in a television receiver fails to satisfy this requirement.
Referring now to FIG. 1 wherein a prior art vertical deflection circuit now under discussion is shown, a circuit arrangement is such that synchronizing pulses emerging from a sync separator 1 are, after having its waveform shaped in an integrator 2, applied to a vertical oscillating circuit 3 which includes a vertical oscillator 4 and a sawtooth deflecting signal generator 5. The vertical oscillator 4 upon receipt of the shaped sync pulses from the integrator 2 is driven to generate a train of pulses synchronized with the vertical synchronizing signal which are subsequently fed to the sawtooth deflecting signal generator 5. The waveform of a sawtooth deflecting signal emerging from the generator 5 is shown in FIG. 2 and this deflecting signal is transferred from the generator 5 to a vertical deflection output circuit 6 which includes a drive circuit 7 for amplifying the sawtooth deflecting signal upon receipt thereof from the generator 5 and a vertical output stage 8 having a vertical deflection coil D.
As shown in FIG. 2, the sawtooth deflecting signal includes rectangular component pulses and the wave-form of an output signal from the vertical output stage 8 which is similar to that of the sawtooth deflecting signal. The portions of the output signal from the vertical output stage 8, which correspond to the rectangular component pulses of the sawtooth deflecting signal are known as flyback pulses.
In the vertical deflection circuit of the above arrangement, the pulse width of the flyback pulses included in the output of the vertical output stage 8 is affected by the pulse width of the rectangular component pulses fed from the oscillator 4 to the output stage 8. More specifically, in the OTL type vertical deflection circuit, since there is no inductance element, such as a vertical output transformer, that determines the pulse width of the flyback pulse, the pulse width of the flyback pulse is mostly determined by the pulse width of the corresponding rectangular component pulse of the sawtooth deflecting signal applied to the output stage 8. Accordingly, variation of the pulse width of the rectangular component pulses produced in the oscillator 4 results in variation of the pulse width of the flyback pulses produced in the output stage 8.
This inconvenience is likely to be avoided if the pulse width of the output pulse from the oscillator 4 is stabilized. However, this stabilization of the pulse width of the output pulse from the oscillator 4 cannot be achieved without difficulties by the following reason.
In the vertical oscillator 4, the start of each output pulse from this oscillator 4 can be accurately determined by the vertical synchronizing signal applied thereto. On the contrary thereto, the time at which the output pulse from the oscillator 4 terminates is solely determined by operational characteristics of the oscillator 4 itself and, therefore, is often adversely affected by and in the presence of external noises. Once the oscillator 4 is adversely affected by and in the presence of the external noises, the duration between the start and termination of the output pulse from said oscillator, that is, the pulse width, varies and, therefore, the problem remains still unsolved.
SUMMARY OF THE INVENTION
Accordingly, an essential object of the present invention is to provide a vertical deflection circuit for use in a television receiver, which substantially eliminates the inconveniences inherent in the conventional circuit of a similar kind and which effectively stabilizes the pulse width of flyback pulses included in a vertical deflection output signal.
Another important object of the present invention is to provide a vertical deflection circuit of the type referred to above, wherein a pulse width control is provided between the vertical oscillator and the vertical output circuit for controlling the pulse width of the output pulses from the oscillator.
A further important object of the present invention is to provide a vertical deflection circuit of the type referred to above, wherein a feedback loop is provided to control the operation of the pulse width control in response to an output signal emerging from the vertical output stage.
A still further important object of the present invention is to provide a vertical deflection circuit of the type referred to above, wherein a feedback loop is provided to control the oscillator in response to an output signal emerging from the vertical output stage for stabilizing the pulse width of the flyback pulses produced in the vertical output stage.
These and other objects and features of the present invention will become clear from the following description taken in conjunction with preferred embodiments of the present invention with reference to the accompanying drawings in which;
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the prior art vertical deflection circuit,
FIG. 2 is a diagram showing the waveform of vertical deflection output produced in the prior art vertical deflection circuit,
FIG. 3 is a block diagram showing one embodiment of the vertical deflection circuit according to the present invention,
FIG. 4 is a circuit diagram showing the details of the vertical deflection circuit shown in FIG. 3,
FIG. 5 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 4.
FIG. 6 is a block diagram showing another embodiment of the vertical deflction circuit according to the present invention,
FIG. 7 is a circuit diagram showing the details of the vertical deflection circuit shown in FIG. 6,
FIG. 8 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 7,
FIG. 9 is a circuit diagram showing a further embodiment of the vertical deflection circuit according to the present invention,
FIG. 10 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 9.
FIG. 11 is a block diagram showing a still further embodiment of the vertical deflection circuit according to the present invention,
FIG. 12 is a circuit diagram showing the details of the vertical deflection circuit shown in FIG. 11, and
FIG. 13 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 12.
Before the description of the present invention proceeds, it should be noted that like parts are designated by like reference numerals throughout the accompanying drawings for the sake of brevity.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 3, between the vertical oscillator 4 and the sawtooth deflecting signal generator 5, there is provided a pulse width control circuit 9 for stabilizing the pulse width of pulses fed to the sawtooth deflecting signal generator 5 from the vertical oscillator 4.
FIG. 4 shows details of the pulse width control circuit 9, which will now be described.
Assuming that a pulse of unstable pulse width is applied from the vertical oscillator 4 to the input terminal T1 of the pulse width control circuit 9, which is in turn applied to the base of a switching transistor Tr1, the latter is triggered on to cause the capacitor C1 to discharge. In other words, when the pulse is applied to the pulse width control circuit 9 from the oscillator 4, that is, when the switching transistor Tr1 is non-conductive, voltage from the D-C power source Vb, after having passed through the resistor of sufficiently high resistance, charges the capacitor C1. However, the charge stored in the capacitor C1 is discharged to the ground through the collector-emitter of the switching transistor Tr1 when the latter starts conducting.
As a result, in the capacitor C1, voltage of sawtooth waveform as shown by the solid line in FIG. 5(b) is generated across said capacitor C1, which is subsequently applied to the base of a switching transistor Tr2. The latter transistor Tr2 starts conducting only when the voltage thus applied to the base thereof exceeds a D-C power source voltage E1 applied to the emitter of said transistor Tr2. Conduction of the switching transistor Tr2 results in a pulsating voltage of rectangular waveform, as shown by the solid line in FIG. 5(c), appearing at the common junction J1 of resistors R2 and R3, both of which are loaded on the collector of the transistor Tr2, due to the saturation characteristic of the transistor Tr2. The pulsating voltage at the common junction J1 is fed to the base of an amplifying transistor Tr3 so that the pulsating voltage is thereby amplified and phase-reversed and, as a result thereof, a phase-reversed pulsating voltage of the waveform as shown by the solid line in FIG. 5(d) appears at the common junction J2 of resistors R4 and R5, both of which are loaded on the collector of the transistor Tr3. This pulsating voltage at the common junction J2 is further phase-reversed by an amplifying transistor Tr4. Therefore, a voltage received by the transistor Tr6 from the collector of the amplifying transistor Tr4 has a waveform similar to that of the pulsating voltage applied to the base of the amplifying transistor Tr3.
Simultaneously, the output pulse at the input terminal T1 is also applied to the base of a transistor Tr5. The transistor Tr5 acts to phase-reverse the output pulse to produce a pulsating voltage of a waveform as shown by the solid line in FIG. 5(e) at the collector of said transistor Tr5. The collector of this transistor Tr5 is connected with the collector of the transistor Tr4, which is in turn connected to the base of the transistor Tr6. This transistor Tr5 is non-conductive when voltage applied to the base threof is zero, in which condition the base of the transistor Tr6 receives a pulse of positive potential, i.e., a high level pulse, whereby it is held in a conductive state with the collector thereof in a zero volt or low level state. If the high level pulse is applied to the base of the transistor Tr4, this high level pulse is amplified and phasereversed by the transistor Tr4 to produce a low level pulse from the collector thereof which is in turn fed to the transistor Tr6 to trigger the latter off. When the transistor Tr6 is thus triggered off, a high level voltage is produced from the collector of the transistor Tr6.
In view of the foregoing, it can be seen that these transistors Tr4, Tr5 and Tr6 cooperate with each other to substantially act as a gating circuit while the pulsating voltage applied to the base of the transistor Tr6 from the transistor Tr4 acts as a trigger pulse. Accordingly, it is clear that the pulse appearing at the collector of the transistor Tr6 has a pulse width, as shown in FIG. 5(f), which corresponds to the pulse width W1 of the output pulse at the input terminal T1 extracted by the pulse width W2 of the high level pulse applied to the base of the transistor Tr4.
As stated hereinbefore, the start of the output pulse from the oscillator 4 can be accurately fixed while it is difficult to fix the termination of the pulse. Assuming, therefore, that the output pulse shown by the broken line in FIG. 5(a) and having a pulse width t1 to t4 which is larger than the desired pulse width t1 to t2 as shown by the solid line in FIG. 5(a), is applied to the pulse width control circuit 9 from the vertical oscillator 4, the transistor Tr1 becomes non-conductive and the voltage across the capacitor C1 accordingly increases as shown by the broken line in FIG. 5(b). On the other hand, the transistor Tr5 becomes non-conductive upon receiving of the input pulse at the base thereof at the time t1, causing the transistor Tr6 to start conducting.
When the voltage at the base of the transistor Tr2 exceeds the emitter voltage defined by the source E1, the transistors Tr2 and Tr3 become conductive and the junction point J2 becomes high level at the time t3 as shown in FIG. 5(d). Accordingly, the collector of the transistor Tr4 becomes low level causing the transistor Tr6 to become non-conductive whereby the collector of the transistor Tr6 becomes high level at the time t3.
From the foregoing, it is clear that, even if the width of the input pulse applied to the pulse width control circuit 9 is larger than the desired or predetermined width, the width output pulse of the control circuit 9 can be defined at the predetermined width as shown in FIG. 5(f).
Accordingly, a rectangular pulse having a predetermined pulse width is applied to the base of the input transistor Tr8 of the sawtooth signal generator 5, whereby the width of the flyback pulses included in the vertical deflection output can be maintained at the desired or predetermined width.
In the embodiment of FIG. 3, the pulse width of the output pulse of the pulse width control circuit 9 may not be suitable for the vertical output circuit. In this case, equalization of the pulse width can be achieved by varying the D-C voltage E1 supplied to the emitter of the transistor Tr2. Specifically, if the voltage E1 increases or decreases the pulse width at the output terminal F of the control circuit 9 is reduced or enlarged, respectively.
FIG. 6 shows another embodiment of the present invention in which the pulse width control circuit 9' receives a feedback signal from the deflection output circuit 8 so that the pulse width of the output signal from the width control circuit 9' can be advantageously controlled to maintain the width of the flyback pulse constant.
FIG. 7 shows the details of the width control circuit 9'. Referring now to FIG. 7, there is provided a differential amplifier 10 composed of transistors Tr13 and Tr14. The base of the transistor Tr13 receives the voltage on the capacitor C1 and feedback voltage fed back from the common junction J6 of the deflection output circuit through the integrator 11 and the resistors R5 and R6.
The collector of the transistor Tr13 is connected to the base of the transistor Tr4 which constitutes the gating circuit in cooperation with the transistors Tr5 and Tr6. The switching level of the transistor Tr13 is defined by base voltage Eo appearing at the junction point J3 of the resistors R7 and R8.
Operation of the circuit arrangement of FIGS. 6 and 7 will now be described.
It is assumed that, during operation of the control circuit 9' with the transistor Tr1 triggered off by the application of the low level pulse from the vertical oscillator 4, voltage supplied from the integrator 11 through the constant current resistor R5 and then a time constant adjusting resistor R6 charges the capacitor C1. Voltage of a sawtooth waveform as shown by the solid line in FIG. 8(b) is generated across the capacitor C1. This sawtooth voltage is subsequently fed to the differential amplifier 10. The charging speed of the capacitor C1 is defined by the voltage E F of the integrator 11.
When the voltage at the base of the transistor Tr13 exceeds the voltage Eo appearing at the base of the transistor Tr14, the transistor Tr13 becomes conductive with the output of the transistor Tr13 becoming low level. At the end of the input pulse, transistor Tr1 becomes conductive, the capacitor C1 is discharged, whereby the transistor Tr13 becomes non-conductive causing the output of the transistor Tr13 to become high level.
Therefore, pulses of rectangular waveform as shown by the solid line in FIG. 8(c) can be generated from the collector of the transistor Tr13. The pulses from the transistor Tr13 are amplified and phase-reversed by the transistor Tr4, which are in turn applied to the base of the transistor Tr7 through the transistor Tr5. It should be noted that the waveform of pulse at the junction J5 between the transistors Tr4 and Tr5 is shown by the solid lines in FIG. 8(d).
Simultaneously, the pulses from the input terminal T1 are also applied to the base of the transistor Tr6. Consequently, in a similar manner as in the circuit arrangement of FIG. 4, pulses of a waveform as shown by the solid line in FIG. 8(f) can be obtained at the collector of the transistor Tr7 and, hence, at the output terminal T2 of the width control circuit 9'.
The output pulses from the width control circuit 9' are supplied to the base of the transistor Tr9 through the transistor Tr8, said transistors Tr8 and Tr9 forming the sawtooth signal generator 5. Output from the sawtooth signal generator 5 is then applied to the base of the transistor Tr10 in the form of sawtooth pulses as shown, thereby causing the transistor Tr10 to generate trigger pulse for driving the vertical output transistors Tr11 and Tr12 in the known manner. The result is that vertical deflection output of a waveform as shown by the solid line in FIG. 8(g) appears at the junction J6 from which it is applied in part to the vertical deflection coil D and in part to the resistor R5 through the feedback loop. The deflection output that has been fed through the feedback loop is, prior to application thereof to the resistor R5, smoothed by the integrator 11 which is composed of the resistor R9 and the capacitor C2, to obtain a control voltage Ef of a suitably divided value.
Assuming that the pulse width Pr of flyback pulses included in the vertical deflection output from the vertical output stage 8 varies, for example, gets smaller and is at a value Pr', the voltage Vr of the flyback pulse accordingly increases by the reason of the following equation: ##EQU1## wherein L is inductance of the vertical deflection coil D, i is vertical deflection current and K is a constant. In other words, while the peak level C of the flyback pulse is determined by the D-C power source voltage Vb2 and, therefore, does not vary, the average D-C voltage level Vm of the vertical deflection output is lowered to read a value Vm' as shown in FIG. 8(g).
Consequently, the pulse width control voltage Ef applied to the resistor R5 through the integrator 11 is lowered and the voltage to which the capacitor C1 is charged is also lowered. The result is such that, as indicated by the broken line in FIG. 8(b), the charging speed of the capacitor C1 is retarded whereby conduction of the transistor Tr13 is delayed. Accordingly, the waveforms of the pulses P1 and P2 at the junctions J4 and J5 are respectively narrowed as shown by the broken lines in FIG. 8(c) and (d). As a result thereof, the pulse width of the output pulse appearing at the output terminal T2 of the width control circuit 9' is broadened as shown by the broken line in FIG. 8(f) since the width of the pulse appearing at the terminal T2 is defined by a difference between the pulse at the base of the transistor Tr6 and the pulse at the base of the transistor Tr5. Therefore, the variation of the pulse width Pr of the vertical flyback pulse can be advantageously and effectively compensated for.
FIG. 9 shows a further embodiment of the present invention. In the circuit arrangement of FIG. 9, the output from the oscillator 4 is first applied to the amplifying transistor Tr15 by which it is amplified and phase-reversed. From this transistor Tr15, the pulse of a waveform as shown in FIG. 10(a) is applied to the base of the transistor Pr1, thereby causing the latter to be triggered on. During a period in which the transistor Tr1 is non-conductive, the capacitor C1 is charged through the constant current transistor Tr16 and, when the transistor Tr1 starts conducting upon receipt of the pulse from the transistor Tr15, voltage charged in the capacitor C1 is discharged through the collector-emitter of the transistor Tr1. By this operation, voltage of the sawtooth waveform as shown in FIG. 10(b) is generated across the capacitor C1. This sawtooth voltage is subsequently applied to a differential amplifier 10 composed of a pair of transistors Tr13 and Tr14. The transistor Tr14 receives control voltage Ef fed from the junction point J6 of the vertical deflection output stage 8 through the integrator 11. By the level Ef of voltage fed to the base of the transistor Tr14, the slicing level of this sawtooth voltage can be varied and, hence, the pulse width of the pulse emerging from the collector of the transistor Tr14 can be varied as indicated by W1 in FIG. 10(c). The output pulse from the collector of the transistor Tr14 is fed to the base of the transistor Tr10 of the drive circuit 7 through the sawtooth signal generator 5. The vertical deflection output of a waveform as shown in FIG. 10(d) is generated at the junction J6 of the vertical output stage 8 after the output transistors Tr11 and Tr12 are driven by drive signal from the drive circuit 7.
Assuming now that the pulse width W of the output from the oscillator 4 is suitably selected such as to be larger than that required in the vertical deflection output from the output stage 8, if the flyback pulse width Tr of the vertical deflection output becomes larger than the pulse width W, the voltage Vr of the flyback pulse is reduced for the same reason as in the embodiment of FIG. 7 while the peak level C thereof remains the same and, accordingly, the average D-C voltage Vm increases, resulting in increase of the control voltage Ef to be applied to the base of the transistor Tr14.
Therefore, the slicing level of the sawtooth voltage determined by the differential amplifier increases as indicated by the broken line in FIG. 10(b) and the pulse width of the output pulse emerging from the collector of the transistor Tr14 is reduced.
In this way, variation of the output pulse from the oscillator 4 resulting from the variation of the oscillator 4 itself can be advantageously and adequately compensated for by the control circuit 9' and the average D-C voltage Vm of output from the output stage 8 and the flyback pulse of the vertical deflection output are respectively controlled to assume a predertermined value.
FIG. 11 shows a still further embodiment of the present invention in which feedback voltage fed from the vertical output stage 8 is applied to the vertical oscillator 4 to maintain the width of the output pulse of the vertical oscillator 4 at a constant value.
The detailed circuit of the vertical oscillator 4 is shown in FIG. 12.
Referring to FIG. 12, the output pulse of the integrator 2 is applied to a base of a transistor Tr21 the collector of which is connected to the base of a transistor Tr22 through a resistor R21. The transistor Tr22 constitutes the differential amplifier in cooperation with a transistor Tr23 the base of which is connected to a capacitor C3 receiving voltage E1 of the D-C power source through a variable resistor VR.
The collector of the transistor Tr23 is connected to the base of an amplifying transistor Tr24 of which the collector is connected to the base of a transistor Tr25 through resistors R24 and R25. The collector of the transistor Tr25 is applied to the base of a transistor Tr26 and collector of a transistor Tr27 through a transistor Tr28. The junction point of the collector Tr27 and the base of the transistor Tr26 is grounded through a resistor R26 and a diode D1. The transistor Tr27 operates as a current stabilizer which is controlled by the collector output of the transistor Tr29. The transistor Tr27 receives control voltage Ec which is fed from the integrator 11 through a transistor Tr29. The collector output of the transistor Tr25 is applied to the base of the transistor Tr8 in the sawtooth signal generator 5.
Operation of the vertical deflection circuit shown in FIG. 12 will now be described.
Assuming that a main switch (not shown) for connection between the circuit and a power source (not shown) is turned on and a capacitor C3 of the oscillator 4, is not charged no voltage is applied to the base of the transistor Tr23 which forms the differential amplifier. During this condition, that is, when the base voltage Vb1 of the transistor Tr23 is zero, the transistor Tr23 is non-conductive while the collector voltage thereof is high and, therefore, a transistor Tr24 is non-conductive. Likewisely, the transistors Tr21 and Tr25 have not yet been switched on and, accordingly, a transistor Tr28 is conductive. The switching transistor Tr26 for generation of sawtooth voltage is at this time non-conductive.
During a period in which the transistor Tr21 is non-conductive, the base voltage Vb2 applied to the base of the transistor Tr22 is represented by the following equation: ##EQU2## wherein r21, r23 and r24 are resistances of the resistors R21, R22 and R23, respectively and E1 is the D-C power source voltage.
Subsequent switching on of the main switch permits the D-C power source voltage E1 to charge the capacitor C3 through the oscillation frequency adjusting resistor VR in such a manner as shown in FIG. 5(b). When the base voltage Vb1 of the transistor Tr23 starts to exceed the base voltage Vb2 of the transistor Tr22 at the time t1 a predetermined time after the capacitor C3 has been charged, the transistors Tr23 and Tr22 are respectively triggered on and off. Upon conduction of the transistor Tr23, the transistors Tr21 and Tr25 start conducting. Conduction of the transistor Tr25 results in reduction of the collector voltage thereof and, therefore, the transistor Tr28 is triggered off.
As the transistor Tr28 becomes non-conductive, the collector voltage of the transistor Tr28 increases, thereby triggering the transistor Tr26 on so that the charge on the capacitor C3 is discharged through the collector-emitter of the transistor Tr26. At this time, the collector current of the transistor Tr26 (i.e., the current flowing through the capacitor C3) is made to be constant by a constant current circuit which is composed of the transistor Tr27 and a diode D1. During this condition, the transistor Tr21 is conductive and, therefore, the base voltage Vb2 of the transistor Tr22 is lowered as represented by the following equation: ##EQU3##
Accodingly, discharge of the potential stored in the capacitor C3 continues at a constant current determined by the base potential of the transistor Tr27 until the base voltage Vb1 of the transistor Tr23 becomes equal to the base voltage ##EQU4## of the transistor Tr22 at the time t2. Thereafter, the transistor Tr23 is again triggered off while the transistor Tr22 is triggered on and this operation is repeated. The result is such that pulses of a rectangular waveform as shown in FIG. 13(e) are generated through the collector J9 of the transistor Tr25. The waveform of output pulse apearing at the output terminal T1 of the integrator 2 is as shown in FIG. 13(a) and this vertical synchronizing pulse is applied to the base of the transistor Tr21 whereby the oscillator 4 is oscillated in synchronizm with said vertical synchronizing pulses.
Waveforms of signals at the junctions J7, J8 and J6 are shown in FIGS. 13(c), (d) and (f), respectively.
On the other hand, though the start time t1 (FIG. 13(e )) of the output pulse from the oscillator 4 can be accurately determined because of synchronization with the vertical synchronizing pulse from the integrator 2, the termination t2 thereof cannot be accurately determined by the reason as hereinbefore described. If the pulse width of the output pulse from the oscillator 4 varies to represent a pulse width between t1 and t2' short of the required pulse width and the output pulse having such a reduced width is applied to the sawtooth signal generator 5 from the oscillator 4 the flyback pulse width Pr of the vertical deflection output at the junction J6 of the vertical output stage 8 is consequently reduced to a value Pr' as shown by the broken line in FIG. 13(f). The result is that the voltage Vr of the flyback pulse increases to represent a value Vr' by the reason as hereinbefore described in connection with the equation (1).
A voltage proportional to the average level Vm of D-C output voltage is extracted from a smoothing circuit 11, which is composed of the resistor R9 and a capacitor C4, and is subsequently fed to a transistor Tr29 for D-C amplification and phase-reversion. The transistor Tr29, upon receipt of this voltage from the smoothening circuit 11, generates voltage from the collector thereof which is used as a pulse width control voltage Ec which is subsequently applied to the base of the transistor Tr27. It is to be noted that the control voltage Ec increases in response to reduction of the flyback pulse width and, accordingly, the emitter-collector current of the transistor Tr27 is lowered upon receipt of the increased control voltage Ec' and the collector current of the transistor Tr26 is also lowered.
As a result thereof, the speed at which the capacitor C3 charges is retarded as indicated by the broken line in FIG. 13(b), thus broadening the pulse width of the output pulse from the oscillator 4. In this way, the oscillation of the oscillator 4 is controlled to render the flyback pulse Pr' to become the required flyback pulse Pr.
It should be noted that, if the speed at which the capacitor C3 charges is varied by controlling the collector current of the switching transistor Tr26, the repetition frequency of the output pulse produced in the oscillator 4 may vary which is negligible in practice.
From the foregoing full description of the present invention, it has now become clear that the arrangement of the present invention is very advantageous in that the pulse width of the flyback pulse can be effectively stabilized. However, it should be noted that various changes and modifications are apparent to those skilled in the art without departing from the true scope of the present invention and therefore, such changes and modifications should be, unless otherwise they depart therefrom, construed as included within the scope of the present invention .
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 E/W PINCUSHION CORRECTION CIRCUIT WITH SATURABLE REACTOR FOR CORRECTING RASTER DISTORTION:
Saturable reactor apparatus in which primary and secondary windings, respectively coupled to horizontal and vertical deflection current sources, are wound on the shaft of a ferrite core at the opposite ends of which are permanent magnets. Flux generated in the core is controlled either by adjustment of the permanent magnets or by the use of a further permanent magnet.
1. Saturable reactor apparatus comprising a ferrite core including a central part and a shaft extending in opposite directions therefrom and flanges on the shaft defining spaces on opposite sides of the central part, primary and secondary windings on the shaft in each of said spaces and in close coupling relationship, the secondary windings being oppositely wound, permanent magnets at opposite ends of the shaft to generate flux in said core, and means to control the thusly generated flux. 2. Apparatus as claimed in claim 1 wherein said means includes means to vary the position of the permanent magnets relative to said shaft. 3. Apparatus as claimed in claim 1 wherein said means includes a further permanent magnet adjacent the core and rotatable about an axis perpendicular to said shaft. 4. Apparatus as claimed in claim 1 wherein said magnets are of plate-form. 5. Apparatus as claimed in claim 1 comprising horizontal and vertical deflection deflection television-receiver circuits generating horizontal and vertical deflection currents, and means for respectively coupling the currents to said primary and secondary windings. 6. Apparatus as claimed in claim 3 wherein said further magnet is of circular form and has peripheral magnetic poles therein. 7. Apparatus as claimed in claim 2 wherein the latter said means includes threaded rods.
A saturable reactor comprised of a cross-shaped core having a yoke on the center portion thereof and protrusions at right angles to the yoke and two coils wound on the yoke. Each coil of the said two coils is divided into two coil parts which are wound on the right and left yoke arms. The first pair of the said two coils is constituted so as to be identical as to the direction of the magnetic generation as is the pair of coils wound on the right and left yoke arms. The second pair of coils is constituted so as to be opposite to each other as to the direction of magnetic flux generation as is the pair of coils wound on the right and left yoke arms.
1. A saturable reactor for correcting raster distortion comprised of a cross-shaped magnetic core consisting essentially of a central yoke portion and a divider portion in the form of a protrusion intersecting the central portion at a right angle and extending to the opposite side thereof, thereby dividing the central yoke portion into separate arm portions and forming a magnetic core which is cross-shaped when viewed in cross-section, and two coils wound on the yoke portion, each of said coils being subdivided into two parts and the thus divided coils being wound on the respective arm portions formed on both sides of the protrusion, the first coil being so constituted that the magnetic fluxes generated in the two divided coil parts assume the same direction when an electric current is caused to flow therethrough, while the said second coil is so constituted that the magnetic fluxes will be generated in opposite directions in the two divided coil parts when an electric current is caused to flow therethrough, and wherein the core is so structured that the cross-sectional dimensions are identical along its entire length, with
2. A saturable reactor for correcting raster distortion according to claim 1, wherein at least one end of the protrusion is extended in a direction 3. A saturable reactor for correcting raster distortion according to claim 1, wherein the protrusion consists of two oppositely positioned 4. A saturable reactor for correcting raster distortion according to claim 1, wherein the protrusion consists of a continuous disc surrounding the 5. A saturable reactor for correcting raster distortion according to claim 1, wherein a cylindrical core is mounted on the cross-shaped core with the inside wall of the cylindrical core in slidable contact with said divider 6. A saturable reactor for correcting raster distortion according to claim 2, wherein the protrusion is extended by attaching thereto core strips in 7. A saturable reactor for correcting raster distortion according to claim 1, wherein a U-shaped permanent magnet having magnetic poles at both ends is mounted on the cross-shaped core so that the said magnetic poles contact the right and left arm portions of the yoke respectively, and 8. A saturable reactor for correcting raster distortion according to claim 1, wherein permanent magnets for bias are mounted on both ends of the 9. A saturable reactor for correcting raster distortion according to claim 1, wherein a cavity is provided in the center of the yoke in the axial direction thereof and a permanent bar magnet magnetized in the axial 10. A saturable reactor for correcting raster distortion according to claim 9, wherein core strips are placed on both ends of the yoke.
The present invention relates to a reactor for controlling or modifying "pincushion" type distortion in cathode ray tube displays. It is particularly well suited for use in conjunction with color display tubes.
Pincushion type distortion of cathode ray tube displays has long been recognized. In black-and-white displays, this type of distortion is corrected to a considerable extent through the use of permanent magnets, which are so shaped and fixed in positions relative to the cathode as to produce an appropriate magnetic biasing effect on the cathode ray beam. In the case of color display tubes, which are based on the use of shadow mask or similar principles, however, fixed correcting magnets cannot be used.
One approach, which has been adopted in connection with the correction of pincushion distortion in color displays involves modulation or variation of one of the sweep currents in such a manner as to produce the desired results.
In the arrangement for correction of raster distortion occurring in the vertical direction (e.g., top and bottom pincushion distortion), the cyclically varying vertical scanning current must be modulated at a higher horizontal rate, such as by adding a horizontal rate correction current alternated parabolically to the vertical deflection current.
In the arrangement for the correction of raster distortion occurring in the horizontal direction (e.g., side pincushion distortion), the cyclically varying horizontal scanning must be varied at a lower vertical rate, since the magnitude of a horizontal scanning must be varied at a lower vertical rate, since the magnitude of a horizontal scanning current is parabolical.
It has further been suggested in the prior art that this modulation be accomplished electromagnetically using a combination of magnetic and electrical circuitry which works on the principle of magnetic saturability.
In general, nominal correction can be produced by this means. There are many kinds of saturable reactor device and circuit connections for correcting pincushion distortion such as those described in U.S. Pats. No. 2,906,919, No. 3,346,765, and No. 3,444,422.
The existing reactor, as seen in the aforementioned U.S. patents, is composed of a core that mutually couples the two ends of three parallel yokes, a coil is shunt-wound on the two yokes on both sides of the said core in opposite winding direction and is connected in series, and another coil is wound on the center of the said core. Since the vertical deflection current has been applied to one of the above-mentioned coils and the horizontal deflection current has been applied to the other coil, the device has disadvantages as described herein.
In the manufacture of a reactor, coils are fitted to respective yokes of an E-shaped core, and I-shaped cores are coupled on the free ends of the yokes of the E-shaped core in order to magnetically couple the yokes. Using this process, the manufacturing process has been time-consuming, making it unsuited to mass-production. Magnetic flux leakage has been small, since the yokes formed a closed magnetic path. However, since current magnetic flux density in the closed magnetic path varied markedly depending on the infinitesimal differences in the gaps in the magnetic path, the characteristics of individual products lost uniformity because of disparity in the gap arising in the coupled part of the E-shaped core and the I-shaped core.
The present invention offers saturable reactors extremely easy to assemble and manufacture and with uniform quality of individual products.
SUMMARY
In accordance with the invention there is provided a saturable reactor for correcting raster distortion comprised of a cross-shaped magnetic core having a
yoke on the center portion thereof and protrusions being provided at right angles thereto, and two coils wound on the said yoke, each coil of the said two coils being divided into two parts and the divided coils wound on the respective arms formed on both sides of the said protrusions, the first coil being so constituted that the magnetic fluxes generated in the two divided coil parts assume the same direction when an electric current is caused to flow therethrough, while the said second coil is so constituted that the magnetic fluxes will be generated in opposite directions in the two divided coil parts when an electric current is caused to flow therethrough.
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 memory-saving all channel digital tuning system:
A tuning system for a television receiver includes fine tune memories and tuning information memories, the latter having reference channel nominal tuning information for each of the various frequency bands, first increment tuning information for each frequency band and second increment tuning information for each channel. The first increment information represents the initial slope of the tuning characteristic and the second increment information represents the slope of the slope of the tuning characteristic for each channel. Accumulator means add the reference channel and first and second increment informations to derive nominal tuning information for any selected channel. Control logic including counters and latches control the operation of the accumulator means and memories. The accumulator means and fine tune counters are interrogated by counter-driven comparators which develop pulse-width modulated signals corresponding to the tuning information therein. A tuning voltage generator develops the final tuning voltage from the pulse-width modulated signals. Increment tuning information representative of the slope of the tuning characteristic at each channel is derived and used to equalize any auxiliary tuning source. The reference channel information is combined with appropriate numbers of first tuning increments and second tuning increments for deriving nominal tuning information for the selected channel.
1. A television tuning system including:
a voltage controlled tuner having a nonlinear tuning voltage-versus-frequency characteristic;
memory means storing reference tuning information, first increment tuning information related to the slope of said characteristic at a base channel and second increment tuning information related to the slope of the slope of said characteristic at each channel;
tuning voltage means generating a tuning voltage for said tuner;
channel address means accessing said memory means and reading out the corresponding tuning informations; and
accumulator means coupled between said memory means and said tuning voltage means for generating nominal tuning information for the selected channel from said reference tuning information, said first increment tuning information and said second increment tuning information.
2. A television tuning system as set forth in claim 1 wherein said reference tuning information comprises nominal tuning information for a reference channel, said first increment tuning information represents the change in nominal tuning information between said reference channel and the next adjacent channel and said second increment tuning information represents the change in said first increment tuning information between adjacent channels;
said accumulator means algebraically adding second increments of tuning information to said first increment of tuning information and to said reference tuning information to derive the nominal tuning information for the selected channel.
3. A television tuning system as set forth in claim 2 wherein the reference channel tuning information is for a channel at one extremity of the frequency band and the first increment tuning information is for an adjacent channel. 4. A television tuning system as set forth in claim 3 wherein the reference channel tuning information and the first increment tuning information correspond to a pseudo channel 6 MHz below the lowest numbered channel in said band, and wherein said accumulator means add second increment tuning information to the pseudo channel tuning informations to derive the nominal tuning information for the selected channel. 5. A television tuning system as set forth in claim 3 further including a source of secondary tuning information;
said accumulator means adding said first and said second increment tuning information to derive a last increment of tuning information;
means proportioning said secondary tuning information by said last increment of tuning information; and
means combining said derived nominal tuning information for the selected channel with the proportioned secondary tuning information.
6. The method of operating a television tuning system including a tuner having a nonlinear tuning voltage-versus-frequency characteristic and a channel-number-accessible memory for storing tuning information, comprising the steps of:
storing in said memory reference tuning information, first increment tuning information related to the slope of said characteristic at a base channel and second increment tuning information related to the slope of the slope of said characteristic at successive channel positions;
reading out the reference and first increment tuning informations and the second increments of tuning informations for a selected channel;
computing the nominal tuning information for the selected channel from the read-out tuning informations; and
producing a tuning voltage therefrom for said tuner.
7. The method of claim 6 wherein said reference tuning information comprises nominal tuning information for a pseudo channel, said first increment tuning information is representative of the change in nominal tuning information between said pseudo tuning information and said base channel and said second increment tuning information is representative of the change in first increment tuning information between successive channels;
said computing step including the step of:
algebraically summing second increment tuning information with said first increment tuning information and the reference channel tuning information to derive nominal tuning information for the selected channel.
8. The method of claim 7 wherein the pseudo channel is located below the lowest numbered channel in the band and wherein said summing step includes the further step of:
adding the second increment tuning informations of successive higher channels to the first increment tuning information and the nominal tuning information of said pseudo channel.
9. The method of claim 8 further including the steps of:
proportioning a source of secondary tuning information with the summation of the first increment tuning information and the second increment tuning informations corresponding to the selected channel; and
combining the derived nominal tuning information for the selected channel with the proportioned secondary tuning information for producing the tuning voltage for said tuner.
10. The method of operating a television tuning system including a tuner having a nonlinear tuning voltage-versus-frequency characteristic and a channel-number-accessible memory for storing tuning information comprising the steps of:
storing in said memory
(a) nominal tuning information and first increment tuning information for a pseudo channel;
(b) second increment tuning information for each channel corresponding to the change in first increment tuning information between successive channels including the pseudo channel, said pseudo channel corresponding to a frequency 6 MHz below the lowest numbered channel in the frequency band;
interrogating said memory for a desired channel to read out the pseudo channel tuning informations and one or more of said second increment informations;
computing the nominal tuning voltage information for said desired channel from said pseudo channel information and said second increment information; and
producing a tuning voltage therefrom for said tuner.
11. The method of claim 10 further including accumulating means having arithmetic logic units and storage registers, and further comprising the steps of:
transferring to one of said storage registers said first increment tuning information and to another of said storage registers said reference tuning information; and
operating said arithmetic logic units to combine said first increment and said reference tuning informations with successive second increment tuning informations.
12. The method of claim 11 further including a channel number counter and a channel number latch, said method further comprising the steps of:
latching the desired channel number in the latch;
resetting the channel number counter and clearing the registers;
operating the channel number counter to count up to the number in the latch; and
interrogating said memory to read the appropriate tuning informations into the registers as the counter is stepped.
13. The method of claim 12 further including a viewer operated channel Up/Dn switch for controlling the counter and means displaying the channel number in the latch to the viewer, and further including the steps of:
automatically replacing the number in the latch with the new channel number in the counter at a given repetition rate in response to operation of the Up/Dn switch; and
repeating said interrogating and computing steps for each new channel number, said latter steps taking significantly less time to perform than the period of said given repetition rate.
14. A television tuning system including a voltage-controlled tuner having a nonlinear voltage-versus-frequency characteristic and a memory having a plurality of accessible locations storing nominal tuning information for a reference channel, first increment tuning information representative of changes in nominal tuning information between said reference channel and the next adjacent channel and second increment tuning information representative of changes in first increment tuning information between successive pairs of adjacent channels;
a channel number counter for accessing said different memory locations in accordance with channel numbers;
a
ccumulator means coupled to said memory for developing nominal tuning information for a selected channel by combining said nominal tuning information for said reference channel and first increment information with second increment tuning informations between said reference channel and said selected channel; and
a tuning voltage generator coupled to said accumulator means for generating a tuning voltage for said tuner from said developed nominal tuning information.
15. A television tuning system as set forth in claim 14 wherein said reference channel is a pseudo channel selected at a point on said characteristic 6 MHz below the frequency corresponding to the lowest numbered channel in the band. 16. A television tuning system as set forth in claim 15 further including control logic means comprising a channel number latch;
a high speed clock;
state counter means driven by said clock for resetting said channel number counter after a channel number change has been stored in said latch and for operating said channel number counter until its count matches the number in said latch; and
comparator means disabling said state counter means when the channel number counter counts to the number in said latch.
17. A television tuning system as set forth in claim 16 wherein said accumulator means include arithmetic logic units and storage registers;
said arithmetic logic units either substituting information in said registers or adding information to previous information therein under control of said state counter means.
18. A television tuning system as set forth in claim 17 including means displaying the channel number in the latch and a viewer-operable Up/Dn switch for producing a channel change initiate signal for said control logic means;
said initiate signal comprising a pulse train of predetermined periodicity and changing the count in said channel number counter;
said state counter means being activated by said initiate signal for latching the new channel number, resetting said channel counter, driving said channel counter from its reset count to the count stored in the latch and disabling itself when the number in the channel counter matches the number in the latch.
19. A television tuning system as set forth in claim 18 wherein said state counter means cycles once for each count change in the channel counter, the maximum cycle time of the state counter means being less than the predetermined periodicity of said pulse train. 20. An all-channel television tuning system including a voltage controlled tuner having a nonlinear voltage-versus-frequency characteristic and a memory having a plurality of locations each accessible by a distinct channel number, said channels being numbered consecutively but lying in more than one distinct frequency band;
one or more of said locations in each distinct frequency band storing nominal tuning information for a reference channel in its associated band and first increment tuning information representative of changes in nominal tuning information between the associated reference channel and the next adjacent channel;
others of said locations in each band storing second increment tuning informations representative of changes in first increment tuning information between successive pairs of adjacent channels in each band;
a channel number counter;
accumulator means coupled to said memory for developing nominal tuning information for any selected channel by combining the nominal tuning information and first increment tuning information for its associated reference channel with second increment tuning information between the associated reference channel and the selected channel;
a tuning voltage generator coupled to the said accumulator means for generating a tuning voltage for said tuner from said developed nominal tuning information;
band decoder means determining the proper frequency band for each channel number; and
memory location translation means for allocating blocks of memory locations to said different frequency bands.
21. An all-channel television tuning system as set forth in claim 20 wherein said channel number counter generates a BCD tens digit and a BCD units digit corresponding to the respective digits of the selected channel number, said units digits being coupled directly to said memory and said tens digit being routed through said memory location translation means along with the output of said band decoder means. 22. An all-channel television tuning system as set forth in claim 21 wherein said reference channels comprise pseudo channels selected to be 6 MHz below the lowest channels in each band.
This application is related to, but not dependent upon, the invention and apparatus disclosed in copending application Ser. No. 791,897 filed Apr. 28, 1977 and application Ser. No. 807,627 filed June 17, 1977, both in the name of Akio Tanaka and assigned to Zenith Radio Corporation.
FIELD OF THE INVENTION
This invention relates generally to digital tuning systems and in particular to all-electronic television receiver digital tuning systems having a memory for storing tuning information.
BACKGROUND OF THE INVENTION AND PRIOR ART
Varactor diode tuners have contributed to the simplification of tuning systems in general, and television receiver tuning systems in particular. In such tuners, which are often referred to as electronic tuners, the varactor diodes exhibit capacitance variations with changes in bias voltage and serve as the variable reactances in-otherwise-conventional tuned circuits. Such tuning systems are easy to tune, free from RF signal carrying contacts and afford the designer great versatility in receiver styling. As pointed out in the related applications, their most serious drawbacks are the limited range of diode capacitance change and the nonlinear relationship between frequency and bias voltage.
The invention in the first-mentioned related application (Ser. No. 791,897)--now U.S. Pat. No. 4,142,157--provides an attractive solution to these problems and the problems associated with implementation of the Federal Communications Commission so-called "equal tuning" rule for VHF and UHF television channels. In brief, that system produces a separate "slope factor" which is related to the slope of the tuning voltage-versus-frequency characteristic for proportioning the "fine" tuning voltage such that equal frequency excursions are experienced for equal tuning information increments. The result is a truly "equalized" tuning system. The slope factors are stored in appropriate channel-number-addressable memories as are the nominal (coarse) tuning informations and fine tuning informations. For each channel selection a nominal tuning voltage information, a fine tuning voltage information and a slope factor are produced. The fine tuning information is multiplied by the slope factor and combined with the nominal tuning information for conversion to the final tuning voltage.
The invention in the second-mentioned copending application Ser. No. 807,627 is concerned with memory utilization in digital tuning systems and the savings in memory which may be achieved by proper utilization of the slope factor. The structure of that invention accomplishes significant memory reduction by storing initial value tuning information for a pseudo channel in each frequency band and separate tuning increment information, representing the tuning voltage changes required to successively tune from one channel to the next, beginning with the pseudo channel. (These increments are the difference equation analog of the slope factors defined in the application Ser. No. 791,897--now U.S. Pat. No. 4,142,157--). Upon occurrence of a channel change, an arithmetic computation is performed in which the initial value information and successive increment informations are added. The initial value tuning information is selected at a point 6 MHz below the lowest numbered channel in the band which point is then referred to as the pseudo channel number. Thus, in the low VHF band, for instance, rather than storing complete information words corresponding to the nominal tuning information for channels 2-4, the nominal tuning information for pseudo channel 1 is stored along with the slope factors or increments required to go from pseudo channel 1 to real channel 2, from channel 2 to channel 3, and from channel 3 to channel 4. Suitable logic and apparatus are provided for summing the pseudo channel information and successive increments for obtaining the nominal tuning information corresponding to the selected channel number.
Since the last increment represents the slope factor of the tuning curve at the selected channel, and since this slope information is separately available, it is readily usable for equalization of any auxiliary tuning voltage source to provide true equalized tuning for the system. In the offset fine tuning system disclosed, one-half of the fine tune information, after equalization, is added to the derived nominal tuning information to produce the final tuning information for the selected channel.
There is no art known to the inventor which is relevant to the invention described and claimed; that is a system which "computes" a tuning voltage by algebraic summation of nominal tuning information for a reference channel and increment tuning information representative of tuning differences between channels.
The present invention represents a further improvement in memory utilization over that obtainable in the system of the Ser. No. 807,627 application. In essence, only the differences in increment tuning information from channel to channel are stored in the memory. Effectively these difference increments result from taking the "slope of the slope" of the tuning characteristic at each channel tuning position, and may be conveniently referred to as a second derivative system. Thus rather than storing a tuning information increment equivalent to a one volt tuning change for example, only the tuning increment change for that channel, which may amount to only a tenth of a volt, is stored and thus a substantial further savings in memory is obtainable. The nominal tuning information for the selected channel is derived by summing the nominal tuning information for the pseudo channel and first increment tuning information in that band with the appropriate number of successive second increment tuning informations. The first and second increment tuning informations are added to produce a last tuning increment for the selected channel, which is the slope factor, and which may be conveniently used to produce equalized tuning as disclosed in the Ser. No. 791,897 application.
OBJECTS OF THE INVENTION
The principal object of this invention is to provide a novel television tuning system.
Another object of this invention is to provide a television tuning system requiring less memory.
SUMMARY OF THE INVENTION
In accordance with the invention a television receiver includes a voltage controlled tuner having a nonlinear tuning voltage-versus-frequency characteristic, tuning voltage means for generating a tuning voltage for the tuner and memory means storing reference tuning information, first increment tuning information related to the slope of the characteristic at a base channel and second increment tuning information related to the slope of the slope of the tuning characteristic at each channel position. The memory means supply the tuning informations to accumulator means which generate therefrom the nominal tuning information and slope factor for the selected channel.
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 VARACTOR TUNER BAND SWITCHING AND SIGNAL INDICATING CIRCUITRY:
A signal receiver having VHF and UHF varactor tuners and a channel indicating group for the upp
er and lower VHF channels and for the UHF channel includes band switching circuitry for selectively coupling a plurality of power sources to the tuners in accordance with activation of a particular channel indicating group. Also, the band switching circuitry is utilized in conjunction with a channel indicating meter circuit for providing a visual indication of the channel selected in each one of the channel indicating groups.
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, AM or PM, the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment, an external controller is disclosed which can be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.
1. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address for application to said memory means means for generating said write-addresses;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and
control means for controlling the reception of a television receiver according to said data read from said memory means.
2. The controller of claim 1 wherein said memory means is a semiconductor memory. 3. The controller of claim 1 wherein said storing means includes a means for generating said write-addresses which is responsive to the position of at least one first switch and a means for generating said data corresponding to channel selections which is responsive to the position of at least one second switch. 4. The controller of claim 1 wherein said controller means controls the reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 5. A programmable television controller comprising: random-access memory means for storing data;
data means for selectively generating data corresponding to a television channel;
write-address means selectively generating a write-address corresponding to a future time for application to said memory means;
program means for selectively storing said data in said memory means at said write-address;
read-address means for generating said read-addresses responsive to real time;
memory read means for applying said read-addresses to said memory means for reading out said data stored in said memory means; and
control means for controlling the reception of a television receiver according to said data read from said memory means.
6. The controller of claim 5 wherein said memory means is a semiconductor memory. 7. The controller of claim 5 wherein said data means comprises at least one switch. 8. The controller of claim 5 wherein said write-address means comprises at least one switch. 9. The controller of claim 5 wherein said program means comprises:
means for normally coupling said read-address means to said memory;
means for normally placing said memory in a read mode;
switching means for momentarily decoupling the read-address means from said memory means, coupling said write-address means to said memory means, and switching said memory means from said read mode to a write mode.
10. The controller of claim 5 wherein said read-addresses are binary coded signals which increment on one-half hour intervals. 11. The controller of claim 5 wherein said control means controls said reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 12. The controller of claim 5 wherein said control means controls the reception of said television receiver by limiting the reception to a channel other than the channel corresponding to said data received from said memory means if said data is present. 13. The controller of claim 5 wherein said control means includes a pretuner means having at least one input for coupling to a television receiver antenna and a pretuner output for coupling to an input on a television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal. 14. The controller of claim 13 wherein said control means further includes a disable means for disabling said control means thereby preventing reception of any channel when a power source powering said controller is interrupted, said disable means continuing to disable said controller until said disable means is reset. 15. The controller of claim 13 wherein said controller is installed within a controller housing, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller. 16. The controller of claim 13 wherein said pretuner output is for coupling to an antenna input on the television receiver and the frequency of said fixed frequency signal corresponds to a predetermined television signal. 17. The controller of claim 13 wherein said pretuner output is for coupling to an input of an intermediate frequency amplifier stage in the television receiver and the frequency of said fixed frequency signal corresponds to the intermediate frequency amplifier stage frequency of operation. 18. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address means for generating said write-addresses for application to said memory means;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and,
control means for controlling the reception of a television receiver according to said data read from said memory means, said control means including a pretuner means having at least one input for coupling to a television receiver antenna and pretuner output for coupling to an input on the television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal;
a controller housing for housing said controller, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller.
1. Field of the Invention
The present invention relates to the field of automatic controllers, and more particularly, to programmable controllers for use with television receivers and like equipment.
2. Prior Art
Many systems have been proposed for the automatic control of television receivers, that is, automatic channel selection for particular times of the day based upon programming information entered into the controller at some previous time. Most of these systems, however, are in substantial part mechanical systems which are not particularly easy to program, thereby being relatively expensive to manufacture and difficult to use. Accordingly, such systems have not enjoyed significant commercial use on conventional receivers.
Simple programmable television receiver controllers would provide a number of advantages over conventional channel selectors, and even over remote controlled channel selectors for a number of reasons. There may be programs of particular merit or interest which a viewer does not want to miss. However, the viewer's attention may inadvertently be drawn to another channel at the time, thereby failing to change channels to the more desirable program at the appropriate time. Also at the present time, a number of programs and movies being shown on T.V. are directed toward an adult audience, which programs may be undesirable or outright unsuitable for viewing by children, a situation which may only be expected to increase in the future. In addition, more andmore homes have at least one television receiver controllable at least a substantial amount of the time by children, whereby with conventional channel selectors the "viewers discretion" cannot be exercised by a parent. Accordingly, aprogrammable controller could be programmed periodically, such as once a week, so that those programs of highest merit or viewer interest, will be automatically selected and/or predetermined unobjectionable programs will be selected at times when objectionable programming is being televised on other channels. As an alternative, of course, objectionable programming itself could be programmed for the purposes of locking out such programs from the viewer's selections, e.g., eliminating such programming from the channel selections accessible from the manual channel selector.
U.S. Pat. Nos. 3,215,798 and 3,388,308 disclose automatic television programming systems of the mechanical or electromechanical type, whereby a rotary device mechanically tied to a time clock is programmed to provide some physical movement indicative of the channel to be selected at that time. Devices of the same general type involving some form of motor driven switching unit are also disclosed in U.S. Pat. Nos. 2,755,424, 3,496438, and 3,569,839. In all of these patents the mechanical complexity of the system disclosed is believed to preclude the widespread adoption thereof on receivers intended for consumer use. Further, most of these systems are operative on a number of switching signals equal to the number of selections desired, though some coding to somewhat reduce the complexity of such systems is known, such as that in U.S. Pat. No. 3,496,438. Also, obviously timing mechanisms or the electromechanical type for various other applications are also known, that disclosed in U.S. Pat. No. 3,603,961 being but one example of such devices.
BRIEF SUMMARY OF THE INVENTION
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, A.M. or P.M., the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment an external controller is disclosed which may be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
One of the major causes for variation of the vertical flyback pulse width is interference by horizontal flyback pulses from the horizontal deflection circuit, in which case sufficient interlaced scanning can not be performed.
In order to avoid these inconveniences, the vertical flyback pulse width must be controlled at a constant width. However, by the reason as will be described with reference to FIG. 1, a prior art vertical deflection circuit in a television receiver fails to satisfy this requirement.
Referring now to FIG. 1 wherein a prior art vertical deflection circuit now under discussion is shown, a circuit arrangement is such that synchronizing pulses emerging from a sync separator 1 are, after having its waveform shaped in an integrator 2, applied to a vertical oscillating circuit 3 which includes a vertical oscillator 4 and a sawtooth deflecting signal generator 5. The vertical oscillator 4 upon receipt of the shaped sync pulses from the integrator 2 is driven to generate a train of pulses synchronized with the vertical synchronizing signal which are subsequently fed to the sawtooth deflecting signal generator 5. The waveform of a sawtooth deflecting signal emerging from the generator 5 is shown in FIG. 2 and this deflecting signal is transferred from the generator 5 to a vertical deflection output circuit 6 which includes a drive circuit 7 for amplifying the sawtooth deflecting signal upon receipt thereof from the generator 5 and a vertical output stage 8 having a vertical deflection coil D.
As shown in FIG. 2, the sawtooth deflecting signal includes rectangular component pulses and the wave-form of an output signal from the vertical output stage 8 which is similar to that of the sawtooth deflecting signal. The portions of the output signal from the vertical output stage 8, which correspond to the rectangular component pulses of the sawtooth deflecting signal are known as flyback pulses.
In the vertical deflection circuit of the above arrangement, the pulse width of the flyback pulses included in the output of the vertical output stage 8 is affected by the pulse width of the rectangular component pulses fed from the oscillator 4 to the output stage 8. More specifically, in the OTL type vertical deflection circuit, since there is no inductance element, such as a vertical output transformer, that determines the pulse width of the flyback pulse, the pulse width of the flyback pulse is mostly determined by the pulse width of the corresponding rectangular component pulse of the sawtooth deflecting signal applied to the output stage 8. Accordingly, variation of the pulse width of the rectangular component pulses produced in the oscillator 4 results in variation of the pulse width of the flyback pulses produced in the output stage 8.
This inconvenience is likely to be avoided if the pulse width of the output pulse from the oscillator 4 is stabilized. However, this stabilization of the pulse width of the output pulse from the oscillator 4 cannot be achieved without difficulties by the following reason.
In the vertical oscillator 4, the start of each output pulse from this oscillator 4 can be accurately determined by the vertical synchronizing signal applied thereto. On the contrary thereto, the time at which the output pulse from the oscillator 4 terminates is solely determined by operational characteristics of the oscillator 4 itself and, therefore, is often adversely affected by and in the presence of external noises. Once the oscillator 4 is adversely affected by and in the presence of the external noises, the duration between the start and termination of the output pulse from said oscillator, that is, the pulse width, varies and, therefore, the problem remains still unsolved.
SUMMARY OF THE INVENTION
Another important object of the present invention is to provide a vertical deflection circuit of the type referred to above, wherein a pulse width control is provided between the vertical oscillator and the vertical output circuit for controlling the pulse width of the output pulses from the oscillator.
A further important object of the present invention is to provide a vertical deflection circuit of the type referred to above, wherein a feedback loop is provided to control the operation of the pulse width control in response to an output signal emerging from the vertical output stage.
A still further important object of the present invention is to provide a vertical deflection circuit of the type referred to above, wherein a feedback loop is provided to control the oscillator in response to an output signal emerging from the vertical output stage for stabilizing the pulse width of the flyback pulses produced in the vertical output stage.
These and other objects and features of the present invention will become clear from the following description taken in conjunction with preferred embodiments of the present invention with reference to the accompanying drawings in which;
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the prior art vertical deflection circuit,
FIG. 2 is a diagram showing the waveform of vertical deflection output produced in the prior art vertical deflection circuit,
FIG. 3 is a block diagram showing one embodiment of the vertical deflection circuit according to the present invention,
FIG. 4 is a circuit diagram showing the details of the vertical deflection circuit shown in FIG. 3,
FIG. 5 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 4.
FIG. 6 is a block diagram showing another embodiment of the vertical deflction circuit according to the present invention,
FIG. 7 is a circuit diagram showing the details of the vertical deflection circuit shown in FIG. 6,
FIG. 8 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 7,
FIG. 9 is a circuit diagram showing a further embodiment of the vertical deflection circuit according to the present invention,
FIG. 10 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 9.
FIG. 11 is a block diagram showing a still further embodiment of the vertical deflection circuit according to the present invention,
FIG. 12 is a circuit diagram showing the details of the vertical deflection circuit shown in FIG. 11, and
FIG. 13 is a diagram showing waveforms of various signals obtainable at various portions of the circuit of FIG. 12.
Before the description of the present invention proceeds, it should be noted that like parts are designated by like reference numerals throughout the accompanying drawings for the sake of brevity.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 3, between the vertical oscillator 4 and the sawtooth deflecting signal generator 5, there is provided a pulse width control circuit 9 for stabilizing the pulse width of pulses fed to the sawtooth deflecting signal generator 5 from the vertical oscillator 4. FIG. 4 shows details of the pulse width control circuit 9, which will now be described.
Assuming that a pulse of unstable pulse width is applied from the vertical oscillator 4 to the input terminal T1 of the pulse width control circuit 9, which is in turn applied to the base of a switching transistor Tr1, the latter is triggered on to cause the capacitor C1 to discharge. In other words, when the pulse is applied to the pulse width control circuit 9 from the oscillator 4, that is, when the switching transistor Tr1 is non-conductive, voltage from the D-C power source Vb, after having passed through the resistor of sufficiently high resistance, charges the capacitor C1. However, the charge stored in the capacitor C1 is discharged to the ground through the collector-emitter of the switching transistor Tr1 when the latter starts conducting.
As a result, in the capacitor C1, voltage of sawtooth waveform as shown by the solid line in FIG. 5(b) is generated across said capacitor C1, which is subsequently applied to the base of a switching transistor Tr2. The latter transistor Tr2 starts conducting only when the voltage thus applied to the base thereof exceeds a D-C power source voltage E1 applied to the emitter of said transistor Tr2. Conduction of the switching transistor Tr2 results in a pulsating voltage of rectangular waveform, as shown by the solid line in FIG. 5(c), appearing at the common junction J1 of resistors R2 and R3, both of which are loaded on the collector of the transistor Tr2, due to the saturation characteristic of the transistor Tr2. The pulsating voltage at the common junction J1 is fed to the base of an amplifying transistor Tr3 so that the pulsating voltage is thereby amplified and phase-reversed and, as a result thereof, a phase-reversed pulsating voltage of the waveform as shown by the solid line in FIG. 5(d) appears at the common junction J2 of resistors R4 and R5, both of which are loaded on the collector of the transistor Tr3. This pulsating voltage at the common junction J2 is further phase-reversed by an amplifying transistor Tr4. Therefore, a voltage received by the transistor Tr6 from the collector of the amplifying transistor Tr4 has a waveform similar to that of the pulsating voltage applied to the base of the amplifying transistor Tr3. Simultaneously, the output pulse at the input terminal T1 is also applied to the base of a transistor Tr5. The transistor Tr5 acts to phase-reverse the output pulse to produce a pulsating voltage of a waveform as shown by the solid line in FIG. 5(e) at the collector of said transistor Tr5. The collector of this transistor Tr5 is connected with the collector of the transistor Tr4, which is in turn connected to the base of the transistor Tr6. This transistor Tr5 is non-conductive when voltage applied to the base threof is zero, in which condition the base of the transistor Tr6 receives a pulse of positive potential, i.e., a high level pulse, whereby it is held in a conductive state with the collector thereof in a zero volt or low level state. If the high level pulse is applied to the base of the transistor Tr4, this high level pulse is amplified and phasereversed by the transistor Tr4 to produce a low level pulse from the collector thereof which is in turn fed to the transistor Tr6 to trigger the latter off. When the transistor Tr6 is thus triggered off, a high level voltage is produced from the collector of the transistor Tr6.
In view of the foregoing, it can be seen that these transistors Tr4, Tr5 and Tr6 cooperate with each other to substantially act as a gating circuit while the pulsating voltage applied to the base of the transistor Tr6 from the transistor Tr4 acts as a trigger pulse. Accordingly, it is clear that the pulse appearing at the collector of the transistor Tr6 has a pulse width, as shown in FIG. 5(f), which corresponds to the pulse width W1 of the output pulse at the input terminal T1 extracted by the pulse width W2 of the high level pulse applied to the base of the transistor Tr4.
As stated hereinbefore, the start of the output pulse from the oscillator 4 can be accurately fixed while it is difficult to fix the termination of the pulse. Assuming, therefore, that the output pulse shown by the broken line in FIG. 5(a) and having a pulse width t1 to t4 which is larger than the desired pulse width t1 to t2 as shown by the solid line in FIG. 5(a), is applied to the pulse width control circuit 9 from the vertical oscillator 4, the transistor Tr1 becomes non-conductive and the voltage across the capacitor C1 accordingly increases as shown by the broken line in FIG. 5(b). On the other hand, the transistor Tr5 becomes non-conductive upon receiving of the input pulse at the base thereof at the time t1, causing the transistor Tr6 to start conducting. When the voltage at the base of the transistor Tr2 exceeds the emitter voltage defined by the source E1, the transistors Tr2 and Tr3 become conductive and the junction point J2 becomes high level at the time t3 as shown in FIG. 5(d). Accordingly, the collector of the transistor Tr4 becomes low level causing the transistor Tr6 to become non-conductive whereby the collector of the transistor Tr6 becomes high level at the time t3.
From the foregoing, it is clear that, even if the width of the input pulse applied to the pulse width control circuit 9 is larger than the desired or predetermined width, the width output pulse of the control circuit 9 can be defined at the predetermined width as shown in FIG. 5(f).
Accordingly, a rectangular pulse having a predetermined pulse width is applied to the base of the input transistor Tr8 of the sawtooth signal generator 5, whereby the width of the flyback pulses included in the vertical deflection output can be maintained at the desired or predetermined width.
In the embodiment of FIG. 3, the pulse width of the output pulse of the pulse width control circuit 9 may not be suitable for the vertical output circuit. In this case, equalization of the pulse width can be achieved by varying the D-C voltage E1 supplied to the emitter of the transistor Tr2. Specifically, if the voltage E1 increases or decreases the pulse width at the output terminal F of the control circuit 9 is reduced or enlarged, respectively.
FIG. 6 shows another embodiment of the present invention in which the pulse width control circuit 9' receives a feedback signal from the deflection output circuit 8 so that the pulse width of the output signal from the width control circuit 9' can be advantageously controlled to maintain the width of the flyback pulse constant.
FIG. 7 shows the details of the width control circuit 9'. Referring now to FIG. 7, there is provided a differential amplifier 10 composed of transistors Tr13 and Tr14. The base of the transistor Tr13 receives the voltage on the capacitor C1 and feedback voltage fed back from the common junction J6 of the deflection output circuit through the integrator 11 and the resistors R5 and R6.
The collector of the transistor Tr13 is connected to the base of the transistor Tr4 which constitutes the gating circuit in cooperation with the transistors Tr5 and Tr6. The switching level of the transistor Tr13 is defined by base voltage Eo appearing at the junction point J3 of the resistors R7 and R8. Operation of the circuit arrangement of FIGS. 6 and 7 will now be described.
It is assumed that, during operation of the control circuit 9' with the transistor Tr1 triggered off by the application of the low level pulse from the vertical oscillator 4, voltage supplied from the integrator 11 through the constant current resistor R5 and then a time constant adjusting resistor R6 charges the capacitor C1. Voltage of a sawtooth waveform as shown by the solid line in FIG. 8(b) is generated across the capacitor C1. This sawtooth voltage is subsequently fed to the differential amplifier 10. The charging speed of the capacitor C1 is defined by the voltage E F of the integrator 11.
When the voltage at the base of the transistor Tr13 exceeds the voltage Eo appearing at the base of the transistor Tr14, the transistor Tr13 becomes conductive with the output of the transistor Tr13 becoming low level. At the end of the input pulse, transistor Tr1 becomes conductive, the capacitor C1 is discharged, whereby the transistor Tr13 becomes non-conductive causing the output of the transistor Tr13 to become high level.
Therefore, pulses of rectangular waveform as shown by the solid line in FIG. 8(c) can be generated from the collector of the transistor Tr13. The pulses from the transistor Tr13 are amplified and phase-reversed by the transistor Tr4, which are in turn applied to the base of the transistor Tr7 through the transistor Tr5. It should be noted that the waveform of pulse at the junction J5 between the transistors Tr4 and Tr5 is shown by the solid lines in FIG. 8(d).
Simultaneously, the pulses from the input terminal T1 are also applied to the base of the transistor Tr6. Consequently, in a similar manner as in the circuit arrangement of FIG. 4, pulses of a waveform as shown by the solid line in FIG. 8(f) can be obtained at the collector of the transistor Tr7 and, hence, at the output terminal T2 of the width control circuit 9'.
Assuming that the pulse width Pr of flyback pulses included in the vertical deflection output from the vertical output stage 8 varies, for example, gets smaller and is at a value Pr', the voltage Vr of the flyback pulse accordingly increases by the reason of the following equation: ##EQU1## wherein L is inductance of the vertical deflection coil D, i is vertical deflection current and K is a constant. In other words, while the peak level C of the flyback pulse is determined by the D-C power source voltage Vb2 and, therefore, does not vary, the average D-C voltage level Vm of the vertical deflection output is lowered to read a value Vm' as shown in FIG. 8(g).
FIG. 9 shows a further embodiment of the present invention. In the circuit arrangement of FIG. 9, the output from the oscillator 4 is first applied to the amplifying transistor Tr15 by which it is amplified and phase-reversed. From this transistor Tr15, the pulse of a waveform as shown in FIG. 10(a) is applied to the base of the transistor Pr1, thereby causing the latter to be triggered on. During a period in which the transistor Tr1 is non-conductive, the capacitor C1 is charged through the constant current transistor Tr16 and, when the transistor Tr1 starts conducting upon receipt of the pulse from the transistor Tr15, voltage charged in the capacitor C1 is discharged through the collector-emitter of the transistor Tr1. By this operation, voltage of the sawtooth waveform as shown in FIG. 10(b) is generated across the capacitor C1. This sawtooth voltage is subsequently applied to a differential amplifier 10 composed of a pair of transistors Tr13 and Tr14. The transistor Tr14 receives control voltage Ef fed from the junction point J6 of the vertical deflection output stage 8 through the integrator 11. By the level Ef of voltage fed to the base of the transistor Tr14, the slicing level of this sawtooth voltage can be varied and, hence, the pulse width of the pulse emerging from the collector of the transistor Tr14 can be varied as indicated by W1 in FIG. 10(c). The output pulse from the collector of the transistor Tr14 is fed to the base of the transistor Tr10 of the drive circuit 7 through the sawtooth signal generator 5. The vertical deflection output of a waveform as shown in FIG. 10(d) is generated at the junction J6 of the vertical output stage 8 after the output transistors Tr11 and Tr12 are driven by drive signal from the drive circuit 7. Assuming now that the pulse width W of the output from the oscillator 4 is suitably selected such as to be larger than that required in the vertical deflection output from the output stage 8, if the flyback pulse width Tr of the vertical deflection output becomes larger than the pulse width W, the voltage Vr of the flyback pulse is reduced for the same reason as in the embodiment of FIG. 7 while the peak level C thereof remains the same and, accordingly, the average D-C voltage Vm increases, resulting in increase of the control voltage Ef to be applied to the base of the transistor Tr14.
Therefore, the slicing level of the sawtooth voltage determined by the differential amplifier increases as indicated by the broken line in FIG. 10(b) and the pulse width of the output pulse emerging from the collector of the transistor Tr14 is reduced.
In this way, variation of the output pulse from the oscillator 4 resulting from the variation of the oscillator 4 itself can be advantageously and adequately compensated for by the control circuit 9' and the average D-C voltage Vm of output from the output stage 8 and the flyback pulse of the vertical deflection output are respectively controlled to assume a predertermined value.
FIG. 11 shows a still further embodiment of the present invention in which feedback voltage fed from the vertical output stage 8 is applied to the vertical oscillator 4 to maintain the width of the output pulse of the vertical oscillator 4 at a constant value.
The detailed circuit of the vertical oscillator 4 is shown in FIG. 12.
Referring to FIG. 12, the output pulse of the integrator 2 is applied to a base of a transistor Tr21 the collector of which is connected to the base of a transistor Tr22 through a resistor R21. The transistor Tr22 constitutes the differential amplifier in cooperation with a transistor Tr23 the base of which is connected to a capacitor C3 receiving voltage E1 of the D-C power source through a variable resistor VR.
The collector of the transistor Tr23 is connected to the base of an amplifying transistor Tr24 of which the collector is connected to the base of a transistor Tr25 through resistors R24 and R25. The collector of the transistor Tr25 is applied to the base of a transistor Tr26 and collector of a transistor Tr27 through a transistor Tr28. The junction point of the collector Tr27 and the base of the transistor Tr26 is grounded through a resistor R26 and a diode D1. The transistor Tr27 operates as a current stabilizer which is controlled by the collector output of the transistor Tr29. The transistor Tr27 receives control voltage Ec which is fed from the integrator 11 through a transistor Tr29. The collector output of the transistor Tr25 is applied to the base of the transistor Tr8 in the sawtooth signal generator 5.
Assuming that a main switch (not shown) for connection between the circuit and a power source (not shown) is turned on and a capacitor C3 of the oscillator 4, is not charged no voltage is applied to the base of the transistor Tr23 which forms the differential amplifier. During this condition, that is, when the base voltage Vb1 of the transistor Tr23 is zero, the transistor Tr23 is non-conductive while the collector voltage thereof is high and, therefore, a transistor Tr24 is non-conductive. Likewisely, the transistors Tr21 and Tr25 have not yet been switched on and, accordingly, a transistor Tr28 is conductive. The switching transistor Tr26 for generation of sawtooth voltage is at this time non-conductive.
During a period in which the transistor Tr21 is non-conductive, the base voltage Vb2 applied to the base of the transistor Tr22 is represented by the following equation: ##EQU2## wherein r21, r23 and r24 are resistances of the resistors R21, R22 and R23, respectively and E1 is the D-C power source voltage.
Subsequent switching on of the main switch permits the D-C power source voltage E1 to charge the capacitor C3 through the oscillation frequency adjusting resistor VR in such a manner as shown in FIG. 5(b). When the base voltage Vb1 of the transistor Tr23 starts to exceed the base voltage Vb2 of the transistor Tr22 at the time t1 a predetermined time after the capacitor C3 has been charged, the transistors Tr23 and Tr22 are respectively triggered on and off. Upon conduction of the transistor Tr23, the transistors Tr21 and Tr25 start conducting. Conduction of the transistor Tr25 results in reduction of the collector voltage thereof and, therefore, the transistor Tr28 is triggered off.
As the transistor Tr28 becomes non-conductive, the collector voltage of the transistor Tr28 increases, thereby triggering the transistor Tr26 on so that the charge on the capacitor C3 is discharged through the collector-emitter of the transistor Tr26. At this time, the collector current of the transistor Tr26 (i.e., the current flowing through the capacitor C3) is made to be constant by a constant current circuit which is composed of the transistor Tr27 and a diode D1. During this condition, the transistor Tr21 is conductive and, therefore, the base voltage Vb2 of the transistor Tr22 is lowered as represented by the following equation: ##EQU3##
Accodingly, discharge of the potential stored in the capacitor C3 continues at a constant current determined by the base potential of the transistor Tr27 until the base voltage Vb1 of the transistor Tr23 becomes equal to the base voltage ##EQU4## of the transistor Tr22 at the time t2. Thereafter, the transistor Tr23 is again triggered off while the transistor Tr22 is triggered on and this operation is repeated. The result is such that pulses of a rectangular waveform as shown in FIG. 13(e) are generated through the collector J9 of the transistor Tr25. The waveform of output pulse apearing at the output terminal T1 of the integrator 2 is as shown in FIG. 13(a) and this vertical synchronizing pulse is applied to the base of the transistor Tr21 whereby the oscillator 4 is oscillated in synchronizm with said vertical synchronizing pulses.
Waveforms of signals at the junctions J7, J8 and J6 are shown in FIGS. 13(c), (d) and (f), respectively.
On the other hand, though the start time t1 (FIG. 13(e )) of the output pulse from the oscillator 4 can be accurately determined because of synchronization with the vertical synchronizing pulse from the integrator 2, the termination t2 thereof cannot be accurately determined by the reason as hereinbefore described. If the pulse width of the output pulse from the oscillator 4 varies to represent a pulse width between t1 and t2' short of the required pulse width and the output pulse having such a reduced width is applied to the sawtooth signal generator 5 from the oscillator 4 the flyback pulse width Pr of the vertical deflection output at the junction J6 of the vertical output stage 8 is consequently reduced to a value Pr' as shown by the broken line in FIG. 13(f). The result is that the voltage Vr of the flyback pulse increases to represent a value Vr' by the reason as hereinbefore described in connection with the equation (1).
A voltage proportional to the average level Vm of D-C output voltage is extracted from a smoothing circuit 11, which is composed of the resistor R9 and a capacitor C4, and is subsequently fed to a transistor Tr29 for D-C amplification and phase-reversion. The transistor Tr29, upon receipt of this voltage from the smoothening circuit 11, generates voltage from the collector thereof which is used as a pulse width control voltage Ec which is subsequently applied to the base of the transistor Tr27. It is to be noted that the control voltage Ec increases in response to reduction of the flyback pulse width and, accordingly, the emitter-collector current of the transistor Tr27 is lowered upon receipt of the increased control voltage Ec' and the collector current of the transistor Tr26 is also lowered.
As a result thereof, the speed at which the capacitor C3 charges is retarded as indicated by the broken line in FIG. 13(b), thus broadening the pulse width of the output pulse from the oscillator 4. In this way, the oscillation of the oscillator 4 is controlled to render the flyback pulse Pr' to become the required flyback pulse Pr.
It should be noted that, if the speed at which the capacitor C3 charges is varied by controlling the collector current of the switching transistor Tr26, the repetition frequency of the output pulse produced in the oscillator 4 may vary which is negligible in practice.
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 E/W PINCUSHION CORRECTION CIRCUIT WITH SATURABLE REACTOR FOR CORRECTING RASTER DISTORTION:
1. Saturable reactor apparatus comprising a ferrite core including a central part and a shaft extending in opposite directions therefrom and flanges on the shaft defining spaces on opposite sides of the central part, primary and secondary windings on the shaft in each of said spaces and in close coupling relationship, the secondary windings being oppositely wound, permanent magnets at opposite ends of the shaft to generate flux in said core, and means to control the thusly generated flux. 2. Apparatus as claimed in claim 1 wherein said means includes means to vary the position of the permanent magnets relative to said shaft. 3. Apparatus as claimed in claim 1 wherein said means includes a further permanent magnet adjacent the core and rotatable about an axis perpendicular to said shaft. 4. Apparatus as claimed in claim 1 wherein said magnets are of plate-form. 5. Apparatus as claimed in claim 1 comprising horizontal and vertical deflection deflection television-receiver circuits generating horizontal and vertical deflection currents, and means for respectively coupling the currents to said primary and secondary windings. 6. Apparatus as claimed in claim 3 wherein said further magnet is of circular form and has peripheral magnetic poles therein. 7. Apparatus as claimed in claim 2 wherein the latter said means includes threaded rods.
A saturable reactor comprised of a cross-shaped core having a yoke on the center portion thereof and protrusions at right angles to the yoke and two coils wound on the yoke. Each coil of the said two coils is divided into two coil parts which are wound on the right and left yoke arms. The first pair of the said two coils is constituted so as to be identical as to the direction of the magnetic generation as is the pair of coils wound on the right and left yoke arms. The second pair of coils is constituted so as to be opposite to each other as to the direction of magnetic flux generation as is the pair of coils wound on the right and left yoke arms.
Description:
BACKGROUND OF THE INVENTIONThe present invention relates to a reactor for controlling or modifying "pincushion" type distortion in cathode ray tube displays. It is particularly well suited for use in conjunction with color display tubes.
One approach, which has been adopted in connection with the correction of pincushion distortion in color displays involves modulation or variation of one of the sweep currents in such a manner as to produce the desired results.
In the arrangement for correction of raster distortion occurring in the vertical direction (e.g., top and bottom pincushion distortion), the cyclically varying vertical scanning current must be modulated at a higher horizontal rate, such as by adding a horizontal rate correction current alternated parabolically to the vertical deflection current.
In the arrangement for the correction of raster distortion occurring in the horizontal direction (e.g., side pincushion distortion), the cyclically varying horizontal scanning must be varied at a lower vertical rate, since the magnitude of a horizontal scanning must be varied at a lower vertical rate, since the magnitude of a horizontal scanning current is parabolical.
It has further been suggested in the prior art that this modulation be accomplished electromagnetically using a combination of magnetic and electrical circuitry which works on the principle of magnetic saturability.
In general, nominal correction can be produced by this means. There are many kinds of saturable reactor device and circuit connections for correcting pincushion distortion such as those described in U.S. Pats. No. 2,906,919, No. 3,346,765, and No. 3,444,422.
The existing reactor, as seen in the aforementioned U.S. patents, is composed of a core that mutually couples the two ends of three parallel yokes, a coil is shunt-wound on the two yokes on both sides of the said core in opposite winding direction and is connected in series, and another coil is wound on the center of the said core. Since the vertical deflection current has been applied to one of the above-mentioned coils and the horizontal deflection current has been applied to the other coil, the device has disadvantages as described herein.
In the manufacture of a reactor, coils are fitted to respective yokes of an E-shaped core, and I-shaped cores are coupled on the free ends of the yokes of the E-shaped core in order to magnetically couple the yokes. Using this process, the manufacturing process has been time-consuming, making it unsuited to mass-production. Magnetic flux leakage has been small, since the yokes formed a closed magnetic path. However, since current magnetic flux density in the closed magnetic path varied markedly depending on the infinitesimal differences in the gaps in the magnetic path, the characteristics of individual products lost uniformity because of disparity in the gap arising in the coupled part of the E-shaped core and the I-shaped core.
The present invention offers saturable reactors extremely easy to assemble and manufacture and with uniform quality of individual products.
SUMMARY
In accordance with the invention there is provided a saturable reactor for correcting raster distortion comprised of a cross-shaped magnetic core having a
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 memory-saving all channel digital tuning system:
a voltage controlled tuner having a nonlinear tuning voltage-versus-frequency characteristic;
memory means storing reference tuning information, first increment tuning information related to the slope of said characteristic at a base channel and second increment tuning information related to the slope of the slope of said characteristic at each channel;
tuning voltage means generating a tuning voltage for said tuner;
channel address means accessing said memory means and reading out the corresponding tuning informations; and
accumulator means coupled between said memory means and said tuning voltage means for generating nominal tuning information for the selected channel from said reference tuning information, said first increment tuning information and said second increment tuning information.
2. A television tuning system as set forth in claim 1 wherein said reference tuning information comprises nominal tuning information for a reference channel, said first increment tuning information represents the change in nominal tuning information between said reference channel and the next adjacent channel and said second increment tuning information represents the change in said first increment tuning information between adjacent channels;
said accumulator means algebraically adding second increments of tuning information to said first increment of tuning information and to said reference tuning information to derive the nominal tuning information for the selected channel.
3. A television tuning system as set forth in claim 2 wherein the reference channel tuning information is for a channel at one extremity of the frequency band and the first increment tuning information is for an adjacent channel. 4. A television tuning system as set forth in claim 3 wherein the reference channel tuning information and the first increment tuning information correspond to a pseudo channel 6 MHz below the lowest numbered channel in said band, and wherein said accumulator means add second increment tuning information to the pseudo channel tuning informations to derive the nominal tuning information for the selected channel. 5. A television tuning system as set forth in claim 3 further including a source of secondary tuning information;
said accumulator means adding said first and said second increment tuning information to derive a last increment of tuning information;
means proportioning said secondary tuning information by said last increment of tuning information; and
means combining said derived nominal tuning information for the selected channel with the proportioned secondary tuning information.
6. The method of operating a television tuning system including a tuner having a nonlinear tuning voltage-versus-frequency characteristic and a channel-number-accessible memory for storing tuning information, comprising the steps of:
storing in said memory reference tuning information, first increment tuning information related to the slope of said characteristic at a base channel and second increment tuning information related to the slope of the slope of said characteristic at successive channel positions;
reading out the reference and first increment tuning informations and the second increments of tuning informations for a selected channel;
computing the nominal tuning information for the selected channel from the read-out tuning informations; and
producing a tuning voltage therefrom for said tuner.
said computing step including the step of:
algebraically summing second increment tuning information with said first increment tuning information and the reference channel tuning information to derive nominal tuning information for the selected channel.
8. The method of claim 7 wherein the pseudo channel is located below the lowest numbered channel in the band and wherein said summing step includes the further step of:
adding the second increment tuning informations of successive higher channels to the first increment tuning information and the nominal tuning information of said pseudo channel.
9. The method of claim 8 further including the steps of:
proportioning a source of secondary tuning information with the summation of the first increment tuning information and the second increment tuning informations corresponding to the selected channel; and
combining the derived nominal tuning information for the selected channel with the proportioned secondary tuning information for producing the tuning voltage for said tuner.
10. The method of operating a television tuning system including a tuner having a nonlinear tuning voltage-versus-frequency characteristic and a channel-number-accessible memory for storing tuning information comprising the steps of:
storing in said memory
(a) nominal tuning information and first increment tuning information for a pseudo channel;
(b) second increment tuning information for each channel corresponding to the change in first increment tuning information between successive channels including the pseudo channel, said pseudo channel corresponding to a frequency 6 MHz below the lowest numbered channel in the frequency band;
computing the nominal tuning voltage information for said desired channel from said pseudo channel information and said second increment information; and
producing a tuning voltage therefrom for said tuner.
11. The method of claim 10 further including accumulating means having arithmetic logic units and storage registers, and further comprising the steps of:
transferring to one of said storage registers said first increment tuning information and to another of said storage registers said reference tuning information; and
operating said arithmetic logic units to combine said first increment and said reference tuning informations with successive second increment tuning informations.
12. The method of claim 11 further including a channel number counter and a channel number latch, said method further comprising the steps of:
latching the desired channel number in the latch;
resetting the channel number counter and clearing the registers;
operating the channel number counter to count up to the number in the latch; and
interrogating said memory to read the appropriate tuning informations into the registers as the counter is stepped.
13. The method of claim 12 further including a viewer operated channel Up/Dn switch for controlling the counter and means displaying the channel number in the latch to the viewer, and further including the steps of:
automatically replacing the number in the latch with the new channel number in the counter at a given repetition rate in response to operation of the Up/Dn switch; and
repeating said interrogating and computing steps for each new channel number, said latter steps taking significantly less time to perform than the period of said given repetition rate.
14. A television tuning system including a voltage-controlled tuner having a nonlinear voltage-versus-frequency characteristic and a memory having a plurality of accessible locations storing nominal tuning information for a reference channel, first increment tuning information representative of changes in nominal tuning information between said reference channel and the next adjacent channel and second increment tuning information representative of changes in first increment tuning information between successive pairs of adjacent channels;
a channel number counter for accessing said different memory locations in accordance with channel numbers;
a
a tuning voltage generator coupled to said accumulator means for generating a tuning voltage for said tuner from said developed nominal tuning information.
15. A television tuning system as set forth in claim 14 wherein said reference channel is a pseudo channel selected at a point on said characteristic 6 MHz below the frequency corresponding to the lowest numbered channel in the band. 16. A television tuning system as set forth in claim 15 further including control logic means comprising a channel number latch;
a high speed clock;
state counter means driven by said clock for resetting said channel number counter after a channel number change has been stored in said latch and for operating said channel number counter until its count matches the number in said latch; and
17. A television tuning system as set forth in claim 16 wherein said accumulator means include arithmetic logic units and storage registers;
said arithmetic logic units either substituting information in said registers or adding information to previous information therein under control of said state counter means.
18. A television tuning system as set forth in claim 17 including means displaying the channel number in the latch and a viewer-operable Up/Dn switch for producing a channel change initiate signal for said control logic means;
said initiate signal comprising a pulse train of predetermined periodicity and changing the count in said channel number counter;
said state counter means being activated by said initiate signal for latching the new channel number, resetting said channel counter, driving said channel counter from its reset count to the count stored in the latch and disabling itself when the number in the channel counter matches the number in the latch.
19. A television tuning system as set forth in claim 18 wherein said state counter means cycles once for each count change in the channel counter, the maximum cycle time of the state counter means being less than the predetermined periodicity of said pulse train. 20. An all-channel television tuning system including a voltage controlled tuner having a nonlinear voltage-versus-frequency characteristic and a memory having a plurality of locations each accessible by a distinct channel number, said channels being numbered consecutively but lying in more than one distinct frequency band;
one or more of said locations in each distinct frequency band storing nominal tuning information for a reference channel in its associated band and first increment tuning information representative of changes in nominal tuning information between the associated reference channel and the next adjacent channel;
others of said locations in each band storing second increment tuning informations representative of changes in first increment tuning information between successive pairs of adjacent channels in each band;
a channel number counter;
accumulator means coupled to said memory for developing nominal tuning information for any selected channel by combining the nominal tuning information and first increment tuning information for its associated reference channel with second increment tuning information between the associated reference channel and the selected channel;
a tuning voltage generator coupled to the said accumulator means for generating a tuning voltage for said tuner from said developed nominal tuning information;
band decoder means determining the proper frequency band for each channel number; and
memory location translation means for allocating blocks of memory locations to said different frequency bands.
Description:
CROSS REFERENCE TO RELATED PATENT APPLICATIONThis application is related to, but not dependent upon, the invention and apparatus disclosed in copending application Ser. No. 791,897 filed Apr. 28, 1977 and application Ser. No. 807,627 filed June 17, 1977, both in the name of Akio Tanaka and assigned to Zenith Radio Corporation.
FIELD OF THE INVENTION
This invention relates generally to digital tuning systems and in particular to all-electronic television receiver digital tuning systems having a memory for storing tuning information.
BACKGROUND OF THE INVENTION AND PRIOR ART
Varactor diode tuners have contributed to the simplification of tuning systems in general, and television receiver tuning systems in particular. In such tuners, which are often referred to as electronic tuners, the varactor diodes exhibit capacitance variations with changes in bias voltage and serve as the variable reactances in-otherwise-conventional tuned circuits. Such tuning systems are easy to tune, free from RF signal carrying contacts and afford the designer great versatility in receiver styling. As pointed out in the related applications, their most serious drawbacks are the limited range of diode capacitance change and the nonlinear relationship between frequency and bias voltage.
The invention in the first-mentioned related application (Ser. No. 791,897)--now U.S. Pat. No. 4,142,157--provides an attractive solution to these problems and the problems associated with implementation of the Federal Communications Commission so-called "equal tuning" rule for VHF and UHF television channels. In brief, that system produces a separate "slope factor" which is related to the slope of the tuning voltage-versus-frequency characteristic for proportioning the "fine" tuning voltage such that equal frequency excursions are experienced for equal tuning information increments. The result is a truly "equalized" tuning system. The slope factors are stored in appropriate channel-number-addressable memories as are the nominal (coarse) tuning informations and fine tuning informations. For each channel selection a nominal tuning voltage information, a fine tuning voltage information and a slope factor are produced. The fine tuning information is multiplied by the slope factor and combined with the nominal tuning information for conversion to the final tuning voltage.
The invention in the second-mentioned copending application Ser. No. 807,627 is concerned with memory utilization in digital tuning systems and the savings in memory which may be achieved by proper utilization of the slope factor. The structure of that invention accomplishes significant memory reduction by storing initial value tuning information for a pseudo channel in each frequency band and separate tuning increment information, representing the tuning voltage changes required to successively tune from one channel to the next, beginning with the pseudo channel. (These increments are the difference equation analog of the slope factors defined in the application Ser. No. 791,897--now U.S. Pat. No. 4,142,157--). Upon occurrence of a channel change, an arithmetic computation is performed in which the initial value information and successive increment informations are added. The initial value tuning information is selected at a point 6 MHz below the lowest numbered channel in the band which point is then referred to as the pseudo channel number. Thus, in the low VHF band, for instance, rather than storing complete information words corresponding to the nominal tuning information for channels 2-4, the nominal tuning information for pseudo channel 1 is stored along with the slope factors or increments required to go from pseudo channel 1 to real channel 2, from channel 2 to channel 3, and from channel 3 to channel 4. Suitable logic and apparatus are provided for summing the pseudo channel information and successive increments for obtaining the nominal tuning information corresponding to the selected channel number.
Since the last increment represents the slope factor of the tuning curve at the selected channel, and since this slope information is separately available, it is readily usable for equalization of any auxiliary tuning voltage source to provide true equalized tuning for the system. In the offset fine tuning system disclosed, one-half of the fine tune information, after equalization, is added to the derived nominal tuning information to produce the final tuning information for the selected channel.
There is no art known to the inventor which is relevant to the invention described and claimed; that is a system which "computes" a tuning voltage by algebraic summation of nominal tuning information for a reference channel and increment tuning information representative of tuning differences between channels.
The present invention represents a further improvement in memory utilization over that obtainable in the system of the Ser. No. 807,627 application. In essence, only the differences in increment tuning information from channel to channel are stored in the memory. Effectively these difference increments result from taking the "slope of the slope" of the tuning characteristic at each channel tuning position, and may be conveniently referred to as a second derivative system. Thus rather than storing a tuning information increment equivalent to a one volt tuning change for example, only the tuning increment change for that channel, which may amount to only a tenth of a volt, is stored and thus a substantial further savings in memory is obtainable. The nominal tuning information for the selected channel is derived by summing the nominal tuning information for the pseudo channel and first increment tuning information in that band with the appropriate number of successive second increment tuning informations. The first and second increment tuning informations are added to produce a last tuning increment for the selected channel, which is the slope factor, and which may be conveniently used to produce equalized tuning as disclosed in the Ser. No. 791,897 application.
OBJECTS OF THE INVENTION
The principal object of this invention is to provide a novel television tuning system.
Another object of this invention is to provide a television tuning system requiring less memory.
SUMMARY OF THE INVENTION
In accordance with the invention a television receiver includes a voltage controlled tuner having a nonlinear tuning voltage-versus-frequency characteristic, tuning voltage means for generating a tuning voltage for the tuner and memory means storing reference tuning information, first increment tuning information related to the slope of the characteristic at a base channel and second increment tuning information related to the slope of the slope of the tuning characteristic at each channel position. The memory means supply the tuning informations to accumulator means which generate therefrom the nominal tuning information and slope factor for the selected channel.
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 VARACTOR TUNER BAND SWITCHING AND SIGNAL INDICATING CIRCUITRY:
A signal receiver having VHF and UHF varactor tuners and a channel indicating group for the upp
er and lower VHF channels and for the UHF channel includes band switching circuitry for selectively coupling a plurality of power sources to the tuners in accordance with activation of a particular channel indicating group. Also, the band switching circuitry is utilized in conjunction with a channel indicating meter circuit for providing a visual indication of the channel selected in each one of the channel indicating groups.
1. In a signal receiver having first, second, and third potential sources; VHF and UHF varactor tuners; first, second, and third channel indicating groups formed for selective coupling to the first potential source; and band switching circuitry having first, second, and third switching means for coupling the potential sources to the VHF and UHF tuners, channel indicating meter circuitry comprising: 2. The channel indicating meter circuitry of claim 1 wherein said means for coupling one of said pair of terminals of said channel indicating meter to a potential reference level and to the junction of said second switching means and third potential source includes a first unidirectional conduction device coupled intermediate said terminal and said potential reference level and a second unidirectional conduction device coupling the junction of said first unidirectional conduction device and potential reference level to said junction of said second switching means and third 3. The channel indicating meter circuitry of claim 1 wherein said means for coupling the other one of said pair of terminals of said channel indicating meter includes a first impedance coupling said terminal to a potential reference level and a second impedance coupling said terminal to 4. The channel indicating meter circuitry of claim 1 wherein said channel indicating meter provides a visual
indication of a selected signal channel in accordance with the potential applied thereto from said channel 5. The channel indicating meter circuitry of claim 1 wherein said channel indicating meter includes a plurality of meter scales for visually indicating channels in the upper and lower bands of the VHF varactor tuner 6. In a signal receiver having first, second, and third potential sources; VHF and UHF varactor tuners; first, second, and third channel indicating groups each formed for selective coupling to a first potential source, band switching and channel indicating meter circuitry comprising in combination: 7. The band switching and channel indicating meter circuitry combination of claim 6 including a first impedance coupling said first terminal to said potential reference level and a second impedance coupling said first 8. The band switching and channel indicating meter circuitry combination of claim 6 including a first unidirectional conduction device coupling said 9. The band switching and channel indicating meter circuitry combination of claim 6 including a first unidirectional conduction device coupling said second terminal to said potential reference level and a second unidirectional conduction device coupled to said first unidirectional conduction device and potential reference level and to said second switching means and third potential source.
Description:
CROSS-REFERENCE TO OTHER APPLICATIONS
An application entitled "Pushbutton Tuning System" filed concurrently herewith in the names of William Lee Arrington and Lee Irving Merz (Ser. No. 326,759) and assigned to the assignee of the present application relates to a pushbutton tuner for selecting a signal channel wherein each one of the channels provide an output potential suitable for use with the band switching and channel indicating meter circuitry set forth in the present application.
BACKGROUND OF THE INVENTION
Generally, present-day television receivers utilize both VHF and UHF tuners with the VHF tuner having the usual upper band portion covering channels 7-13 and a lower band portion covering channels 2-6. Also, present-day tuners are commonly of the varactor type wherein channel or frequency selection is determined by the potentials applied to the tuners.
In the prior art it has been a common practice to provide ordinary mechanical switches for band switching the high and low bands of the VHF tuner and the UHF tuner. Moreover, printed circuit type switches have been utilized in an effort to overcome the usual problems associated with mechanical switches. However, printed circuits have not provided the answers for such mechanical problems as wear, contact failure, and lack of reliability even though the cost is undesirably increased.
Additionally, total electronic tuning systems using logic and digital techniques have been proposed for use with varactor tuners. In one known example, channel numbers are coded into binary numbers and the selection of a preset voltage on varactor diodes is made by a corresponding binary coded signal.
However, electronic tuning systems using logic and digital systems appear to be relatively expensive, require a large number of components, and have a reliability and repeatability factor which is relatively unknown in the industry. Moreover, repair and service problems associated with such a departure from known and more frequently employed techniques remains an unknown factor.
Additionally, it is highly desirable to provide some form of visual indicating apparatus whereby an operator is aware of the approximate tuning of the receiver. Obviously, the provision of such visual indicating apparatus at a minimum cost of materials and labor is of utmost importance.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention is to provide enhanced band switching circuitry for a multi-band signal receiver. Another object of the invention is to provide improved electronic band switching circuitry for varactor tuners in a signal receiver. Still another object of the invention is to provide improved visual indicating apparatus utilized with band switching circuitry in a multi-band signal receiver.
These and other and further objects, advantages and capabilities are achieved in one aspect of the invention by a multi-band signal receiver having VHF and UHF varactor tuners with channel indicating groups for the upper and lower VHF bands and the UHF band and band switching circuitry for selectively coupling a plurality of potential sources to the tuners in accordance with the particular channel indicating group selected. Also, channel indicating meter circuitry acts in conjunction with the band switching circuitry to provide a visual indication of the signal channel selected.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a diagrammatic illustration, in block and schematic form, of electronic band switching and channel indicating meter circuitry suitable for use in a multi-band signal receiver; and
FIG. 2 is an alternative embodiment of a channel indicating meter circuit.
PREFERRED EMBODIMENT OF THE INVENTION
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in conjunction with the accompanying drawings.
Referring to the drawings, band switching and channel indicating meter circuitry suitable for use in a television receiver includes first, second, and third channel indicating groups 3, 5, and 7 respectively. Each one of the channel indicating groups, 3, 5, and 7 includes a plurality of parallel coupled signal channels and each signal channel has a series connected neon bulb 9 and selector switch 11 coupled to a first potential source 13. Also, each channel includes a signal selector switch 14, ganged to the selector switch 11, and connected to an adjustable resistor 12 intermediate the first potential source 13 and a potential reference level such as circuit ground. Thus, the first channel indicating group 3, preferably includes signal channels 7-13, the second channel indicating group 5, includes signal channels 2-6, and the third channel indicating group 7 includes a selection of channels 14-83.
In operation, selection of a signal channel in any one of the first, second, or third channel indicating groups 3, 5, and 7 is effected upon closure of a selector switch 11 whereupon a potential from the first potential source 13 is applied to the series connected neon bulb 9 by the selector switch 11. Also, a potential representative of a signal channel within the channel indicating group 3, 5, and 7 is available at the ganged signal selector switch 14. Thus, there is provided a potential representative of the channel indicating group and another potential representative of a specific channel within the channel indicating group.
Coupled to the channel indicating groups 3, 5, and 7 respectively, is band switching circuitry including first, second, and third switching means 15, 17, and 19 respectively. The first switching means 15, in the formof a transistor 16 in this instance, has a base electrode coupled to the first channel indicating group 3, representative of the upper band of signal channels 7-13. A collector electrode is coupled to a second potential source B+ while an emitter electrode is coupled to a varactor or varicap VHF type tuner 21. Obviously, the transistor may be replaced by other forms of electronic switching apparatus.
The second switching means 17 includes a pair of DC coupled PNP and NPN transistors, 23 and 25 respectively. The PNP transistor 23 has an emitter coupled to the second potential source B+, a collector DC coupled to the base of the NPN transistor 25, and a base electrode coupled via a biasing resistor 27 to circuit ground and by way of a first unidirectional conduction device 29 to the second channel indicating group 5 (channels 2-6). Also, a second unidirectional conduction device 31 couples the junction of the first unidirectional conduction device 29 and second channel indicating group 5 to the junction of the first channel indicating group 3 and first switching means 15. The NPN transistor 25 has a collector electrode coupled to the second potential source B+ and an emitter electrode coupled via a resistor 33 to a third potential source B- and to the VHF varactor or varicap tuner 21.
The third switching means 19 includes a transistor 35 having a base electrode connected to the third channel indicating group 7 and a collector electrode coupled to the second potential source B+. The emitter electrode of the transistor 35 is coupled to a UHF varicap or varactor tuner 37.
Additionally, channel indicating meter circuitry includes a meter 39 having a first terminal 41 coupled via resistors 42 and 44 to the signal selector switches 14 of the series connected first, second, and third channel indicating groups 3, 5, and 7 respectively and to the junction of the VHF and UHF tuners 21 and 37. This first terminal 41 of the meter 39 is also connected via a series connected first unidirectional conduction device 43 and resistor 45 to circuit ground. The junction of this first unidirectional conduction device 43 and resistor 45 is coupled via a second unidirectional conduction device 47 to the junction of the second switching means 17, the resistor 33 connected to the third potential source B-, and to the VHF tuner 21. Moreover, a second terminal 49 of the indicating meter 39 is coupled by a first resistor 51 to a potential reference level and by a second resistor 53 to the second potential source B+.
FIG. 2 illustrates an alternative form of channel indicating circuitry wherein an indicating meter 39 has a first terminal 55 coupled to the signal indicating or tuning means 57 of the first, second, and third channel indicating groups 3, 5, and 7 and via a series connected diode 59, first alterable resistor 61, and second alterable resistor 63 to a potential reference level. The terminal 55 is also coupled to the second alterable resistor 63.
A second terminal 65 of the meter 39 is coupled to the second potential source B+ and to the potential reference level. Also, the second terminal 65 is coupled via a resistor 67 and diode 69 to the junction of the second switching means 17, to the resistor 33 coupled to the third potential source B-, and to the VHF tuner 21. Moreover, a third diode 71 couples the second diode 69 and junction of the second switching means 17 to the alterable resistor 61.
As to operation, selection of any one of the parallel connected signal channels (channels 7-13) of the first channel indicating group 3 causes application of a potential from the first potential source 13 to the first switching means 15. The first switching means 15 including the transistor 16 is normally nonconductive or open-circuited. However, application of a potential from the potential source 13 renders the transistor 16 conductive whereupon a potential from the second potential source B+ is applied to the VHF tuner 21.
Also, it is to be noted that the second switching means 17 is normally conductive whereupon the potential from the third potential source B- coupled to the VHF tuner 21 is "swamped-out" by the potential from the second potential source B+. Thus, activation of a signal channel (channels 7-13) of the first channel indicating group 3 causes application of a potential from the second potential source B+ to the VHF tuner 21 and "swamping-out" of a potential from the third potential source B- which is, in turn, coupled to the band switching terminal of the VHF tuner 21.
Activation of a parallel connected signal channel of the second channel indicating group 5 which includes the low portion (channels 2-6) of the VHF signal band, causes application of a potential from the first potential source 13 to the first switching means 15 via the diode 31 and to the second switching means 17 via diode 29. Thereupon, the first switching means 15 is rendered conductive and a potential from the second potential source B+ is applied to the VHF tuner 21. The second switching means 17 is rendered non-conductive, due to the bias potential developed across the resistor 27 via diode 29, whereupon the third potential source B- is no longer "swamped-out" but rather, is applied to the band switching terminal of the VHF tuner 21.
Selection of one of the parallel connected signal channels (channels 14-83) in the UHF band of signals causes activation of the third channel indicating group 7. Thereupon, a potential from the first potential source 13 is applied to the third switching means 19. This applied potential renders the transistor 35 conductive whereupon a potential from the second potential source B+ is applied to the UHF tuner 3. Thus, activation of the UHF tuner 3 is provided upon selection of a high frequency signal channel (channels 14-83).
It may be noted that each one of the switches 11 in each channel of the first, second, and third channel indicating groups 3, 5, and 7 is mechanically connected to the others in a manner such that only one of the switches 11 is operable at a time. In other words, activation of a second one of the switches 11 causes de-activation of a first one of the switches 11. Such a switching system is clearly set forth in the cross-referenced application entitled "Pushbutton Tuning System" filed concurrently herewith.
Additionally, the channel indicating meter circuitry is responsive to selection of a channel in any one of the first, second, and third channel indicating groups 3, 5, and 7. Upon selection of a channel (channels 7-13) in the upper portion of the VHF signal range, a positive potential provided by second potential source B+ will appear at the junction of the second switching means 17, resistor 33 coupled to the third potential source B-, and the band switching terminal of the VHF tuner 21. This positive potential appears at the junction of the first and second unidirectional conduction devices 43 and 47 back biasing the first unidirectional conduction device 43 whereupon conduction therethrough ceases and the potential of the first terminal 41 of the indicating meter 39 is raised to provide an approximate half-scale reading of the channel indicating meter 39. The indicating meter 39 is further advanced in accordance with a potential applied to the first terminal 41 via the series connected resistors 42 and 44 coupled to the particular channel (channels 7-13) selected. Thus, this further advance of the indicating meter 39 is effected by current flow via the series connected resistors 44 and 42, the indicating meter 39 and the resistor 51 coupled to circuit ground.
Upon selection of a channel (channels 2-6) in the lower portion of the VHF signal band, the third potential source B- is no longer "swamped-out" because of the non-conductivity of the second band switching circuitry 17 but rather, is applied to the second unidirectional conduction device 47 to effect a back-bias thereon. Thus, current supplied by the tuning voltage, derived via the first potential source 13 and second channel indicating group 5, flows through the indicating meter 39 via the resistors 44 and 42 and to circuit ground by way of the resistor 51. Also, a predetermined portion of this current flows to circuit ground by way of the first unidirectional conduction device 43 and resistor 45 coupled thereto. Thus, compression to the lower portion of the scale of the indicating meter 39 provides a maximum utilization of scale length.
In the UHF signal band (channels 14-83), a positive potential appears at the first terminal 41 as previously explained with respect to the upper portion (channels 7-13) of the VHF signal band. Also, a substantially equal positive potential is applied to the second terminal 49 of the indicating meter 39 as derived from the second potential source B+ via the resistor 53 coupled to the second terminal 49. Thus, by application of substantially equal potentials to the first and second terminals 41 and 49 of the indicating meter 39, the total length of the indicating scale may be employed. Moreover, the tuning voltage, as derived from the first potential source 13 and third channel indicating group 7, is applied via the resistors 44 and 42 to the first terminal 41 of the indicating meter 39 to provide a visual indication of the channel selected.
Thus, there has been provided a unique band switching circuit as well as a unique channel indicating meter circuit for a multi-channel signal receiver employing both VHF and UHF varicap or varactor tuners. This improved circuitry is inexpensive of components, circuitry, and assembly time while reliability and repeatability of results are enhanced. Not only is the undesired wear associated with mechanical systems eliminated but, more importantly, the electronic switching technique increases the time switching capabilities without appreciable increase in cost.
While there has been shown and described what is at present considered the preferred embodiment of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.
An application entitled "Pushbutton Tuning System" filed concurrently herewith in the names of William Lee Arrington and Lee Irving Merz (Ser. No. 326,759) and assigned to the assignee of the present application relates to a pushbutton tuner for selecting a signal channel wherein each one of the channels provide an output potential suitable for use with the band switching and channel indicating meter circuitry set forth in the present application.
BACKGROUND OF THE INVENTION
Generally, present-day television receivers utilize both VHF and UHF tuners with the VHF tuner having the usual upper band portion covering channels 7-13 and a lower band portion covering channels 2-6. Also, present-day tuners are commonly of the varactor type wherein channel or frequency selection is determined by the potentials applied to the tuners.
In the prior art it has been a common practice to provide ordinary mechanical switches for band switching the high and low bands of the VHF tuner and the UHF tuner. Moreover, printed circuit type switches have been utilized in an effort to overcome the usual problems associated with mechanical switches. However, printed circuits have not provided the answers for such mechanical problems as wear, contact failure, and lack of reliability even though the cost is undesirably increased.
Additionally, total electronic tuning systems using logic and digital techniques have been proposed for use with varactor tuners. In one known example, channel numbers are coded into binary numbers and the selection of a preset voltage on varactor diodes is made by a corresponding binary coded signal.
However, electronic tuning systems using logic and digital systems appear to be relatively expensive, require a large number of components, and have a reliability and repeatability factor which is relatively unknown in the industry. Moreover, repair and service problems associated with such a departure from known and more frequently employed techniques remains an unknown factor.
Additionally, it is highly desirable to provide some form of visual indicating apparatus whereby an operator is aware of the approximate tuning of the receiver. Obviously, the provision of such visual indicating apparatus at a minimum cost of materials and labor is of utmost importance.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention is to provide enhanced band switching circuitry for a multi-band signal receiver. Another object of the invention is to provide improved electronic band switching circuitry for varactor tuners in a signal receiver. Still another object of the invention is to provide improved visual indicating apparatus utilized with band switching circuitry in a multi-band signal receiver.
These and other and further objects, advantages and capabilities are achieved in one aspect of the invention by a multi-band signal receiver having VHF and UHF varactor tuners with channel indicating groups for the upper and lower VHF bands and the UHF band and band switching circuitry for selectively coupling a plurality of potential sources to the tuners in accordance with the particular channel indicating group selected. Also, channel indicating meter circuitry acts in conjunction with the band switching circuitry to provide a visual indication of the signal channel selected.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a diagrammatic illustration, in block and schematic form, of electronic band switching and channel indicating meter circuitry suitable for use in a multi-band signal receiver; and
FIG. 2 is an alternative embodiment of a channel indicating meter circuit.
PREFERRED EMBODIMENT OF THE INVENTION
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in conjunction with the accompanying drawings.
Referring to the drawings, band switching and channel indicating meter circuitry suitable for use in a television receiver includes first, second, and third channel indicating groups 3, 5, and 7 respectively. Each one of the channel indicating groups, 3, 5, and 7 includes a plurality of parallel coupled signal channels and each signal channel has a series connected neon bulb 9 and selector switch 11 coupled to a first potential source 13. Also, each channel includes a signal selector switch 14, ganged to the selector switch 11, and connected to an adjustable resistor 12 intermediate the first potential source 13 and a potential reference level such as circuit ground. Thus, the first channel indicating group 3, preferably includes signal channels 7-13, the second channel indicating group 5, includes signal channels 2-6, and the third channel indicating group 7 includes a selection of channels 14-83.
In operation, selection of a signal channel in any one of the first, second, or third channel indicating groups 3, 5, and 7 is effected upon closure of a selector switch 11 whereupon a potential from the first potential source 13 is applied to the series connected neon bulb 9 by the selector switch 11. Also, a potential representative of a signal channel within the channel indicating group 3, 5, and 7 is available at the ganged signal selector switch 14. Thus, there is provided a potential representative of the channel indicating group and another potential representative of a specific channel within the channel indicating group.
Coupled to the channel indicating groups 3, 5, and 7 respectively, is band switching circuitry including first, second, and third switching means 15, 17, and 19 respectively. The first switching means 15, in the form
of a transistor 16 in this instance, has a base electrode coupled to the first channel indicating group 3, representative of the upper band of signal channels 7-13. A collector electrode is coupled to a second potential source B+ while an emitter electrode is coupled to a varactor or varicap VHF type tuner 21. Obviously, the transistor may be replaced by other forms of electronic switching apparatus.The second switching means 17 includes a pair of DC coupled PNP and NPN transistors, 23 and 25 respectively. The PNP transistor 23 has an emitter coupled to the second potential source B+, a collector DC coupled to the base of the NPN transistor 25, and a base electrode coupled via a biasing resistor 27 to circuit ground and by way of a first unidirectional conduction device 29 to the second channel indicating group 5 (channels 2-6). Also, a second unidirectional conduction device 31 couples the junction of the first unidirectional conduction device 29 and second channel indicating group 5 to the junction of the first channel indicating group 3 and first switching means 15. The NPN transistor 25 has a collector electrode coupled to the second potential source B+ and an emitter electrode coupled via a resistor 33 to a third potential source B- and to the VHF varactor or varicap tuner 21.
The third switching means 19 includes a transistor 35 having a base electrode connected to the third channel indicating group 7 and a collector electrode coupled to the second potential source B+. The emitter electrode of the transistor 35 is coupled to a UHF varicap or varactor tuner 37.
Additionally, channel indicating meter circuitry includes a meter 39 having a first terminal 41 coupled via resistors 42 and 44 to the signal selector switches 14 of the series connected first, second, and third channel indicating groups 3, 5, and 7 respectively and to the junction of the VHF and UHF tuners 21 and 37. This first terminal 41 of the meter 39 is also connected via a series connected first unidirectional conduction device 43 and resistor 45 to circuit ground. The junction of this first unidirectional conduction device 43 and resistor 45 is coupled via a second unidirectional conduction device 47 to the junction of the second switching means 17, the resistor 33 connected to the third potential source B-, and to the VHF tuner 21. Moreover, a second terminal 49 of the indicating meter 39 is coupled by a first resistor 51 to a potential reference level and by a second resistor 53 to the second potential source B+.
FIG. 2 illustrates an alternative form of channel indicating circuitry wherein an indicating meter 39 has a first terminal 55 coupled to the signal indicating or tuning means 57 of the first, second, and third channel indicating groups 3, 5, and 7 and via a series connected diode 59, first alterable resistor 61, and second alterable resistor 63 to a potential reference level. The terminal 55 is also coupled to the second alterable resistor 63.
A second terminal 65 of the meter 39 is coupled to the second potential source B+ and to the potential reference level. Also, the second terminal 65 is coupled via a resistor 67 and diode 69 to the junction of the second switching means 17, to the resistor 33 coupled to the third potential source B-, and to the VHF tuner 21. Moreover, a third diode 71 couples the second diode 69 and junction of the second switching means 17 to the alterable resistor 61.
As to operation, selection of any one of the parallel connected signal channels (channels 7-13) of the first channel indicating group 3 causes application of a potential from the first potential source 13 to the first switching means 15. The first switching means 15 including the transistor 16 is normally nonconductive or open-circuited. However, application of a potential from the potential source 13 renders the transistor 16 conductive whereupon a potential from the second potential source B+ is applied to the VHF tuner 21.
Also, it is to be noted
that the second switching means 17 is normally conductive whereupon the potential from the third potential source B- coupled to the VHF tuner 21 is "swamped-out" by the potential from the second potential source B+. Thus, activation of a signal channel (channels 7-13) of the first channel indicating group 3 causes application of a potential from the second potential source B+ to the VHF tuner 21 and "swamping-out" of a potential from the third potential source B- which is, in turn, coupled to the band switching terminal of the VHF tuner 21.Activation of a parallel connected signal channel of the second channel indicating group 5 which includes the low portion (channels 2-6) of the VHF signal band, causes application of a potential from the first potential source 13 to the first switching means 15 via the diode 31 and to the second switching means 17 via diode 29. Thereupon, the first switching means 15 is rendered conductive and a potential from the second potential source B+ is applied to the VHF tuner 21. The second switching means 17 is rendered non-conductive, due to the bias potential developed across the resistor 27 via diode 29, whereupon the third potential source B- is no longer "swamped-out" but rather, is applied to the band switching terminal of the VHF tuner 21.
It may be noted that each one of the switches 11 in each channel of the first, second, and third channel indicating groups 3, 5, and 7 is mechanically connected to the others in a manner such that only one of the switches 11 is operable at a time. In other words, activation of a second one of the switches 11 causes de-activation of a first one of the switches 11. Such a switching system is clearly set forth in the cross-referenced application entitled "Pushbutton Tuning System" filed concurrently herewith.
Additionally, the channel indicating meter circuitry is responsive to selection of a channel in any one of the first, second, and third channel indicating groups 3, 5, and 7. Upon selection of a channel (channels 7-13) in the upper portion of the VHF signal range, a positive potential provided by second potential source B+ will appear at the junction of the second switching means 17, resistor 33 coupled to the third potential source B-, and the band switching terminal of the VHF tuner 21. This positive potential appears at the junction of the first and second unidirectional conduction devices 43 and 47 back biasing the first unidirectional conduction device 43 whereupon conduction therethrough ceases and the potential of the first terminal 41 of the indicating meter 39 is raised to provide an approximate half-scale reading of the channel indicating meter 39. The indicating meter 39 is further advanced in accordance with a potential applied to the first terminal 41 via the series connected resistors 42 and 44 coupled to the particular channel (channels 7-13) selected. Thus, this further advance of the indicating meter 39 is effected by current flow via the series connected resistors 44 and 42, the indicating meter 39 and the resistor 51 coupled to circuit ground.
Upon selection of a channel (channels 2-6) in the lower portion of the VHF signal band, the third potential source B- is no longer "swamped-out" because of the non-conductivity of the second band switching circuitry 17 but rather, is applied to the second unidirectional conduction device 47 to effect a back-bias thereon. Thus, current supplied by the tuning voltage, derived via the first potential source 13 and second channel indicating group 5, flows through the indicating meter 39 via the resistors 44 and 42 and to circuit ground by way of the resistor 51. Also, a predetermined portion of this current flows to circuit ground by way of the first unidirectional conduction device 43 and resistor 45 coupled thereto. Thus, compression to the lower portion of the scale of the indicating meter 39 provides a maximum utilization of scale length.
In the UHF signal band (channels 14-83), a positive potential appears at the first terminal 41 as previously explained with respect to the upper portion (channels 7-13) of the VHF signal band. Also, a substantially equal positive potential is applied to the second terminal 49 of the indicating meter 39 as derived from the second potential source B+ via the resistor 53 coupled to the second terminal 49. Thus, by application of substantially equal potentials to the first and second terminals 41 and 49 of the indicating meter 39, the total length of the indicating scale may be employed. Moreover, the tuning voltage, as derived from the first potential source 13 and third channel indicating group 7, is applied via the resistors 44 and 42 to the first terminal 41 of the indicating meter 39 to provide a visual indication of the channel selected.
Thus, there has been provided a unique band switching circuit as well as a unique channel indicating meter circuit for a multi-channel signal receiver employing both VHF and UHF varicap or varactor tuners. This improved circuitry is inexpensive of components, circuitry, and assembly time while reliability and repeatability of results are enhanced. Not only is the undesired wear associated with mechanical systems eliminated but, more importantly, the electronic switching technique increases the time switching capabilities without appreciable increase in cost.
While there has been shown and described what is at present considered the preferred embodiment of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.
TOSHIBA COLOR TV MODEL N. C2295T1 CHASSIS TP6014 Programmable timer television receiver controllers:
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, AM or PM, the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment, an external controller is disclosed which can be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.
1. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address for application to said memory means means for generating said write-addresses;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and
control means for controlling the reception of a television receiver according to said data read from said memory means.
2. The controller of claim 1 wherein said memory means is a semiconductor memory. 3. The controller of claim 1 wherein said storing means includes a means for generating said write-addresses which is responsive to the position of at least one first switch and a means for generating said data corresponding to channel selections which is responsive to the position of at least one second switch. 4. The controller of claim 1 wherein said controller means controls the reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 5. A programmable television controller comprising: random-access memory means for storing data;
write-address means selectively generating a write-address corresponding to a future time for application to said memory means;
program means for selectively storing said data in said memory means at said write-address;
read-address means for generating said read-addresses responsive to real time;
memory read means for applying said read-addresses to said memory means for reading out said data stored in said memory means; and
control means for controlling the reception of a television receiver according to said data read from said memory means.
6. The controller of claim 5 wherein said memory means is a semiconductor memory. 7. The controller of claim 5 wherein said data means comprises at least one switch. 8. The controller of claim 5 wherein said write-address means comprises at least one switch. 9. The controller of claim 5 wherein said program means comprises:
means for normally coupling said read-address means to said memory;
means for normally placing said memory in a read mode;
switching means for momentarily decoupling the read-address means from said memory means, coupling said write-address means to said memory means, and switching said memory means from said read mode to a write mode.
10. The controller of claim 5 wherein said read-addresses are binary coded signals which increment on one-half hour intervals. 11. The controller of claim 5 wherein said control means controls said reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 12. The controller of claim 5 wherein said control means controls the reception of said television receiver by limiting the reception to a channel other than the channel corresponding to said data received from said memory means if said data is present. 13. The controller of claim 5 wherein said control means includes a pretuner means having at least one input for coupling to a television receiver antenna and a pretuner output for coupling to an input on a television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal. 14. The controller of claim 13 wherein said control means further includes a disable means for disabling said control means thereby preventing reception of any channel when a power source powering said controller is interrupted, said disable means continuing to disable said controller until said disable means is reset. 15. The controller of claim 13 wherein said controller is installed within a controller housing, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller. 16. The controller of claim 13 wherein said pretuner output is for coupling to an antenna input on the television receiver and the frequency of said fixed frequency signal corresponds to a predetermined television signal. 17. The controller of claim 13 wherein said pretuner output is for coupling to an input of an intermediate frequency amplifier stage in the television receiver and the frequency of said fixed frequency signal corresponds to the intermediate frequency amplifier stage frequency of operation. 18. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address means for generating said write-addresses for application to said memory means;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and,
control means for controlling the reception of a television receiver according to said data read from said memory means, said control means including a pretuner means having at least one input for coupling to a television receiver antenna and pretuner output for coupling to an input on the television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal;
a controller housing for housing said controller, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller.
Description:
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to the field of automatic controllers, and more particularly, to programmable controllers for use with television receivers and like equipment.
2. Prior Art
Many systems have been proposed for the automatic control of television receivers, that is, automatic channel selection for particular times of the day based upon programming information entered into the controller at some previous time. Most of these systems, however, are in substantial part mechanical systems which are not particularly easy to program, thereby being relatively expensive to manufacture and difficult to use. Accordingly, such systems have not enjoyed significant commercial use on conventional receivers.
Simple programmable television receiver controllers would provide a number of advantages over conventional channel selectors, and even over remote controlled channel selectors for a number of reasons. There may be programs of particular merit or interest which a viewer does not want to miss. However, the viewer's attention may inadvertently be drawn to another channel at the time, thereby failing to change channels to the more desirable program at the appropriate time. Also at the present time, a number of programs and movies being shown on T.V. are directed toward an adult audience, which programs may be undesirable or outright unsuitable for viewing by children, a situation which may only be expected to increase in the future. In addition, more andmore homes have at least one television receiver controllable at least a substantial amount of the time by children, whereby with conventional channel selectors the "viewers discretion" cannot be exercised by a parent. Accordingly, aprogrammable controller could be programmed periodically, such as once a week, so that those programs of highest merit or viewer interest, will be automatically selected and/or predetermined unobjectionable programs will be selected at times when objectionable programming is being televised on other channels. As an alternative, of course, objectionable programming itself could be programmed for the purposes of locking out such programs from the viewer's selections, e.g., eliminating such programming from the channel selections accessible from the manual channel selector.
U.S. Pat. Nos. 3,215,798 and 3,388,308 disclose automatic television programming systems of the mechanical or electromechanical type, whereby a rotary device mechanically tied to a time clock is programmed to provide some physical movement indicative of the channel to be selected at that time. Devices of the same general type involving some form of motor driven switching unit are also disclosed in U.S. Pat. Nos. 2,755,424, 3,496438, and 3,569,839. In all of these patents the mechanical complexity of the system disclosed is believed to preclude the widespread adoption thereof on receivers intended for consumer use. Further, most of these systems are operative on a number of switching signals equal to the number of selections desired, though some coding to somewhat reduce the complexity of such systems is known, such as that in U.S. Pat. No. 3,496,438. Also, obviously timing mechanisms or the electromechanical type for various other applications are also known, that disclosed in U.S. Pat. No. 3,603,961 being but one example of such devices.
BRIEF SUMMARY OF THE INVENTION
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