MIVAR 28S1 STEREO TVD PIP CHASSIS 3796 INTERNAL VIEW.

The MIVAR CHASSIS TV3796 was replacing almost all previous versions for 110° CRT TUBES.

It introduces new circuitry which was quickly replaced with chassis technology employing the TDA8390 asic types.

So these aren't much around and they're pretty unique in the VIDEO CHROMA SECTION.

Furthermore this version is featuring the PIP UNIT which in such class of fair price sets is quite rare.

Last MIVAR featuring TEA2029C + TEA2164 POWER SUPPLY DESIGN.


MIVAR 28S1 STEREO TVD PIP  CHASSIS 3796 CIRCUITS DESCRIPTIONS:





















TDA5330T VHF, UHF and Hyperband mixer/oscillator for TV and VCR 3-band tuners

GENERAL DESCRIPTION
The TDA5330T is a monolithic integrated circuit that performs the band A, band B and band C mixer/oscillator functions
in TV and VCR tuners. This device gives the designer the capability to design an economical and physically small 3-band
tuner which will be capable of meeting the most stringent requirements e.g. FTZ or FCC. The tuner development time
can be drastically reduced by using this device.
Features
· Balanced mixer with a common emitter input for band A
· Amplitude-controlled oscillator for band A
· Balanced mixer with common base input for band B and C
· Balanced oscillator for band B and C
· Local oscillator buffer output for external prescaler
· SAW filter preamplifier with an output impedance of 100 W
· Bandgap voltage stabilizer for oscillator stability
· Electronic bandswitch

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TSA5511 1.3 GHz Bidirectional I2C-bus

FEATURES
· Complete 1.3 GHz single chip system
· Low power 5 V, 35 mA
· I2C-bus programming
· In-lock flag
· Varicap drive disable
· Low radiation
· Address selection for Picture-In-Picture (PIP), DBS
tuner (3 addresses)
· Analog-to-digital converter
· 8 bus controlled ports (5 for TSA5511T), 4 current
limited outputs (1 for TSA5511T), 4 open collector
outputs (bi-directional)
· Power-down flag
APPLICATIONS
· TV tuners
· VCR Tuners

GENERAL DESCRIPTION
The TSA5511 is a single chip PLL frequency synthesizer
designed for TV tuning systems. Control data is entered
via the I2C-bus; five serial bytes are required to address
the device, select the oscillator frequency, programme the
eight output ports and set the charge-pump current. Four
of these ports can also be used as input ports (three
general purpose I/O ports, one ADC). Digital information
concerning those ports can be read out of the TSA5511 on
the SDA line (one status byte) during a READ operation.
A flag is set when the loop is “in-lock” and is read during a
READ operation. The device has one fixed I2C-bus
address and 3 programmable addresses, programmed by
applying a specific voltage on Port 3. The phase
comparator operates at 7.8125 kHz when a 4 MHz crystal
is used.
controlled synthesizer


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TDA8341 Television IF amplifier and demodulator

DESCRIPTION
The TDA8340;Q and TDA8341;Q are integrated IF
amplifier and demodulator circuits for colour or black/white
television receivers, the TDA8340;Q is for application with
n-p-n tuners and the TDA8341;Q for p-n-p tuners.
The TDA8340;Q and TDA8341;Q are pin-compatible
successors with improved performance to types
TDA2540/2541;Q and TDA3540/3541;Q.
Features
· Full range gain-controlled wide-band IF amplifier
· Linear synchronous demodulator with excellent
intermodulation performance
· White spot inverter
· Wide-band video amplifier with noise protection
· AFC circuit with AFC on/off switching and
sample-and-hold function
· Low impedance AFC output
· AGC circuit with noise gating
· Tuner AGC output for n-p-n tuners (TDA8340) or p-n-p
tuners (TDA8341)
· External video switch for switching-off the video output
· Reduced sensitivity for high sound carriers
· Integrated filter to limit second harmonic IF signals
· Wide supply voltage range
· Requires few external components



TEA2164 SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT

.POSITIVE AND NEGATIVE OUTPUT CURRENT
UP TO 1.2AAND – 1.7A .A TWO LEVEL COLLECTOR CURRENT LIMITATION
.COMPLETE TURN OFF AFTER LONG DURATION
OVERLOADS .UNDER AND OVER VOLTAGELOCK-OUT .SOFT START BY PROGRESSIVE CURRENT
LIMITATION .DOUBLE PULSE SUPPRESSION .BURST MODE OPERATION UNDER STANDBY
CONDITIONS
DESCRIPTION
In amaster slave architecture, the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
Located at the primary side the TEA2164 Control
IC ensures :
- the power supply start-up
- the power supply control under stand-by conditions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive of the bipolarswitching transistor
- the protection of the transistor and the power
supply under abnormal conditions.

II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Control
IC, located at the primary side of an off line
power supply achievesthe slave function ;whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
pulse transformer

In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- stand-bymode
- power supply start-up
- abnormal conditions : off load, short circuit, ...
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse widthmodulatedsignal issued from themonitoring
of the output voltage which needs the best
accuracy (in TV applications : the horizontal deflection
stagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon
commands ; and negative pulses are transistor
switching-offcommands (Figure 4). In this configuration,
only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
II.2. Stand-by Mode
In this configuration the master circuit no longer
sends PWM signals, the structure is not synchronized
; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W 3 P 3 6W (as it is
consumed in TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
output voltages.Voltage on feed-back is applied on
Pin 9.
Burst period is externally programmedby capacitor
C1.
II.3. Power Supply Start-up
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage.When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during startup.

Overvoltage Protection
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.


Synchronized switch-mode power supply:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.

Description:

The invention relates to switch-mode power supplies.

Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.

To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.

Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.

It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.

It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.

A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.


MIVAR 28S1 STEREO TVD PIP  CHASSIS 3796 Switch-mode power supply with burst mode standby operation:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of a transformer for generating pulses of a switching current. A secondary winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a control signal in the capacitor. The control signal is applied to a mains coupled chopper second transistor for generating and regulating supply voltages in accordance with pulse width modulation of the control signal. During standby operation, the first and second transistors operate in a burst mode that is repetitive at a frequency of the AC mains supply voltage such as 50 Hz. In the burst mode operation, during intervals in which pulses of the switching current occur, the pulse width and peak amplitude of the switching current pulses progressively increase in accordance with the waveform of the mains supply voltage to provide a soft start operation in the standby mode of operation within each burst group.

Description:

The invention relates to switch-mode power supplies.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of a flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce DC output supply voltages such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver and a voltage that energizes a remote control unit.

During normal operation, the DC output supply voltages are regulated by the pulse width modulator in a negative feedback manner. During standby operation, the SMPS is required to generate the DC output supply voltage that energizes the remote control unit. However, most other stages of the television receiver are inoperative and do not draw supply currents. Consequently, the average value of the duty cycle of the chopper transistor may have to be substantially lower during standby than during normal operation.

Because of, for example, storage time limitation in the chopper transistor, it may not be possible to reduce the length of the conduction interval in a given cycle below a minimum level. Thus, in order to maintain the average value of the duty cycle low, it may be desirable to operate the chopper transistor in an intermittent or burst mode, during standby. During standby, a long dead time interval occurs between consecutively occurring burst mode operation intervals. Only during the burst mode operation interval switching operation occurs in the chopper transistor. The result is that each of the conduction intervals is of a sufficient length.

In accordance with an aspect of the invention, burst mode operation intervals are initiated and occur at a rate that is determined by a repetitive signal at the frequency of the AC mains supply voltage. For example, when the mains supply voltage is at 50 Hz, each burst mode operation interval, when switching cycles occur, may last 5 milliseconds and the dead time interval when no switching cycles occur, may last during the remainder portion or 15 milliseconds. Such arrangement that is triggered by a signal at the frequency of the mains supply voltage simplifies the design of the SMPS.

The burst mode operation intervals that occur in standby operation are synchronized to the 50 Hz signal. During each such interval, pulses of current are produced in transformers and inductances of the SMPS. The pulses of current occur in clusters that are repetitive at 50 Hz. The pulses of current occur at a frequency that is equal to the switching frequency of the chopper transistor within each burst mode operation interval. Such qurrent pulses might produce an objectionable sound during power-off or standby operation. The objectionable sound might be produced due to possible parasitic mechanical vibrations as a result of the pulse currents in, for example, the inductances and transformers of the SMPS.

In accordance with another aspect of the invention, the change in the AC mains supply voltage during each period causes the length of the conduction interval in consecutively occurring switching cycle during the burst mode operation interval to increase progressively. Such operation that occurs during each burst mode operation interval may be referred to as soft start operation. The soft start operation causes, for example, gradual charging of capacitors in the SMPS. Consequently, the parasitic mechanical vibrations are substantially reduced. Also, the frequency of the switching cycles within each burst mode operation interval is maintained above the audible range for further reducing the level of such audible noise during standby operation.

A switch mode power supply, embodying an aspect of the invention, for generating an output supply voltage during both a standby-mode of operation and during a run-mode of operation includes a source of AC mains input supply voltage. A control signal at a given frequency is generated. A switching arrangement energized by the input supply voltage and responsive to the first control signal produces a switching current during both the standby-mode of operation and the run-mode operation. The output supply voltage is generated from the switching current. An arrangement coupled to the switching arrangement and responsive to a standby-mode/run-mode control signal and to a signal at a frequency that is determined by a frequency of the AC mains input supply voltage controls the switching arrangement in a burst mode manner during the standby-mode of operation. During a burst interval, a plurality of switching cycles are performed and during an alternating dead time interval no switching cycles are performed. The two intervals alternate at a frequency that is determined by the frequency of the AC mains input supply voltage.
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- Deflection power processing with TEA2029C

DESCRIPTION
The TEA2029C is a complete (horizontal and vertical)
deflection processor with secondary to primary
SMPS control for color TV sets.

DEFLECTION .CERAMIC 500kHz RESONATOR FREQUENCY
REFERENCE .NO LINE AND FRAME OSCILLATOR ADJUSTMENT
.DUAL PLL FOR LINE DEFLECTION .HIGH PERFORMANCE SYNCHRONIZATION .SUPER SANDCASTLE OUTPUT .VIDEO IDENTIFICATION CIRCUIT .AUTOMATIC 50/60Hz STANDARD IDENTIFICATION
.EXCELLENT INTERLACING CONTROL .SPECIALPATENTED FRAME SYNCHRO DEVICE
FOR VCR OPERATION .FRAME SAW-TOOTH GENERATOR .FRAME PHASE MODULATOR FOR THYRISTOR
SMPS CONTROL .ERROR AMPLIFIER AND PHASE MODULATOR
.SYNCHRONIZATION WITH HORIZONTAL
DEFLECTION .SECURITY CIRCUIT AND START UP PROCESSOR
.OUTPUT PULSES ARE SENT TO THE PRIMARY
SMPS IC (TEA2261) THROUGH A
LOW COST TRANSFORMER

GENERAL DESCRIPTION
This integrated circuit uses I2L bipolar technology
and combines analog signal processing with digital
processing.
Timing signals are obtainedfrom a voltage-controlled
oscillator (VCO) operatingat 500KHzby means
of a cheap ceramic resonator. This avoids the
frequency adjustment normally required with line
and frame oscillators.
A chain of dividers and appropriate logic circuitry
produce very accurately defined sampling pulses
and the necessary timing signals.
The principal functions implemented are :
- Horizontal scanning processor.
- Frame scanning processor. Two applications are
possible :
- D Class : Power stage using an external
thyristor.
- B Class : Powerstageusing an externalpower
amplifier with fly-back generator
such as the TDA8170.
- Secondary switch mode power regulation.
The SMPS output synchronize a primary I.C.
(TEA2260/61)at the mains part.
This concept allows ACTIVE STANDBY facilities.
- Dual phase-locked loop horizontal scanning.
- High performance frameand line synchronization
with interlacing control.
- Video identification circuit.
- Super sandcastle.
- AGC key pulse output.
- Automatic 50-60Hz standard identification.
- VCR input for PLL time constant and frame synchro
switching.
- Frame saw-tooth generator and phase modulator.
- Switchingmode regulated power supplycomprising
error amplifier and phase modulator.
- Security circuit and start-up processor.
- 500kHzVCO
The circuit is supplied in a 28 pin DIP case.
VCC = 12V.
Synchronization Separator
Line synchronization separator is clamped to
black level of input video signal with synchronization
pulse bottom level measurement.
The synchronization pulses are divided centrally
between the black level and the synchronization
pulse bottom level, to improve performance on
video signals in noise conditions.
Frame Synchronization
Frame synchronization is fully integrated (no external
capacitor required).
The frame timing identification logic permits automatic
adaptation to 50 - 60Hz standards or non-interlaced
video.
An automatic synchronization window width system
provides :
- fast frame capture (6.7ms wide window),
- good noise immunity (0.4ms narrow window).
The internal generator starts the discharge of the
saw-tooth generator capacitor so that it is not disturbed
by line fly back effects.
Thanks to the logic control, the beginning of the
charge phase does not depend on any disturbing
effect of the line fly-back.
A 32ms timing is automatically applied on standardized
transmissions, for perfect interlacing.
In VCR mode, the discharge time is controlled by
an internal monostable independent of the line
frequency and gives a direct frame synchronization.
Horizontal Scanning
The horizontalscanningfrequencyis obtainedfrom
the 500kHz VCO.
The circuit uses two phase-locked loops (PLL) :
the first one controls the frequency, the second one
controls the relative phase of the synchronization
and line fly-back signals.
The frequency PLL has two switched time constants
to provide :
- capture with a short time constant,
- good noise immunity after capture with a long
time constant.
The output pulse has a constant duration of 26ms,
independent of VCC and any delay in switching off
the scanning transistor.
Video Identification
The horizontal synchronization signal is sampled
by a 2ms pulse within the synchronization pulse.
The signal is integrated by an external capacitor.
The identification function provides three different
levels :
- 0V : no video identification
- 6V : 60Hz video identification
- 12V : 50Hz video identification
This information may be used for timing research
in the case of frequency or voltage synthetizer type
receivers, and for audio muting.
Super Sandcastle with 3 levels : burst, line flyback,
frame blanking
In the event of vertical scanning failure, the frame
blanking level goes high to protect the tube.
Frame blanking time (start with reset of Frame
divider) is 24 lines.
VCR Input
This provides for continuous use of the short time
constant of the first phase-locked loop (frequency).
In VCR mode, the frame synchronization window
widens out to a search window and there is no
delay of frame fly-back (direct synchronization).
Frame Scanning
FRAME SAW-TOOTH GENERATOR. The current
to charge the capacitoris automatically switched to
60Hz operation to maintain constant amplitude.
FRAME PHASE MODULATOR (WITH TWO DIFFERENTIAL
INPUTS). The output signal is a pulse
at the line frequency, pulse width modulatedby the
voltage at the differential pre-amplifier input.
This signal is used to control a thyristor which
provides the scanning current to the yoke. The
saw-tooth output is a low impedance,however, and
can therefore be used in class B operation with a
power amplifier circuit.
Switch Mode Power Supply (SMPS) Secondary
to Primary Regulation
This power supply uses a differential error amplifier
with an internal reference voltage of 1.26V and a
phase modulator operating at the line frequency.
The powertransistor is turnedoff bythe falling edge
of the horizontal saw-tooth.
The ”soft start” device imposes a very small conduction
angle on starting up, this angle progressively
increases to its nominal regulation value.
The maximum conductionangle may be monitored
by forcing a voltage on pin 15. This pin may also
be used for current limitation.
The outputpulse is sent to the primaryS.M.P.S. I.C.
(TEA2261) via a low cost synchro transformer.
Security Circuit and Start Up Processor
When the security input (pin 28) is at a voltage
exceeding 1.26V the three outputs are simultaneously
cut off until this voltagedrops below the 1.26V
threshold again. In this case the switch mode
power supply is restarted by the ”soft start” system.
If this cycle is repeated three times, the three
outputs are cut off definitively. To reset the safety
logic circuits, VCC must be zero volt.
This circuit eliminates the risk to switch off the TV
receiver in the event of a flash affecting the tube.
On starting up, the horizontal and vertical scanning
functions come into operation at VCC = 6V. The
power supply then comes into operation progressively.
On shutting down, the three functions are interrupted
simultaneously after the first line fly-back.

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-


SDA2516 EAROM

Features
- Word-organized reprogrammable nonvolatile memory
in n-channel floating-gate technology (E2PROM)
- 128 ´ 8-bit organization
- Supply voltage 5 V
- Serial 2-line bus for data input and output (I2C Bus)
- Reprogramming mode, 10 ms erase/write cycle
- Reprogramming by means of on-chip control (without
external control)
- Check for end of programming process
- Data retention > 10 years
- More than 104 reprogramming cycles per address
- Compatible with SDA 2516. Exception:
Conditions for total erase and current consumption.

I2C Bus Interface
The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to VCC (open drain output stage).
The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I2C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the trailing edge of the eighth clock pulse and a ninth acknowledge clock pulse, the memory component sets the SDA line to low as a confirmation
of reception, if the chip select conditions have been met. During the output of data, the data output
of the memory is high in impedance during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the I2C Bus is summarized in figure 2.
Control Functions of the I2C Bus
The memory component is controlled by the controller (master) via the I2C Bus in two operating
modes: read-out cycle, and reprogramming cycle, including erase and write to a memory address.
In both operating modes, the controller, as transmitter, has to provide 3 bytes and an additional
acknowledge clock pulse to the bus after the start condition. During a memory read, at least nine
additional clock pulses are required to accept the data from the memory and the acknowledge
master, before the stop condition may follow. In the case of programming, the active programming
process is only started by the stop condition after data input (see figure 3).
The chip select word contains the 3 chip select bits CS0, CS1 and CS2, thus allowing 8 memory
chips to be connected in parallel. Chip select is achieved when the three control bits logically
correspond to the selected conditions at the select inputs.
Check for End of Programming or Abortion of Programming Process
If the chip is addressed during active reprogramming by entering CS/E, the programming process
is terminated. If, however, it is addressed by entering CS/A, the entry will be ignored. Only after
programming has been terminated will the chip respond to CS/A. This allows the user to check
whether the end of the programming process has been reached (see figure 3).
Memory Read
After the input of the first two control words CS/E and WA, the resetting of the start condition and the
input of a third control word CS/A, the memory is set ready to read. During acknowledge clock
nine, the memory information is transferred in parallel mode to the shift register. Subsequent to the
trailing edge of the acknowledge clock, the data output is low impedance and the first data bit can
be sampled, (see figure 4).
With every shift clock, an additional bit reaches the output. After reading a byte, the internal address
counter is automatically incremented when the master receiver switches the data line to “low” during
the ninth clock (acknowledge master). Any number of memory locations can thus be read one after
the other. At address 128, an overflow to address 0 is not initiated. With the stop condition, the data
output returns to high-impedance mode. The internal sequence control of the memory component
is reset from the read to the quiescent with the stop condition.

Memory Reprogramming
The reprogramming cycle of a memory word comprises an erase and a subsequent write process.
During erase, all eight bits of the selected word are set into "1" state. During write, "0" states are
generated according to the information in the internal data register, i.e. according to the third input
control word.
After the 27th and the last clock of the control word input, the active programming process is started
by the stop condition. The active reprogramming process is executed under onchip control.
The time required for reprogramming depends on component deviation and data patterns.
Therefore, with rated supply voltage, the erase/write process extends over max. 20 ms, or more
typically, 10 ms. In the case of data word input without write request (write request is defined as data
bit in data register set to “0”), the write process is suppressed and the programming time is
shortened. During a subsequent programming of an already erased memory address, the erase
process is suppressed again, so that the reprogramming time is also shortened.



TDA8145 TV EAST/WEST CORRECTION CIRCUIT FOR SQUARE TUBES

FEATURES SUMMARY
■ LOW DISSIPATION
■ SQUARE GENERATOR FOR PARABOLIC
CURRENT SPECIALLY DESIGNED FOR
SQUARE C.R.T. CORRECTION
■ EXTERNAL KEYSTONE ADJUSTMENT
(symmetry of the parabola)
■ INPUT FOR DYNAMIC FIELD CORRECTION
(beam current change)
■ STATIC PICTURE WIDTH ADJUSTMENT
■ PULSE-WIDTH MODULATOR
■ FINAL STAGE D-CLASS WITH ENERGY
REDELIVERY
■ PARASITIC PARABOLA SUPPRESSION,
DURING FLYBACK TIME OF THE VERTICAL
SAWTOOTH
DESCRIPTION
The TDA8145 is a monolithic integrated circuit in a
8 pin minidip plastic package designed for use in
the square C.R.T. east-west pin-cushion correction
by driving a diode modulator in TV and monitor
applications.

CIRCUIT OPERATION
(see the shematic diagram)
A differential amplifier OP1 is driven by a vertical
frequency sawtooth current of ± 33µA which is
produced via an external resistor fromthe sawtooth
voltage. The non–inverting input of this amplifier
is connected with a reference voltage
corresponding to the DC level of the sawtooth voltage.
This DC voltage should be adjustable for the
keystone correction. The rectified output current of
this amplifier drives the parabola networkwhich
provides a parabolic output current.
This output current produces the corresponding
voltage due to the voltage drop across the external
resistor at pin 7.
If the input is overmodulated (> 40µA) the internal
current is limited to 40µA. This limitation can be
used for suppressing the parasitic parabolic current
generated during the flyback time of the frame
sawtooth.
A comparator OP2 is driven by the parabolic current.
The second input of the comparator is connected
with a horizontal frequency sawtooth
voltage the DC level of which can be changed by
the external circuitry for the adjustment of the picture
width.
The horizontal frequency pulse–width modulated
output signal drives the final stage. It consists of a
class D push–pull output amplifier that drives, via
an external inductor, the diode modulator.


TV Stereo Decoder with Matrix TDA 6600 2 (TDA6600)
SIEMENSPreliminary Data Bipolar IC
The TDA 6600-2 includes an advanced decoder for the identification signals for the
multichannel TV sound systems according to the dual-carrier system as well as a matrix
switched by the decoder to provide the L-Ft-information.
Features
0 Increased switching reliability and recognition by means of two PLLs for stereo
(117 Hz) and / or dual channel (274 Hz)
0 Separate bandwidth selection for dual-tone (pins 17-18) and stereo (pins 14-15)
0 Separate setting for the PLL time constants for dual-tone (pin 10) and stereo (pin 11)
0 Adjustable cut level for dual-tone (pin 8) and stereo (pin 9)
0 Cross-talk rejection independent of external component accuracy
0 Adjustment to minimal cross-talk level through external DC voltage
0 Suitable for TV sets with a 15625-Hz signal.
Type Ordering Code Package
TDA 6600-2 Q67000-A8210 P-DlP-24
Circuit Description
The circuitry has two functional sections:
Two phase locked loops for generating the required comparison frequencies (54.96
kHz and 54.8 kHz) from the line frequency. The phase detectors of the control loops
operate in a frequency range of 117 Hz and/or 274 Hz.
Four demodulators to evaluate the 54-kHz pilot signal. The capacitors at the mixer
outputs determine the bandwidth (and thus the signal-to-noise ratio) of the pilot tone
recognition.
An evaluation circuitry for decoding "stereo", "dual sound", and "mono" from the mixer
output levels. ln order to assure interference-free operation in case of high noise level
input signals, the individual signals "stereo" and "dual sound" are delayed via an
externally adjustable integrator. The subsequent digital evaluation provides the
information "mono", "dual sound", or "stereo" to the matrix and the 4 level input/output
(to drive the TDA 6200). If this four level input/output is connected to ground externally
(e.g. by the TDA 6200), the decoder will recognize this signal as "forced mono".
A stereo matrix with deemphasis and SCART output switched by the pilot frequency
decoder. The SCART output can be disabled by a MUTE signal (coincidence).

TDA8390 PAL DECODER AND RGB MATRIX

GENERAL DESCRIPTION
The TDA8390 is a one-chip PAL colour decoder which is designed to be used in combination with
the P’ CCD Delay Line (TDA8451) and the Filter Combination (TDA8452). The IC combines the
circuits that are required for the identification and demodulation of PAL signals, RGB matrixing and
amplification. SECAM signals can be handled when the IC is used in combination with the SECAM
decoder TDA8490.
Inductive components are not required due to the integration of the filters and the delay lines.
The TDA8390 provides a crystal precise reference signal for the clock generator circuits in TDA8451
and TDA8452. Therefore, no adjustments are required to the filters and delay times. The decoder
contains separate inputs for RGB signal insertion (analogue or digital) which can, for example, be used
for text display systems (e.g. channel number display, Teletext, Antiope etc.).
Features:

I A blackcurrent stabilizer which controls the black currents of the three electron guns
I Contrast and brightness control of inserted RGB signals
0 Self aligned oscillator
0 Capacitive coupling with black level clamping of the luminance, colour difference and RGB inputs
0 Equal black levels for internal TV and external signals
0 12 MHz bandwidth
O Emitter follower outputs for driving the RGB output stages.

FUNCTIONAL DESCRIPTION
Colour decoder
The input chroma signal is amplified and applied to the burst phase detector (reference signal R-Y
phase), the ACC and identification detector (reference signal i R-Y phase) and the two demodulators.
The burst phase detector controls the oscillator which operates at a frequency of 4.43 MHz. By
connecting pin 6 to 12 V, the free~running frequency of the oscillator can be adjusted (phase detector
and colour killer switched off). The gain control stage of the oscillator is biased in such a way that
sinewave signals are generated. The output from the oscillator is fed to a Miller integrator in order to
obtain the required 90° phase shift. The reference signals obtained from the oscillator and 90° phase
shift network are applied to the various demodulators.
The output signal from the ACC and identification detector is peak detected to generate the ACC
voltage and detected in a sample and hold circuit to obtain the identification and killer information.
Because the P’ CCD delay line (TDA8451) and the PZCCD filter combination (TDA8452) both require
a reference signal (2 x fsc) the oscillator frequency is doubled, internally, and is made available at pin 28.
The demodulated signals, with the correct amplitude ratio, are applied to the TDA8451.
The TDA8390 can be combined with the SECAM decoder TDA8490 (Fig.3) by direct connection
of their outputs. The output DC levels have been chosen so that the PAL decoder has priority
(output level during PAL is higher than output level during SECAM).
Control circuit
The luminance and colour difference signals together with the RGB inputs and fast switching pulse
form the inputs to the control circuit. The required luminance input signal (from TDA8452) has a
peak-to»peak value of 0.45 V (including sync). The colour difference input signals (from TDA8451)
have a negative phase with a 0.62 V (R-Y) and 0.8 V (B-Y) peak-to-peak value. After amplification,
the luminance signal is applied to the RGB matrix.
The colour difference signals are fed to the saturation control circuit before being applied to the RGB
matrix (the G-Y signal is generated after the saturation control circuit).
The normal matrix for PAL is: (G-Y) = -0.51 (Fl-Y)—0.19 (B-Y).
The signals from the RGB matrix are applied to a fast switching circuit from where external RGB
signals can be selected. The fast switching circuit is controlled by the video switching input. After
amplification the RGB signals (internal or external video) are controlled on the contrast and
brightness before being fed to the outputs. A typical output signal amplitude is 4 V black-to-white
(nominal controls).
The black level of the RGB output signals is detemiined by the black current stabilization circuit. The
information regarding the black current level of the picture tube is obtained in the same manner as
the TDA3562A. The beam current limiter input is used to reduce the output signal amplitude via the
contrast and brightness control circuits.




SDA 9087 Analog-Digital-Interface for inserted Picture

Features
O 3 separate ND converters
o Resolution: 5 bit
o Samplig rate: 13.5 Ml-lz. 3.375 Ml-lz
0 clamping circuit for the input signals
O Adjtstmle delay tor the lurritanee signal (9 steps)
o color ciiterence signals Y andV can be inverted
0 Multiplexed output interface (DMSD ccrnpatble)
0 Internal clock synchronization by sandcastle signal
Q System clock generation lor piaure insertion processor
o BLN synch signal
description
Together with an analog color decoder and e sync separator tor the i-i, V sync signals,
the SDA 9087 forms an analog picture channel on whose input the analog CVBS signal is
applied. This output produces the digital oornponents Y. U. V plus the sync signals oi th
CVBS signal The resolution or the dgtal output signals is 5 bit.
Furthermore, with the aid oi PLL. the SDA 9087 generates the tine locked clock LL8 (nom.
13-5 Mi-iz) and the blanking signal BLN.
The picture channel descrbed can replace a high-grade and costly digital picture
channel consisting oi the devices 7-bit ADO, rlgital muili-standard decoder (DMSDI and
central clock generator (OOGJJ-lowever. the quality oi the picture is reduced , and tor this
reason the more obvious application is as a picture channel for the inset picture that is
inserted in a picture-in-picture (PIP) system.
Y, U and V are digithed by 5-bit llesh converters and output in a iorrnat that matches the
interface of the PIP processor. The PLL synchronizes to an eattemal, horizontal sync
signal that is derived trorn the OCV signal oi the itset picture.
Circuit Description
The Umitance signal Y and the chrorrtlnanee signals U. V are led to the SDA 9087 by
means ct coupling capacitors. The black level ct Y is clamped to Vnert; the color
stbcrrier must be filtered out of Y-
The three signals components are digitized by converters: the sampling
rate is determined by LL3. Y is output as binary oitset code. The digitized Y simal is
delayed in a delay bloclr. This delay can be varied In increments ct two LL3 cycles in a
range oi 0 through 16 LL3 cycles on pins .l to compensate lor different delays in the
preceding luminance and crominance decoders.
The white level ot U and V is clamped to 0.5 x (Vnem + Vrmrt). U, V are titan converted hto a
5-bit two's complement code. The digitized U, V signals can be inverted via CNEG control
input. A multiplexer selects every fourth U. V sample and applies this tdbit information in
four clock cycles ‘I1 a nibble lorrnat to pins UV (0:3).

The horizontal PLL, consisting of a horizontal timer, phase comparator and V00.
generates the line-locked picture-in-picture system clock LL3 and the intemal chip timing.
The horizontal timer divides the LL3 dodr by 864 (the same for PAL and NTSC) and
appies this signal as s horizontal reference signal to the phase comparator (PC). The
external horizontal signal is decoded trom the sandcestle signal and matched in its pulse
width (= 345 LL3 cycles) to the reference signal. The clgitei phase comparator is
trequency- and phase-sensitivite (type 4) and produces current pulses at its output. The
up/down pulses ot the phase comparator are filtered on pin R0. The filtered signal is the
control voltage of the V00. The horizontal timer also determines the start time and the
width oi the 0|8l'l'I)ll'lfl pulse as tvel as the location of the blanking sigtal BLN, which in
tum deiines the horizontal duration oi the picture information on the Y output and should
be synchronous with It. BLN is consequently delayed to the same degree as Y.


TDA2595 Horizontal combination

GENERAL DESCRIPTION
The TDA2595 is a monolithic integrated circuit intended for use in colour television receivers.
Features
· Positive video input; capacitively coupled (source impedance < 200 W)
· Adaptive sync separator; slicing level at 50% of sync amplitude
· Internal vertical pulse separator with double slope integrator
· Output stage for vertical sync pulse or composite sync depending on the load; both are switched off at muting
· j1 phase control between horizontal sync and oscillator
· Coincidence detector j3 for automatic time-constant switching; overruled by the VCR switch
· Time-constant switch between two external time-constants or loop-gain; both controlled by the coincidence detector j3
· j1 gating pulse controlled by coincidence detector j3
· Mute circuit depending on TV transmitter identification
· j2 phase control between line flyback and oscillator; the slicing levels for j2 control and horizontal blanking can be set
separately
· Burst keying and horizontal blanking pulse generation, in combination with clamping of the vertical blanking pulse
(three-level sandcastle)
· Horizontal drive output with constant duty cycle inhibited by the protection circuit or the supply voltage sensor
· Detector for too low supply voltage
· Protection circuit for switching off the horizontal drive output continuously if the input voltage is below 4 V or higher
than 8 V
· Line flyback control causing the horizontal blanking level at the sandcastle output continuously in case of a missing
flyback pulse
· Spot-suppressor controlled by the line flyback control.

TDA4510 PAL decoder

GENERAL DESCRIPTION
The TDA4510 is a colour decoder for the PAL standard, which is pin sequent compatible with multistandard decoder
TDA4555 and also pin compatible with NTSC decoder TDA4570. It incorporates the following functions:
Chrominance part
· Gain controlled chrominance amplifier with operating point control stage
· Chrominance output stage for driving the 64 ms delay line
· Blanking circuit for the colour burst signal
· Automatic chrominance control (ACC) with sampled rectifier during burst-key

Oscillator and control voltage part
· Reference oscillator for double subcarrier frequency
· Gated phase comparison
· Identification demodulator and automatic colour killer
· Sandcastle pulse detector
· Service switch
Demodulator part
· Two synchronous demodulators for the (B-Y) and (R-Y) signals
· PAL flip-flop and PAL switch
· Colour switching stages
· Separate colour switching output
· (B-Y) and (R-Y) signal output stages
· Internal filtering of residual carrier

FUNCTIONAL DESCRIPTION
DIVIDER STAGES
The divider stages provide -(R-Y) and -(B-Y) reference signals with the correct 90 degrees relation for the demodulators.
PHASE COMPARATOR
The phase comparator compares the -(R-Y) reference signal with the burst pulse and controls the frequency and phase
of the reference oscillator.
IDENTIFICATION DEMODULATOR
The identification demodulator delivers a positive going identification signal for PAL-signals at pin 14, also used for the
automatic colour-killer.
SERVICE SWITCH
The service switch has two functions. The first position (V14-3 < 1 V) allows the adjustment of the reference oscillator.
Therefore the colour is switched on and the burst for the oscillator PLL is switched off. The second position (V14-3 > 5 V)
switches the colour on and the output signals can be observed.
SANDCASTLE PULSE DETECTOR
Sandcastle pulse detector for burst-gate, line and blanking (horizontal and vertical) pulse detection. The vertical part of
the sandcastle pulse is needed for the internal colour-on and colour-off delay.
PULSE PROCESSING PART
Pulse processing part which shall prevent a premature switching on of the colour. The colour-on delay, two or three field
periods after identification of the PAL signal, is achieved by a counter. The colour is switched off immediately or at the
latest one field period after disappearance of the identification voltage.

TDA8170 TV VERTICAL DEFLECTION OUTPUT CIRCUIT:
DESCRIPTION
The TDA8170 is a monolithic integrated circuit in
HEPTAWATTTM package. It is a high efficiency
power booster for direct driving of verticalwindings
of TV yokes. It is intended for use in Colour and B
&Wtelevision receivers as well as in monitorsand
displays.

The functions incorporated are :
.POWERAMPLIFIER
.FLYBACKGENERATOR
.REFERENCE VOLTAGE
.THERMAL PROTECTION

The power dissipated in the circuit must be removed
by adding an external heatsink.
Thanks to the HEPTAWATTTM package attaching
the heatsink is very simple, a screwa compression
spring (clip) being sufficient. Betweenthe heatsink
andthe packageit isbetter to insert a layerof silicon
grease, to optimizethe thermal contact ; no electrical
isolation is needed between the two surfaces.


ABSOLUTE MAXIMUMRATINGS
Symbol Parameter Value Unit
VS Supply Voltage (pin 2) 35 V
V5, V6 Flyback Peak Voltage 60 V
V3 Voltage at Pin 3 + Vs
V1, V7 Amplifier Input Voltage + Vs, – 0.5 V
Io Output Peak Current (non repetitive, t = 2 msec) 2.5 A
Io Output Peak Current at f = 50 or 60 Hz, t 3 10 msec 3 A
Io Output Peak Current at f = 50 or 60 Hz, t > 10 msec 2 A
I3 Pin 3 DC Current at V5 < V2 100 mA
I3 Pin 3 Peak to Peak Flyback Current at f= 50 or 60 Hz, tfly 31.5msec 3 A
Ptot Total Power Dissipation at Tcase = 90 °C 20 W
Tstg, Tj Storage and Junction Temperature – 40, +150 °C