GRUNDIG P37-730 TEXT CHASSIS CUC7301 INTERNAL VIEW.

 

 

The CHASSIS CUC7301 is the successor of the GRUNDIG CUC7300, more integrated and light weight !

Was integrating all teletext functions in a SDA5254P/E (PHILIPS)

Major fault source was the power supply with the mains DC capacitor leaking frequently causing further damage in semiconductors power supply related such as
mosfet and controller UC3842.

GRUNDIG P37-730 TEXT CHASSIS CUC7301 UC3842 Control IC for Switched-Mode Power Supplies usingMOS-Transistor:
 

   
The UC3842A, UC3843A series of high performance fixed frequency
current mode controllers are specifically designed for off–line and dc–to–dc
converter applications offering the designer a cost effective solution with
minimal external components. These integrated circuits feature a trimmed
oscillator for precise duty cycle control, a temperature compensated
reference, high gain error amplifier, current sensing comparator, and a high
current totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
programmable output deadtime, and a latch for single pulse metering.
These devices are available in an 8–pin dual–in–line plastic package as
well as the 14–pin plastic surface mount (SO–14). The SO–14 package has
separate power and ground pins for the totem pole output stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX843A is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).
• Trimmed Oscillator Discharge Current for Precise Duty Cycle Control
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with Motorola SENSEFET Products.

 The UC3842A, UC3843A series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost effective solution
with minimal external components. A representative block
diagram is shown in Figure 17.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates and internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 1 shows RT versus Oscillator Frequency
and Figure 2, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated, and the
discharge current is trimmed and guaranteed to within ± 10%
at TJ = 25°C. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 3 and 4.
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 20. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 21. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved.
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 7). The noninverting
input is internally biased at 2.5 V and is not pinned out. The
converter output voltage is typically divided down and
monitored by the inverting input. The maximum input bias
current is –2.0 mA which can cause an output voltage error
that is equal to the product of the input bias current and the
equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 30). The output voltage is offset by two
diode drops (9 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
when Pin 1 is at its lowest state (VOL). This occurs when the
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 23, 24). The Error
Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
voltage (VOH) to reach the comparator’s 1.0 V clamp level:
Rf(min) 9 3.0 (1.0 V) + 1.4 V
0.5 mA
= 8800 W
Current Sense Comparator and PWM Latch
The UC3842A, UC3843A operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin1). Thus the error signal controls
the peak inductor current on a cycle–by–cycle basis. The
current Sense Comparator PWM Latch configuration used
ensures that only a single pulse appears at the Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting the ground referenced sense resistor
RS in series with the source of output switch Q1. This voltage
is monitored by the Current Sense Input (Pin 3) and
compared a level derived from the Error Amp Output. The
peak inductor current under normal operating conditions is
controlled by the voltage at pin 1 where:
Ipk =
V(Pin 1) – 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 22. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability;

 UC3842A, 43A UC2842A, 43A
9 MOTOROLA ANALOG IC DEVICE DATA
PIN FUNCTION DESCRIPTION
Pin
F i D i i 8–Pin 14–Pin Function Description
1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation.
2 3 Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
5 – Gnd This pin is the combined control circuitry and power ground (8–pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through
resistor RT.
– 8 Power Ground This pin is a separate power ground return (14–pin package only) that is connected back to the
power source. It is used to reduce the effects of switching transient noise on the control circuitry.
– 11 VC The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With
a separate power source connection, it can reduce the effects of switching transient noise on the
control circuitry.
– 9 Gnd This pin is the control circuitry ground return (14–pin package only) and is connected back to the
power source ground.
– 2,4,6,13 NC No connection (14–pin package only). These pins are not internally connected.

Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842A,
and 8.4 V/7.6 V for the UCX843A. The Vref comparator upper
and lower thresholds are 3.6V/3.4 V. The large hysteresis
and low startup current of the UCX842A makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 33). The
UCX843A is intended for lower voltage dc to dc converter
applications. A 36 V zener is connected as a shunt regulator
form VCC to ground. Its purpose is to protect the IC from
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX842A is 11 V and
8.2 V for the UCX843A.
Output
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current and
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. The separate VC supply input allows the designer
added flexibility in tailoring the drive voltage independent of
VCC. A zener clamp is typically connected to this input when
driving power MOSFETs in systems where VCC is greater that
20 V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET
application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the
UC384XA. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.

DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulsewidth
jitter. This is usually caused by excessive noise pick–up
imposed on the Current Sense or Voltage Feedback inputs.
Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed–loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 19A
shows the phenomenon graphically. At t0, switch conduction
begins, causing the inductor current to rise at a slope of m1.
This slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2 until
the next oscillator cycle. The unstable condition can be
shown if a pertubation is added to the control voltage,
resulting in a small DI (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn–on (t2) is increased by DI + DI m2/m1.
The minimum current at the next cycle (t3) decreases to (DI +
DI m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on
each succeeding cycle, alternately increasing and
decreasing the inductor current at switch turn–on. Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If
m2/m1 is greater than 1, the converter will be unstable. Figure
19B shows that by adding an artificial ramp that is
synchronized with the PWM clock to the control voltage, the
DI pertubation will decrease to zero on succeeding cycles.
This compensation ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability. With m2/2 slope
compensation, the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense
inputs.




GENERAL BASIC TRANSISTOR LINE OUTPUT STAGE OPERATION:

The basic essentials of a transistor line output stage are shown in Fig. 1(a). They comprise: a line output transformer which provides the d.c. feed to the line output transistor and serves mainly to generate the high -voltage pulse from which the e.h.t. is derived, and also in practice other supplies for various sections of the receiver; the line output transistor and its parallel efficiency diode which form a bidirectional switch; a tuning capacitor which resonates with the line output transformer primary winding and the scan coils to determine the flyback time; and the scan coils, with a series capacitor which provides a d.c. block and also serves to provide slight integration of the deflection current to compensate for the scan distortion that would otherwise be present due to the use of flat screen, wide deflection angle c.r.t.s. This basic circuit is widely used in small -screen portable receivers with little elaboration - some use a pnp output transistor however, with its collector connected to chassis.

Circuit Variations:
Variations to the basic circuit commonly found include: transposition of the scan coils and the correction capacitor; connection of the line output transformer primary winding and its e.h.t. overwinding in series; connection of the deflection components to a tap on the transformer to obtain correct matching of the components and conditions in the stage; use of a boost diode which operates in identical manner to the arrangement used in valve line output stages, thereby increasing the effective supply to the stage; omission of the efficiency diode where the stage is operated from an h.t. line, the collector -base junction of the line output transistor then providing the efficiency diode action without, in doing so, producing scan distortion; addition of inductors to provide linearity and width adjustment; use of a pair of series -connected line output transistors in some large -screen colour chassis; and in colour sets the addition of line convergence circuitry which is normally connected in series between the line scan coils and chassis. These variations on the basic circuit do not alter the basic mode of operation however.

Resonance
The most important fact to appreciate about the circuit is that when the transistor and diode are cut off during the flyback period - when the beam is being rapidly returned from the right-hand side of the screen to the left-hand side the tuning capacitor together with the scan coils and the primary winding of the line output transformer form a parallel resonant circuit: the equivalent circuit is shown in Fig. 1(b). The line output transformer primary winding and the tuning capacitor as drawn in Fig. 1(a) may look like a series tuned circuit, but from the signal point of view the end of the transformer primary winding connected to the power supply is earthy, giving the equivalent arrangement shown in Fig. 1(b).

The Flyback Period:
Since the operation of the circuit depends mainly upon what happens during the line flyback period, the simplest point at which to break into the scanning cycle is at the end of the forward scan, i.e. with the beam deflected to the right-hand side of the screen, see Fig. 2. At this point the line output transistor is suddenly switched off by the squarewave drive applied to its base. Prior to this action a linearly increasing current has been flowing in the line output transformer primary winding and the scan coils, and as a result magnetic fields have been built up around these components. When the transistor is switched off these fields collapse, maintaining a flow of current which rapidly decays to zero and returns the beam to the centre of the screen. This flow of current charges the tuning capacitor, and the voltage at A rises to a high positive value - of the order of 1- 2k V in large -screen sets, 200V in the case of mains/battery portable sets. The energy in the circuit is now stored in the tuning capacitor which next discharges, reversing the flow of current in the circuit with the result that the beam is rapidly deflected to the left-hand side of the screen - see Fig. 3. When the tuning capacitor has discharged, the voltage at A has fallen to zero and the circuit energy is once more stored in the form of magnetic fields around the inductive components. One half -cycle of oscillation has occurred, and the flyback is complete.

Energy Recovery:
First Part of Forward Scan The circuit then tries to continue the cycle of oscillation, i.e. the magnetic fields again collapse, maintaining a current flow which this time would charge the tuning capacitor negatively (upper plate). When the voltage at A reaches about -0.6V however the efficiency diode becomes forward biased and switches on. This damps the circuit, preventing further oscillation, but the magnetic fields continue to collapse and in doing so produce a linearly decaying current flow which provides the first part of the forward scan, the beam returning towards the centre of the screen - see Fig. 4. The diode shorts out the tuning capacitor but the scan correction capacitor charges during this period, its right-hand plate becoming positive with respect to its left-hand plate, i.e. point A. Completion of Forward Scan When the current falls to zero, the diode will switch off. Shortly before this state of affairs is reached however the transistor is switched on. In practice this is usually about a third of the way through the scan. The squarewave applied to its base drives it rapidly to saturation, clamping the voltage at point A at a small positive value - the collector emitter saturation voltage of the transistor. Current now flows via the transistor and the primary winding of the line output transformer, the scan correction capacitor discharges, and the resultant flow of current in the line scan coils drives the beam to the right-hand side of the screen see Fig. 5.

Efficiency:
The transistor is then cut off again, to give the flyback, and the cycle of events recurs. The efficiency of the circuit is high since there is negligible resistance present. Energy is fed into the circuit in the form of the magnetic fields that build up when the output transistor is switched on. This action connects the line output transformer primary winding across the supply, and as a result a linearly increasing current flows through it. Since the width is
dependent on the supply voltage, this must be stabilised.

Harmonic Tuning:
There is another oscillatory action in the circuit during the flyback period. The considerable leakage inductance between the primary and the e.h.t. windings of the line output transformer, and the appreciable self -capacitance present, form a tuned circuit which is shocked into oscillation by the flyback pulse. Unless this oscillation is controlled, it will continue into and modulate the scan. The technique used to overcome this effect is to tune the leakage inductance and the associated capacitance to an odd harmonic of the line flyback oscillation frequency. By doing this the oscillatory actions present at the beginning of the scan cancel. Either third or fifth harmonic tuning is used. Third harmonic tuning also has the effect of increasing the amplitude of the e.h.t. pulse, and is generally used where a half -wave e.h.t. rectifier is employed. Fifth harmonic tuning results in a flat-topped e.h.t. pulse, giving improved e.h.t. regulation, and is generally used where an e.h.t. tripler is employed to produce the e.h.t. The tuning is mainly built into the line output transformer, though an external variable inductance is commonly found in colour chassis so that the tuning can be adjusted. With a following post I will go into the subject of modern TV line timebases in greater detail with other models and technology shown here at  Obsolete Technology Tellye !




GRUNDIG P37-730 TEXT CHASSIS CUC7301 TDA3653B TDA3653C Vertical deflection and guard circuit (90°):

GENERAL DESCRIPTION

The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to
1.5 A peak-to-peak.
Features
· Driver
· Output stage
· Thermal protection and output stage protection
· Flyback generator
· Voltage stabilizer
· Guard circuit

QUICK REFERENCE DATA
Note to the quick reference data
1. The maximum supply voltage should be chosen such that during flyback the voltage at pin 5 does not exceed 60 V.

 FUNCTIONAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
Flyback generator
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
Guard circuit
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.


PACKAGE OUTLINES
TDA3653B: 9-lead SIL; plastic (SOT110B); SOT110-1; 1996 November 25.
TDA3653C: 9-lead SIL; plastic power (SOT131); SOT131-2 November 25.
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply (note 1)
Supply voltage range
pin 9 VP = V9-4 10 - 40 V
pin 6 V6-4 - - 60 V
Output (pin 5)
Peak output voltage during flyback V5-4M - - 60 V
Output current I5(p-p) - 1.2 1.5 A
Operating junction temperature range Tj -25 - +150 °C
Thermal resistance junction to mounting base
(SOT110B) Rth j-mb - 10 - K/W
(SOT131) Rth j-mb - 3.5 - K/W.




GRUNDIG P37-730 TEXT CHASSIS CUC7301 TDA8361 Integrated PAL and PAL/NTSC TV processor

PHILIPS TDA8362 (TDA8361) MAIN CHARACTERISTICS
The TDA8362 television processor microcircuit contains an intermediate frequency (IF) signal processing circuit, a multi-standard demodulator of a frequency-modulated sound signal, automatically tuned notch and band-pass filters in the video signal processing channel, a luminance signal delay line, a color signal decoder in the PAL and NTSC system with automatic detection systems, TV / AV input selector, RGB signal switching scheme, horizontal and vertical scanning synchronization circuits.
Variant TDA8362A also contains automatic white balance circuits. Thus, the TDA8362 includes all the basic low signal circuits needed to build a color television receiver.
The minimum number of elements connected to external circuits and only one element requiring adjustment (reference circuit of the IF signal demodulator) creates an exceptional usability of the TDA8362. As a result, the TDA8362 processor has become one of the most widely used chips in modern television technology.
The main characteristics of TDA8362 are given in table. 1.

Parameter	Value
Supply voltage	8 ± 0.8
Current consumption, mA	80
Power consumption	0.7
Sensitivity of the IFI, μV	70
Sensitivity UPCHZ, mV	1
Sound signal from an external input, mVeff	350
Video signal from external input, Vp_p	1
Signals at the inputs in RGB, Bn n	0.7
Demodulated PTsTS, Vp-p	2,4
Tuner AGC control current, mA	0 ... 5
The range of voltage changes AFCG, V	6
Audio output signal (vyv. 50), mV	700
Output signals in RGB, Bn_n	4
Horizontal line output current, mA	10
Framing output current, mA	1
Control voltage range, V	0 ... 5

Table 1. Key Features of the TDA8362 Processor

The construction, pinout and basic parameters of all modifications of the TDA8362 microcircuits (with the exception of the TDA8362A variant) are the same. Features of their application will be discussed below.
 

DESCRIPTION OF STRUCTURAL SCHEME

Table 2 gives the pin assignment of TDA8362, and also shows the difference in pinout of the TDA8362 and TDA8362A options.
The latter contains a circuit for automatic white balance, the measuring signal at the input of which comes from pin 14 of TDA8362.

TDA8362	TDA8362A	Pin assignment
1	1	Pre-emphasis correction of sound signal and switching to positive modulation
2	2	IF signal demodulator reference circuit
3	3	IF signal demodulator reference circuit
4	4	Video identification circuit output, sound switch input
5	5	IF signal input and volume control
6	6	Audio input from external connectors
7	7	PCTS output
8	8	Decoupling capacitor of the power supply circuit of the digital part
9	41	Earth 1 (common)
10	10	Power input
eleven	eleven	Earth 2 (common)
12	12	Decoupling capacitor filter settings
thirteen	thirteen	Internal video input
14	14	RF correction circuit adjustment input (sharpness)
fifteen	fifteen	External video input
16	16	Chroma input
17	17	Brightness adjustment
18	18	Exit to
19	19	Output G
20	20	Output R
21	21	RGB switch and blanking output
22	22	Signal output R (from external sources)
23	23	Signal output G (from external sources)
24	24	Signal output B (from external sources)
25	25	Contrast adjustment
26	26	Saturation Adjustment
27	27	Color tone adjustment (or color signal output)
28	28	CV input BY (from delay line)
29th	29th	RRS input RY (from delay line)
thirty	thirty	RCS RY output (to delay line)
31	31	TsRS BY output (to the delay line)
32	32	4.43 MHz reference signal output on TDA8395
33	33	Phase detector filter
34	34	Conclusion connection of a quartz resonator of 3.58 MHz
35	35	4.43 MHz quartz resonator connection terminal
36	36	Power output to trigger horizontal scanning
37	37	Horizontal scan trigger output
38	38	Horizontal Flyback Pulse Input / Gating Pulse Output (SSC)
39	39	Phase Detector Filter 2
40	40	Phase Detector Filter 1
41	42	Frame Reverse Pulse Input
42	43	Conclusion conclusion of an RC chain of ZG frame scan
43	44	Firing trigger pulses output
44	9	AFC output
45	45	IF signal input 1
46	46	IF signal input 2
47	47	AGC circuit output
48	48	A conclusion of the connection of the decoupling capacitor of the AGC circuit
49	49	Tuner AGC adjustment input
fifty	fifty	Sound output
51	51	Conclusion connection output decoupling capacitor demodulator sound
52	52	Decoupling capacitor of the power control circuit

Table 2. TDA8362 Processor Pin Assignment

 IF SIGNAL PROCESSING CIRCUIT
The IF image signal amplifier (IFI) is a three-stage differential amplifier with an adjustable gain and a symmetrical differential input (vyv. 45 and 46 TDA8362). The gain variation range is at least 64 dB. The sensitivity of the IFI (70 μV) is comparable to the parameters of modern specialized TDA8362 IFI.
Maximum input signal up to 100 mV eff. The IF signal is demodulated using a reference carrier frequency generated by passive regeneration of the carrier image. The reference circuit of the demodulator is connected to pin 2 and 3 of the TDA8362. It is the only item that needs to be configured. The demodulator provides the ability to process IF signals with both negative and positive modulation. The automatic frequency control circuit (AFC) generates a signal at pin 44 of TDA8362, which provides tuning of the tuner local oscillator frequency with an error of no more than 50 kHz.
The circuit uses the same reference signal as for the demodulator.
The built-in sampling-storage circuit ensures the protection of the AFC circuit from the penetration of a video signal. A storage capacitor is built into the TDA8362. The steepness of the characteristics of the AFC circuit (33 mV / kHz) directly depends on the quality factor of the reference circuit. To reduce the steepness, a resistor is connected to pin 44 of the TDA8362. The output voltage range is 6 V (at a nominal frequency of 3.5 V). The characteristic of the AFC for the TDA8362-N5 modification is optimized for the European IF standard. The automatic gain control (AGC) circuit generates the control voltage of the amplifier and the tuner (vv. 47 TDA8362), ensuring a constant amplitude of the signals at the input of the amplifier and at the output of the video amplifier.
To exclude the influence of the AGC circuit on the tuner at low levels of the input signal, an AGC response delay is introduced. The delay value is regulated by applying a control voltage to pin 49 of the TDA8362. The voltage variation range is 0.5 ... 4.5 V. The minimum and maximum signal levels at pin 49, at which the tuner AGC is triggered, are 0.2 mV eff and 150 mV eff, respectively.
The AGC detector monitors the amplitude of the clock pulses with negative modulation of the IF signal and white peaks with positive modulation. To ensure noise immunity, the gating of the detector is used. Gating is disabled for the duration of the reverse frame scan. This allows you to avoid changing the amplitude of the video signal in the playback mode from the VCR due to phase shifts that occur during the switching of video heads. A capacitor (usually 2.2 μF) is connected to pin 48 of the TDA8362, which sets the time constant of the AGC circuit.

The external connection of this capacitor provides the flexibility of using the TDA8362. The permissible leakage current of the capacitor is 10 μA for negative and 200 nA for positive modulation. An increase in leakage current degrades the characteristics of the AGC circuit and leads to a change in the amplitude of the video signal during the field. The voltage at the output of the AGC circuit (vyv. 47) is at maximum gain (U pit +1) V and at minimum gain (saturation voltage) - 0.3 V.
Switching the demodulator and the AGC circuit to the IF signal processing mode with positive modulation is carried out by supplying voltage (U pit -1) V to pin 1 of TDA8362. The video signal identification circuit works independently of the synchronization circuit, which ensures that the setting is saved to the received television channel during translation TV to monitor mode.
The circuit generates the following signals at the output (pin 4 of TDA8362):

• voltage no more than 0.5 V in the absence of a video signal (in this case, the sound detector is turned off);
• voltage of 6 V when receiving a signal with a frequency of a subcarrier of color of 3.58 MHz;
• voltage of 8 V when receiving a signal with a frequency of a subcarrier of color 4.43 MHz.

In the modification of TDA8362-N5, an identification mode is provided for tuner detuning. To do this, when the signal is weak, the gating of the tuner AGC circuitry for the time of receiving horizontal synchronization pulses is disabled, which prevents erroneous identification of color subcarrier outbreaks by signals. The video amplifier provides amplification of the detected video signal, matching with the load and limiting noise emissions in the video signal.
The signal amplitude at the output (pin 7 of TDA8362) is 2.4 V. The output impedance of the amplifier is not more than 50 Ohms, the load current is not more than 5 mA. The bandwidth of the video amplifier (at the level of -3 dB) is up to 9 MHz, which makes it possible to use TDA8362 in all broadcasting standards. The emission control scheme provides the inversion of white peaks exceeding 4.8 V, noise emissions having a level below 1.4 V (the tops of the clock pulses have a level of 2 V), and their introduction into the video signal at 3.2 V and 2.6 V , respectively. At the same time, the noise emission inversion circuit only works during the reception of a large signal, since with a weak signal it negatively affects the operation of the audio signal processing channel.
In the modification of TDA8362-N4, an ultra-white peaks binding scheme is used in the video signal. The TDA8362-N5 modification does not use a white peak limiting scheme, since when there are a large number of white peaks, inverting and introducing them at 3.2 V results in the image becoming gray.

SOUND PROCESSING CHAIN

The sound signal to the second PC sound extracted from the full television signal is fed to pin 5 of the television processor (TDA8362). To the same output, a control voltage is supplied through the resistor to adjust the volume. The control voltage range is 0 ... 5 V.
The IF signal of the sound is limited and fed to the demodulator, made in the form of a phase locked loop (PLL). The PLL system is automatically tuned to the input frequency and does not require adjustments. The PLL system capture range is 4.2 ... 6.8 MHz.
The preliminary amplifier (PU) provides amplification of the detected sound signal to a level of 350 mV eff. This signal, which is not adjustable in magnitude, is fed to pin 1 of the TDA8362, to which an external capacitor is connected to correct the distortion of the sound signal, and to the switching and volume control circuitry. PU also provides mute when there is no identification of the video signal.
The signal from pin 1 of the TDA8362 is used to output to external connectors (for example, SCART). The sound signal from external connectors is fed to pin 6 of the TDA8362, its magnitude is 350 mV eff. The switching circuit, controlled by the voltage supplied to pin 16 of the TDA8362, provides for the output of pin 50 of the TDA8362 sound output signal, which then goes to the low-frequency amplifier.
The value of the output signal, which is -6 dB from the maximum is 700 mB eff, when adjusting the volume changes in the range of 80 dB. DC voltage at the terminal 50 TDA8362 3.3 V (when turning off the sound 10 ... 50 mB). The TDA8362-N5 modification provides click protection in the speakers when the sound is turned on, while using the previous TDA8362 modifications, a 290 kOhm resistor was needed between pin 1 of the TDA8362 and the +8 B bus to solve this problem.
Switching the TDA8362 to the signal processing mode with positive modulation is carried out by supplying at least 1 (U pit - 1) V to pin 1 of the TDA8362.

SYNCHRONIZATION CHAIN

The selection of clock pulses (SI) from the video signal arriving at vyv.13 or 15 TDA8362 is carried out by a selector containing an amplifier, an amplitude selector and a circuit for the selection of lowercase and frame SI.
Lower case SIs are supplied to the first phase detector (PD1) and a coincidence detector, which identifies the presence of a video signal and controls the synchronization of the master oscillator (ZG) of horizontal scanning. In the absence of synchronization, the voltage at pin 14 of the TDA8362 becomes low, which can be used to identify the presence of a video signal. PD1, together with a low-pass filter (LPF) connected to pin 40 of TDA8362, and a horizontal scan line generator form a PLL that provides frequency and phase adjustment of the pulse pulses to lower case SI parameters.
The time constant ФД1 is automatically switched (by switching internal resistance) according to the signals from the noise detector and from the coincidence detector. With an increase in the noise level in the video signal at pin 13 of TDA8362, the PD1 time constant increases (the output current is 30 μA). In the absence of a video signal, the time constant increases even more (output current 6 μA), which ensures synchronization in the on-screen display (OSD) mode.
When a normal signal is received, as well as when processing a signal fed to pin 15 of the TDA8362, the time constant decreases (output current 180 μA) to expand the capture band and increase the noise immunity of the synchronization circuit.
To ensure quick compensation of the phase error that occurs in the signal from the VCR when switching the video heads, the time constant is further reduced by about 1.5 times for the reverse scan time of the vertical scan (output current 270 μA). Thus, good synchronization circuit characteristics are achieved both in the case of receiving a weak signal and in the case of signal processing from a VCR.
The video signal span on pin 13 of the TDA8362 (including sync pulses) must be at least 2 V when a normal signal is received. Otherwise, the noise detector will switch the time constant at a lower IF signal level (switching occurs at a signal-to-noise ratio of 20 dB), which will lead to a “jitter” phase of the horizontal scanning signal.
To ensure the independence of the image phase from the horizontal frequency (15.625 or 15.734 kHz), the PD1 static characteristic has a very high slope. Horizontal scanning operates at a double horizontal scanning frequency. Its frequency is automatically calibrated using the tuning circuit by comparing it with the frequency of the generator with quartz stabilization of the color decoder. As a result, the frequency of free oscillations of the GB has a deviation of no more than 2% of the central value. At startup, calibration is always performed with 4.43 MHz quartz, unless the 3.58 MHz quartz forced mode is selected.
The second phase detector (FD2) ensures the formation of horizontal line triggering pulses on pin 37 of the TDA8362 and maintaining the phase of these pulses relative to 3G pulses in the capture mode in PD1. PD2 together with the low-pass filter connected to pin 39 of the TDA8362 and the 3G form a PLL. The initial phase of the image is set by changing the external load connected to pin 39 of TDA8362. The shift range is ± 2 μs when the control current changes within ± 6 μA. The horizontal flyback pulses necessary for the operation of PD2 are received at pin 38 of TDA8362.
At the same output, combined strobe pulses are formed, which are necessary for operation of integrated delay line microcircuits (TDA4661 or TDA4665) and SECAM decoder (TDA 8395).
Gating pulses have the following parameters:

• binding voltage during the reverse pulse: 3 ± 0.4 V;
• voltage during the quenching pulse: 2 ± 0.2 V;
• voltage during the color subcarrier flash: 5.3 ± 0.5 V;
• field blanking pulse width: 14 lines;
• flash highlight pulse width: 3.5 ± 0.2 μs.

When using the TDA8362 in question, X-ray protection can be implemented. For this, the external detector must provide switching of a constant voltage (at least 6 V) on pin 39 of TDA8362. In this case, the formation of horizontal line triggering pulses stops, and the voltage at pin 37 of the TDA8362 becomes approximately equal to the supply voltage. If the voltage on pin 39 returns to its normal level, then trigger pulses reappear on pin 37.
Parameters of pulses of start of horizontal scanning:

• lower level of output voltage: 0.3 V;
• maximum level: U pit;
• pulse duty cycle: 2;
• maximum permissible output current: 10 mA.

The launch of the horizontal scanning line is carried out by applying a voltage of 8 V to terminal 36 of the TDA8362 (minimum starting current of 6.5 mA). It should be noted that it is possible to start when the current is 5.5 mA. At the same time, calibration of the ZG is not carried out and its frequency will be higher than the nominal (maximum frequency deviation is 75%).
 In TDA8362-N5, the maximum trigger pulse frequency is limited to 20 kHz. When the voltage on pin 36 of TDA8362 decreases to 5.8, the formation of start pulses immediately stops. If the pre-start mode of the ЗГ is not used, then pin 36 and 10 of the TDA8362 are connected to the 8 V power bus. With separate power supply, the voltage at pin 36 must always be greater than or equal to the voltage at pin 10 of the TDA8362.

The control pulses for the HR horizontal scan, which is a sawtooth voltage generator, are obtained by dividing the frequency of the horizontal horizontal scan.
The frequency divider has two operating modes.
The “large window” mode is activated when there is no synchronization or when a non-standard signal is received (the number of lines in a half-frame is from 311 to 314 in 50 Hz mode and from 261 to 264 in 60 Hz mode). In this case, the divider is in search mode and switches from a frequency of 45 Hz to a frequency of 64.5 Hz.
The narrow window mode is activated when more than 15 consecutive frame sync pulses are detected.
This is the standard mode of operation. In the absence of clock pulses, the reverse motion of Zr turns on at the end of the half-frame (window), which ensures minimal image distortion.
The divider switches back to search mode if there are no frame sync pulses for 6 consecutive periods of frame scan. To pin 42 of TDA8362 is connected an external RC chain of a 3G frame scan.
The amplitude of the sawtooth voltage at pin 42 is 1.5 ... 1.8 V. At pin 41 of the TDA8362, reverse-frequency pulses of a vertical sweep (from the output stage) are applied to ensure the linearity of the output voltage.
The constant voltage on pin 41 is 2.5 ± 0.5 V, the alternating voltage is 1 V. In the TDA8362, the kinescope is protected against burn-through in the event of a frame scan failure, which dampens the rays when the direct voltage on pin 41 of the TDA8362 increases or decreases by 1 5 in (relative to the above). Framing control pulses are formed on pin 43 of TDA8362. The maximum and minimum voltage are respectively 4 and 0.3 V.
The maximum permissible output current is 1 mA. The delay in turning on the vertical scan at power-on is 140 ms, and the output voltage is high. When you start the HR frame scan is turned on at a frequency of 60 Hz.
In the TDA8362-N5 modification, the launch is carried out at a frequency of 50 Hz, which is used for the on-screen display. The voltage at pin 43 of the TDA8362 when turned on is low, which makes it easier to start the frame sweep.
TDA8362 synchronization circuit The TDA8362 provides reliable horizontal and frame synchronization of the image when processing a signal from a VCR, both in the case of phase displacement of the clock pulses (with a stretched tape), and in the case of playing back video tapes with copy protection.

TDA8362 VIDEO PROCESSING CIRCUIT
The full color television signal allocated on pin 7 of the TDA8362 passes notch filters to suppress the second intermediate frequency of the sound and goes to pin 13 of the TDA8362 (internal signal). On pin 15 of the TDA8362, a signal is supplied from external inputs (external signal).
The signal swing at pin 13 (including sync pulses) is 2 ... 2.8 V, and at pin 15 is TDA8362 1 ... 1.4 V. Switching the input video signal is carried out by a switching circuit controlled by voltage level on pin 16 of TDA8362 (U 16). At U 16 <0.5B, internal video and audio signals are processed (a notch filter that suppresses the color signal is turned on). With 3 <U16 <5V, external video and audio signals in the S-VHS standard are processed. In this case, a color signal is supplied to pin 16 of the TDA8362, and a brightness signal to pin 15. The notch filter is disabled in this mode. At U16> 7.5 V, external video and audio signals are processed (notch filter on).
The TDA8362 contains notch and bandpass filters to separate color and luminance signals.
The filter tuning scheme provides automatic adjustment of the filters in accordance with the frequency of the crystal oscillator included in the decoder. A pin 12 of the TDA8362 is connected to a decoupling capacitor of the tuning circuit.

In modification TDA8362-N5, the resonant frequency of the notch filter during signal processing in the SECAM system is reduced to 4.2 MHz to provide better suppression of the DR and DB subcarriers in the luminance signal. Filters are calibrated during the reverse frame scan. The luminance signal enters the delay line (480 ns) and the RF correction circuit, which provides an increase in the frequency response in the high-frequency region, and then to the matrixing circuit. pin 14 TDA8362 is used to control the RF correction circuit (image sharpness). The control voltage range is 0 ... 5 V. When a voltage of 7 V is applied to pin 14, the correction circuit is switched off (nominal mode). In the absence of a video signal, the current consumed by TDA8362 according to pin 14 increases to 1 mA (in versions N3 and N4 - up to 200 μA). The voltage on pin 14 is reduced. This information can be used to identify the video signal.

 The color signal is fed to a band-pass filter and an amplifier with AGC, and then to a decoder, which includes a generator with quartz frequency stabilization, a color difference signal demodulator (CRS), and a color off circuit.
The generator generating the signal of the reference subcarrier, the PD, and the low-pass filter connected to pin 33 of the TDA8362 form a PLL system that provides synchronization in frequency and phase of the signals of the reference subcarrier with a color burst signal (SCC). Quartz resonators are connected to pin 34 and 35 of the TDA8362, while a resonator with a frequency of 4.43 MHz is connected to pin 35. This frequency is used for calibrating 3G horizontal scanning, and to pin 34 - a resonator with a frequency of 3.58 MHz.
When using one quartz or connecting two quartz to one pin (usually to pin 34) and using an external switching circuit, pin 35, the TDA8362 is connected to the power bus through a 47 kOhm resistor. This ensures the forced inclusion of the generator.

When using modifications N4 and N5 TDA8362, the value of the resistor is reduced to 8.2 kOhm. This is essential to enable 3G line scan calibration. The system's automatic detection circuitry provides recognition of color signals in PAL and NTSC systems and switching of signal processing circuits.
To process the color signal in the SECAM system, a TDA8395 decoder is used, to which a 4.43 MHz reference signal is supplied from pin 32 of the TDA8362. The amplitude of the reference signal is 0.25 ± 0.5 V. In the case of identifying a color signal in a PAL or NTSC system, the voltage at pin 32 of the TDA8362 is 1.5 V. If there is no identification, the color scheme disables the outputs of the demodulator central circuit (pin 30 and 31) , and the voltage on pin 32 of the TDA8362 increases to 5 V. This voltage blocks the TDA8395 color shutdown circuit in m / s and connects its outputs to the central control system.

The current consumed by TDA8395 with pin 32 of TDA8362 when identifying a color signal in the SECAM system is 150 μA. Increasing the current to this value forces the TDA8362 to SECAM mode. In this case, the system automatic detection circuit does not search for color signals in PAL and SECAM systems. Forcing the TDA8362 to NTSC mode is not possible.

The color signal for the TDA8395 can be obtained on pin 27 of the TDA8362 by connecting this output to the power bus via a 4.7 ... 12 kΩ resistor. The signal span is 330 mV. This combination of chips can only be used as a PAL / SECAM decoder. In the case of color signals processing, PAL / SECAM / NTSC systems use an external color signal extraction circuit for TDA8395.

It should be noted that when using modifications N4 and N5 of TDA8362, to prevent erroneous identification of the signal from the video recorder in the SECAM system as NTSC, it is necessary to provide a voltage at the terminal 27 of TDA8362 of at least 6 V.

GENERAL DESCRIPTION
The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
deflection.
Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.
The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
possible).
The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.
For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.

FUNCTIONAL DESCRIPTION
Video IF amplifier
The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.
The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.
In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.
The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.
The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.
The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.
To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.
The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependent on the frequency of the
incoming chrominance signal.

Sound circuit
The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.
The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of -6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.
The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.
Synchronization circuit
The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
amplitude.
The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.
The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
typical value.
The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.
X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.
The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8 V supply line.
The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.
Integrated video filters
The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
decoder.
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.
When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
applications.
The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.
Colour decoder
The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.

TDA8361
This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5 kW or 10 kW resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.
TDA8362
In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
decoder TDA8395.
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 mA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R-Y and B-Y outputs
and increase the voltage level on PIN 32.


RGB output circuit
The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.
The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.

LIST OF COMMON FAULTS  / TROUBLESHOOTING OF GRUNDIG CHASSIS CUC7301:

Grundig CUC7301 Blown psu caused by R661 220R going hi res also replaced IC630 UC3842, T665 MJFS8004, D663 3v6 Zener
Grundig CUC7301 Dead Dry joint C669 blows T665 & IC630
Grundig CUC7301 Dead C669 1000pf dry joints & burnt; MJF18004 T665 s/c; ZD663 had 25R reverse resistance, D624/621 1N4007 mains rects s/c & UC3842AN faulty
Grundig CUC7301 Dead - Chopper T665 blown plus - IC630, D633 3v6 zener, D662 BA157, bridge rects D621-4 1N4007, R661 220R, R663 18R, 3 x sm diodes under psu sect, dry joints C669
Grundig CUC7301 Dead - lop tr s/c & replacement ran hot CT169 BC858B buffer sm leaky
Grundig CUC7301 Dead - R542 10k or 13k o/c When replaced overheated again - crack in print by lopt
Grundig CUC7301 Low sound & no set up menu In hotel mode - to exit - hold down "i" button at sw on
Grundig CUC7301 low sound -stuck in hotel mode hold 'i' button whilst switching tv on. Use rc arrows to select hotel mode then off
Grundig CUC7301 off chopper tr s/c c-b T665 MJE18004C, D664, 666 1N4003, CD654,CD656 LS4148, IC630 UC3842A, D663 6.3v zener, R661 220R replaced & dry joint C669
Grundig CUC7301 off with a bang C669 1000pf had dry joints causing burn up of pcb. Following parts replaced :- 2.5A fuse, IC638 uC3842AN, T665 chopper tr MJF18004C, D662 BA157 s/c, D663 ZPD3.6 3.6v zener s/c, R663 18R, R661 220R hi res, R669 5w
Grundig CUC7301 Pic pulled across to right CT169 BC858B sm leaky
Grundig CUC7301 Poor regulation of psu sm diodes cd 654 and cd656 leaky. They are type
LS4148 but standard 1N4148 ,s work ok.
Grundig CUC7301 Reduced width and line tearing when TV gets hot. Replace surface mount transistor CT169 BC858B
Grundig CUC7301 St/by only C667 100µ 35v.
Grundig CUC7301 Tripping with front led flashing No HT on dummy load - HT preset R654 470R o/c
Grundig CUC7301 Dead aft few mins - line drive lost Buffer CT169 BC858B sm tr faulty.
Grundig CUC7303 Dead - PSU blown Chopper tfmr, S2055 LOPTr & FOP chip
Grundig CUC7303 off burning smell bad joints mains sw
Grundig CUC7303 Won't go fully into st/by - crt heaters stay lit etc Pin 1 IC676 should drop to 1.2v in st/by - was staying at 10.7v. BC848 sm tr downstream from pin 1 was faulty though checked ok.