The CHASSIS CUC7301 is the successor of the GRUNDIG CUC7300, more integrated and light weight !
Was integrating all teletext functions in a SDA5254P/E (PHILIPS)
Major fault source was the power supply with the mains DC capacitor leaking frequently causing further damage in semiconductors power supply related such as
mosfet and controller UC3842.
GRUNDIG P37-730 TEXT CHASSIS CUC7301 UC3842 Control IC for Switched-Mode Power Supplies usingMOS-Transistor:
The UC3842A, UC3843A series of high performance fixed frequency
current mode controllers are specifically designed for off–line and dc–to–dc
converter applications offering the designer a cost effective solution with
minimal external components. These integrated circuits feature a trimmed
oscillator for precise duty cycle control, a temperature compensated
reference, high gain error amplifier, current sensing comparator, and a high
current totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
programmable output deadtime, and a latch for single pulse metering.
These devices are available in an 8–pin dual–in–line plastic package as
well as the 14–pin plastic surface mount (SO–14). The SO–14 package has
separate power and ground pins for the totem pole output stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX843A is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).
• Trimmed Oscillator Discharge Current for Precise Duty Cycle Control
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with Motorola SENSEFET Products.
The UC3842A, UC3843A series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost effective solution
with minimal external components. A representative block
diagram is shown in Figure 17.
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates and internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 1 shows RT versus Oscillator Frequency
and Figure 2, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated, and the
discharge current is trimmed and guaranteed to within ± 10%
at TJ = 25°C. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 3 and 4.
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 20. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 21. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 7). The noninverting
input is internally biased at 2.5 V and is not pinned out. The
converter output voltage is typically divided down and
monitored by the inverting input. The maximum input bias
current is –2.0 mA which can cause an output voltage error
that is equal to the product of the input bias current and the
equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 30). The output voltage is offset by two
diode drops (9 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
when Pin 1 is at its lowest state (VOL). This occurs when the
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 23, 24). The Error
Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
voltage (VOH) to reach the comparator’s 1.0 V clamp level:
Rf(min) 9 3.0 (1.0 V) + 1.4 V
= 8800 W
Current Sense Comparator and PWM Latch
The UC3842A, UC3843A operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin1). Thus the error signal controls
the peak inductor current on a cycle–by–cycle basis. The
current Sense Comparator PWM Latch configuration used
ensures that only a single pulse appears at the Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting the ground referenced sense resistor
RS in series with the source of output switch Q1. This voltage
is monitored by the Current Sense Input (Pin 3) and
compared a level derived from the Error Amp Output. The
peak inductor current under normal operating conditions is
controlled by the voltage at pin 1 where:
V(Pin 1) – 1.4 V
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 22. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability;
UC3842A, 43A UC2842A, 43A
9 MOTOROLA ANALOG IC DEVICE DATA
PIN FUNCTION DESCRIPTION
F i D i i 8–Pin 14–Pin Function Description
1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation.
2 3 Voltage
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
5 – Gnd This pin is the combined control circuitry and power ground (8–pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through
– 8 Power Ground This pin is a separate power ground return (14–pin package only) that is connected back to the
power source. It is used to reduce the effects of switching transient noise on the control circuitry.
– 11 VC The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With
a separate power source connection, it can reduce the effects of switching transient noise on the
– 9 Gnd This pin is the control circuitry ground return (14–pin package only) and is connected back to the
power source ground.
– 2,4,6,13 NC No connection (14–pin package only). These pins are not internally connected.
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842A,
and 8.4 V/7.6 V for the UCX843A. The Vref comparator upper
and lower thresholds are 3.6V/3.4 V. The large hysteresis
and low startup current of the UCX842A makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 33). The
UCX843A is intended for lower voltage dc to dc converter
applications. A 36 V zener is connected as a shunt regulator
form VCC to ground. Its purpose is to protect the IC from
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX842A is 11 V and
8.2 V for the UCX843A.
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current and
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. The separate VC supply input allows the designer
added flexibility in tailoring the drive voltage independent of
VCC. A zener clamp is typically connected to this input when
driving power MOSFETs in systems where VCC is greater that
20 V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the
UC384XA. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulsewidth
jitter. This is usually caused by excessive noise pick–up
imposed on the Current Sense or Voltage Feedback inputs.
Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other noise
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed–loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 19A
shows the phenomenon graphically. At t0, switch conduction
begins, causing the inductor current to rise at a slope of m1.
This slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2 until
the next oscillator cycle. The unstable condition can be
shown if a pertubation is added to the control voltage,
resulting in a small DI (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn–on (t2) is increased by DI + DI m2/m1.
The minimum current at the next cycle (t3) decreases to (DI +
DI m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on
each succeeding cycle, alternately increasing and
decreasing the inductor current at switch turn–on. Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If
m2/m1 is greater than 1, the converter will be unstable. Figure
19B shows that by adding an artificial ramp that is
synchronized with the PWM clock to the control voltage, the
DI pertubation will decrease to zero on succeeding cycles.
This compensation ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability. With m2/2 slope
compensation, the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense
GRUNDIG P37-730 TEXT CHASSIS CUC7301 TDA3653B TDA3653C Vertical deflection and guard circuit (90°):
1.5 A peak-to-peak.
· Output stage
· Thermal protection and output stage protection
· Flyback generator
· Voltage stabilizer
· Guard circuit
QUICK REFERENCE DATA
Note to the quick reference data
1. The maximum supply voltage should be chosen such that during flyback the voltage at pin 5 does not exceed 60 V.
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.
TDA3653B: 9-lead SIL; plastic (SOT110B); SOT110-1; 1996 November 25.
TDA3653C: 9-lead SIL; plastic power (SOT131); SOT131-2 November 25.
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply (note 1)
Supply voltage range
pin 9 VP = V9-4 10 - 40 V
pin 6 V6-4 - - 60 V
Output (pin 5)
Peak output voltage during flyback V5-4M - - 60 V
Output current I5(p-p) - 1.2 1.5 A
Operating junction temperature range Tj -25 - +150 °C
Thermal resistance junction to mounting base
(SOT110B) Rth j-mb - 10 - K/W
(SOT131) Rth j-mb - 3.5 - K/W.
GRUNDIG P37-730 TEXT CHASSIS CUC7301 TDA8361 Integrated PAL and PAL/NTSC TV processor
The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.
The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.
For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.
Video IF amplifier
The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.
The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.
In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.
The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.
The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.
The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.
To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.
The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependent on the frequency of the
incoming chrominance signal.
The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.
The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of -6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.
The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.
The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.
The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.
X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.
The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8 V supply line.
The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.
Integrated video filters
The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.
When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.
The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.
This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5 kW or 10 kW resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.
In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 mA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R-Y and B-Y outputs
and increase the voltage level on PIN 32.
RGB output circuit
The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.
The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.
LIST OF COMMON FAULTS / TROUBLESHOOTING OF GRUNDIG CHASSIS CUC7301:
Grundig CUC7301 Dead Dry joint C669 blows T665 & IC630
Grundig CUC7301 Dead C669 1000pf dry joints & burnt; MJF18004 T665 s/c; ZD663 had 25R reverse resistance, D624/621 1N4007 mains rects s/c & UC3842AN faulty
Grundig CUC7301 Dead - Chopper T665 blown plus - IC630, D633 3v6 zener, D662 BA157, bridge rects D621-4 1N4007, R661 220R, R663 18R, 3 x sm diodes under psu sect, dry joints C669
Grundig CUC7301 Dead - lop tr s/c & replacement ran hot CT169 BC858B buffer sm leaky
Grundig CUC7301 Dead - R542 10k or 13k o/c When replaced overheated again - crack in print by lopt
Grundig CUC7301 Low sound & no set up menu In hotel mode - to exit - hold down "i" button at sw on
Grundig CUC7301 low sound -stuck in hotel mode hold 'i' button whilst switching tv on. Use rc arrows to select hotel mode then off
Grundig CUC7301 off chopper tr s/c c-b T665 MJE18004C, D664, 666 1N4003, CD654,CD656 LS4148, IC630 UC3842A, D663 6.3v zener, R661 220R replaced & dry joint C669
Grundig CUC7301 off with a bang C669 1000pf had dry joints causing burn up of pcb. Following parts replaced :- 2.5A fuse, IC638 uC3842AN, T665 chopper tr MJF18004C, D662 BA157 s/c, D663 ZPD3.6 3.6v zener s/c, R663 18R, R661 220R hi res, R669 5w
Grundig CUC7301 Pic pulled across to right CT169 BC858B sm leaky
Grundig CUC7301 Poor regulation of psu sm diodes cd 654 and cd656 leaky. They are type
LS4148 but standard 1N4148 ,s work ok.
Grundig CUC7301 Reduced width and line tearing when TV gets hot. Replace surface mount transistor CT169 BC858B
Grundig CUC7301 St/by only C667 100µ 35v.
Grundig CUC7301 Tripping with front led flashing No HT on dummy load - HT preset R654 470R o/c
Grundig CUC7301 Dead aft few mins - line drive lost Buffer CT169 BC858B sm tr faulty.
Grundig CUC7303 Dead - PSU blown Chopper tfmr, S2055 LOPTr & FOP chip
Grundig CUC7303 off burning smell bad joints mains sw
Grundig CUC7303 Won't go fully into st/by - crt heaters stay lit etc Pin 1 IC676 should drop to 1.2v in st/by - was staying at 10.7v. BC848 sm tr downstream from pin 1 was faulty though checked ok.