PANASONIC TX-25W3C CHASSIS EURO-1 INTERNAL VIEW.

The Panasonic EURO-1 Is the first PANASONIC TV CHASSIS entirely Digital Technology.

IT Is completely based on the ITT DIGIVISION DIGIT2000 Chipset technology but furtherer improved by ITT adding more improvement functions in the original DIGIT2000.


For a complete technology reference of the Digivision ITT DIGIT2000 you can Read HERE

Indeed there are newly named IC's such as:

- VDU2146 Video Display Unit.

- DTI2223 Digital Transient Improvement

- ACVP2205 Adaptive Combifilter Video Processing

- MCU2600 Main Clock Unit

- SPU2243 Secam Processing Unit

- DPU2553 Deflection Processor Unit

- SAD2140 Signal Analog to Digital Conversion

- TPU2735 Teletext Processor Unit

- CCU3000 Computer control Unit

- MN8333 Digital feature Unit (Panasonic)

- ACP2371 Audio Control Processing

Construction
The chassis EURO-1 construction (see Fig. ) is much simplified in comparison with the Alph 3 chassis used in the W2 series models. Basically the Euro 1 chassis consists of a main analogue mother board and a plug-in digital pack. A few smaller boards are used for the front panel controls, sockets and of course the c.r.t. base. The main board (E -PCB) contains the power supply, the field and line output stages, the audio amplifiers, the tuner and the i.f. module. All processing between the i.f. module and the output stages is carried out in the digital pack, board A -PCB, which is mounted in a metal screening can. It contains the signal switching, Nicam, video and audio processing, sync and timebase generator/driver sections. The AV switches and rear panel sockets are also on this panel. The majority of the chips it uses are from the ITT Digit 2000 series and are surface mounted. Continental variants of the chassis use basically the same boards but may omit the Nicam chip or add a Secam processor. They may also have a different i.f. module. With satellite and picture -in -picture equipped models an extra panel B -PCB is fitted inside the same shield case as panel A -PCB. The first thing one notices when the back cover is removed is the reduced number of interconnecting cables in comparison with previous Panasonic models. As with its predecessors, the Euro 1 chassis is put in the service position by hooking it on to clips near the back of the left speaker enclosure. This provides easy access to the conventional analogue circuits on panel E -PCB. To work on the digital pack the shielding case has to be removed. The A -PCB can then be probed from the top side. Extension cables are required to operate the set with improved access to the rear of the A -PCB. They are available as part of a service kit. Also available is a surface -mount repair kit which contains various cutting and removal tools plus a gas soldering iron with special surface -mount soldering tips.

Service Modes As an aid to servicing, the Euro 1 chassis has several service modes that can be entered only by the service engi- neer. They are all protected against accidental customer operation because a combination of keys has to be depressed. For example to enter the basic service mode 1, which is used to adjust the scan sizes, picture geometry, colour reference oscillator, colour temperature etc., you first adjust the audio controls on the set simultaneously for maximum bass and minimum treble then depress the remote control text reset button whilst at the same time depressing the volume down button on the set. Service mode I then appears and each function can be selected by using the remote control unit's red and green flof keys. Updown adjustment of the settings is done by using the yellow and cyan keys. The new setting must then be stored by using the tuning store button 's' on the TV set, otherwise moving on to the next item will result in the new value automatically reverting to the old one. The service manual shows typical normal values, but these will vary slightly from set to set depending on screen size and the tolerances of the analogue components. The first service mode 1 option enables all the preset program positions to be memorised in an external memory pack or, conversely, to be loaded: the memory pack must be plugged into the AV2 connector before the set is switched on and the service mode is entered. This is useful when a dealer has to tune large numbers of sets to the same channels - one set's presets can be learnt and transferred to all the others. There's a similar function in service mode 2, enabling a set's adjustment settings to be stored or copied. All the other adjustments in mode I can then be stepped through and adjusted if necessary. Service mode 2 is entered from the last option of service mode 1 by pressing the text hold button. In this mode option bytes that define the set's characteristics appear, hardware permitting. These are best left alone, otherwise the software may be led to believe things that the hardware doesn't! Leaving the service modes resets the receiver's customer presets to their last stored condition - including the bass and treble settings. Note that the surest way to hard reset the receiver is to turn off at the mains switch. Other service modes enable basic fault diagnosis to be carried out, even with a dead set, by flashing the standby LED at different speeds. It's thus possible, by using different remote control keys, to find out on which internal bus a fault is present. When the remote control unit's off -timer button is pressed at the same time as the set's volume down button, another self -check mode shows numerical values on screen for the main components. They can then be checked against the values specified in the service manual. After leaving this mode the user presets are all reset to the factory positions. Finally, fixed -mode operation forces the receiver into the PAL, NTSC or modified NTSC mode. This requires the use of the service remote control unit which has one extra button compared to the standard unit. Apart from these adjustments via the service modes the only adjustments available in the set are focus, c.r.t. cut-off and screen (first anode voltage) - the latter two are used in conjunction with service mode 1.

 Repairs The main E -PCB panel is of conventional construction, using leaded components. Most of the semiconductor devices are fitted to heatsinks with snap -on retaining clips that are easy to remove. Replacement of semiconductor devices should rarely be necessary however as the set is protected by over -voltage and excess -current circuits in the primary side of the power supply and fuses in the secondary side. Some of the more important supply lines, such as the 5V supply for the digital circuitry, have series -regulator circuits that use a field-effect transistor as the series element. The reason for this is the low voltage drop across the device. Thus in the worst possible case, an internal short between the input and output of the series element, the output voltage increase can be only small. This is important if you think of all the digital chips that are powered by the 5V supply: a voltage rise to 6V is not as catastrophic as a rise to say 12V, which could happen if a conventional regulator shorted internally. The a.c. mains input glass fuse is on panel P -PCB along with the mains switch and the mains filter. The four internal supply line fuses are positioned near the centre of panel E - PCB. They are of the black, vertical Siemens type. The idea of fault-finding on digital panel A -PCB, where the signal processing takes place, may worry some service engineers. By using the service modes described above and referring to the service manual it should however be relatively easy to isolate the bus on which the fault is present and thus the suspect chip. The recommended process is then to cut the chip's legs with a scalpel, remove the body and desolder the pins from the PCB. Most of the passive components on this panel are of the surface -mounted type, as are many of the components in the vision i.f. pack and on the c.r.t. base panel.

In the past digital TV chassis have been notoriously unreliable, have performed poorly and been difficult to service. Time alone will judge the reliability of this chassis. But if performance and serviceability are anything to go by we should have few problems. Now we will look at the circuitry used in the chassis.



Power Supply Circuitry
Previous Panasonic chassis used either the Sanken STR54041 chopper control chip or else employed discrete component circuitry.
The Euro 1 chassis however is of European design. This is reflected in the choice of the Siemens TDA4601 chopper control chip. The power supply circuit is similar to that used in many other models by various manufacturers, being of the self -oscillating flyback converter type. As some features are not always understood too thoroughly, we'll run over the operation of the circuit. Fig. 1 shows the non -mains isolated side of the power supply, excluding the mains switch, the fuse, the line filter and the degaussing circuit components. Chopper trans- former T639 has three primary windings, P1-2 being the main power winding, Fl the winding that provides a feed so that the supply is self -powering, and F2 the feedback control winding. P1 is connected to the output from the mains bridge rectifier and P2 to the collector of the chopper transistor Q624, regulation being achieved by controlling the width of the drive pulses applied to its base. The pulse width is determined by the chip which samples, at pin 3, rectified pulses fed back from winding F2. At switch on a start-up voltage is applied to pin 9 of IC611 via R621 and R622. It's used to provide, internally, a 4V reference voltage at pin 1.

When the voltage at pin 9 reaches 12V, the reference voltage appears and the circuit starts up. Once the circuit is oscillating, a 20V supply becomes available from winding Fl and the associated rectifier circuit consisting of D622 and C622: this takes over the supply to IC611. The timing of the very first drive pulse to Q624 must be calculated by IC611. This is done by measuring the collector current via the network connected to pin 4. The second and subsequent drive pulses are timed by detecting the zero crossover of the feedback pulses from F2 at pin 2 of IC611. In normal operation the circuit oscillates at frequencies between 20kHz and 35kHz depending on the load conditions and the input supply voltage. In these circumstances the conduction period of the chopper transistor remains at an almost constant 33 per cent of the drive waveform's duty cycle. In the standby mode, when the power consumption is reduced to several watts, the oscillation frequency can increase to 70kHz with the conduction period of Q624 falling to less than ten per cent.

Overload protection is provided by monitoring the voltage at pin 9 of IC611. Under heavy load conditions the voltage, also that at pin 5, falls. IC611 will then cut off its chopper transistor base drive amplifier, thus stopping Q624. The circuit will next try to start up again, as described above. An additional overload protector and a standby monitor function are connected to pin 3, where feedback pulses from F2 provide a control voltage after rectification by D636 and C634. By using this voltage in conjunction with the collector current sensing at pin 4, the chip can limit its output drive. P633 enables the sensitivity to be adjusted so that the output voltages can be set up. The mains -isolated side of the chopper transformer provides several separate supplies:

Fig. 2 shows the circuitry used here. These supplies are the main 155V line, fused 5V, 12V and 27V supplies, a fused 5V standby supply and split +20V and -20V supplies for the audio amplifiers. In the standby mode the main 5V and I 2V supplies are shut down by removing the gate drive to the field-effect transistors Q663 and Q674. This is done by applying a positive voltage, which comes from the CCU (central control unit) processor chip on the digital board, to the base of Q697. Switching off the 155V h.t. and 27V line driver stage supplies is not necessary because, in this mode, the CCU prevents line drive. Thus only the 5V standby supply is active, powering the infra -red remote control receiver, the CCU (microcontroller) chip and the start-up circuit for the deflection processor chip. When the CCU brings the set out of standby, the main 5V and 12V supplies are reinstated and line drive is enabled. As the 5V line rises, the line output stage is soft -started.

As mentioned , field-effect transistors are used to stabilise the main 5V and 12V supplies - because of their large current capacity and low source -drain voltage. 
They are used in conjunction with normal TL431 regulator chips to provide the control action, the f.e.t.s being used as series elements to boost the current and provide standby switching. One per cent tolerance resistors are used to set the exact reference levels for both the TL431 devices (IC666 and IC676). The split supplies for the audio amplifiers are not regu- lated. They are obtained from a half -wave rectifier arrangement. At first sight the circuit looks strange because the two half -wave rectifier circuits are effectively in parallel. The reason for using this arrangement is to reduce the power consumption in the standby mode. In normal operation Q682 is switched on, its base being at a negative voltage with respect to its emitter. It thus supplies current to the audio circuits. In the standby mode the current demand from the audio circuits is reduced. Because of this, current is shunted via R681/2/3. Q681 's base voltage moves negatively with respect to its emitter and it switches on. Q682 is thus switched off, because Q681 shorts its base and emitter.

The net result is a reduction in the supply to the audio chips. Audio muting will be described later. Because of the power supply design, all the secondary voltages are present even when the set is in the standby mode. It's advisable, before repairing the unit, to disconnect the mains supply and carefully discharge the mains bridge rectifier's reservoir capacitor C618. As an aid to fault location in a dead set, the power supply can be isolated by removing the h.t. rectifier diode D651, the 27V supply rectifier diode D656 and the 5V and 12V supply rectifier diodes D671 and D661. The hi supply line can then be loaded using a 60W bulb. You can isolate the line output stage simply by omitting the connection to the DPU (deflection processor unit) chip. When using the extension lead kit this is easily done by omitting the lead that connects W1451 on the digital pack to W51 1 on the main PCB.

Line Scanning
 Fig. 3 shows in simplified form the line driver, output and EW correction circuitry. The arrangements are similar to those used in other sets, so only a few points will be made. Line drive pulses from the DPU chip are applied to the base of the line driver transistor Q526 which provides the necessary current to operate the line driver transformer T528. This has a winding ratio of seven to one. With no 27V supply there is of course no drive to the line output transistor Q534, which has a low -impedance base circuit to ensure rapid switching. Note that the line output and chopper transistors are of the same type, S2000AF, with an internal diode (not shown). D536 and D537 are the EW modulator diodes. The EW correction circuit is driven by a field -frequency waveform that's derived from the DPU's field output section. It arrives at R583 and is then buffered and amplified by the d.c. coupled circuitry shown.



Field Scanning 
 The TDA8I75 chip IC561 drives the field scan coils. This chip is basically a power amplifier with a built-in flyback generator to virtually double the available supply voltage. D561 and C563 form part of this arrangement. The circuitry here is again conventional (see Fig. 4). The input from the DPU is a pulse waveform that's integrated by R566 and C567. There are two separate protection circuits here. To avoid the possibility of c.r.t. screen burn because of loss of field drive, a sample of the pulse waveform present at pin 3 of 10561 is fed back to the DPU. If the pulses are missing, the DPU generates a continuous blanking signal that cuts off the RGB outputs from the VDU (video display unit) chip. Beam current is thus minimised. The second circuit provides protection in the event of the field output coupling capacitor C574 going short-circuit - otherwise the supply to the field output circuit would directly heat the scan coils! Zener diode D567 monitors the field drive. If C574 becomes short-circuit the voltage applied to D567 will fall: this voltage change is fed back to pin 43 of the CCU chip IC1801 (see Fig. 6) which will then initiate the shut -down mode. Other faults will result in the CCU chip shutting the set down with a characteristic five second flash of the standby LED as the system tries to restart. These will be covered in a later writeup.


 







RGB Output Circuitry
 The RGB output stages are mounted on the c.r.t. base board. They are more complex than those used in previous Panasonic chassis and thus call for some explanation. Fig. 5 shows the blue output stage and the spot -suppression circuit which is common to all three channels. The RGB drives from the VDU chip come via the scanvelocity modulation board. Each RGB channel has four transistors. In the B channel shown the first transistor Q3371 is an emitter -follower which provides a low - impedance, d.c. drive at the base of the class A amplifier Q3373. This provides the required voltage gain.
For optimum h.f. response a low -impedance output is essential to rapidly charge/discharge the load capacitance present. On a positive -going voltage transition at the collector of Q3373, Q3374 switches on to provide, by emitter -follower action, a low -impedance charging path via D3377. With a negative - going transition D3377 is cut off and Q3377, again acting as an emitter -follower, provides a low -impedance discharge path. D3374 and Q3373 ensure that Q3377's base current is rapidly dissipated so that the process can be repeated. Q3377 serves a second purpose, as part of the automatic grey -scale adjustment system. Its collector is earthed via R3379 and the ACVP (active comb filter and video processor) chip on the digital board. During the course of the field blanking (flyback) period the transistor (and its equivalents in the red and green channels, Q3397 and Q3387 respectively) is used to sample the black and peak - white levels.

 There is also a c.r.t. leakage measurement. This is done over a four -field cycle as follows: Field one: c.r.t. leakage. Field two: black and peak -white levels, red channel. Field three: black and peak -white levels, green channel. Field four: black and peak -white levels, blue channel.

 Transistors Q3377/87/97 are connected to the ACVP chip via connector W191 on the scan -velocity modulation board. During the leakage check there is no drive to Q3377/87/97 and whatever current flows is measured.
During the next three fields Q3377/87/97 are switched on in turn to check the black and peak -white currents. The measurements are made by the ACVP chip, which commu- nicates the results to the CCU chip.

This compares them with values stored in the associated memory chip. If any differences are detected, the RGB drives are automatically adjusted to compensate. This is useful during the tube's warm-up period, when uneven emission could cause a colour tint. It is also useful over the long term, enabling the grey -scale tracking to be maintained as the tube ages. It also means that all colour temperature and white -balance adjustments can be carried out via the software during service mode one. Despite the fact that c.r.t. cut-off automatically tracks the setting of the screen (first anode) control P3362, it may be necessary to carry out realignment when a new tube is fitted. To do so the set is put into service mode 1, as described in the previous article, and the 'screen' option is selected. P3362 should then be turned to minimum: use a non-conductive trimmer, as a metal screwdriver can bridge the potentiometer's spark gap rather nicely!
The set will now display numeric values for the red, green and blue channels. Select the channel with the highest value and connect a high -impedance scope probe directly to the relevant cathode. With the scope set to the field frequency, the blanking interval test signal can be seen as a pair of steps. Adjust the cut-off control P3368 (see Fig. 5) so that the voltage from the top step to earth is 150V. Remove the scope connection and increase the setting of the screen control P3362 until the highest channel numeric display reads approximately 40. Alignment is now complete. This set-up procedure is one of the few physical alignments possible with the set.

You can adopt the timehonoured method of using a high -impedance voltmeter to set the cut-off (at approximately 180V) but this is not so accurate. Factory software settings for the RGB low- and high -light levels don't need to be adjusted when a new tube has been fitted as the automatic grey -scale tracking will ensure that the tube operates correctly.

Spot Suppression
The possibility of spot bum at switch on and switch off is prevented by the components around transistor Q3357 and in the cut-off circuit. At swatch on C3353 charges slowly via R3352. Thus a voltage appears at the anode of D3353 which conducts. Q3359 switches on and Q3368 switches off. The full 12V is therefore applied to the emitter of Q3373 and the equivalent transistors in the red and green channels, and all three are cut off. When C3353 has fully charged the voltage at the anode of D3353 falls and the circuit reverts to normal operation. At switch off the voltage on the 12V line falls. As C3358 has been charged to 12V, the voltage at the base of Q3357 falls below that at its emitter and it conducts, switching Q3359 on and Q3368 off. The action at this point is the same as during the switch -on spot suppression period and lasts until C3369 has discharged via R3359.

Beam Limiting
 Beam limiting is carried out within the VDU chip, deter- mined by the voltage at pins 7 and 8, see Fig. 6. This voltage is derived from a sampled line flyback pulse, which is processed by transistor Q1642 and the associated circuitry. With excessive beam current the pulses at the base of QI642 become negative and it can no longer charge C1648. If the voltage at pins 7/8 of the VDU chip falls below a 4V threshold, contrast limiting is initiated. If the voltage falls below 3V brightness limiting is also applied. At OV the beam current is reduced to zero.




 



The Audio Amplifiers
A pair of TDA2030A chips provide the audio outputs. They are powered by split supplies, as we have seen. The audio signals from the ACP (audio control processor) chip are buffered on the digital board and are fed to the non -inverting chip inputs. Fig. 7 shows the left-hand audio circuit. It's of conventional design, with the protection diodes D477 and D478 clamping the supply lines to the output. Audio - frequency roll -off is set by the RC networks in the feedback and non -inverting input circuits. A Zobell network (C479, R479) at the output helps to prevent any instability. In addition to audio signal muting within the ACP chip during the channel change and search operations, switch -on muting is provided by Q498 and the equivalent transistor in the right channel. These transistors are controlled by the CCU chip. When switched on, they short the audio inputs to chassis.

Tuner and IF
Four different tuner and i.f. pack types are used in the chassis, depending on the country in which the receiver is to be sold. The UK version has a u.h.f. only tuner from Ecom, covering 471-25-847.25MHz. Continental versions equipped to receive v.h.f. and cable channels as well usually have a Philips or Telefunken tuner - one other version featuring D2 -MAC reception uses a combination tuner/i.f. pack of Loewe manufacture. We'll concentrate on the UK version except where the differences make circuit explana- tion easier. The tuner and i.f. modules are both mounted on the main, analogue circuit board (PCB E). The tuner is an I2C-bus controlled type whose output is fed to the i.f. module via the E PCB. Fig. 1 shows the arrangement in simplified form. The tuner's unbalanced i.f. output passes first to a dual SAW filter, X4704, which supplies separate, filtered outputs to the vision and sound i.f./demodulator chips, IC700 and IC800 respectively. IC700, type TDA3853T, contains all the circuitry required to provide a composite, analogue video output. It also provides an a.g.c. output for the tuner. IC800, type TDA3857, is a complete quasi -split sound demodulator that provides an f.m. audio plus Nicam carrier output which is passed to the digital board for decoding. There is no need to go into the operation of the i.f. section in detail as it follows conventional analogue practice, the differences starting once the signals have left this module. IC502 is not used in UK sets. The next point to consider is the analogue signal routeing through the AV switching system.

Signal Routeing
When the composite video signal from the i.f. module arrives at the digital board it enters the video/luminance switching chip ICI 101, see Fig. 2. This is a TEA6415 cross- point switch which has eight inputs (only five are used in UK sets), five fixed outputs and one variable output. Apart from the video from the i.f. module there are four AV inputs. As the device is connected to an I2C bus, the Central Control Unit (CCU) can control which video (or lumi- nance) signal is passed to the digital circuits for processing, also which signal goes out via AV1 or AV2. A similar chip, IC1106, takes care of chroma switching with S -VHS signals. A third switching chip, IC1021, is used for the audio signals. This is a TEA6420 which is slightly different, being a dual, five -input, four -output cross -point switch. The point to remember here is that the audio from the tuner doesn't come straight from the i.f. module: it's digitally processed before it reaches this switch, whereas the video signal is processed after it leaves the switch. This is done so that AV signals routed through the scan and S -video sockets are not processed unnecessarily. The chroma and audio switching circuits are similar to the video/luminance switch shown in Fig. 2. Before we go on to the video processing we should consider some of the CCU's functions: this is the device that manages the complete system.

The CCU and the Buses
The CCU3000 chip, to quote its device type number, is a custom -designed microcontroller chip from ITT-Intermetall. Its core is the familiar 6502 8 -bit microprocessor. Internal features include three timers, two IM bus interfaces, four input/output control ports and a 16 -bit memory address bus. A 4MHz clock is used, controlled by crystal X1853. This clock also synchronises the deflection processor. A simple reset circuit, consisting of a CR network, is connected to pin 6 - a separate reset circuit based on Q1963 and Q1967, which are connected to the 5V and 12V lines, is used to reset most of the other digital chips at power up. The CCU chip controls the set's operations via three data buses, see Fig. 3. These are arranged as two I2C buses (two lines each, data and clock) and one IM bus (three lines, data, identify and clock). A second IM bus is used in D2 -MAC - and PIP -equipped sets. The first I2C bus is used for tuner and i.f. control. It's connected to IC1941, an EEPROM chip that holds the tuning data and preset values stored in service modes 1 and 2. It's here that the CCU looks first at switch on. Thus a faulty or missing EEPROM chip will effectively disable the set. The second I2C bus is connected to the cross -point switches mentioned above and to pins 10 and 12 of scart socket AV2. This bus is used for reading from and storing in the memory module during service modes 1 and 2. Satellite - equipped sets also tag on to it. The IM bus runs around all the digital processing chips, some of which have already been mentioned. Table 1 provides a complete list of their names and functions. The Main Clock Unit (MCU) and Video Display Unit (VDU) chips are not connected to the IM bus: they receive modified control signals via the ACVP chip. Continental variants of the chassis may also include a Secam Processor Unit (SPU). In addition to the EEPROM there's a 1Mbit EPROM (IC1871) for system software and a 256Kbyte dynamic RAM (IC1786) that's used as the teletext memory. One of the most important functions of the CCU is to protect the major components in the set in the event of a fault condition. Field collapse or excessive beam current are, as mentioned in Part 1, sensed at the protection circuit input pin 43 of the CCU. If a fault is detected by the CCU it shuts the set down then attempts a restart five seconds later. If the fault persists, the standby LED will flash at five second intervals but there will be no further attempt to restart. Remember that any fault which results in loss of scan will produce this symptom. Failure of the main 5V line fuse for example will result in the deflection processor being inoperative. Hence no scan (amongst other things), so the CCU shuts the set down. Another major function of the CCU is to carry out remote control commands. So that it can operate at all times, during standby and power rail failures, the CCU, unlike the other digital chips, is powered by the 5V standby supply. Remote control commands are received by a preamplifier (U6301) at the front of the set on the M PCB, which is fitted inside the on -board control drawer. Signals from this are fed to the digital module via connector W1833. They then pass via an amplifier transistor, Q1839, to pin 60 of the CCU chip. The signal at this pin should be at 5V peak -to -peak - it's only IV peak -to -peak at the output from U6301. There are no remote control receiver adjustments. The on -board keys and standby LED in the control drawer are connected to one of the CCU chip's control ports via the same connector, W1833. On/standby control signals are produced at pin 62 of the CCU chip. They control the operation of the power supply by switching Q1723 on the digital PCB then Q697 in the power supply (see Fig. 2 ABOVE). As an aid to fault- finding, the set can be forced on via Q1723. Fig. 4 shows the CCU chip's main elements and Table 2 the pin connections. Now that we have outlined how the signals are controlled we can start to look at the digital processing.

Table 1: The ITT  digital circuitry chips.
Position/type
 Name and function
IC1801 CCU3000
IC1301 ACP2371
IC1401 MSP2410
IC1431 AMU2481
IC1501 DPU2553
IC1601 SAD2140
IC1631 ACVP2205
IC1651 MCU2600
IC1661 DTI2223
IC1671 VDU2146
IC1761 MN8333
IC1771 TPU2735
CCU - Central Control Unit
ACP - Audio Control Processor
MSP - Multi Sound Processor
AMU -Audio Multiplexer Unit
DPU - Deflection Processor
Unit
SAD - S-VHS/composite video
ADC
ACVP - Comb filter and video
processor
MCU - Master Clock Unit
DTI - Digital Transient
Improvement
VDU - Video Display Unit
DFU - Digital Features Unit
TPU - Teletext Processor Unit

The Video Signal
After leaving the video source switching the composite video or separate S -VHS luminance and chroma signals, depending on source, enter the SAD chip 1C1601 (see Fig. 5). To maintain synchronisation, the video chips are all clocked by the MCU chip. This uses two reference crystals, a 17.7MHz one for PAL and a 14.3MHz one for NTSC. A D2 -MAC -equipped set must in addition have a 20.25MHz crystal. These frequencies are approximate multiples of the PAL and NTSC colour subcarrier frequencies. 17.7MHz is not an exact multiple of 4.43MHz. This is deliberate. The difference is small enough to lock to a 4.43MHz signal, but in the absence of such a signal, for example at first switch on, the derived frequency results in a reduced line frequency and thus slight overscan. The same applies with the 14.3MHz crystal. During normal PAL reception the burst received from the ACVP chip locks the MCU to 17.72MHz (4 x 4.43MHz). Likewise an NTSC AV signal locks the system to 14.32MHz. When the colour killer is in operation and no burst is received the system free -runs at 17.7MHz. This also occurs with Secam reception. The SAD chip converts the analogue composite video or separate luminance and chroma signals to 8 -bit digital signals. To reduce the effect of bit errors the signals are Grey rather than binary coded. These signals are then time - multiplexed together so that only eight bus lines are required. The relationship between the clock and the digi- tised, multiplexed YC signal is illustrated in Fig. 5. This 8 - bit bus leads to the ACVP chip, where to start with the signal is converted back to binary form and demultiplexed. The bus also provides feeds to the teletext and deflection processor chips (TPU and DPU) which we'll return to later. The ACVP chip then filters the Y and C signals, using either a bandpass/stop filtering system or a three -line comb filter depending on the video content. Delay and level adjustment are then applied to the luminance signal while the chroma signal is decoded to produce the two colour - difference signals (U and V). Before these leave the chip they are multiplexed together so that a 4 -bit bus can be used. At this point the automatic grey -scale control signals (black and peak white plus c.r.t. leakage) generated during the field blanking interval are added. Because of a certain 'bottlenecking' of information, there's a delay of a few seconds between adjustment of the RGB cut-off points in service mode 1 and the actual colour changes seen in the display. The use of this 4 -bit bus saves on panel space and chip pins without compromising on the quality of the colour -difference signals. The Secam processor in Continental models is fitted in parallel with the ACVP chip, processing the Secam chroma separately for reinsertion after the ACVP. After leaving the ACVP chip the digital luminance and chrominance signals enter the DTI chip, see Fig. 6. As Digital Transient Improvement is also built into the DFU (Digital Features Unit) chip, the DTI chip is used simply as a delay line to compensate for the processing delays in the DFU. It has one other main purpose: the nibble demultiplexer converts the 4 -bit colour -difference signals back to 8 - bit form. Next comes the DFU chip, which carries out the picture processing functions LTI (Luminance Transient improvement), CTI (Chroma Transient Improvement) and Scene Control (or 'artificial intelligence'). Unfortunately little information is available on this Matsushita chip. We can assume however that the LTI function is conventional in that the luminance signal is sharpened by being delayed during level changes, from black to white for example. This has the effect of crispening the transients without recourse to peaking circuits. Adjustment of the picture sharpness control varies the symmetry of the luminance transient improvement, thereby altering the visual effect obtained. Colour transient improvement is carried out by processing the chroma signal and delaying the luminance signal to match. Scene control on the other hand works by numerical analysis of the luminance signal, as described in my introductory article on the chassis in the July issue (see page 654). Black -level expansion, where necessary, and gamma correction are then applied, the output being passed to the VDU (Video Display Unit) chip. This chip is the final device in the chain, being the one that converts the signals back to analogue form so that the tube can be driven. It also controls the beam current and carries out conventional RGB matrixing. In addition to the digital video signal inputs this chip receives RGB plus blanking signals from the text processor chip, and the external RGB inputs. We'll return to these next time. Because the VDU chip isn't connected to the CCU's IM bus, it's controlled via the ACVP chip. This is done by storing the IM bus commands in a buffer and then transfer- ring them, during the field blanking period, to the VDU chip via two of the digital chroma signal lines.

CHASSIS EURO-1  Possible Problems
Finally this time a few comments about the video processing system and some possible problems. For analogue -to -digital conversion to be carried out correctly by the SAD chip its video input signal must be clamped at the correct levels. The chip has only a 2V window for signal slicing, so 5V line -frequency clamp pulses are fed in at pin 35. This ensures that the video signal at the input pin 13 sits between 5V and 7V. If the clamp pulses aren't present the video d.c. level will increase and the result will be a grey or white picture. Missing video data signals can cause a resolution loss that's best described as `pixelisation' of the image. Take for example the 8 -bit video bus link between the SAD and ACVP chips. Loss of the least significant bit (VO, SAD pin 32) may not be noticeable, as the resolution reduction is small. Loss of the next least significant bit (VI, SAD pin 33) would be noticeable as pixelisation. At the other end of the scale loss of the most significant bit (V7, SAD pin 40) would result in loss of the picture as the sync pulses would disappear. The ACVP chip requires, at pin 1, a burst gating signal from the DPU chip. If this is missing the colour is lost and the contrast is reduced. Pin 19 is a voltage reference input. No voltage here means that the picture will slowly darken, as the grey -scale level drifts. If the luminance signal is lost within the ACVP chip the screen image looks as if `solarisation' effects have been added.

Teletext
The text decoder is based on the ITT-Intermetall TPU2735 teletext processor chip. Apart from peripheral components all that it requires in addition is a RAM chip. It provides full level -one functions (FLOF) plus TOP text, the alternative text magazine structure used by some German broadcasters. As its internal ROM contains a full Conti- nental character set, the correct text can be displayed with all European satellite transmissions. With D2 -MAC equipped models the chip can also decode MAC vertical blanking interval type text such as that transmitted by The teletext processor chip (TPU) operates in the same way as a conventional text processor but expects a digital video input. An advantage is that this digital input allows it to provide ghost cancellation, which can improve text reception when short-term multipath signals with a delay of up to 0-8p.sec are present. Other internal features include a small dynamic RAM buffer for the external memory, and RGB switching between the text and any external RGB signals entering via the AV1 scart connector. These 'external' signals can include picture -in -picture information in a suit - ably -equipped receiver. The TPU chip's character generator section also provides the many on -screen display messages available - in up to six languages. Conventional page memory is provided by an MN41256 DRAM, which is arranged as 32K by 8 bits. This is enough to store sixteen pages of text though there will be a reduc- tion, depending on the text mode, because of the FLOF index and TOP table. Fig. 1 shows a block diagram of the text system.

Audio Processing
The Audio Control Processor (ACP), the Multi Sound Processor (MSP), the Audio Multiplex Unit (AMU) and a few peripheral components, including an 18.432MHz audio clock crystal, take care of the audio processing. Fig. 2 shows the arrangement. Models that can receive only basic f.m. sound and the German Zwietone signals use just the ACP chip: for Nicam reception the MSP and AMU chips have to be added. The ACP chip processes all the audio signals - analogue f.m., external via the AV inputs, digital Nicam and D2 - MAC. It has inputs for the demodulated mono f.m. carrier, stereo or second -language f.m., Secam a.m. and D2 -MAC sound. When unused, these inputs are connected to chassis via capacitors. Any audio option can thus be selected. With sets intended for sale in the UK the demodulated f.m. inputs are not used, since there are no analogue multisound services. Instead, the f.m. signal is processed with the Nicam signal in the MSP and AMU chips, reducing the number of filters required. When the audio section in a Continental model receives demodulated f.m. and Zwietone signals each input is gain - adjusted to avoid distortion, then de-emphasised and dematrixed as necessary. The left- and right -channel signals are digitised by two pulse -width modulators, producing two single -bit data streams. A third pulse -width modulator is included for digitising the pilot tone with Zwietone transmissions. At this point in the chain any digital Nicam signals from the AMU chip appear on the digital sound bus (the S -bus). Information on which analogue and digital audio options are available is sent to the CCU chip via the IM bus: the CCU then enables selection of mono f.m., Nicam, etc. as required. The ACP chip carries out this input selection then digitises the signal which is passed to the chip's audio control block for balance, tone and ambience adjustment. Ambience effects are achieved by using frequency -selective filtering for each channel then phase -shifting and feeding the result back to the opposite channel. The final sections of the ACP chip provide volume control and then DA conversion, after which the signals leave the chip to head for the audio amplifiers. The Nicam signal is decoded and sorted out inside the MSP and AMU chips. All UK receivers are fitted with these two i.c.s. The Nicam and f.m. sound signals from the i.f. strip arrive at pin 41 of the MSP chip via a simple CR filter network. Internal functional blocks within this device include a 17.7MHz Nicam clock, AD conversion for the f.m. signal, a quadrature mixer and a Nicam decoder. The audio output from this chip, in the form of 64 -bit data sequences, is passed to the AMU chip via the S -bus. This bus has three lines, for separate data, clock and ident signals. The AMU chip is used to provide further de - emphasis and filtering for the Nicam signal, which leaves via another section of S -bus to pass to the ACP chip for selection as required.


Scan Processing
The Deflection Processor Unit (DPU) chip is responsible for generating and processing the scan signals: it contains line, field and EW parabola generators and protection circuits, and requires very few peripheral components. Its IM bus interface with the CCU chip enables software adjustments of the scan parameters to be carried out in Service Mode 1. Fig. 3 shows a simplified block diagram.
The digital video signal from the video analogue -to - digital converter chip (SAD, see Fig. 5 ABOVE) is fed to pins 32-38 of the DPU chip. Though the SAD chip provides an 8 -bit video output, only seven bits are fed to the DPU chip, the least significant bit (VO) being ignored. The DPU chip low-pass filters the video input then passes it to independent line and field sync separators. This parallel processing results in excellent sync performance - I've found for example that the receivers lock perfectly to scrambled satellite TV signals or poorly amplified signals too. There's also a composite sync input, at pin 29, for use with MAC signals - pre-processing is required in this case because the DPU chip cannot decode digital packet sync. Since UK sets are not equipped for MAC reception this pin is simply linked to chassis via a small capacitor. An internal counter that calculates the number of fields from the received line frequency provides field synchronisa- tion. During normal 'coupled' operation this is fixed at 50 or 60Hz. 'Uncoupled' operation occurs when the received sync signals are weak. In this mode a range of operation is allowed: with a PAL signal it's 45-55Hz while with an NTSC signal it's 54-66Hz. The same range is used for VCR operation, where the signal is strong but of unstable frequency: in this mode the trigger window is narrower. The DPU chip determines the appropriate mode of operation and constantly monitors it. The sync signals are then used to generate line and field waveforms. An internal high-speed processor also produces an EW parabolic waveform. The field and EW signals leave the DPU chip in the form of pulse -width modulation, being integrated by the external circuits described in Part 1. When the set is first powered no external sync signals are available. In this situation the DPU chip divides the 4MHz clock signal from the CCU chip to produce a line -frequency output at 15.25kHz. Since the frequency is low there's slight overscan. which is useful under warm-up conditions. Once standard sync data is read from the EEROM via the I2C bus the line frequency is raised to 15.625kHz. As soon as external signals are available the DPU chip locks to them, using the sandcastle pulses as a reference. To avoid on- screen disturbances these changes take place during the field blanking interval. The 4MHz clock is also used as a fall- back when the video source is changed from PAL to NTSC. A 15.25kHz scan is maintained during the brief period when the system clock is being switched over. Other signals generated by the DPU chip include a combined chroma burst and line blanking pulse (at pin 43) which is used by the ACVP chip for chroma switching and by this chip and the VDU chip to produce the vertical blanking interval drive pulses for black and peak -white correction. A composite field and delayed line pulse output at pin 3 is used by the VDU chip for blanking, while a line blanking pulse output is provided at pin 5 for DTI and DFU operations. A special pulse is provided at pin 21 in the full- screen text mode. It produces a small vertical shift on every other field, the effect being to merge the two fields to avoid interlace flicker. Because of this a text/mix mode is not available. though interlaced text is allowed for subtitles and newsflash displays. To operate correctly the DPU chip requires two further inputs. The first of these is a flyback pulse from the line output transformer. It's obtained from pin 1 of the trans- former. where the pulse amplitude is typically around 60V peak -to -peak. After passing through D1506 and R1506 and being clamped by D1507 the pulse amplitude at pin 4 of the DPU chip should be 5V. The second input is a flyback pulse from the field output stage (see Fig. 4 ABOVE). This is fed in at pin 6 and, as previously explained, is used to prevent excessive current in the field scan coils in the event of failure of the output coupling capacitor. Note however that the chip is only looking for the presence of a 2V d.c. signal at pin 6, so it can be made to operate if one is provided. It's common practice in TV receiver servicing to check the field output waveform provided by the sync/timebase generator or the jungle chip. As the output from the DPU chip consists of pulse -width modulation, it will be displayed as a difficult to view digital waveform. A better place to check is at the junction of C567 and R566 (see Fig. 4 ABOVE) where the signal is integrated. When any type of scan problem occurs it's worth checking the 4MHz clock pulses from the CCU chip as a first step.


Scan -velocity Modulation
An item not previously mentioned is the Scan -velocity Modulation (SVM) board. This modulates the line scan speed in accordance with the content of the video signal to improve the sharpness of black -to -white and white -to -black transitions. It's not something new, but the SVM board used in the Euro 1 chassis is significantly more complicated than that used in the Alpha 3 chassis. Fig. 4 shows a simplified circuit of the red channel and the SVM system. The RGB outputs from the VDU chip pass from the digital panel to the c.r.t. base panel (board Y) via the SVM panel (board S) - Fig. 6 in Part 2 ABOVE was incorrect in this respect. When the RGB signals arrive at the S panel they are delayed by three 100 nsec delay lines. An emitter -follower and two -stage amplifier in each channel return the signals to their initial level, after which they are fed to panel Y. The SVM circuit needs to know when luminance transi- tions occur. So a sample of the undelayed signals is fed via the 2.2pF capacitor C3101, which acts as a high-pass filter, to the emitter -follower Q3109. After amplification by Q3108/3111 the signal is a.c. coupled to Q3122 by C3122. At this point the signal consists of positive and negative pulses that coincide with black -white and white -black tran- sitions respectively. Q3126 and Q3127 form a push-pull amplifier, with Q3131 and Q3136 as the output transistors that drive positive and negative needle pulses through the SVM coil. This is positioned on the neck of the tube. During a black -white transition the positive pulse accel- erates the line scan slightly. Conversely with a white -black transition the scan is decelerated. The net processing delay in the SVM circuit is 10Onsec, which is matched by the delay added to the RGB signals.


Secam
Models sold in countries that use the Secam colour system have an additional chip in the decoder section. It's called the Secam Processor Unit (SPU) and is fitted in parallel with the ACVP chip, being brought into action only when a Secam signal is detected. Fig. 1 shows a simplified block diagram. As the SPU chip performs true Secam decoding rather than Secam-PAL conversion, the results are much better than with previous models. The SPU chip is fitted in sets sold in the French and German markets (model number suffixes F and C): the German version is also supplied to most central European countries.

MAC, PIP and Satellite
This rather wide option is fitted in special sets for the German market only, suffix CM. As well as having a dual- LNB input satellite tuner and an extra digital features panel these models have the tuner and i.f. section combined as a single unit that's made by Loewe - in fact the complete TV receiver is made on a special Panasonic production line at the Loewe factory in Kronach. Model TX28W3CM is capable of PAL B/G, D/K and I, Secam B/G, D/K and L/L', and D2MAC reception via either an aerial or cable input, with Nicam B/G and Zwietone stereo. Because of the extra digital circuits and satellite operation the chopper transformer and power supply are uprated. The software is also more complex, with more on- screen menus and service -mode functions. Because of this a 24C16 instead of a 24C08 EEROM is used.

Satellite Receiver
A Salora satellite tuner is used, fitted with two Belling - Lee type aerial connectors, one male and one female. It is assembled on a receiver module that's attached to the main chassis frame. Power supplies for the module and the LNBs are derived from a 150V feed from the main chassis. While working on one of these sets don't leave the earth lead from the satellite tuner to the main tuner disconnected - other - wise you'll be reminded when you try to connect the satel- lite dish! Fig. 2 shows a greatly simplified block diagram of the satellite receiver. All the signal processing is carried out in analogue form, the outputs being converted to digital form on the main chassis. The tuner itself is controlled by the main CCU via one of the I2C buses. Audio mode, PAL/MAC selection and the polariser are controlled by a U3082 I2C bus expander (IC800). Analogue baseband video from the tuner is amplified and then passed to two filters, one for PAL and the other for D2MAC signals. These filters are in parallel, the PAL filter being switched in by IC800 via a diode when the PAL mode is selected. The filtered signal is processed by a TDA6151 video processor chip (IC500), buffered and fed out to the digital board. The audio signals are extracted before the PAL/MAC filters and are fed to an NE612 sound i.f./demodulator chip (IC270). This device's output passes through three ceramic filters (10.7MHz/280kHz, 107MHz/180kHz and 1052MHz/180kHz) to obtain the carriers for the main mono and stereo narrow -band audio channels. Selection of these is performed by a TDA8741 audio processor/switch (IC400). Selectable J17 and 60[Isec de -emphasis is provided, but there's no Wegener Panda for Astra. When the video and audio signals reach the digital panel they enter the appropriate cross -point switches and are then digitised. This is important: it means that scrambled signals are not converted unnecessarily before they are fed to external decoders. MAC audio and video cannot be processed here: they are passed to the features board for decoding.

Stereo Sound Reception
As we saw ABOVE , the AMU and MSP chips provide Nicam signal decoding and processing. In addition to UK models they are fitted in sets supplied to the Spanish and Scandinavian markets, for Nicam B/G reception. Other Continental countries use either the Zwietone stereo/bilin- gual system (Germany and France) or have no stereo broad- cast system. Zwietone reception is catered for by the ACP chip, which is fitted to all models. Some countries, such as Denmark, can receive Nicam signals from Sweden and Zwietone signals from Germany: they are fitted with the Scandinavian version of the chassis (suffix S) which is equipped for both.

The Features Board
 The features board performs D2MAC decoding and the picture -in -picture functions. The main devices on this board and their functions are listed in Table 1. Some of these devices have already been encountered, as they are also used on the main digital panel. Others are new. A few other devices are present: a TEA5114 RGB switch, two 41464 DRAMs for the PIP processor and a third 41464 DRAM for the D2MAC decoder.

Table 1: The features board chips.
Position/type
 Name and function
IC301 AMU2481
IC731 SAD2140
IC861 VDU2146
IC771 DMA2281
IC810 MSE3000
IC791 MCU2600
IC681 PIP2250
IC631 SPU2243
IC601 VCU2133
IC641 VSP2860
AMU - Audio Multiplex Unit
SAD -S -VHF and composite DAC
VDU - Video Display Unit
DMA - D2MAC decoder
MSE - Multi -Standard Encoder
MCU - Master Clock Unit
PIP - Picture In Picture
SPU - Secam Processor Unit
VCU - Video Coder/encoder Unit
VSP - Video Sync Processor


D2MAC Decoding
Fig. 3 shows in block diagram form the D2MAC section of the features board. Baseband MAC signals from the satel- lite or main tuner are low-pass filtered then digitised in the SAD chip. The output from this is fed to the D2MAC decoder chip (DMA) for decoding and expansion in the time domain to produce digital Y, C and audio outputs (remember that MAC signals are time -division multi- plexed). A DRAM is used as a temporary store for the expansion process. The digital Y and C signals next go to a very interesting chip, the MSE, which is able to convert one digital video format to another format. It's used here to convert D2MAC into a PAL S -VHS output for connector AV3 to give improved quality MAC signal recording. The Y and C signals then pass to the DTI chip, which acts as a delay line, and finally to a VDU chip which converts them to analogue RGB signals. These are finally passed to the TEA5114 switch chip. After processing by the DMA chip the MAC digital packet audio signals are fed via the local sound bus to the AMU (audio multiplex unit) chip which converts them to another S -bus form which can be accepted by the ACP chip on the main digital panel. Note that during MAC reception the 18.432MHz MAC clock becomes the master clock on the main digital panel. MAC text is stripped off the video signal by the DMA chip and is sent to the main panel teletext processor chip (TPU).


Picture in Picture
Fig. 4 shows in block diagram form the PIP part of the features board. As the set has only one TV tuner, it's not possible to watch two channels simultaneously unless one is a satellite TV channel or the signal comes from a VCR through one of the AV inputs. When the viewer selects PIP, the required PIP video source is selected and switched via the video cross -point switching chip on themain digital panel. The signal is in analogue form of course: it's fed to the VCU chip, which incorporates a seven -bit resolution analogue -to -digital converter (this resolution is not a limitation when you consider the size of the inset picture). The digitised output goes to parallel VSP and SPU chips: this takes care of both PAL/NTSC and Secam signals. The next chip in the chain is a  DTI type that's used to compress the picture to a third of its original height. This is done by simply ignoring two out of every three video lines. The following PIP chip carries out the required horizontal reduction. It does this by writing the signals into and then reading them from external DRAMs at different speeds. The line time is in this way reduced to a third, the net result being that the PIP picture is now a ninth of its original size. To inset the PIP picture in the main picture the PIP chip generates a blanking signal that's sent via the TEA5114 i.c. to the TPU chip. The digital Y and C signals from the PIP i.c. then go back to a DA converter in the VCU chip, emerging from this i.c. as analogue RGB signals which are switched by the TEA5114 chip (shared with the MAC circuit) and are finally sent to the TPU chip for insertion into the main picture. As PIP operation uses the TPU's external RGB inputs, analogue RGB signals from connector AV 1 are routed to the PIP chip which simply passes them on to the VCU and then the TEA5114 chip. Note that after the PIP chip the luminance part of the PIP signal is limited to six -bit resolution: this is done by disregarding the least significant bit and, again, is not a serious limitation. The PIP and D2MAC functions are controlled via buses IM4 and IM5, which are not used in other models. As some of the PIP and MAC chip addresses conflict, a small switch circuit is incorporated in the bus to avoid problems.



Technology overview:ACVP2205 (Adaptive Combifilter Video Processing)
In a chroma control circuit for a digital television receiver, the system clock lies in the range of four-times the chrominance-subcarrier frequency. The originally received color-burst signal is locked in frequency and phase to the system clock by means of an all-digital phase-locked loop. The phase-difference angle between the color-burst signal and the system clock appears as a sine or cosine value in the two standard color-difference signals of the chrominance demodulator during the reception of the color-burst signal. One of the standard color-difference signals, the B-Y signal, is fed through a horizontal-frequency-suppressing loop filter to a digital oscillator. The latter determines the speed of rotation of a hue adjustment angle rotating at approximately constant angular speed. The respective sine and cosine values of the hue adjustment angle are read as data values from first and second read-only memories, respectively, and are fed to the sine and cosine inputs of a hue adjuster in a calculating stage which derives the color-burst signal and the chrominance signal.The ACVP 2205 is a digital real–time signal processor for multistandard color TV sets based on the DIGIT2000
system. It handles composite video signals as well as
S–VHS signals. For PAL and NTSC a 2H adaptive
combfilter is implemented. It considerably improves the
picture quality by a sophisticated luminance and chrominance
separation. A single silicon chip contains the following
functions:
– selectable 7 or 8 bit video input
– code converter and a data demultiplexer for composite
and S–VHS input signals
– 2H adaptive combfilter for PAL and NTSC composite
video signals
– adjustable horizontal and vertical peaking filter for luminance
– selectable luminance filter for enhanced frequency response
– black–level–expander for improving the picture contrast
and the gamma correction
– contrast multiplier with limiter for the luminance signal
– adjustable chrominance filter
– all color signal processing circuits such as automatic
color control (ACC), color killer, PAL identification, decoder
with PAL compensation, hue correction
– color saturation multiplier with multiplexer for the color
difference signals
– IM bus interface for communication with the CCU 2070
or CCU 3000 Central Control Unit
– circuitry for measuring dark current (CRT spot–cutoff),
white level and photo current, and for transferring this
data to the CCU.
The ACVP 2205 is pin compatible to the PVPU 2204 . It
is designed in N–MOS technology and is available in a
40 pin Dil plastic package.
2. Functional Description
Supplied by one of the DIGIT2000 A/D converters (VCU
2136 or SAD 2140), the ACVP 2205 separates the video
signal into luminance and chrominance. These two signals
are processed in different circuits, which will be described
in the following. The output signals are reconverted
to analog signals in the VCU 2136 or VDU 2146.
Their RGB output amplifiers are used to drive the cathodes
of the CRT (see Fig. 2–4). Additionally, the ACVP
2205 performs a number of measurements and control
operations (in conjunction with the VCU 2136 or VDU
2146)relating to picture tube alignment such as spot–
cutoff current adjustment, white level control, beam current
limiting, etc.
For a multistandard application including SECAM, the
SPU 2243 SECAM Chroma Processor must be connected
in parallel to the ACVP 2205 for chroma processing.
The different processing delays Dt can be equalized
in the DTI 2223.

A comb filter arrangement operating at a reduced data rate is provided, which requires comparably fewer storage locations than previous arrangements. A digitized composite video signal of a given codeword rate is applied to a bandpass filter, which produces a filtered signal restricted to a portion of the passband of the composite video signal. The filtered signal is then subsampled at a rate which satisfies the Nyquist criterion for information of the restricted passband. Codewords, now at a reduced data rate, are applied to a one-H delay line, and delayed and undelayed signals are combined to produce a first comb-filtered signal. The first comb-filtered signal is then applied to an interpolator, which provides a sequence of codewords at the codeword rate of the original digitized composite video signal. This sequence of codewords is then combined with the codewords of the composite video signal to produce a second comb-filtered signal.
This invention relates to signal separation systems and, in particular, to a comb filter arrangement for separating the luminance and chrominance components of a digitized video signal at a reduced data rate.

Conventional television broadcast systems are arranged so that much of the brightness (luminance) information contained in an image is represented by signal frequencies which are concentrated about integer multiples of the horizontal linescanning frequency. Color (chrominance) information is encoded and inserted in a portion of the luminance signal spectrum around frequencies which lie halfway between the multiples of the line scanning frequency (i.e., at odd multiples of one-half theline scanning frequency).

Chrominance and luminance information can be separated by appropriately combing the composite signal spectrum. Known combing arrangements take advantage of the fact that the odd multiple relationship between chrominance signal components andhalf the line scanning frequency causes the chrominance signal components for corresponding image areas on successive lines to be 180.degree. out of phase with each other. Luminance signal components for corresponding image areas on successive linesare substantially in phase with each other.

In a comb filter system, one or more replicas of the composite image-representative signal are produced which are time delayed from each other by at least one line scanning interval (a so-called one-H delay). The signals from one line are addedto signals from a preceding line, resulting in the cancellation of the chrominance components, while reinforcing the luminance components. By subtracting the signals of two successive lines (e.g., by inverting the signals of one line and then combiningthe two), the luminance components are cancelled while the chrominance components are reinforced. Thus, the luminance and chrominance signals may be mutually combed and thereby may be separated advantageously.

The composite video signal may be comb filtered in an analog form, a sampled data form, or a digital form. Comb filters using analog signal glass delay lines for the (approximately) one-H delay lines are commonly employed in PAL-type receiversto separate the red and blue color difference signals, taking advantage of the one-quarter line frequency offset of the interlacing of the two signals. An example of a comb filter system for a sampled data signal is shown in U.S. Pat. No. 4,096,516,in which the delay line comprises a 6821/2 stage charge-coupled device (CCD) delay line which shifts signal samples from stage to stage at a 10.7 MHz rate to achieve a one-H delay. The article "Digital Television Image Enhancement" by John P. Rossi,published in Volume 84 of the Journal of the Society of Motion Picture and Television Engineers (1974) beginning at page 37 shows a digital comb filter in which the one-H delay is provided by a digital storage medium for 682 codewords which is accessedat a 10.7 MHz rate.

In the CCD delay line described in the above-referenced U.S. patent, 6821/2 stages are needed to transfer charge packets related to the analog video signal. But in the digital delay line described in the Rossi article, the video signal is inthe form of eight-bit digital codewords. This arrangement requires the use of eight storage locations for each of the 682 codewords in a horizontal line, or a storage medium for 5,456 bits. Moreover, this delay line is only of sufficient size for asystem in which an NTSC color video signal is sampled at a rate of three times per subcarrier cycle (i.e., using a 10.738635 MHz sampling signal). A frequently discussed sampling frequency for digitizing the analog video signal is 14.3181818 MHz, orfour times the color subcarrier frequency. A one-H digital delay line operating at this frequency requires storage for 910 codewords which, at eight bits per codeword, requires a total of 7280 storage locations. Since a storage medium of this capacityis difficult to fabricate economically, it is desirable to provide a digital comb filter system which requires fewer storage locations.

In accordance with the principles of the present invention, a comb filter arrangement operating at a reduced data rate is provided, which requires comparably fewer storage locations than previous arrangements. A digitized composite video signalof a given codeword rate is applied to a bandpass filter, which produces a filtered signal restricted to a portion of the passband of the composite video signal. The filtered signal is then subsampled at a rate which satisfies the Nyquist criterion forinformation of the restricted passband. Codewords, now at a reduced data rate, are applied to a one-H delay line, and delayed and undelayed signals are combined to produce a first comb-filtered signal. The first comb-filtered signal is then applied toan interpolator, which provides a sequence of codewords at the codeword rate of the original digitized composite video signal. This sequence of codewords is then combined with the codewords of the composite video signal to produce a second comb-filteredsignal.

The invention pertains to a chroma control circuit for a digital television receiver.
A chroma control circuit of this kind is described in an INTERMETALL Data Book entitled "Digit 2000 VLSI Digital TV System", Freiburg/Br., June 1985, pages 163 to 174, which explain the CVPU 2210 NTSC comb-filter video processor. The chroma control circuit according to the aforementioned preambles is contained especially in FIG. 10-2 on page 165, which is described in Section 10.1.4 on page 167 and in Section 10.1.6 on page 168.
In the NTSC and PAL television standards, the hue of a picture element can be represented as an angle-coded signal with respect to a transmitter reference system. The different phase angles from 0° to 360° correspond to hues assigned thereto, the zero reference phase being the zero phase of one of the two standard color-difference signals, namely the B-Y signal. The transmitter reference system is the unmodulated chrominance subcarrier, which is suppressed during the horizontal trace period but is transmitted for a short time as a burst signal during the horizontal retrace period, the phase of the burst signal, referred to the B-Y color-difference signal, being
-180° in the case of the NTSC television standard, and
+/-135° in the case of the PAL television standard.
In the prior art chroma circuit, the receiver reference system is the system clock, which has four times the frequency of, and is locked in frequency and phase to, the unmodulated chrominance subcarrier; four successive system-clock pulses, beginning with the zero phase of the B-Y color-difference signal, correspond to the phase angles of 0°, 90°, 180° and 270° of the unmodulated chrominance subcarrier. The latter, which is included in the composite color signal as mentioned above, is fed to the chroma control circuit after the chrominance and luminance components have been separated from the composite color signal by means of the chrominance filter.
In the NTSC and PAL television standards, the zero reference phase of the receiver reference system is the zero phase of the B-Y color-difference signal during the reception of the color burst. In that case, the R-Y color-difference signal is zero, and the phase comparison in the phase-locked loop is very simple.
If this chroma control circuit is to operate correctly, the chrominance subcarrier and the system clock, which has four times the chrominance-subcarrier frequency, must be locked together in frequency and phase. This is accomplished with a phase-locked loop, which causes the system clock to lock with the unmodulated chrominance subcarrier.
During the further development and improvement of this integrated chroma control circuit, the inventors discovered that the action of the phase-locked loop on the frequency and phase of the system clock is disadvantageous. For example, the phase-locked loop requires a voltage-controlled oscillator for the system clock whose deviation from the reference phase during a line period must not exceed 3°. This corresponds to a permissible deviation of the system-clock frequency of only 0.03 per mill from its nominal value if the phase difference at the beginning of the scanned line is zero. Otherwise, the permissible frequency deviation is even smaller. The necessary frequency stability and control accuracy are thus very high, so that tunable crystal oscillators are used for generating the system clock.
In addition, the data resulting from the phase comparison must be fed to the voltage-controlled oscillator, which is a tunable crystal oscillator forming part of a separate monolithic integrated circuit, so that additional terminals and interconnecting leads are required for both integrated circuits.
Another problem arises if such chroma control circuits are used in television receivers with two or more receiving units which present the information from two or more signal sources or television channels on the screen simultaneously. Each of those receiving units requires a separate clock system whose frequency must be synchronized with the frequency of the respective color-burst signal. With the small differences in the frequencies of the various received color-burst signals, interaction of the associated voltage-controlled oscillators is hardly avoidable, which results in interferences on the screen. The greater the lock-in range of the tunable crystal oscillators, the stronger the interaction will be, because the frequency stability of the oscillators decreases with increasing lock-in range.
SUMMARY OF THE INVENTION
Accordingly, one object of the invention is to improve the prior art chroma control circuit in such a way that the system clock need not be locked to four times the frequency of the originally received chrominance subcarrier, so that it can be locked to other system-related signals, such as a fixed-frequency signal, and that the phase-locked loop is an all-digital circuit.
The fundamental idea of the invention is to achieve the correct adjustment of the frequency and phase between the system clock, which forms the receiver reference system, and the color-burst signal not by locking the system clock to four times the frequency and four times the phase of the color-burst signal by means of a voltage-controlled oscillator, i.e., by analog means, as has been done so far, but by leaving the frequency and phase of the system clock unchanged and taking the necessary locking measures on the received color-burst and chrominance signals. The phase of the digitalized burst signal is, therefore, rotated with respect to the zero phase of the receiver reference system purely digitally by means of a phase-locked loop until it is -180° or +/-135° in accordance with the NTSC or PAL television standard, respectively; at the same time, frequency equality is established between the rotated burst signal and the system clock. The necessary correction angle is then applied to the chrominance signal too. In case of large frequency differences between the original received color-burst signal and the system clock, the correction of the chrominance signals during the scanning line must be interpolated.
A special advantage of the invention that one or more chroma control circuits in accordance with the invention can be added to the prior art chroma control circuit to produce a television receiver for multipicture reproduction that has only a single system clock for all receiving systems.
Another important advantage is that the system clock can be synchronized with signals which are locked to the horizontal frequency or a multiple thereof. This offers advantages during operation of a video recorder and in signal processing for picture enhancement as is performed, for example, to obtain a flicker-free television picture.
Finally, the necessary interpolation of the chroma correction during the scanning line is achieved by the invention in an advantageous manner even in case of large frequency differences between the originally received color-burst signal and the system clock.




CCU 3000, CCU 3000-I Main System Processor
CCU 3001, CCU 3001-I
MICRONAS INTERMETALL

1. Introduction
The CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I
are integrated circuits designed in 1.2 mm CMOS
technology, with the exception of CCU 3000, TC18 and
TC19, which is designed in 1 mm CMOS technology. The
CPU contained on the chips is a functionally unchanged
65C02-core, which means that for program development,
systems can be used which are on the market; including
high level language compilers.
The pin numbers mentioned in this data sheet refer to
the 68-pin PLCC package unless otherwise designated.
The CCU 3000-I is described separately in an addendum
on page 66.
1.1. Features of the CCU 3000, CCU 3000-I,
CCU 3001, CCU 3001-I
– CCU 3000 = ROM-less version of the CCU 3001
– 65C02 CPU with max. 8 MHz clock
– 32 kByte internal ROM (CCU 3001 only)
– 1344 internal Bytes RAM with stand-by option
– 51 I/O lines (CCU 3001)
– 26 I/O lines (CCU 3000)
– clock generator with programmable clock frequency
– 8 level interrupt controller
– CCU 3000, CCU 3001:
2 Multimaster IM bus interfaces
– CCU 3000-I, CCU 3001-I: 1I2C/IM bus and
1 Multimaster IM bus interface (see addendum)
– IR-input for software-decoded IR-systems
– on-chip power on, stand-by and clock supervision
logic
– on-chip watchdog
– 3 multifunctional timers
– supports memory banking (external 2MBytes)
– power down signal for external memory
– mask option: EMU mode
– programs can be written in Assembler or in “C”
– CCU 3000 TC 18/19: 1.0 mm CMOS technology, (see
addendum)
– application software available.

Functional Description
2.1. ROM
The chip is equipped with 32 kByte mask-programmable
ROM. The ROM uses up the address space from 8000H
to FFFFH. This ROM can be supplemented or replaced
externally. Only the CCU 3001 has an internal ROM.
2.2. RAM
The RAM area is split into three parts:
– page 0 (address 0 to FFH)
– page 1 (address 100H to 1FFH)
– page 3, 4, 5, 6 (address 300H to 63FH)
Page 0 offers a particularly fast access to the 65C02 and
is therefore very valuable for fast, compact programs.
Page 1 contains the stack and must therefore also have
RAM. The remaining RAM-memory follows in pages 3,
4, 5, 6, as page 2 is reserved as I/O address space. The
RAM can be kept in the stand-by mode via stand-by pin.
2.3. CPU
The CPU core is fully compatible with the 65C02 microprocessor.
However, not all the pins of the 65C02 processor
are accessible for the user outside the chip. One
switch in the control register allows the CPU to be
switched off, so that an external processor can take over
its tasks. This external processor can of course also be
an in-circuit emulator, which makes near-hardware
emulation possible, even though the status and control
lines of the internal CPU are not accessible. If an external
processor is used, all hardware blocks of the chip are
as accessible to it as if it were the internal CPU.
2.4. Clock Generator
An integrated two-pin oscillator generates the clock for
the microcontroller. The frequency created by the oscillator
can be programmed to be reduced with a divider
by the factor 1 ... 255. This enables the user to decrease
the current consumption by the controller by reducing
the working frequency as well as to increase the access
time for the (slower) external memory. This divider contains
the value 4 after a reset, so that the system can also
start with a slow external memory. If the mask-option
OSC is set (EMU version), a switch in the control register
makes it possible to receive the internal clock F2 at
XTAL2. In this case the oscillator must be external and
the clock must be fed to the pin XTAL1. In this way, the
user gets a time reference for internal operations in the
microcomputer. This is especially important with the interrupt
controller. The production version of the CCU
does not have this function!
2.5. PORT 1 to PORT 3, PORT 6 to PORT 8
8 ports belong to the system, of which 5 are 8 bits wide,
one 6 bit, one 4 bit and one 1 bit wide. All port lines of
PORTS 1 to 3 and 6 to 8 can be used as inputs or outputs
independently from each other. One register per port
defines the direction. PORT1 to PORT3 have push-pull
outputs and PORT6 to PORT8 have open drain outputs.
Even a line defined as output can be read, the pin level
being important. This property makes it possible for the
software to find desired and undesired short circuits.
Each port reserves a byte for the direction register and
the data in the I/O page. If the corresponding bit in the
direction register is set to 0, the output mode is switched
on. After a reset, all bits of a direction register are set
to 1. The falling edge of bit 7 of PORT 8 generates interrupts
if the priority of the corresponding interrupt controller
source (7) is not set to 0.
2.6. PORT 4
PORT 4 consists of only one line (LSB, P40). After a reset,
PORT 4 operates as an input only. As soon as PORT
4 is written for the first time, it is switched to output mode
(push-pull). Later read accesses read the actual level at
port 4. If bit 3 in the control word is active, P4 is used as
an R/W-line. If the internal CPU is active, R/W is an output
line, otherwise it is an input. But P4 has another, very
important function during RESET. The level at P4 during
RESET decides whether the control word is read from
the internal ROM (FFF9H) or from the external memory.
It is therefore important that the desired level during RESET
is set at P4. An internal pull-down resistor of approx.
100 kW is integrated in the CCU 3001, which ensures
that the control word is read by the internal ROM. The
external control word access is obtained via an external
pull-up resistor of approx. 5 kW. The CCU 3000 has an
internal pull-up resistor at P4 (external ROM access).
The further mode of operation of the CCU 3000, CCU
3001 depends only on the control word though.
Please note that this mode is always necessary for
the CCU 3000 since this device does not have internal
ROM!
2.7. I/O-Lines P50 to P55
The 6 additional I/O-lines have a two-fold function:
– input or output line (open drain output) or
– fully decoded I/O-select lines (push-pull outputs)
As a rule these lines can be used as input or output lines.
As soon as ports 1 to 4 are used as system bus, they are
lost as I/O-channels. However, a total of 48 port lines (24
inputs and outputs each) can be reconstructed without
difficulties (1 housing for 8 lines), if the additional 6 I/Olines
of the CCU 3000, CCU 3001 are switched into the
port select mode. They then represent the select lines of
the original ports 1 to 3. Each line can be defined as I/O
or port select line separately. In the I/O-page three bytes
are needed.


TEA6415C Bus-Controlled Video Matrix Switch
Main Features
20 MHz Bandwidth
Cascadable with another TEA6415C (Internal
Address can be changed by Pin 7 Voltage)
8 Inputs (CVBS, RGB, Chroma, ...)
6 Outputs
Possibility of Chroma Signal for each Input
by switching off the Clamp with an external
Resistor Bridge
Bus Controlled
6.5 dB Gain between any Input and Output
-55 dB Crosstalk at 5 MHz
Full ESD Protection

Description
The main function of the TEA6415C is to switch 8
video input sources on the 6 outputs.
Each output can be switched to only one of the
inputs, whereas any single input may be connected
to several outputs.
All switching possibilities are controlled through the
I2C bus.

Driving a 75 W load requires an external transistor.
The switches configuration is defined by words of 16 bits: one word of 16 bits for each output
channel.
So, 6 words of 16 bits are necessary to determine the starting configuration upon power-on (power supply: 0 to 10V). But a new configuration needs only the words of the changed output channels.

Using a Second TEA6415C
The programming input pin (PROG) allows two TEA6415C circuits to operate in parallel and to select them independently through the I²C bus by modifying the address byte. Consequently, the switching capabilities are doubled, or IC1 and IC2 can be cascaded.




TEA6420 BUS-CONTROLLED AUDIO MATRIX SWITCH


5 Stereo Inputs
4 Stereo Ouputs
Gain Control 0/2/4/6dB/Mute for each Output cascadable (2 different addresses) Serial Bus Controlled Very low Noise
Very low Distorsion
DESCRIPTION The TEA6420 switches 5 stereo audio inputs on 4stereo outputs. All the switching possibilities are changed through the I2C bus.



The power Supply is based on TDA4601 (SIEMENS)





Power supply is based on TDA4601d (SIEMENS)

TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.

Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.
The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

TDA8175 TV VERTICAL DEFLECTION OUTPUT CIRCUIT:

 DESCRIPTION
The TDA8175 is a monolithic integrated circuit in
HEPTAWATT package. It is a high efficiency power
booster for direct driving of vertical windings of TV
yokes. It is intended for use in Color and B & W
television sets as well as in monitors and displays.

 .POWER AMPLIFIER
 .FLYBACK GENERATOR 
.AUTOMATIC PUMPING COMPENSATION 
.THERMAL PROTECTION .
.REFERENCE VOLTAGE

ABSOLUTE MAXIMUMRATINGS
Symbol Parameter Value Unit
VS Supply Voltage (PIn 2) 35 V
V5, V6 Flyback Peak Voltage 60 V
V3 Voltage at PIn 3 +VS
V1, V7 Amplifier Input Voltage +VS
IO Output Peak Current (non-repetitive, t = 2ms) 2.5 A
IO Output Peak Current at :
f = 50 or 60Hz, t 3 10ms
f = 50 or 60Hz, t > 10ms
32
AA
I3 Pin 3 DC Current at V5 < V2 100 mA
I3 Pin 3 Peak-to-peak Flyback Current at f = 50 or 60Hz, tfly 3 1.5ms 3 A
Ptot Total Power Dissipation at Tcase = 70oC 20 W
Tj, Tstg Storage and Junction Temperature -40, +150 oC.


PANASONIC TX-25W3C CHASSIS EURO-1  Display device using scan velocity modulation:

 To improve pictures to be displayed on a display screen of a display device, it is known to use scan velocity modulation. In scan velocity modulation the (horizontal) deflection rate of the electron beam(s) is modulated with the luminance component of the video signal. As a result of scan velocity modulation, the information of the video signal will no longer be displayed at the correct position on the display screen. By using the modulation signal applied to the scan velocity modulator also for modulating the (read) clock rate of the video signal from the memory, it can be ensured that the video signal and the (modulated) deflection signal are always in synchronism with each other.

  1. A display device for displaying a video signal on a display screen of a display tube comprising at least one control electrode and deflection coils for deflecting at least one electron beam current, said display device further having an input for receiving the video signal, means for determining a derivative of a luminance component of the video signal, a scan velocity modulator for modulating the deflection rate of the electron beam current in the display tube in dependence upon the determined derivative, a position error correction circuit for correcting the video signal in dependence upon the derivative of the luminance component of the video signal, and means for applying the corrected video signal to the control electrode of the display tube, characterized in that the position error correction circuit comprises a frequency-modulatable clock (16) which is coupled to the means for determining the derivative of the luminance component of the video signal, said frequency-modulatable clock thereby generating a read clock signal; and a memory into which said video signal is written, said memory having a read clock signal input to which said read clock signal is applied, whereby the video signal stored in said memory is read at a frequency-modulated clock rate in dependence on said derivative of the luminance component.

2. A display device as claimed in claim 1, characterized in that the means for determining the derivative of the luminance component of the video signal comprise a clock signal generator, a further memory and a differentiator, the luminance Component of the video signal being written into said further memory under the control of said clock signal generator, and the luminance component stored in said further memory being applied to the differentiator.

3. A display device as claimed in claim 2, characterized in that the output of the differentiator is coupled to the scan velocity modulator for supplying a modulation signal.

4. A display device as claimed in claim 2, characterized in that the memory includes a write clock signal input coupled to the output of said clock signal generator so that the video signal is written into said memory at a fixed write clock rate under control of the clock generator.

5. A display device as claimed in claim 1, characterized in that the means for applying the corrected video signal comprises a display tube control circuit for receiving the modulated video signal read from the memory and for applying the video signal suitable for display to the control electrode(s) of the display tube.

6. A display device as claimed in claim 1, characterized in that the display device further comprises a beam current modulator coupled to an output of said means for determining a derivative for modulating the electron beam current in dependence upon the determined derivative of the luminance component in the video signal.

7. A display device as claimed in claim 6, characterized in that the beam current modulator has an output coupled to the means for applying the corrected video signal to the control electrode of the display tube for adapting the video signal in the applying means in dependence upon the output signal of the beam current modulator.

8. A display device as claimed in claim 1, characterized in that the display device also comprises an aperture correction circuit for correcting the luminance component of the video signal in dependence upon the derivative of the luminance component, the display device comprising a comparator for comparing the luminance component with a reference value and for aperture-correcting said component in dependence upon the output signal of the comparator.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a display device for displaying a video signal on a display screen of a display tube comprising at least one control electrode and deflection coils for deflecting at least one electron beam current, said display device further having an input for receiving the video signal, means for determining a derivative of a luminance component of the video signal, a scan velocity modulator for modulating the deflection rate of the electron beam current in the display tube in dependence upon the determined derivative, a position error correction circuit for correcting the video signal in dependence upon the derivative of the luminance component of the video signal, and means for applying the corrected video signal to the control electrode of the display tube.
2. Description of the Related Art
A display device of this type is known from U.S. Pat. No. 4,183,064. In this known display device, the position error is corrected by enlarging the portion of a display line having a higher luminance with respect to a portion having a smaller luminance and by subsequently applying scan velocity modulation (so as to obtain an improved definition) at which the dark/light transition is delayed and the light/dark transition is brought forward. As a result, the picture to be displayed is displayed with the original picture contents (the same quantity of light and dark portions as in the original video signal). In this solution, a second error (enlarging the light portions) is deliberately introduced to correct the first error (reducing the light portions as a result of scan velocity modulation). This is not an ideal solution because the two errors must compensate each other in this case. Correcting a non-linear error by means of a linear system is not very well possible. The drawback is that the position error cannot be satisfactorily corrected in this way. At a less sharp transition from light to dark (or conversely), the second error will be too large so that it will overcompensate the first error, whereas with a very sharp transition, the second error is too small so that the first error is not fully compensated. A further drawback is that it is not easy to enlarge the portions of the video signal having a higher luminance/brightness. Moreover, by enlarging the light portion, the beam current is increased so that the definition is adversely influenced due to spot growth.
To give pictures a better (impression of) sharpness, manufacturers focus on improvements of the display tube, inter alia by providing an improved phosphor layer and by improving the electron gun/guns. Moreover, scan velocity modulation of the electron beam deflection is used in a display tube (as is described, for example in the above-mentioned U.S. Patent). In this method the scan velocity (deflection rate) is adapted to the picture contents, notably to brightness variations. In scan velocity modulation, the derivative of the luminance component of the video signal is determined. Generally, the second derivative of the luminance component is used, which second derivative is applied to a voltage amplifier, an output of which applies a voltage to, for example, a scan velocity modulation coil. If a voltage-controlled current source is used instead of the voltage amplifier, the first derivative of the luminance component is taken. Actually, the scan velocity modulation coil is then the second differentiator. The scan velocity modulation is proportional to the second derivative of the voltage across the coil. By using scan velocity modulation, a position error is produced on the display screen (the video information rate is no longer synchronous with the scan velocity) at which a dark/light transition of the video signal is shifted to the right and a light/dark transition of the video signal is shifted to the left on the display screen. Consequently, portions of the video signal having a higher brightness/luminance are reduced with respect to portions of the video signal having a smaller light intensity. For example, when a plurality of successive squares (for example, a chessboard) is displayed, this effect can be clearly observed: larger (darker) and smaller (lighter) squares instead of squares all having the same size.
SUMMARY OF THE INVENTION
It is, inter alia an object of the invention to eliminate the above-mentioned drawbacks. To this end, the display device according to the invention is characterized in that the position error correction circuit comprises a frequency-modulatable clock which is coupled to the means for determining the derivative of the luminance component of the video signal for frequency-modulating the read clock rate of the video signal stored in a memory.
By modulating (varying) the clock rate at which the video information is written or read, the position error caused by scan velocity modulation can be corrected. The video signal is applied to the display tube at the same information rate as the scan velocity. Here, a (position) error which would arise due to scan velocity modulation is thus corrected instead of making two errors which hopefully counteract each other and are equally large as described in said U.S. patent.
Literature describes all kinds of examples in which higher derivatives or combinations of different derivatives for correcting the position error are used instead of the first and second derivatives of the video signal for use in scan velocity modulation. However, this results in a full correction of the position error at most for given slopes of transitions from light to dark and vice versa, whereas the picture will only degrade in the case of other slopes. Moreover, this renders the scan velocity modulation circuit much more complicated and hence more expensive. The display device according to the invention provides a solution which is completely different. This solution is that it is not attempted to correct the position error by means of the scan velocity modulation method (or by introducing a second error) but by modulating the clock with which the video information and the deflection is maintained synchronous at all times, thus principally precluding a position error.
The clock modulator is controlled by the same signal or by a corresponding signal with which the scan velocity modulator is controlled.
An embodiment of a display device according to the invention is characterized in that the display device further comprises a beam current modulator for modulating the electron beam current in dependence upon the determined derivative of the video signal. By using beam current modulation, brightness modulations occurring as undershoots and overshoots which may be produced by scan velocity modulation can be prevented or in any case reduced. This provides the possibility of using scan velocity modulation at a larger amplitude without this being a hindrance to the user of the display device, while a better picture sharpness is obtained. A larger amplitude of the scan velocity modulation results in a larger position error, which position error can be simply corrected again by means of the clock modulation.
A further embodiment of a display device according to the invention is characterized in that the display device also comprises an aperture correction circuit for correcting the luminance component of the video signal. By combining the scan velocity modulation with an aperture correction, a picture which is even sharper is obtained. At small or less steep jumps in the beam currents, the scan velocity modulation does not yield considerable improvements of the picture sharpness, whereas the opposite is true for aperture correction. By combining scan velocity modulation with an aperture correction, the sharpness of the picture can also be improved at these beam currents.