PHILIPS TDA8305A SMALL SIGNAL COMBINATION IC FOR COLOUR TV
The TDA8305A is TV sub-system circuit, for colour television receivers with the following features.
Vision IF amplifier with synchronous demodulator
Automatic gain control (AGC) detector suitable for negative modulation
Automatic frequency control (AFC) circuit with sample-and-hold
Sound lF amplifier and demodulator
DC volume control or separate supply for starting the horizontal oscillator
Horizontal synchronization circuit with two control loops
Vertical synchronization (divider system) and sawtooth generation with automatic amplitude
adjustment for 50 and 60 Hz
Transmitter identification (mute)
Generation of sandcastle pulse
Vision IF amplifier, demodulator and video amplifier
The IF amplifier of the TDA8305A has three AC~coupled stages, each stage having a control range
that exceeds 20 dB. AC-coupling means that the DC-feedback circuitry of the ampiifier (present in
the TDA4505) can be omitted, resulting in a saving of one pin. An additional advantage is the
symmetry of the amplifier which results in a less critical application.
In the TDA8305A the regenerated carrier signal islimited by a logarithmic limiter circuit before it is
passed on to a passive synchronous demodulator. The limiter has a very low differential phase shift
which results in good differential gain and phase figures.
The TDA8305A's video amplifier has a higher bandwidth and better linearity compared with that of
the TDA4505. A noise clamp is included in the video amplifier that limits the interference pulses
to a level just below the top sync. This circuit is more effective than the noise inverter used in the
TDA4505 and results in an improved picture stability, with respect to interference.
In the TDA4505 and TDA8305A, the reference signal for the AFC circuit is obtained from the
demodulator tuned circuit which means only one tuned circuit and adjustment are needed. The
disadvantage with this method is that the frequency spectrum fed to the detector is determined by the
SAW filter characteristic. This spectrum is asymmetrical with respect to the picture carrier so that the
AFC output voltage is dependent on the video signal. This was the main problem found with the
TDA4505's AFC circuit.
To remove this problem the TDA8305A is equipped with a sample-and-hold circuit which samples
during the sync level of the signal. This means that only the carrier signal is available to the AFC
and it will not be affected by the video information. The additional pin required for this circuit is
provided by the pin that became available when the DC feedback circuit was removed from the IF
amplifier (see previous section).
Weak input signals will cause the drive signal of the AFC to contain a lot of noise. This noise signal
has an asymmetrical frequency spectrum that causes an offset in the AFC output voltage, this
offset can be reduced by applying a notch to the demodulator circuit. The sample-and-hold circuit
is followed by a high output impedance amplifier, therefore the AFC's control steepness is
dependent on the load impedance.
The TDA8305A's AGC detector differs from that of the TDA4505 in that it doesn’t need the charge
resistor but has an internal current source. Also the circuitry between the detector capacitor and the
control stages has been changed to improve the signal-to-noise ratio of the video output signal
(no dips in the S/N ratio depending on the input signal amplitude). The point of tuner take-over
is preset by the voltage level at pin 1.
Sound circuit and horizontal oscillator starting function:
The input to the sound IF amplifier is by means of a bandpass filter coupling from the video output
(pin 17). The sound is demodulated and passed via a volume control stage to the audio
output amplifier. Volume control is obtained by connecting a potentiometer (10 k9.) between pin 11
and ground, or by supplying pin 11 with a variable voitage. Sound output is suppressed by an
internal mute signal when no TV signal is identified.
Improvement of sound quality was one of the main reasons for redesigning the TDA4505. To obtain
a better idea of the performance of the various circuits of the TDA4505 the following measurements
were carried out:
Weak signal performance when a TBA120 is driven with an intercarrier signal obtained from the
vision IF circuit of the TDA4505 (the sound IF of the latter was not used)
The same measurement for the sound IF circuit of the TDA4505 driven from another TDA4505
(again without using the sound IF circuit)
The same measurement as in the first case but with the sound IF of the TDA4505 connected
From the results of these measurements it was established that the sound problem was caused by an
interaction between vision IF and sound circuits. The improved sound quality of the TDA8305A as
compared to the TDA4505 was achieved by:
A very symmetrical vision-IF amplifier which is less sensitive to radiation from the sound IF
0 A change to the internal ground and supply connections of the IC to reduce coupling between
DC volume control/Horizontal oscillator start
Horizontal oscillator; the operation depending on the application. During switchon if no current is
supplied to pin 11 this pin will act as a volume control. When a current of 9.0 mA is supplied to
pin 11 the volume control is set to a fixed output signal and the device will generate drive pulses
for the horizontal deflection. The main supply can then be derived from the horizontal deflection
The video input signal (positive video) is connected to pin 25. The horizontal synchronization has
two control loops that generate a sandcastle pulse. Using the oscillator sawtooth facilitates
accurate timing of the burst key pulse. Therefore, the phase of this sawtooth must have a fixed
relationship to the sync pulse, which is achieved by use of the second control loop.
The TDA8305A's horizontal synchronization circuit differs from that of the TDA4505 in that:
The horizontal oscil|ator's retrace occurs during the horizontal retrace and not during the scan
period. This means that with weak input signals no interference will be visible on the screen.
It also prevents video crosstalk from disturbing the picture phase
The reference signal for the horizontal phase detector is nearer to being symmetrical and is
independent of the supply voltage and temperature. As a consequence the frequency shift of
the horizontal oscillator during noise is reduced
The current ratio of the phase detector for strong and weak signals is increased to obtain better
behaviour during both VCR-playback and weak signal reception. The switching level is independent
of supply voltage and temperature.
Horizontal phase detector
The circuit has the following operating conditions.
(a) Strong input signal, synchronized or non-synchronized.
(The strong/weak signal condition is obtained from the AGC circuit; the in-sync/out«of—sync
from the coincidence detector). In this condition the time constant is optimum for VCR-playback
i.e. fast time constant during the vertical retrace (to be able to correct VCR head-errors) and
such, that during scan, fluctuations of the sync are corrected. The phase detector is not gated.
lb) Weak signal — synchronized
In this condition the time constant is increased compared to condition (a). Also the phase
detector is gated when the oscillator is synchronized. This ensures a stable display which is not
disturbed by noise in the video signal.
(c) Weak signal - non-synchronized.
in this condition the time constant during scan and vertical retrace are the same as during scan
in condition (3).
The TDA8305A's vertical circuit differs from that ofthe TDA4505 in that it has:
Improved interlacing ~ the timing of the internal pulses is now close to a 50/50 ratio. This timing
is independent of supply voltage and temperature
The temperature drift of the vertical amplitude has been reduced
Reduction of noise in the vertical output signal so that modulation of the line distance will no
longer be visible on large screen sets.
When out-of-sync is detected by the horizontal circuit the divider is switched to 625 lines.
This results in a stable amplitude when no input signal is available. In the TDA4505 the divider
remains in the wide window during this condition which means interference may affect stability.
Vertical sync pulse
The vertical sync pulse integrator will not be disturbed when the vertical sync pulses have a width
of 10 ,us with a separation of 22 ps. These types of vertical sync pulses are sometimes generated by
video tapes with anti-copy guard.
Vertical divider system
The TDA8305A embodies a synchronized divider system for generating the vertical sawtooth at pin 2.
The divider system has an internal frequency doubling circuit, which allows the horizontal oscillator to
operate at its normal line frequency. One line period equals 2 clock pulses.
Use of the divider system avoids the requirement for vertical frequency adjustment. The divider has
a discriminator window for automatic switching from 60 Hz to 50 Hz mode. When the trigger pulse
comes before line 576 the 60 Hz mode is selected, otherwise the 50 Hz mode is selected.
The divider system operates with 2 different divider reset windows for maximum interference}
The windows are activated via an up/down counter.
The counter increases its counter value by 1 each time the separated vertical sync pulse is within the
search window. When not within the search window this value is decreased by 1.
The operating modes of the divider system are as follows:
Large search window (divider ratio between 488 and 722)
This mode is valid for the following conditions:
Divider is looking for a new transmitter
Divider ratio found - not within the narrow window limits
Up/down counter value of the divider system operating in the narrow window mode drops below
Narrow window (divider ratio between 522 to 528, 60 Hz; or 622 to 628, 50 Hz)
The divider system switches over to this mode when the up/down counter has reached its maximum
value of 15 approved vertical sync pulses. when the divider operates in this mode and a vertical sync
pulse is missing within the window, the divider is reset at the end of the window and the counter value
is decreased by 1. At a counter value below 10 the divider system switches over to the large window
The divider system also generates an anti-topflutter pulse which inhibits the phase 1 detector during
the vertical sync pulse. The pulse width is dependent on the divider mode. In Mode A the start is
generated by reset of the divider
in Mode B the anti-topflutter pulse starts at the beginning of the first equalizing pulse.
The anti-topflutter pulse ends at count 10 for the 50 Hz mode and count 12 for the 60 Hz mode.
The vertical blanking pulse is also generated via the divider system. The start is by reset of the divider
while the blanking pulse width is 34 (17 lines) for the 60 Hz mode and at count 42 (21 lines) for
the 50 Hz mode.
The vertical blanking pulse at the sandcastle output (pin 27) is generated by adding the anti-topflutter
pulse to the blanking pulse. Thus the vertical blanking pulse starts at the beginning of the first
equalizing pulse when the divider operates in Mode B. The length of the vertical blanking in this
condition is 21 lines in the 60 Hz mode and 25 lines in the 50 Hz mode.
Application when external video signals require synchronization
The input to the sync separator is externally available via pin 25. For normal application the video
output signal at pin 17 is AC coupled to this input as shown in Fig.11. It is possible to interrupt this
connection and drive the sync separator from other sources such as:
A teletext decoder in serial mode
An external video signal via a peritelevision connector
When a teletext decoder is applied the IF amplifier and synchronization circuit are operating in the
same phase which means that various connections between the two sections li.e. AGC gating) can
remain active. When external signals are applied to the sync separator the connections between the
two parts must be interrupted. This can be achieved by connecting pin 22 to ground, which results
in the following conditions:
AGC detector is not gated
AFC circuit is active
Mute circuit not active — sound channel remains switched on
Phase detector 1 has an optimal time constant for external video sources and is not gated.
By forcing pin 1 below 1 V the horizontal output changes to a high resistance. The protection can be
released by switching off the mains.
The AFC control voltage is obtained by multiplying the IF output signal (which is also used to
drive the synchronous demodulator) with a reference carrier. This reference carrier is obtained
from the demodulator tuned circuit via a 90 degree phase shift network. The IF output signal
has an asymmetrical frequency spectrum with respect to the carrier frequency. To avoid
problems due to this asymmetrical signal the AFC circuit is followed by a sample-and-hold
circuit which samples during the sync level. As a result the AFC output voltage contains no
video information. The specified control steepness is without using an external load resistor.
The control steepness decreases when the AFC output is loaded with two resistors between
the voltage supply and ground.
At very weak input signals the drive signal for the AFC circuit will have a high noise content.
This noise input has an asymmetrical frequency spectrum which will cause an offset of the
AFC output voltage. To avoid problems due to this effect a notch filter can be built in to the
demodulator tuned circuit. The characteristics given for weak input signals are measured without
a notch circuit, with a SAW filter connected in front of the IC (input signal such that the input
signal of the IC is 150 uV (RMS value).
The minimum value is obtained with a 1.8 k9. series resistor connected between pin 17 and
pin 25. The slicing level can be varied by changing the value of this resistor (a higher resistance
results in a larger value of the minimum sync pulse amplitude). The slicing level is independent
of the video information.
Frequency control is obtained by supplying a correction current to the oscillator RC-network.
This is achieved via a resistor connected between the phase 1 detector output and the oscillator
network. The oscillator can be adjusted to the correct frequency by:
short-circuit the sync separator bias network (pin 25) to the voltage supply.
To avoid the necessity of a VCR switch, the time constant of the phase detector at strong input
signals is sufficiently short to obtain a stable picture during VCFl playback. During the vertical
retrace period the time constant is even shorter so that VCR head errors are compensated for at
the beginning of the scan. During weak signal conditions (information derived from the AGC
circuit) the time constant is increased to obtain a good noise immunity.
This figure is valid for an external load impedance of 82 kfl connected between pin 28 and
the shift adjustment potentiometer.
The horizontal flyback input and the sandcastle output have been combined on pin 27. The
flyback pulse is clamped to a level of 4.5 V. The minimum current to drive the second control
loop is 0.1 mA.
The functions in—sync/out-of-sync and transmitter identification have been combined on pin 22.
The capacitor is charged during the sync pulse and discharged during the time difference
between gating and sync pulse.
The vertical scan is synchronized by means of a divider system, therefore no adjustment is
required for the ramp generator. The divider detects whether the incoming signal has a vertical
frequency of 50 or 60 Hz and corrects the vertical amplitude.
To avoid screenburn due to a collapse of the vertical deflection, a continuous blanking level is
inserted into the sandcastle pulse when the feedback voltage of the vertical deflection is not
within the specified limits.
PHILIPS TDA3565 PAL decoder:
The TDA3565 PAL decoder contains all the functions required for PAL signal decoding and colour matrixing and is contained within an 18-pin package. The oscillator, a.c.c. detector and burst phase detector each have single-pin outputs and the coupling capacitor for the luminance input at pin 8 doubles as a storage capacitor for the black level clamping circuit. Black level clamping of the three colour channels is performed using feedback proportional to the red channel black level. This feedback (variable with the brightness control) controls the input level of the luminance amplifier and therefore the clamping levels of all three colour signal outputs.
PHILIPS TDA3653B TDA3653C Vertical deflection and guard circuit (90˚)
The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to 1.5 A peak-to-peak.
• Output stage
• Thermal protection and output stage protection
• Flyback generator
• Voltage stabilizer
• Guard circuit
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the resistor at pin 8
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than 1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus prevent screen damage.
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive current of the output stage being affected by supply voltage variations.
PHONOLA (PHILIPS) 37KV1232 CHASSIS GR1AX Switched-mode self oscillating supply voltage circuit:POWER SUPPLY (PHILIPS SOPS - Self Oscillating Power Supply)
A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or a load connected to the output voltage. The circuit comprises a first controllable switch connected in series with a transformer winding and a second controllable switch for turning-off the first switch. The conduction period of the first switch is controlled by means of a control voltage present on a control electrode of the second switch. The circuit can be switched-over to a stand-up state in which the energy supplied to the load is reduced to zero. A starting network is connected between the input voltage and the second switch so that the current therein flows through the second switch during the period of time this switch conducts and does not flow to the control electode of the first switch in the stand-by state.
1. A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage, comprising a transformer having a primary and a feedback winding, a first controllable switch connected in series with the primary winding, the series arrangement thus formed being coupled between terminals for the input voltage, a second controllable switch coupled via a turn-off capacitor to the control electrode of the first switch to turn it off, means coupling the feedback winding to said control electrode, a transformer winding being coupled via a rectifier to an output capacitor having terminals which supply the output voltage, an output voltage-dependent control voltage being present on a control electrode of the second switch for controlling the conduction period of the first switch, the circuit being switchable between an operating state and a stand-by state in which relative to the operating state the supply energy supplied to the load is considerably reduced, a starting network connected to a terminal for the input voltage, means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off, a connection which carries current during the conduction period for the second controllable switch being provided between the starting network and said second switch, and means providing a connection between the starting network and the control electrode of the first switch, which connection does not carry current in the stand-by state.
2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.
3. A supply voltage circuit as claimed in claim 2, characterized in that the second controllable switch comprises a thyristor having a main current path included in the control electrode connection of the first controllable switch, said thyristor having a first control gate electrode for adjusting the turn-off instant of the first switch and a second control electrode to which the starting network and the resistor are connected.
4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.
Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
In the stand-by state the transistor is non-conducting in a large part of the period of the generated oscillation so that little energy is stored in the transformer. However, the starting resistor is connected via a diode to the second controllable switch, which is a thyristor. As the sum of the voltages across these elements is higher than the base-emitter threshold voltage of the transistor, the diode and the thyristor cannot simultaneously carry current. This implies that current flows through the starting resistor to the base of the transistor via the feedback winding after a capacitor connected to the feedback winding has been charged.
The invention has for its object to provide an improved circuit of the same type in which in the stand-by state the supply energy applied to the load is reduced to zero. The prior art circuit cannot be improved in this respect without the use of mechanical switches, for example relays. According to the invention, the switched-mode self-oscillating supply voltage circuit does not comprise such relays and is characterized in that it further comprises means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off. A connection which carries current during the conduction period of the second controllable switch is provided between the starting network and said second switch while a connection present between the starting network and the control electrode of the first switch does not carry current in the stand-by state.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.
The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V B of, for example, 300 V. Voltage V B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2. The series arrangement of a diode D1 and a 2.2 Ohm-limiting resistor R3 is arranged between the other terminal of capacitor C2 and the other end of winding L2 and the series arrangement of a resistor R4 of 12 Ohm and a diode D2 is arranged between the same end of winding L2 and the emitter of transistor Tr1. A 150 nF capacitor C3 is connected in parallel with diode D2. The anode of diode D1 is connected to that end of winding L2 which is not connected to capacitor C2, while the anode of diode D2 is connected to the emitter of transistor Tr1. In the FIGURE the winding sense of windings L1 and L2 is indicated by means of dots.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because of the feedback the described circuit oscillates independently as soon as the steady state is achieved. It will be described hereinafter how this state is obtained. During the time transistor Tr1 conducts the current flowing through the resistor R1 increases linearly. The resistor R4 then partly determines the base current of transistor Tr1. Capacitor C4 and resistor R7 form a voltage source the voltage of which is subtracted from the voltage drop across resistor R1. As soon as the voltage on the base of transistor Tr3 is equal to approximately 0.7 V this transistor becomes conductive, as a result of which the thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive and remains so. Across capacitor C2 there is a negative voltage by means of which transistor Tr1 is turned off. The inverse base current thereof flows through thyristor Tr2, Tr3. This causes charge to be withdrawn from capacitor C2, while the charge carriers stored in transistor Tr1 are removed with the aid of inductance L3. As soon as the collector current of transistor Tr1 has been turned off, the voltage across winding L2 reverses its polarity, which current recharges the capacitor. Now the voltage at the junction of components C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish.
Secondary windings L4, L5 and L6 are provided on the core of transformer T with the indicated winding senses. When transistor Tr1 is turned off, a current which recharges a smoothing capacitor C5, C6 or C7 via a rectifier D3, D4 or D5 flows through each of these windings. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in the FIGURE, are, for example, portions of a television receiver.
In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flows via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V B and to a Zener diode Z1 which has a positive voltage of approximately 7.5 V, while the base is unconnected. The other end of diode Z1 is connected to ground. A light-emitting diode D8, whose cathode is connected to the collector of an npn-transistor Tr5, is optically coupled to transistor Tr4. By means of a potentiometer R11 the base of transistor Tr5 can be adjusted to a d.c. voltage which is derived from the voltage V 0 of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V 1 of approximately 13 V. A resistor R12 is also connected to voltage V 1 , the other end of the resistor being connected to the emitter of transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage of approximately 7.5 V and to a smoothing capacitor C10. The other ends of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can be generated by means of a transformer connected to the electric AC supply and a rectifier, which are not shown for the sake of simplicity, more specifically for a remote control to which constantly supply energy is always applied, even when the majority of the components of the receiver in what is referred to as the stand-by state are not supplied with supply energy.
A portion of voltage V 0 is compared with the voltage of diode Z2 by means of transistor Tr5. The measured difference determines the collector current of transistor Tr5 and consequently the emitter current of transistor Tr4. This emitter current produces across resistor R6 a voltage drop whose polarity is the opposite of the polarity of the voltage source formed by resistor R7 and capacitor C4. Under the influence of this voltage drop the turn-on instant of thyristor Tr2, Tr3 is controlled as a function of voltage V 0 . If, for example, voltage V 0 tends to decrease owing to an increasing load thereon and/or in response to a decrease in voltage V B , then the collector current of transistor Tr5 decreases and consequently also the said voltage drop. Thyristor Tr2, Tr3 is turned on at a later instant than would otherwise be the case, causing transistor Tr1 to be cut-off at a later instant. The final value of the collector current of this transistor is consequently higher. Consequently, the ratio of the time interval in which transistor Tr1 is conductive to the entire period, commonly referred to as the duty cycle, increases, while the frequency decreases.
ontinues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
The circuit comprises a 1 MOhm starting resistor R16, one end of which is connected to the base of transistor Tr2 and the other end to the conductor which carries the voltage V B . Upon turn-on of the circuit current flows through resistors R16 and R5 and through capacitor C2, which has as yet no charge, to the base of transistor Tr1. The voltage drop thus produced across resistor R5 keeps transistor Tr2, and consequently also transistor Tr3, in the non-conductive state, while transistor Tr1 is made conductive and is maintained so by this current. Current also flows through winding L2. In this manner the circuit can start as energy is built up in transformer T.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state.
If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur. If in the operating state transistor Tr1 conducts while thyristor Tr2, Tr3 is cut-off, then the current flows through resistor R16 in the same manner as it flows during the start to the base of transistor Tr1, but has relatively little influence as the base current caused by the energy stored in winding L2 is many times larger. If both transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the current through resistor R16 flows through components R5, C2, L2, R4, C3 and R1. In this stand-by state capacitor C2 has indeed substantially no negative charge any longer but, in spite thereof, transistor Tr1 cannot become conductive since no current flows to its base. It will furthermore be noted that the circuit is protected in the event that thyristor Tr2, Tr3 has an interruption. Namely, in such a case the circuit cannot start.