Supply is based on the well TDA4601 (Siemens)
In this version was introduced first time the OSD feature with the ITT TVPO control unit instead of the earlier Motorola control unit.
It was very durable and gave not big problems except for some dry joint and leaked Electrolytic caps.
REX 21RM429 CHASSIS BS700.4 PHILIPS TDA4502A SMALL SIGNAL COMBINATION FOR COLOUR TV
The integration into a single package of all small signal functions required for colour TV reception is
achieved in the TDA4502A. The only additional circuits required for colour TV reception are the
deflection output stages, a sound detector and amplifier, and a colour decoder.
The IC includes a vision IF amplifier and video switching circuit, AFC circuit, AGC detector with
tuner output, an integral three—level sandcastle pulse generator, fully synchronized vertical and
horizontal drive outputs and a mute circuit with external availability. A triggered vertical divider
automatically adapts to 50 or 60 Hz operating mode thereby eliminating the need for external vertical
frequency control. The sound signal must be demodulated and amplified externally.
Vision IF amplifier with synchronous demodulator
AGC detector, suitable for negative modulation
AGC output to tuner
AFC circuit with ON/OFF switch
Video switch to select the internal, or an external, video signal
Horizontal synchronization circuit with two control loops
Vertical synchronization [divider system) and sawtooth generation with automatic amplitude
adjustment for 50 and 60 Hz
Transmitter identification (mute)
O Sandcastle pulse generator
QUICK REFERENCE DATA
K7 parameter symbol min. typ. max. unit
Supply voltage (pin 7) V7 9.5 12 13.2 V
Supply current (pin 7) I7 — 125 — ‘ mA
Supply current (pin 11) ‘‘ V11 — 6.0 8.5 mA
Operating ambient temperature range Tamb -25 - + 65 °C
Storage temperature range Tstg -25 — + 150 °C
Total power dissipation Ptot — — 2.3 W
28—lead DI L; plastic with internal heat spreader (SOT117).
IF amplifier, synchronous demodulator and AFC
The IF amplifier (pins 8 and 9) has a symmetrical input, the impedance of which enables SAW-filtering
to be used. The synchronous demodulator and the AFC circuit share an external reference tuned
circuit (pins 20 and 21). An internal RC—network provides the necessary phase—shift for AFC operation.
The AFC circuit provides a control voltage output with a voltage swing greater than 9 V at pin 18.
In the internal and external mode the AFC can be switched OFF when pin 22 is connected to positive
AGC gating is performed to reduce sensitivity of the IF amplifier to external noise. The AGC time
constant is provided by an RC circuit 19.
agc connected from is pin supplied tuner voltage pin 5. The point of tuner takeover is preset by the voltage level at pin 1.
Video switch circuit
The IC has a video switch with two video inputs and one video output. One input is connected to the
demodulated IF signal which is also fed to the video output pin of the peritelevision connector. The
other input can be switched to an external signal which is applied to the video input of the
peritelevision connector. The video output signal of the switch is fed to pin 25 of the IC, which is
the wnchronization part and, to the colour decoder. When the video switch is in the external mode,
the synchronization circuit is switched to the external signal. The vision IF, AGC and AFC circuits
will not be affected by the switching action and will, therefore, operate in the normal mode. Gating
for the AGC detector is switched OFF when the switch is in the external mode. The first control
loop is not switched to a low time constant when weak signals are received.
Horizontal oscillator start function
The horizontal oscillator start function is achieved by applying a current of 8.5 mA to pin 11 during the
switch-on period. This current can be taken from the mains rectifier. The main supply, pin 7, can then
be obtained from the horizontal output stage. The load current of the driver has to be added to the
The positive video input signal is applied to pin 25. The horizontal synchronization has two control
loops which have been introduced to generate a sandcastle pulse. By using the oscillator sawtooth, an
accurate timing of the burst-key pulse can be made. Therefore, the phase of this sawtooth pulse must
have a fixed relationship to the sync pulse.
Horizontal phase detector
The circuit has two operating conditions:
The first loop has afixed time constant and a gated phase detector, this enables optimum
performance for co-channel interference. The VCR mode is obtained by an additional load on
In this condition the time constant is the same as during the VCR mode.
Vertical sync pulse
The vertical sync pulse integrator will not be disturbed when the vertical sync pulses have a width of
10 ps and a separation of 22 us. This type of vertical sync pulse is generated by video tapes with
Vertical divider system
A synchronized divider system generates the vertical sawtooth wavefonns at pin 2. The system uses an
internal frequency doubler circuit to enable the horizontal oscillator to operate at its normal line
frequency. One line period equals 2 clock pulses.
Using the divider system avoids the requirement for vertical frequency adjustment. The divider has a
discriminator window for automatic switching from 50 Hz to 60 Hz mode. When the trigger pulse
arrives before line 576 the 60 Hz mode is selected, if not, the 50 Hz mode is selected.
The divider system operates with two different reset windows to give maximum interferencel
disturbance protection. The windows are activated via an up/down counter.
The counter is increased by 1 each time the separated vertical sync pulse is within the narrow window.
When the sync pulse is not within the narrow window the counter is decreased by 1.
The operation modes of the divider system are as follows:
Large (search) window (divider ratio between 488 and 722)
This mode is valid for the following conditions:
0 Divider is looking for a new transmitter
O Divider ratio found — not within the narrow window limits
0 A non—standard composite video signal is detected — when a double or enlarged vertical sync pulse is
detected after the internally generated anti-top~flutter pulse has ended. This means a vertical sync
pulse width > 10 clock pulses (50 Hz); > 12 clock pulses (60 Hz). This mode is normally activated
for video tape recorders operating in the feature trick mode
0 Up/down counter value of the divider system, operating in the narrow window mode, drops below
Narrow window (divider ratio between 522 to 528 (60 Hz) or 622 to 628 (50 Hz))
The divider system switches over to this mode when the up/down counter has reached its maximum
value of 15 approved vertical sync pulses. When the divider operates in this mode and, a vertical sync
pulse is missing within the window, the divider is reset at the end of the window and the counter value
is decreased by 1. At a counter value below 6 the divider system switches over to the large window
The divider system also generates an anti—top-flutter pulse which inhibits the Phase 1 detector during
the vertical sync pulse. The pulse width is dependent on the divider mode. In ‘Mode A’ the start is
generated by resetting the divider. In ’Mode B’ the anti—top-flutter pulse starts at the beginning of the
first equalizing pulse. The anti—top-flutter pulse ends at count 10 for the 50 Hz mode and count 12 for
the 60 Hz mode.
The vertical blanking pulse is also generated via the divider system. The start is initiated by resetting
the divider while the blanking pulse width is at count 34, (17 l
count 42, (21 lines), for the 50 Hz mode. The vertical blanking pulse, at the sandcastle output
(pin 27), is generated by adding the anti—top-flutter pulse to the blanking pulse. When the divider
operates in ‘Mode B’, the vertical blanking pulse starts at the beginning of the first equalizing pulse.
The length of the vertical blanking in this condition is 21 lines in the 60 Hz mode and 25 lines in the
50 Hz mode.
Limiting values in accordance with the Absolute Maximum System llEC 134)
parameter symbol min. max. unit
Supply voltage Vp = V7.5 — 13.2 V
Total power dissipation Pmt - 2.3 W
Operating ambient temperature range Tamb -25 + 65 °C
Storage temperature range Tstg -25 + 150 °C
Vp = V7 = 12 V; Tamb = 25 °C; unless otherwise specified; all voltages are referenced to ground
(pin 6) unless otherwise specified
parameter conditions symbol min. typ. max. unit
Supply voltage (pin 7) V7 9.5 12.0 13.2 V
Supply current (pin 7) I7 — 125 — mA
Supply current (pin 1 1) note 1 l 11 — 6 8.5 mA
Vision IF amplifier (pins 8 and 9)
Input sensitivity at 38.9 MHz note 2 V8 40 80 120 uV
Input sensitivity at 45.75 MHz note 2 V3 — 100 ~ uV
Differential input resistance
(pin 8 to pin 9) note 3 R3_g 0.8 1.3 1.8 kﬂ
Differential input capacitance
(pin 8 to pin 9) note 3 C39 — 5 —- pF
Gain control range G3_g — 62 — dB
Maximum input signal V3.9 50 100 — mV
Expansion of output signal for
50 dB variation of input signal note 4 AV17 — 1 — dB
Video amplifier note 5
Output level for zero signal input note 6 V17 3.3 3.7 4.1 V
Output signal top sync level V17 1.5 1.7 1.9 V
Amplitude of video output signal
(peak-to-peak value) note 7 V17(p_p) 1.4 1.8 2.2 V
Internal bias current of output
transistor (npn emitter
follower) l17(int) 1.4 2.0 — mA
Bandwidth of demodulated
output signal B 4.0 5.0 — M Hz
Differential gain note 8 G 17 — 5 10 %
Differential phase note 8 lp — 5 10 %
REX 21RM429 CHASSIS BS700.4 Power supply Description based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload con
dition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- Line deflection output (S2000)
REX 21RM429 CHASSIS BS700.4 - VIDEO CHROMA PROCESSING WITH TDA3301 (MOTOROLA)
TDA3300 / 3301 TV COLOR PROCESSOR
TDA3300 3301 TV COLOR PROCESSOR
The Decoder IC The centre -piece of the decoder is the Motorola TDA3300B i.c. which carries out all the luminance and U V Inputs from PAL delay line 9V Frequency nlyv Z 2RV2 100k chroma signal processing required. Features of this 40 -pin chip include: (1) Automatic black -current control via feedback from the RGB output circuits. (2) Peak beam current limiting to prevent blooming on highlights - in addition to the normal beam current limit- ing action. (3) Separate R, G and B input pins for the injection of teletext/data signals (or on -screen display of the channel number with frequency synthesis tuning). These signals can be varied by means of the user brightness and con- trast controls. (4) Low dissipation - about 600mW. (5) By adding a small adaptor panel with a TDA3030A SECAM-to-PAL converter i.c. during production the receiver is given multistandard (PAL, SECAM and NTSC-4.43) capability.
A block diagram of the TDA3300B i.c. is shown in Fig. 3. As with the better known TDA3560 single -chip decoder, both the chroma and the burst pass through the chroma delay line. The U output from this enters the TDA3300B at pin 8, passing to the U detector and to the burst detector. The latter is part of a phase -locked loop, the detector's output being applied via an H/2 (half-line frequency) switch to the 4.43MHz voltage -controlled crystal oscillator. The 4.43MHz reference oscillator's output is applied for PAL switching, and to the U detector via a voltage -controlled 90° phase shifter. This shifter is under the control of the 90° detec- tor which compares its output with the oscillator's output coming via the PAL switch: when the phase shift is cor- rect, the output from the 90° phase detector is zero. The combined effect of the two H/2 switches in the reference oscillator control loop - the two shown on the right-hand side - cancels phase detector offsets. The outputs from the U and V detectors include burst "flag" pulses which are used for a.c.c., ident and colour -killing - there are two colour -killing actions. RGB Output Stages The RGB output stages are of the class AB type and incorporate extra circuitry for c.r.t. black -current sampl- ing and beam limiting. Fig. 4 shows the red output stage. Under most conditions transistor 2TR1 acts as a class A amplifier, driving the tube's cathode via 2D5 and 2TR7. A high -value collector load resistor (2R33) is used to reduce the dissipation in 2TR1. The stage gain is set by the ratio of 2R40 and 2R36 to 2R25 and 2RV3, the latter setting the drive level. For good transient response it's necessary for the tube/base capacitance to be rapidly charged/discharged in accordance with the signal swings. There is no problem when 2TR1 is being driven from off to on, since the capacitance is discharged rapidly via 2D5 and 2TR1. When 2TR1 is driven from on to off however 2D5 will become reverse biased. Under these conditions 2TR4 acts as an emitter -follower so that the capacitance charges rapidly. Black -level stability is critical for good results. As we've 2R46 5k6 2R51 120k 2TR7 BF493S 2C43l Sampling circuit L -J 1k5 Field blanking J Red cathode _Tube input T"and base 810capacitance nlrr Reference Line pedestal blanking Sample -and - hold amplifier-ws switched on rt- Video Urn seen, the TDA3300B chip incorporates circuitry for automatic black -current correction. Making use of this reduces service calls and ensures constant performance despite tube ageing or circuit misadjustment. Feedback is required, and this is provided by the sampling circuit shown in the box with the broken outline. Transistor 2TR7 acts as an emitter -follower between the video output stage and the c.r.t.'s cathode. It's a low leakage type, the components 2C40, 2D10 and 2C43 ensuring that the circuit has negligible effect on the video signal. Since the beam current flows via 2R51, a voltage proportional to the beam current is produced across this resistor. It's fed into the TDA3300B at pin 22. Black -current Control For automatic black -current control the important thing is the small beam current that flows when the tube is biased just above cut off. To enable this current to be sampled, the TDA3300B replaces the video signal with a fixed reference pedestal voltage for a couple of lines at the end of each field blanking period (this pedestal can be seen as a grey line at the top of the picture if the height control's setting is reduced). The sample voltage at pin 22 of the i.c. is fed to one input of a sample -and -hold amp- lifier which is switched on to sample the input for one line only of the reference pedestal period. 2C33 acts as the black -current control reservoir capacitor, holding the charge acquired during the sampling time for the whole field period. This charge is added to the video signal within the i.c., thus maintaining the correct red gun black current. It's interesting to notice that when a set is switched on from cold there's a momentary screen bright -up with flyback lines as the beam current begins to flow. This is because it takes several fields for 2C33 (and the corre- sponding capacitors in the green and blue channels) to charge fully. Since the voltage continuously available across 2R51 is proportional to beam current, it's used within the i.c. for peak beam current limiting during the active line periods. This is in addition to beam current limiting via the con- trast control - and a crowbar trip that operates should the beam current exceed 3mA.
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
The major design considerations apart from optimum
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass netw
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Beam current sampling
On-screen display blanking
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.
Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
PHILIPS TDA3653B TDA3653C Vertical deflection and guard circuit (90°):
1.5 A peak-to-peak.
· Output stage
· Thermal protection and output stage protection
· Flyback generator
· Voltage stabilizer
· Guard circuit
QUICK REFERENCE DATA
Note to the quick reference data
1. The maximum supply voltage should be chosen such that during flyback the voltage at pin 5 does not exceed 60 V.
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
current of the output stage being affected by supply voltage variations.
TDA3653B: 9-lead SIL; plastic (SOT110B); SOT110-1; 1996 November 25.
TDA3653C: 9-lead SIL; plastic power (SOT131); SOT131-2 November 25.
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply (note 1)
Supply voltage range
pin 9 VP = V9-4 10 - 40 V
pin 6 V6-4 - - 60 V
Output (pin 5)
Peak output voltage during flyback V5-4M - - 60 V
Output current I5(p-p) - 1.2 1.5 A
Operating junction temperature range Tj -25 - +150 °C
Thermal resistance junction to mounting base
(SOT110B) Rth j-mb - 10 - K/W
(SOT131) Rth j-mb - 3.5 - K/W.
ITT TVPO2066 TV Controller with On-Screen Display for TV Receivers.
In comparison to the older TVPO 2065 hardware, the
port 3 of the TVPO 2066 consists of 6 x 12 V/2 mA open–
drain outputs instead of 5 V/25 mA open–drain outputs.
“TVPO 2066” is the name of the unprogrammed hard-
ware. The programmed versions will be called:
– TVPO 2066–Axx
for analog TV–sets
– TVPO 2066–Dxx
for digital TV–sets
with the version–no. xx. Application diagrams and de-
scriptions of different software versions are available in
additional data sheets.
The TVPO 2066 is an intelligent microcomputer in N–
channel MOS technology. On one silicon chip, it con-
tains all operating and tuning functions of a modern TV
receiver. Thus, along with the non–volatile memory
(MDA 2062, NVM 3060), the SAA 1250, IRT 1250 or IRT
1260 remote–control transmitter and the TBA 2800 pre-
amplifier this offers a very economic solution for TV re-
ceivers with on–screen display and voltage synthesizer.
The device is available in 44–pin PLCC package and
40–pin DIL package. The PLCC version has 4 pins more
for digital combined inputs/outputs.
2. The Functional Blocks of the TVPO 2066
The hardware components of the TVPO 2066 are:
– 8048–core, fully compatible to 8048 instruction set
– 10K ROM, 256 byte RAM
– four 64 steps analog output to control vol., color etc.
– single 4032 steps analog output for controlling of a
– IR decoder for ITT–IR (remote control with IRT
– mains flip–flop for standby mode
– IM–bus interface for non–volatile memory and devices
of DIGIT 2000 system for digital video–processing.
– fast counter input (T1) for automatic search (for analog
– 12 digital combined inputs/outputs (8 or 10 for DIL–
– 8 digital outputs
– integrated 12–digit on–screen display
2.1. The 8049 Microcomputer
For the description of the commands and characteristics
of the 8049, please refer to the CCU 2030, CCU 2050,
CCU 2070 data sheet.
The 8049 provides separate address space for program,
data, in/out, and external data. The ROM is organized in
banks of 2 K Bytes. Bank 0 occupies the addresses 0 to
2047. The other banks (10, 11, 12, 13) share the ad-
dresses 2048 to 4095. The different banks are selected
through the bank select register 15 as described for the
CCU 2070 in the CCU 2030, 2050, 2070 data sheet.
Banks 14 through 17 of the CCU 2070 are not available
in the TVPO.
The data and control registers of the TVPO’s peripheral
units are located in the address space of external data.
They are accessed by the “Move External” instruction
(MOVX). Electrically, the connection is provided by the
lines DB0 to DB7, RD, WR, and ALE. These connections
of the 8049 microcomputer are not available during nor-
mal operation. In “Test Mode” (EA = 5 V or EA = 12 V),
some pins are switched so that the TVPO’s peripherals
can be accessed from the outside via DB0 to DB7.
In normal operation, only P2 of the 8049’s original ports
remains unchanged. During test operation, RD, WR,
ALE and PSEN are connected to P24 to P27 (compare
CCU 2030, CCU 2050, CCU 2070 data sheet).
2.2. The Remote–Control Decoder
In the already mentioned standby mode, and also during
normal operation, the remote–control decoder expects
infrared–transmitted signals that were transmitted by
the SAA 1250, IRT 1250 or IRT 1260 remote–control
transmitter IC, received by an infrared photo diode, and
amplified by the TBA 2800 infrared preamplifier IC. The
decoder frees the remote–control signal from interfer-
ence and decodes each command word that is recog-
nized as correct. A valid command word is made avail-
able to the microcomputer by way of two registers. No
interrupt is initiated. Rather, it is the task of the program
to continuously check the infrared registers.
A command word transmitted via infrared consists of 10
bits – four address bits and six data bits. These two parts
of the command word are provided in two different regis-
ters. Bit 7 in the address register is low when a valid com-
mand word is detected. When the data word is read,
both infrared registers are cleared.
It is possible to mask–program which infrared com-
mands also carry the power–on information and switch
the TVPO from standby to full operation. For this pur-
pose, up to five groups of commands within a binary de-
coder matrix are programmable for one infrared address
(compare CCU 2030, CCU 2050, CCU 2070 data
2.3. The Mains Flip–Flop and Reset Circuit
Mains flip–flop and reset circuit operate from the stand-
by supply. After switching on the standby supply it takes
100 ms at most until the TVPO is in full standby opera-
tion. The Mains output is controlled by the mains flip–
flop. In the
“Mains off” position the output is high.
The mains flip–flop is set by means of the infrared
“Mains on” commands or by an active low level applied
to the Mains output for at least 20 µs. A reset for the
mains flip–flop is generated whenever:
1. The standby supply voltage is less than approx. 3.5 V
(e.g. during power–on)
2. The microcomputer executes a “Mains off” command.
The microcomputer clears the mains flip–flop by writing
a 1 into bit 3 of the external register 13. In order to proper-
ly charge the stray capacitances at the Mains output, the
mains flip–flop remains blocked in the “Mains off” posi-
tion for 16 ms after any reset. After this time has elapsed,
the TV set may be turned on again.
With no Reset option set (compare CCU 2030, CCU
2050, CCU 2070 data sheet), the mains flip–flop is also
reset by any Reset signal going low. The TVPO–internal
Reset’, which is different from the externally–applied
Reset is high only when both Mains is in the low state
and Reset is at high level. Two options are mask–pro-
grammable in this respect:
Reset 1: The Reset signal, going low, does not reset the
mains flip–flop. If the customer does not specify, this op-
tion will be set as default.
Reset 2: The TVPO–internal Reset’ is identical to the
Reset signal and independent of the state of the mains
Resetting the mains flip–flop clears the remote–control
decoder. The other parts of the TVPO are cleared by the
TVPO–internal Reset’ signal via the Reset input. Delay-
ing the Reset signal with respect to the VDD supply volt-
age is done by an external RC network at the Reset in-
The input voltage of the regulator for the 5 V VDD supply
voltage should be monitored to prevent the system’s cir-
cuits from resetting improperly and the NVM 3060 EE-
PROM from programming false data.
With no Reset option set, any spike or excessive noise
present on the Reset line may cause the mains flip–flop
to be reset. In such cases, a ceramic filter capacitor
should be provided near the Reset pin.
2.4. The IM–Bus and Non–Volatile–Memory
It is by means of this part of the circuit that the TVPO
2066 communicates with the non–volatile memory
(MDA 2062 or NVM 3060) which stores the tuning and
analog data, acquired during the Memo procedure and
the options. The IM–Bus consists of three lines Clock,
Ident and Data. Clock and Ident are unidirectional sig-
nals from the TVPO 2066 to the memory (and to the
VSP–processor in case of a digital TV set), and Data is
bidirectional for transferring the data in both directions.
In addition, the MDA 2062 (not the NVM 3060) requires
a memory clock signal which is issued from the TVPO
2066 (approx. 1 kHz). All these signals on the IM–Bus
have TTL level. In the nonoperative state all three bus
lines are high. The start of a telegram is initiated when
Ident and Data are low. Data takeover occurs at the posi-
tive edge of Clock. For a detailed description of the IM–
Bus protocol please refer to the data sheet of the MDA
2062 or NVM 3060.
2.5. The Clock Generator and the Sequence Control
For the purpose of generating the clock signals required
to operate the TVPO 2066 the chip contains an oscillator
which is designed for crystals in the frequency range
from 3.5 to 4.5 MHz. For the exact requirement of “off–
timer” and “sleep–timer” functions, a 4 MHz crystal is
needed. The crystal is connected to the ‘Xtal’ input. All
timing specification in this data sheet relate to a crystal
frequency of 4 MHz. With other crystal frequencies,
there will be corresponding variations.
2.6. The D/A Converters for the Analog Outputs
The TVPO 2066 provides four analog outputs for adjust-
ment of the TV’s basic settings (e.g. volume and for ana-
log TV sets additional brightness, contrast and color sat-
uration). These control voltages are made available as
pulse/pause modulated signals, where the ratio can be
varied in 64 steps. The needed DC level signal is ob-
tained by means of a simple RC lowpass filter.
2.7. The Tuning Voltage Generator
The tuning voltage for the capacitance diodes of the TV
tuner is generated as a pulse/interval modulated signal
by a modified rate multiplier. The range of variation of the
pulse/interval ratio extends from 0 (no pulses) to infinity
(continuous signal) with a resolution of 4032 steps. At a
clock frequency of 4 MHz the basic period of the rate
multiplier is 0.5 ms which results in tolerable filter expen-
2.8. The Ports
The TVPO 2066 has two ports (Port 2 and Port 3) which
are used by the software versions as control outputs/in-
puts for a keyboard, band selection, multi–standard indi-
cators, multi–video indicators and AFC switch.
The PLCC version of the TVPO 2066 has in addition four
pins of Port 1 (P14...P17). The DIL version of the TVPO
2066 is also available in other pinnings: the D/A conver-
ter DA3 and DA4 can be exchanged to port input/out-
puts. DA3 to Port 1, Bit 5 (P15) and DA4 to Port 1, Bit 6
(P16). This possibility is very useful in digital TV sets, be-
cause in this case only one D/A converter is needed for
2.9. The On–Screen Display
2.9.1. Outputs and Inputs for the OSD
The OSD is an additional hardware module on the
TVPO 2066 chip, which allows the display of 12 different
characters such as the program number and analog val-
ues (volume, brightness etc.) on a TV screen. The TVPO
2066 software controls the OSD through a set of 16 ex-
ternal write registers.
The TVPO 2066 delivers four additional output signals:
character signal red
character signal green
character signal blue
Fast blanking is used for switching between video and
OSD signals and shows the validity of the R, G, B out-
For synchronization and to place the display, the
TVPO 2066 needs two additional input signals:
2.9.2. Display Format
The OSD generates a rectangular display block, which
contains 2 rows of 6 characters each (see Fig. 2–1). The
characters are addressed depending on their position
within this display block. Each address is attached to
one TVPO 2066 register. The content of each register
describes the character type and its color.
Pin Descriptions for 44–Pin PLCC
Pin 1 – Vsup
This pin must be connected to the positive of the 5 V sup-
Pin 2 – Ground
This pin must be connected to the negative of the supply.
Pin 3 – Vstb: Standby Supply pin +5 V
Via this pin, clock oscillator, reset circuit and remote–
control decoder are powered. By means of this, it is pos-
sible to switch on the TV receiver by remote control. The
standby consumption is very small.
Pins 4 to 7, 8 to 21 – Port P2, Bits 0 to 7
The internal configuration of these in/outputs is shown
in Fig. 4–3. Direct data transfer with the µC can be ex-
ecuted via this port. The push–pull outputs drive one
Pins 8 to 11 – Port P1, Bits 4 to 7
The internal configuration of these in/outputs is shown
in Fig. 4–4. Direct data transfer with the µC can be ex-
ecuted via this port. The outputs are open–drain with a
12 V rating. Four outputs are available in the 44–pin
PLCC package. In the 40–pin DIL package up to two
P1–outputs (instead of analog outputs) are available by
changing the bonding.
Pins 12 and 13 – Vertical and Horizontal synchronization
These inputs are shown in Fig. 4–5. They are used to
synchronize the on–screen display. Negative pulses are
needed. The internal delayed–clock–generator for the
OSD section synchronizes to the positive edge of the
Pin 14 – Fast Blank Output
This output, which is shown in Fig. 4–6, is used to stop
the normal display, and thus characters can be dis-
played on the screen.
Pins 15 to 17 – Video Outputs Red, Green and Blue
These outputs are shown in Fig. 4–7 and used for on–
screen display outputs. Therefore, there are different
colors to represent the output.
Pins 22 to 29 – Port P3, Bits 0 to 7
The diagram of these open–drain outputs is shown in
Fig. 4–8. The voltage handling capability of Port–bits 0
and 1 (pins 28 and 29) is limited to Vsup, but supplies a
high output current. The Port–bits 2 to 7 (pins 22 to 27)
are outputs with a 12 V rating and a lower output current.
In standby, bit 7 of P3 is grounded.
Pin 30 – Tuning Voltage Output
Fig. 4–9 shows the diagram of this push–pull output. Pin
30 supplies the tuning voltage for the capacitance
diodes of the TV tuner in the shape of a pulsewidth–mo-
dulated signal. After amplification by an external transis-
tor, the tuner DC voltage is derived by multiple RC filter-
ing. A temperature–compensated Zener diode ZTK 33
must be provided for stabilizing the tuning voltage
against variations of supply voltage and ambient tem-
Pin 31 – IR: Remote–Control Input
The internal configuration of this pin is shown in
Fig. 4–10. Via an external coupling capacitor of 10 nF,
the remote–control signal, amplified by the TBA 2800
preamplifier IC, is fed to the remote–control decoder.
The input is self–biasing to approximately 1.4 V, and the
input DC resistance is approximately 150 kOhm. For
highest input sensitivity, this pin must not be loaded re-
sistively. A small capacitor connected from pin 31 to
ground can be useful to suppress steep transients.
Pins 32 to 35 – Analog Outputs
These pins are open–drain outputs with diagram shown
in Fig. 4–11. They supply the squarewave signals whose
variable pulse/interval ratio is described in section 2.5.
These signals serve for actuating the analog control ele-
ments. External pull–up resistors are required to pro-
duce the squarewave output signals.
Pins 36 to 38 – IM Bus Connections
The internal configuration of these pins are shown in
Figs. 4–12 and 4–13. Via these pins, the ITT TVPO 2066 is
connected to the IM bus (see section 2.3.). This bus in-
terlinks the TVPO 2066 and the non–volatile memory.
The ident and clock outputs are unidirectional (see
Fig. 4–12). The data pin acts as input and output for
reading and writing data (Fig. 4–13).
Pin 40 – Mains: Mains Switch Input/Output
The internal configuration of this input/output is shown
in Fig. 4–13. Pin 40 represents the output of the mains
flip–flop with a resistive pull–up. The output is active low
(mains on). In the case of infrared remote control, this
pin acts as output and drives an external switching am-
plifier, the mains relay, In the case of direct operation,
this pin is used as input for switching on the TV receiver
by means of an active low level applied to this pin, which
sets the main flip–flop.
Pin 41 – Reset: Reset Input
The internal configuration of this input is shown in
Fig. 4–14. The function of this pin is explained in section
2.4. The input circuit is of a Schmitt trigger configuration
and provides some noise immunity. In critical applica-
tions, however, an additional ceramic capacitor, con-
nected between this pin and GND, may be necessary to
increase noise immunity.
Pin 42 – Osc Out: fosc/4096 Output
The internal configuration of this output is shown in
Fig. 4–15. This push–pull output provides the memory
clock signal for the non–volatile memory MDA 2062
EEPROM (1 kHz). The drive capability of this pin is one
TTL gate. This pin is not needed for the non–volatile
memory NVM 3060.
Pin 43 – T1: T1 Input
This input can be used as timer input or normal input
(e.g. to count the pulses of the horizontal frequency for
autosearch function in analog TV sets). For more details
about this input, see the CCU 2030, CCU 2050,
CCU2070 data sheet.
Pin 44 – Xtal: Oscillator Crystal
The internal configuration of this input/output is shown
in Fig. 4–16. For normal use, a 4 MHz crystal is con-
nected to this oscillator pin and to GND. The input is self–
biasing to approximately 3.8 V, input DC resistance is
approx. 350 kOhm. The output signal is the 4 MHz clock
signal of the TVPO 2066.
Programmed Versions of TVPO 2066
Some programmed versions of the TVPO 2066 are
available (all versions use the non–volatile–memory
– TVPO 2066–A25
for analog TV–sets. With auto–searching of stations,
4 multi–standards, up to 99 stations, sleep–timer,
Teletext with TPU 2735 with FLOF & exended charac-
ters (Spanish, Polish, Hungarian and Turkish).
– TVPO 2066–D03
for digital TV–sets. Along with the VSP 2860 and the
VCU 2133 it offers a very economical solution of digital
TV–sets (simple TV). Some features are 4 standards:
PAL, NTSC, SECAM East/West, up to 99 stations, 3
video modes, auto–searching analog output for ana-
log audio (volume) control and more.
Separate data sheets are available for analog and digital
versions. Application diagrams will be found there. The
last page shows an application diagram for analog TV–
5.5. User Options
If the manufacturer writes his own software for the TVPO
2066, he can choose some options by program mask or