Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.


Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....
Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !
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©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of
Engineer Frank Sharp. NOTHING HERE IS FOR SALE !

Saturday, January 15, 2011

MIVAR 29MF101 100HZ CHASSIS CS1118 VIDEO DIGITAL BOARD CS1114-1
























PRIMUS Powerful Scan-Rate Converter including Multistandard Color Decoder.

1. Introduction
The VSP 94x2A (PRIMUS) is a new component of the
Micronas MEGAVISION® IC set in a CMOS embedded
DRAM technology. The VSP 94x2A comprises all
main functions of a digital featurebox in one monolithic
IC. The number of features is limited in favor of a lowcost
solution, but no trade-off has been made concerning
picture quality.
The family is ideally suited to work in conjunction with

the deflection processors SDA 9380 (9402/32) and
DDP 3315C (9412/42). In combination with the ’digital
TV decoder’ MDE 9500, double-scan iDTV is possible.
The package is upward pin-compatible to other
medium-range and high-end devices of the VSP 94xy
family. A 50/60 Hz derivative is also available (9432,
9442). The device comprises a digital multistandard

color decoder, an RGB interface with fast-blank capability
(SCART), digital ITU656 input, scaling units
including panorama, embedded DRAM for upconversion,
picture improvements, temporal noise reduction,
as well as A/D and D/A converters.

1.1. Features
– Integrated video matrix switch
• Up to seven CVBS inputs, up to two Y/C inputs,
• Three CVBS outputs (Y/C inputs signals are combined
to CVBS output format)
• 9 bit amplitude resolution for CVBS, Y/C A/D converter
• AGC (Automatic Gain Control)
– Multi-standard color decoder
• PAL/NTSC/SECAM including all substandards
• Automatic recognition of chroma standard
• Only one crystal necessary for all standards
– RGB-FBL or YUV-H-V input

• 8 bit amplitude resolution for RGB or YUV
• 8 bit amplitude resolution for FBL or H
– ITU656 support (version dependent, refer to next
chapter)
• ITU656 input/output
• DS656 output (double-scan ‘656-like’ output)
– Letterbox detection
– Noise reduction
• Temporal noise reduction
• Field-based temporal noise reduction for luminance
and chrominance
• Different motion detectors for luminance and
chrominance or identical
• Flexible programming of the temporal noise
reduction parameters
• Automatic measurement of the noise level
– Horizontal scaling of the 1fH signal
• Split-screen possible with additional PiP or Text
processor
– Flexible digital horizontal scaling of the 2fH signal

• Scaling factors: 3, ..., 0.75 including 16:9 compatibility
• 5 zone panorama generator
– Embedded memory
• On-chip memory controller
• Embedded DRAM core for field memory
• SRAM for PAL/SECAM delay line
– Data format 4:2:2
– Flexible clock and synchronization concept
• Horizontal line-locked or free-running mode
• Vertical locked or free-running mode
– Scan-rate-conversion
• Simple interlaced modes (100/120 Hz): AABB,
AAAA, BBBB (9402A/9412A only)
• No scan-rate-conversion modes (50/60 Hz): AB,
AA, BB (9432A/9442A only)
– Flexible output sync controller
• Flexible positioning of the output signal
• Flexible programming of the output sync raster
• ‘Blank signal’ generation
– Signal manipulations
• Still field
• Insertion of colored background
• Windowing
• Vertical chrominance shift for improved VCR picture
quality

– Sharpness improvement
• Digital color transition improvement (DCTI)
• Peaking (luminance)
– Three D/A converters
• 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) output
• 72 MHz clock frequency
• Two-fold oversampling for anti-imaging
• Simplification of external analog postfiltering
– 1920 active pixel/per line in default configuration
– I2C-bus control (400 kHz)
• Selectable I2C address
– 1.8V ±5% and 3.3 V ±5% supply voltages
– PMQFP80-1 package.

---------------------------------------


SDA 9380-B21
EDDC
Enhanced Deflection
Controller and
RGB Processor


















1 General description
The SDA 9380 is a highly integrated deflection controller and RGB video processor for CTV receivers
with 15 to 19kHz or 31 to 38kHz line frequencies. The deflection component controls among others
an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output
stage and an East-West raster correction circuit. All adjustable output parameters are I²C-Bus controlled.
Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock
system which includes the=χΝ=and χΟ=control loops.
The RGB processor has two YUV/RGB inputs and one RGB input. One YUV/RGB input and the
RGB input are for SVGA and text/OSD with fast blanking. The RGB output stage has two control
loops for cut off and white level with halt capability in vertical shrink modes. An overall Y output and
an adjustable delay of the RGB outputs related to this signal are suitable for a scan velocity modulation
circuit.
The supply voltages of the IC are 3.3V and 8V. It is mounted in a P-MQFP package with 64 pins.
2 Features
2.1 Deflection
=No external clock needed
=χΝ=PLL and=χΟ=PLL on chip
=Standard line frequencies for NTSC and PAL
= =18.75kHz line frequency for 625 lines/60 Hz
= =Doubled line frequencies for NTSC and PAL, MUSE standard, DTV standard
Also suitable for VGA, Macintosh (35kHz) and SVGA standard (38kHz, 800*600*60Hz)
=Automatic switching between 31, 35 and 38kHz in Monitor mode with 2 digital outputs for
Controlling B+ and 1 analog input to keep watch on it
=I²C-Bus alignment of all deflection parameters
=All EW-, V- and H- functions
=Picture width and picture height EHT compensation
=Dynamic PH EHT compensation (white bar)
=Compensation of H-phase deviation (e.g. caused by white bar)
=Upper/lower EW-corner correction separately adjustable
=Extreme EW-corner correction (coefficient of sixth order) for super flat tubes
=V-angle and V-bow correction
=Two special control items for vertical zoom/shrink and scroll function with absolutely
correct tracking of the E/W and HD-output signals
=No re-adjustment of E/W after changing vertical S-correction and linearity needed
=H-frequent PWM output signal for generating an adjustable vertical frequent parabola or
a constant pulse width, selectable by I²C
=H- and V-blanking time adjustable
=Partial overscan adjustable to hide the cut off control measuring lines in the reduced
scan modes
=Self adaptation of V-frequency / number of lines per field between 192 and 680 for
each possible line frequency
=Selectable Black Switch-Off behaviour via I²C-Bus


-------------------------------------------
SDA5553




















1. Introduction
The Micronas SDA 55xx TV microcontroller is dedicated
to 8 bit applications for TV control and provides
dedicated graphic features designed for modern low
class to mid range TV sets.
The SDA 55xx is a microcontroller and single chip teletext
decoder for decoding World System Teletext data
as well as other data services as Video Programming
System (VPS), Program Delivery Control (PDC), and
Wide Screen Signalling (WSS) data used for PAL plus
transmissions (in line 23). The data slicer and display
part of the SDA 55xx supports a wide range of TV
standards including PAL, NTSC as well as the acquisition
of the above mention data services as VPS, WSS,
PDC, TTX and Closed Caption data.
The slicer combined with its dedicated hardware
stores TTX data in a VBI buffer of 1 kByte. The Microcontroller
firmware available from Micronas performs
all the acquisition tasks (hamming and parity checks,
page search and evaluation of header control bits)
once per field. Additionally, the firmware can provide
high end teletext features like Packet-26-handling,
FLOF, TOP and list page mode. The Application Program
Interface (API) to the user software is optimized
for a minimum SW overhead.
The on-chip display unit used to display teletext data
up to level 1.5 can also be used for customer defined
on-screen displays (OSD). The display generator is
able to handle parallel display attributes, pixel oriented
displays and dynamically re-definable characters
(DRCS).
The SDA 55xx provides also an integrated generalpurpose,
fully 8051-compatible microcontroller with
specific hardware features especially suitable in TV
sets. The microcontroller core has been enhanced to
provide powerful features such as memory banking,
data pointers and additional interrupts, etc.
The internal XRAM consists of up to 16 kBytes. The
microcontroller provides an internal ROM of up to
128 kBytes. ROMless versions can access up to
1 MByte of external RAM and ROM.
The 8-bit microcontroller runs at 33.33 MHz internal
clock. SDA 55xx is realized in 0.25 micron technology
with 2.5 V supply voltage for the core and 3.3 V for the
I/O port pins to make them TTL compatible.
Based on the SDA 55xx microcontroller the MINTS
software package was developed and provides dedicated
device drivers for many Micronas video & audio
products and includes a full blown TV control SW for
the PEPER application chassis. The SDA 55xx is also
supported with powerful design tools like emulators
from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler
and TEDIpro OSD development SW by Tara Systems.
This support provided by Micronas leads to:
– Shorter time to market
– Re-usability of the SW also for future Micronas
products
– Target independent SW development based on
ANSI C.
– Verification and validation of SW before targeting
and improved SW test concept
– Graphical interface design requiring a minimum
effort for OSD programming and TV controlled know
how.
– Complete, modular and open tool chain available
and configurable by customer.
1.1. General Features
– 8051 compatible microcontroller with TV related
special features and advanced OSD display
– Feature selection via special function register
– Simultaneous processing of TTX, VPS, PDC and
WSS (line 23) data
– Supply voltage 2.5 V for core and 3.3 V for ports
– ROM version package PSDIP52-2, PMQFP64-1
– Romless version package PMQFP100-2
– 128 kByte Flash ROM version package PSDIP52-2
1.1.1. External Crystal and Programmable Clock
Speed
– Normal mode 33.33 MHz CPU clock, power save
mode 8.33 MHz
– CPU clock speed selectable via special function
registers.
– Single external 6 MHz crystal, all necessary clock
signals are generated internally by means of PLLs
1.1.2. Microcontroller Features
– 8-bit 8051 instruction set compatible CPU
– Two 16-bit timers
– Watchdog timer
– Capture compare timer for infrared remote control
decoding
– Pulse width modulation unit (2 channels 14 bit,
6 channels 8 bit).

– ADC (4 channels, 8 bit)
– UART
1.1.3. Memory
– Non-multiplexed 8-bit data and 16…20-bit address
bus (ROMless version)
– Memory banking up to 1 MByte (ROMless version)
– Up to 128 kByte on-chip program ROM
– Eight 16-bit data pointer registers (DPTR)
– 256-bytes on-chip processor internal RAM (IRAM)
– 128 bytes extended stack memory
– Display RAM and TXT/VPS/PDC/WSS Data Acquisition
Buffer directly accessible via MOVX command
– Up to 16 kByte on-chip extended RAM (XRAM) consisting
of
• 1 kByte on-chip ACQ buffer RAM (access via
MOVX)
• 1 kByte on-chip extended RAM (XRAM, access via
MOVX) for user software
• 3 kByte display memory
1.1.4. Display Features
– ROM character set supports all east and west European
languages in a single device
– Mosaic graphic character set
– Parallel display attributes
– Single/double width/height of characters
– Variable flash rate
– Programmable screen size
(25 rows × 33 … 64 columns)
– Flexible character matrixes (H x V) 12 x 9 … 16
– Up to 256 dynamically re-definable characters in
standard mode; 1024 dynamically re-definable characters
in enhanced mode
– CLUT with up to 4096 color combinations
– Up to 16 colors per DRCS character
– One out of eight colors for foreground and background
colors for 1-bit DRCS and ROM characters
– Shadowing & contrast reduction
– Pixel by pixel shiftable cursor with up to 4 different
colors
– Support of progressive and 100 Hz double scan
– 3 × 4 bits RGB-DACs on chip
– Free programmable pixel clock from 10 MHz to
32 MHz
– Pixel clock independent from CPU clock
– Multinorm H/V-display synchronization in master or
slave mode
1.1.5. Acquisition Features
– Multistandard digital data slicer
– Parallel multinorm slicing (TTX, VPS, WSS, CC, G+)
– Four different framing codes available
– Data caption only limited by available memory
– Programmable VBI-buffer
– Full channel data slicing supported
– Fully digital signal processing
– Noise measurement and controlled noise compensation
– Attenuation measurement and compensation
– Group delay measurement and compensation
– Exact decoding of echo disturbed signals
1.1.6. Ports
– One 8-bit I/O-port with open drain output and
optional I2C bus emulation support (Port 0)
– Two 8-bit multifunction I/O-ports (Port 1, Port 3)
– One 4-bit port working as digital or analog inputs for
the ADC (Port 2)
– One 2-bit I/O-port with secondary functions (P4.2,
4.3, 4.7)
– One 4-bit I/O-port with secondary function (P4.0,
4.1, 4.4) Not available in PSDIP52-2)

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