RADIOMARELLI PROFESSIONAL RCM 22P CHASSIS T219RCM
The chassis is a monocarrier with 2 daughter board units carrying Video and Audio Units.
GENERAL BASIC TRANSISTOR LINE OUTPUT STAGE OPERATION:
The
basic essentials of a transistor line output stage are shown in Fig.
1(a). They comprise: a line output transformer which provides the d.c.
feed to the line output transistor and serves mainly to generate the
high -voltage pulse from which the e.h.t. is derived, and also in
practice other supplies for various sections of the receiver; the line
output transistor and its parallel efficiency diode which form a
bidirectional switch; a tuning capacitor which resonates with the line
output transformer primary winding and the scan coils to determine the
flyback time; and the scan coils, with a series capacitor which provides
a d.c. block and also serves to provide slight integration of the
deflection current to compensate for the scan distortion that would
otherwise be present due to the use of flat screen, wide deflection
angle c.r.t.s. This basic circuit is widely used in small -screen
portable receivers with little elaboration - some use a pnp output
transistor however, with its collector connected to chassis.
Circuit Variations:
Variations
to the basic circuit commonly found include: transposition of the scan
coils and the correction capacitor; connection of the line output
transformer primary winding and its e.h.t. overwinding
in series; connection of the deflection components to a tap on the
transformer to obtain correct matching of the components and conditions
in the stage; use of a boost diode which operates in identical manner to
the arrangement used in valve line output stages, thereby increasing
the effective supply to the stage; omission of the efficiency diode
where the stage is operated from an h.t. line, the collector -base
junction of the line output transistor then providing the efficiency
diode action without, in doing so, producing scan distortion; addition
of inductors to provide linearity and width adjustment; use of a pair of
series -connected line output transistors in some large -screen colour
chassis; and in colour sets the addition of line convergence circuitry
which is normally connected in series between the line scan coils and
chassis. These variations on the basic circuit do not alter the basic
mode of operation however.
Resonance
The
most important fact to appreciate about the circuit is that when the
transistor and diode are cut off during the flyback period - when the
beam is being rapidly returned from the right-hand side of the screen to
the left-hand side the tuning capacitor together with the scan coils
and the primary winding of the line output transformer form a parallel
resonant circuit: the equivalent circuit is shown in Fig. 1(b). The line
output transformer primary winding and the tuning capacitor as drawn in
Fig. 1(a) may look like a series tuned circuit, but from the signal
point of view the end of the transformer primary winding connected to
the power supply is earthy, giving the equivalent arrangement shown in
Fig. 1(b).
The Flyback Period:
Since the operation of the
circuit depends mainly upon what happens during the line flyback period,
the simplest point at which to break into the scanning cycle is at the
end of the forward scan, i.e. with the
beam deflected to the right-hand side of the screen, see Fig. 2. At
this point the line output transistor is suddenly switched off by the
squarewave drive applied to its base. Prior to this action a linearly
increasing current has been flowing in the line output transformer
primary winding and the scan coils, and as a result magnetic fields have
been built up around these components. When the transistor is switched
off these fields collapse, maintaining a flow of current which rapidly
decays to zero and returns the beam to the centre of the screen. This
flow of current charges the tuning capacitor, and the voltage at A rises
to a high positive value - of the order of 1- 2k V in large -screen
sets, 200V in the case of mains/battery portable sets. The e
nergy
in the circuit is now stored in the tuning capacitor which next
discharges, reversing the flow of current in the circuit with the result
that the beam is rapidly deflected to the left-hand side of the screen -
see Fig. 3. When the tuning capacitor has discharged, the voltage at A
has fallen to zero and the circuit energy is once more stored in the
form of magnetic fields around the inductive components. One half -cycle
of oscillation has occurred, and the flyback is complete.
Energy Recovery:
First
Part of Forward Scan The circuit then tries to continue the cycle of
oscillation, i.e. the magnetic fields again collapse, maintaining a
current flow which this time would charge the tuning capacitor
negatively (upper plate). When the voltage at A reaches about -0.6V
however the efficiency diode becomes forward biased and switches on.
This damps the circuit, preventing further oscillation, but the magnetic
fields continue to collapse and in doing so produce a linearly decaying
current flow which provides the first part of the forward s
can,
the beam returning towards the centre of the screen - see Fig. 4. The
diode shorts out the tuning capacitor but the scan correction capacitor
charges during this period, its right-hand plate becoming positive with
respect to its left-hand plate, i.e. point A. Completion of Forward Scan
When the current falls to zero, the diode will switch off. Shortly
before this state of affairs is reached however the transistor is
switched on. In practice this is usually about a third of the way
through the scan. The squarewave applied to its base drives it rapidly
to saturation, clamping the vol
tage
at point A at a small positive value - the collector emitter saturation
voltage of the transistor. Current now flows via the transistor and the
primary winding of the line output transformer, the scan correction
capacitor discharges, and the resultant flow of current in the line scan
coils drives the beam to the right-hand side of the screen see Fig. 5.
Efficiency:
The
transistor is then cut off again, to give the flyback, and the cycle of
events recurs. The efficiency of the circuit is high since there is
negligible resistance present. Energy is fed into the circuit in the
form of the magnetic fields that build up when the output transistor is
switched on. This action connects the line output transformer primary
winding across the supply, and as a result a linearly increasing current
flows through it. Since the width is
dependent on the supply voltage, this must be stabilised.
Harmonic Tuning:
There
is another oscillatory action in the circuit during the flyback period.
The considerable leakage inductance between the primary and the e.h.t.
windings of the line output transformer, and the appreciable self
-capacitance present, form a tuned circuit which is shocked into
oscillation by the flyback pulse. Unless this oscillation is controlled,
it will continue into and modulate the scan. The technique used to
overcome this effect is to tune the leakage inductance and the
associated capacitance to an odd harmonic of the line flyback
oscillation frequency. By doing this the oscillatory actions present at
the beginning of the scan cancel. Either third or fifth harmonic tuning
is used. Third harmonic tuning also has the effect of increasing the
amplitude of the e.h.t. pulse, and is generally used where a half -wave
e.h.t. rectifier is employed. Fifth harmonic tuning results in a
flat-topped e.h.t. pulse, giving improved e.h.t. regulation, and is
generally used where an e.h.t. tripler is employed to produce the e.h.t.
The tuning is mainly built into the line output transformer, though an
external variable inductance is commonly found in colour chassis so that
the tuning can be adjusted. With a following post I will go into the
subject of modern TV line timebases in greater detail with other models
and technology shown here at Obsolete Technology Tellye !
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Power supply is realized with mains transformer
and Linear transistorized power supply stabilizer, A DC power supply
apparatus includes a rectifier circuit which rectifies an input
commercial AC voltage. The rectifier output voltage is smoothed in a
smoothing capacitor. Voltage stabilization is provided in the
stabilizing circuits by the use of Zener diode circuits to provide
biasing to control the collector-emitter paths of respective
transistors.A linear regulator circuit according to an embodiment of
the present invention has an input node receiving an unregulated
voltage and an output node providing a regulated voltage. The linear
regulator circuit includes a voltage regulator, a bias circuit, and a
current control device.
In one embodiment, the current
control device is implemented as an NPN bipolar junction transistor
(BJT) having a collector electrode forming the input node of the linear
regulator circuit, an emitter electrode coupled to the input of the
voltage regulator, and a base electrode coupled to the second terminal
of the bias circuit. A first capacitor may be coupled between the input
and reference terminals of the voltage regulator and a second
capacitor may be coupled between the output and reference terminals of
the voltage regulator. The voltage regulator may be implemented as
known to those skilled in the art, such as an LDO or non-LDO 3-terminal
regulator or the like.
In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
A circuit is disclosed for improving operation of a linear regulator, having an input terminal, an output terminal, and a reference terminal. The circuit includes an input node, a transistor, a bias circuit, and first and second capacitors. The transistor has a first current electrode coupled to the input node, a second current electrode for coupling to the input terminal of the linear regulator, and a control electrode. The bias circuit has a first terminal for coupling to the output terminal of the linear regulator and a second terminal coupled to the control electrode of the transistor. The first capacitor is for coupling between the input and reference terminals of the linear regulator, and the second capacitor is for coupling between the output and reference terminals of the linear regulator. The bias circuit develops a voltage sufficient to drive the control terminal of the transistor and to operate the linear regulator. The bias circuit may be a battery, a bias device and a current source, a floating power supply, a charge pump, or any combination thereof. The transistor may be implemented as a BJT or FET or any other suitable current controlled device.
Power Supply: The examples chosen are taken from manufacturers' circuit diagrams and are usually simplified to emphasise the fundamental nature of the circuit. For each example the particular transistor properties that are exploited to achieve the desired performance are made clear. As a rough and ready classification the circuits are arranged in order of frequency: this part is devoted to circuits used at zero frequency, field frequency and audio frequencies. Series Regulator Circuit Portable television receivers are designed to operate from batteries (usually 12V car batteries) and from the a.c. mains. The receiver usually has an 11V supply line, and circuitry is required to ensure that the supply line is at this voltage whether the power source is a battery or the mains. The supply line also needs to have good regulation, i.e. a low output resistance, to ensure that the voltage remains constant in spite of variations in the mean current taken by some of the stages in the receiver. Fig. 1 shows a typical circuit of the power -supply arrangements. The mains transformer and bridge rectifier are designed to deliver about 16V. The battery can be assumed to give just over 12V. Both feed the regulator circuit Trl, Tr2, Tr3, which gives an 11V output and can be regarded as a three -stage direct -coupled amplifier. The first stage Tr 1 is required to give an output current proportional to the difference between two voltages, one being a constant voltage derived from the voltage reference diode D I (which is biased via R3 from the stabilised supply). The second voltage is obtained from a preset potential divider connected across the output of the unit, and is therefore a sample of the output voltage. In effect therefore Tr 1 compares the output voltage of the unit with a fixed voltage and gives an output current proportional to the difference between them. Clearly a field-effect transistor could do this, but the low input resistance of a bipolar transistor is no disadvantage and it can give a current output many times that of a field-effect transistor and is generally preferred therefore. The output current of the first stage is amplified by the two subsequent stages and then becomes the output current of the unit. Clearly therefore Tr2 and Tr3 should be current amplifiers and they normally take the form of emitter followers or common emitter stages (which have the same current gain). By adjusting the preset control we can alter the fraction of the output voltage' applied to the first stage and can thus set the output voltage of the unit at any desired value within a certain range. By making assumptions about the current gain of the transistors we can calculate the degree of regulation obtainable. For example, suppose the gain of Tr2 and Tr3 in cascade is 1,000, and that the current output demanded from the unit changes by 0.1A (for example due to the disconnection of part of the load). The corresponding change in Tr l's collector current is 0.1mA and, if the standing collector current of Tr 1 is 1mA, then its mutual conductance is approximately 4OmA/V and the base voltage must change by 2.5mV to bring about the required change in collector current. If the preset potential divider feeds one half of the output voltage to Tr l's base, then the change in output voltage must be 5mV. Thus an 0.1A change in output current brings about only 5mV change in output voltage: this represents an output resistance of only 0.0552.
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Frequency synthesizer tuning system for television receivers:
SHOWING M3870 Microcomputer + M206 PLL
" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"
PLL Synthesizer first time using a micro controller M3870 type With the PLL synthesized tuning color television with frequency synthesized tuning system, a television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver, featured with a Microcomputer M3870 driven synthesis system. The 3870 Fairchild, Motorola, SGS (SGS-Thomson)(MK3870) 8-bit microcontroller was a single chip implementation of Fairchild F8 (Mostek 3850). The microcontroller included up to 4 KB mask-programmable ROM, 64 bytes scratchpad RAM and up to 64 bytes executable RAM. The MCU also integrated 32-bit I/O and programmable timer. In addition to generic MK3870/xxx-xx markings the 3870 chips also had device order number in the form "MK#####x-xx".Mostek also produced MK38P70 - development version of the 3870 MCU that supported external EPROM chip. The system employed in the tv permits utilization of a frequency synthesizer tuning system which correctly tunes to a desired television station or channel even if the transmitted signals from that station are not precisely maintained at the proper frequencies even in combination of a fine tuning adjustable by the user.The 3870, manufactured by Mostek, is a 3850 and 3856 on a single chip.
A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The tuning consists of three discrete time periods. First, a settling time to allow channel change transients to settle; second, a short period of forced search at a relatively rapid rate to insure proper tuning; and third, a slower rate of step-by-step correction to accomodate for station drift and the like during reception. This third time period is initiated either by the passage of a fixed length of time following the start of the forced search period or by sensing a preestablished number of changes of state in the output of the frequency discriminator during the forced/search period.
1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase
comparator means having one input coupled with the first output of
said programmable frequency divider means and having another input
coupled with the second output of said programmable frequency
divider means for developing a control signal and applying such
control signal to said local oscillator for controlling the output
frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.
Both of the above mentioned pat
ents
are directed to frequency synthesizer tuning systems for use with
television receivers to enable operation of the receivers with
minimal viewer fine tuning adjustments. By the utilization of the
frequency synthesizer tuning systems of these patents, the fine
tuning adjustment which is necessary with conventional types of
television receiver tuning systems has been substantially
eliminated. The system employed in the '953 patent permits utilization
of a frequency synthesizer tuning system which correctly tunes to a
desired television station or channel even if the transmitted
signals from that station are not precisely maintained at the
proper frequencies. The '535 patent is directed to a signal seek
tuning system adaptation of the frequency synthesizer tuning system
of the '953 patent which still permits implementation of all of
the desired wide-band pull in range of the frequency synthesizer
system of the '953 patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.
The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st
of the circuitry of this receiver is conventional, and for that
reason it has not been shown in FIG. 1. Added to the conventional
television receiver circuitry of FIG. 1, however, is a frequency
synthesizer tuning system, in accordance with a preferred embodiment
of the invention, which is capable of automatically changing the
reference frequency when a frequency offset exists in the received
signal for a particular channel.Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circ
uit
for producing an output in response to the presence of vertical
synchronizatin pulses, a picture carrier detection circuit, and an
automatic gain control (AGC) amplifier. Outputs representative of
these sensor components are shown as being coupled over a group of
lead 20 to sensory circuitry 22, which in turn couples outputs
representative of the operation of these various sensor circuits to
a microprocessor unit 23 for controlling the operation of the
microprocessor unit.The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The microprocessor M3870 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he
interface between the keyboard 25, the microprocessor unit 23, and
the circuitry used in the frequency synthesizer portions of the
system. A commercially available microprocessor which has been used
for the microprocessor 23, and which forms the basis for the
diagramatic representation of the microprocessor in FIG. 2, is the
Matsushita Electronics Corporation MN1402 four-bit single-chip
microcomputer. This microcomputer has two, four-bit parallel input
ports labeled "A" and "B". In addition, three output ports, a five-bit
output port "C" and two four-bit output ports "D" and "E" are
provided. The internal configuration of the microcomputer 23 includes
an arithmetic logic unit (ALU), a read only memory (ROM) for
storing instructions and constants, and a random access memory
(RAM) used for data memory, arranged into four files, each file
containing 16 four-bit words. These words are selected by X and Y
registers and this memory is used, for example, for timers,
counters, etc., and also is used to hold intermediate results. To
facilitate an understanding of the operation of the system, a
portion of this memory is shown in FIG. 2 as a clock 81 and a
reversible counter 82 connected between the "B" input port and the
"D" output port. The microcomputer 23 is programmed to permit it to
operate in conjunction with the remainder of the circuits shown in
FIG. 2. The programming techniques are standard, and the
microcomputer 23 itself is a standard commercially available
circuit component.There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the tim
e
division multiplex sequence of operation of the microcomputer 23
to the five latch circuits 44, 45, 46, 49 and 50, respectively. At
any given time in the sequence, only one of these latch circuits is
enabled for operation. A latch load signal is applied from the
upper output (EO3) at each cycle of operation of the signals
appearing on the E output port to set the latch circuit which is
enabled by the output of the decoding circuit 52 with the data
appearing on the other inputs to the latch circuit. This data
simultaneously appears on the four outputs of the D output port of
the microcomputer 23.Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The s
ystem
shown in the drawings has a capability of correcting for frequency
offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2
MHz on channels 6 and 13. The remainder of the channels have a
range between these two values.If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.
The comparator 61 simply is a conventional comparator for determining whether or not the output of the frequency discriminator is positive or negative, as indicated in the upper waveform of FIG. 5. The comparators 62 and 63 are each adjusted with appropriate reference input levels to provide a narrow window centered about the center tuning frequency (fc) of the receiver. If the tuning of the receiver, as indicated by the output of the frequency discriminator 60, is outside this window on either side of the central axis shown in FIG. 5, one output condition is indicated on the input terminal B11 of the microcomputer. Only when the tuning frequency is within the tuning window, indicative of a properly tuned receiver, is the appropriate input applied to the microcomputer input terminal B11. This input overrides any other input that may be present on the input terminal B12 and is indicative of a properly tuned receiver. The input from the frequency discriminator 60, as applied to the microcomputer on its input port B12, is used to determine the direction of operation of the counter 82 of the microcomputer for the localized search count signals applied to the latch circuits 49 and 50 to change the count of the reference programmable divider counter 35 on a step-by-step basis.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this sign
al
is identified by the microcomputer 23 to cause the counter 82 in
it to operate in the reverse direction. As this count is applied on
a step-by-step basis through the latch circuits 49 and 50 to the
reference counter 35, the division ratio or count of the reference
counter (divider) 35 is changed. As a result, the reference
oscillator signal applied to the phase comparator 37 causes the
phase comparator 37 output to drive the local oscillator frequency
in a direction opposite to that considered in the first example.
This is shown by the vector interconnecting the top of the arrow
representative of f2 to point A on the time/frequency graph of FIG.
5.As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in th
e
first example considered for frequency f1; so that the counter 82
of the microprocessor 23 operates to change the count in the
reference counter 35 in a manner to cause the local oscillator
frequency to go higher toward a frequency f3 +Δf, as shown in FIG.
5.A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.
The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the microcomputer 23 causes a signal to be applied through the outputs of the E output port to the decoder circuit 52 indicative of the completion of this time interval. The decoder 52 then applies a pulse on an output lead connected to the B13 input of the B input port of the microcomputer 23. This pulse is sensed by the microcomputer 23 and is applied to the clock 81 to change the clock rate to a much slower rate, approximately one-third (1/3) or one-fourth (1/4) the rate used previously during the forced search mode of operation. This then permits the system to accomodate station drifts which normally occur at a very slow rate during the transmission and reception of a television signal. As a consequence, it is possible to use more filtering in the filter 39 on the tuning line (FIG. 1) and employ a smaller frequency window for the channel verification sensed by the circuitry shown in FIG. 3.
The result is a more precise tuning from the receiver than is otherwise possible if only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output signal to the SNS1 sensory input of the microcomputer 23 only when vertical synchronizing signal components are present.
In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
For a system that does not use signal seek operation, only the frequency discriminator sensory input is required for proper operation. The discriminator 60 is used for both fine tuning direction information and to produce a frequency window to indicate the presence of a correctly tuned station (channel verification). Initially, after a channel change, there is a 250 millisecond settling time, the same as the operation described above with compatible seek. After that, however, comes a period of time where a forced localized search is produced by the microcomputer 23. The forced search is needed to insure that the system will correctly tune to stations that initially may be tuned to the undesired zero voltage crossover in the right half of the upper curve of FIG. 5. Such signals may be within the frequency window of the discriminator 60; and if a search is not forced, this system will not correctly tune. The compatible seek system described previously correctly tunes the local oscillator without a forced search, because the picture carrier detector and vertical detector do not give an output for this situation and the system automatically goes into its search mode of operation. However, the non-seek system does not have a picture carrier sensor input and must be forced to search for an initial period of time sufficient to allow the system to tune up to its maximum frequency and then reset (loop) back to a frequency of 2 Δf lower. Then it is tuned to the positive left half portion of the discriminator curve (FIG. 5) and the frequency window created by the discriminator 60 is sufficient to insure proper tuning. If the discriminator output produced by the desired incoming signal created an initial situation that produces the correct tuning direction information, i.e., in the left half of the curve of FIG. 5, or in the right half portion that gives the correct direction and
frequency window information, the forced search would not be needed. However, the forced search will produce a correct tuning situation anyway. In these cases, the tuning either is correct to begin with or correct tuning is reached quickly. Then, even though the forced search is active, it simply alternates up and down through the correct tuning point because each time the receiver is tuned a little high in frequency, it produces a negative output from the discriminator 60; and the tuning direction signal causes the system to tune down in frequency.
Then, a positive discriminator output is produced, and the system tunes up in frequency. This continues until the forced search is removed by time-out of the microcomputer 23 (a fraction of a second). At such time, the receiver is correctly tuned by the frequency window of the discriminator to be very near fc. The system cannot tune to the undesired discriminator crossover shown in the right half portion of FIG. 5 because the polarity of the tuning direction signal always causes it to tune away from that point.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the inventi
on, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.
M206 PLL TV MICROCOMPUTER INTERFACE:
HIGHLY INTEGRATED SOLUTION INCLUDING PLL SYNTHESIZER, NV MEMORY, D/A CONVERTERS, BAND SELECT OUTPUTS,CLOCK OSCILLATOR, IR SIGNAL PRE PROCESSOR 32 x 16 BITS AND OF NV SERIAL MEMORY BUS INTERFACE WITH LIFETIMES OF 104 CYCLES/WORD AND MINIMUM 10 YEARS RETENTION STORES TUNING
- DATA FOR 30 CHANNELS PLUS PRESET VAL PRE-PROCESSOR UES FOR THE SIX ANALOG FOR OUTPUTS
- INFRARED REMOTE CONTROL SIGNALS REDUCES COMPONENT SIX PWMCOUNT
- D/A CONVERTERS WITH 64-STEP RESOLUTION
- FOUR OPEN-DRAIN BAND SELECT OUTPUTS ON-CHIP RATED 4 MHz TOCLOCK 13.2 V
- OSCILLATOR WITH INTEGRATED BUFFERED OUTPUT
- DIGITAL POWER-ON RESET 3-WIRE SERIAL BUS TO LOAD/READ INTERNAL REGISTERS.
The M206 is a highly integrated, programmable LSI integrated circuit for microcomputer controlled TV applications, realized using an advanced N-channel double polysilicon gate technology (NVMOS) that allows the integration of non-volatile memory and standard logic on the same chip. It contains a phase-locked loop (PLL) synthesizer, six pulse-width modulation (PWM) digital/analog converters, a four-bit parallel output buffer, clock oscillator with buffered output, pre-processor for infrared remote control signals and a 3-wire serial bus interface. The M206 interfaces with a microcomputer through the three-wire serial bus and is programmed by loading thirteen internal registers - twelve of which are readable to simplify programming. The PLL synthesizer requires an external 64 + 15/16 prescaler and divider and works with a phase comparator reference frequency of 0.9765 kHz. Outputs are provided to control the division ratio of the prescaler and to signal the out-of-lock condition to the microcomputer.
The infrared remote control signal pre-processor consists of a preamplifier, a squarer and a digital filter to separate noise from signals transmitted by the M708, M709 and M710 remote control transmitters. The output of this pre-processor is con- nected to the interrupt input of a microcomputer programmed to receive and decode the signal. The M206 is supplied with two separate 5 V supply inputs, each provided with internal power-on reset circuits. The first, VDD1, supplies the remote control and clock circuits in both standby and TV set operation. The second, VDD2, supplies the rest of the circuits and is only active during TV operation. The M206 is packaged in a 28-pin dual in-line plastic package.
To use the internal oscillator a 4MHz quartz crystal is connected between the pins CLIN and CLOUT. If an external clock is used this must be connected to CLIN and CLOUT left unconnectedor, if required as a clock output, loaded by a capacitor up to 15pF. The minimum external clock amplitude is 2V peak- to-peak. A buffered clock output, CLBUF, is provided which can drive up to three ± 100μA loads.
Register Reading
M206 registers are read by transmitting a 15-bit word with R/W low and the address of the register to be read in A0, A1, A2, A3. Bits D0-D7 can be high or low except when register 9 is addressed. If this word is received correctly the SBE line is immediately pulled low by the M206 and after 24μs the contents of the addressed register will be available to be read (see Figure 4). The microprocessor reads this data by sending eight clock pulses. Data is output on the low-high transition of SBC and the first data bit is available before the first clock pulse. Loading the Non-volatile Memory Data is stored in the 32 x 16-bit NV memory by loading the new contents into registers 10 and 11 then the address into register 9. The memory modify cycle begins when the address has been loaded and successful completion is indicated by a logic ”1” in bit zero of register 12. The time for a modify cycle varies from a few milliseconds to several hundred milliseconds during the device lifetime and is not internally limited. The storage operation should be aborted after one second if it proves unsuccessful. This is done by setting bit zero of register 12.
Reading the Non-volatile Memory
The NV memory is read by loading the address into register 9. The contents of the addressed word are automatically loaded into registers 10 and 11 and can be read by two register read operations. The data is ready 200μs after the address load. PLL Counter The PLL counter consists of a single counter that acts as the program counter (11-bit) and is swallow counter (4-bit) alternately. Data for the PLL counter is loaded into registers 6 and 7. Register 6 must be loaded first because the register 7 load operation initiates the data transfer to the PLL counter. The reference frequency is produced by dividing the clock frequency by 4096. With a 4MHz clock this gives a reference frequency of 976.5Hz. An out-of-lock signal is generated (output OL) when the phase error between the reference frequency and the input frequency exceed s 0.72 (2μs). The phase comparator output, PCO, has a threestate push pull configuration with a high level of 5V and a low level of 0V (with zero current sink or pump). The output impedance (both states) is typically 200Ω (400Ω maximum). The phase compara- tor output can be set to a high impedance state (both sink and pump transistors off) by setting bit 4 of register 8. The output is held in the high impedance state until this bit is reset. The phase comparatoroutput should be set to high impedance when changing band.
Recovering Lock
The phase comparator output can also be set to high and low levels to restore normal operation when the oscillator stops or the prescaler functions incorrectly at high frequency. In the first condition (oscillator off) the prescaler sometimes oscillates, at high frequency. The loop reacts by reducing the varicap voltage in an attempt to reduce the frequency, thus worsening the situation. This out-of-lock condition is signalled to the microprocessor (by the OL output) which can set the phase comparator output to low level, forcing the varicap voltage up and restarting the oscillator. The phase comparator output is forced low by setting bit 5 of register 8. After about 1ms this bit is automatically reset and the loop should lock again. When the out-of-lock condition is caused by a failure of the prescaler to operate correctly at high frequencies the loop reacts by increasing the voltage, hence the frequency, again worsening the situation. To recover from this condition the phase comparator output is set high. This is done by setting bit 6 of register 8 which, as in the previous case, resets itself after 1ms. The out-of-lock condition could also be caused by unwanted changesin band or PLL counter contents provoked by external interference (spikes on supply etc.). For this reason it is always advisable to reload the band and PLL counter registers before attempting to recover lock as described above. If the phase comparator output is in the high impedance state, the OL output signals the reset condition but not the out-of-lock condition.
Digital/Analog Converters
The six pulse-width modulation (PWM) D/A converters have a resolution of 64 steps and an output frequency of 16kHz (with 4MHz clock). At power on reset they are set to a duty cycle of zero. Power On Reset The V DD1 and VDD2 supplies have an integrated digital power on reset with a duration of 250ms. The reset condition is signalled by a low level on the out-of-lock output, OL. The microprocessor can test this condition by reading bit 1 of register 12. This bit is zero during power on reset and the OL output remains active until it is read. Reading this bit automatically restores it to a high state. During power on reset time commands from the micoprocessor are not acknowledged. Power on reset also sets the phase comparator output to a high impedance, state. It is restored by resetting bit 4 of register 8. Remote Control Signal Pre-processor This section contains a preamplifier, squarer, digital filter and a pulse generator.The digital filter enables the pulse generator only if three successive nega- tive going pulses (4 edges) are detected. The dis-tance between these pulses must be in the range 24-27μs (about 37-41kHz with a 4MHz clock). The input is not tested for the duration of the output pulse (192-256μs). If this pre-processor is used in conjunction with M709 or M710 remote control transmitters valid signals can be recognized in the presence of extreme noise conditions. Separating the signals from the noise externally in this way reduces the number of interrupts that the microcomputer has to handle thus allowing it to concentrate on other takes. To take advantage of this section the M708, 709, 710 transmitters must operate with a clock frequency in the range 492-508kHz. The input can be DC or AC compled to the I.R. preamplifier. In case of DC coupling the quiescent input level is suggested to be 1.5V.PHILIPS TDA2791 Television sound combination
TDA3561A (PHILIPS) Luminance+Chrominance+RGB MATRIX
PAL decoder TDA3561A
GENERAL DESCRIPTION
The
PHILIPS TDA3561A is a decoder for the PAL colour television standard.
It combines all functions required for the identification
and demodulation of PAL signals.
Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages.
The
circuit also contains separate inputs for data insertion, analogue as
well as digital, which can be used for text display systems (e.g.
(Teletext/broadcast antiope), channel number display, etc. Additional to
the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded.
The start of the
limiting
function is delayed by one line period. This avoids peak white limiting
by test patterns which have abrupt transitions from colour to white
signals.
· The brightness
control is obtained by inserting a variable pulse in the luminance
channel. Therefore the ratio of brightness variation and signal
amplitude at the three outputs will be identical and independent of the
difference in gain of the three channels. Thus discolouring due to
adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 µF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 µs for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kΩ luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
11. Brightness control
The black level of the RGB outputs can be set by the
voltage on this pin (see Fig.5). The black level can be set
higher than 4 V however the available output signal
amplitude is reduced (see pin 7). Brightness control also
operates on the black level of the inserted signals.
12, 14, 16. RGB outputs
The output circuits for red, green and blue are identical.
Output signals are 5,25 V (R, G and B) at nominal input
signals and control settings. The black levels of the three
outputs have the same value. The blanking level at the
outputs is 2,1 V. The peak white level is limited to 9,3 V.
When this level exceeded the output signal amplitude is
reduced via the contrast control (see pin 7).
13, 15, 17. Inputs for external RGB signals
The external signals must be a.c.-coupled to the inputs via
a coupling capacitor of about 100 nF. Source impedance
should not exceed 150 Ω. The input signal required for
a 5 V peak-to-peak output signal is 1 V peak-to-peak.
At the RGB outputs the black level of the inserted signal is
identical to that of normal RGB signals. When these inputs
are not used the coupling capacitors have to be connected
to the negative supply.
18, 19, 20. Black level clamp capacitors
The black level clamp capacitors for the three channels are
connected to these pins. The value of each capacitor
should be about 100 nF.
21, 22. Inputs (B-Y) and (R-Y) demodulators
The input signal is automatically fixed to the required level
by means of the burst phase detector and A.C.C.
generator which are connected to pin 21 and pin 22. As the
burst (applied differentially to those pins) is kept constant
by the A.C.C., the colour difference signals automatically
have the correct value.
23, 24. Burst phase detector outputs
At these pins the output of the burst phase detector is
filtered and controls the reference oscillator. An adequate
catching range is obtained with the time constants given in
the application circuit (see Fig.6).
25, 26. Reference oscillator
The frequency of the oscillator is adjusted by the variable
capacitor C1. For frequency adjustment interconnect pin
21 and pin 22. The frequency can be measured by
connecting a suitable frequency counter to pin 25.
28. Output of the chroma amplifier
Both burst and chroma signals are available at the output.
The burst-to-chroma ratio at the output is identical to that
at the input for nominal control settings. The burst signal is
not affected by the controls. The amplitude of the input
signal to the demodulator is kept constant by the A.C.C.
Therefore the output signal at pin 28 will depend on the
signal loss in the delay line.
TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET
.
LINE OSCILLATOR (two levels switching)
.
PHASE COMPARISON BETWEEN SYN CHRO-PULSE AND OSCILLATOR VOLTAGE Ø 1, ENABLED BY AN INTERNAL PULSE,
.
PHASE (better parasitic COMPARISON immunity)
BETWEEN THE FLYBACK PULSES AND THE OSCILLATOR VOL COINCIDENCE TAGE Ø 2
DETECTOR PROVIDING A FILTER LARGE HOLD-IN-RANGE CHARACTERISTICS AND GATE
SWITCHING FOR VIDEO RECORDER NOISE APPLICATION GATED SYNCHRO SEPARATOR
.
FRAME PULSE SEPARATOR
.
BLANKING AND SANDCASTLE OUTPUT
.
HORIZONTAL PULSES POWER STAGE PHASE LAGGING SWITCHING CIRCUIT OF CONTROL OUTPUT PULSE WIDTH
SEPARATED SUPPLY VOLTAGE OUTPUT STAGE ALLOWING DIRECT DRIVE OF SECURITY SCR’S CIRCUIT CIRCUIT MAKES THE OUTPUT PULSE SUPPRESSED WHEN LOW SUPPLY VOLTAGE.
The TDA2593 is a circuit intended for the horizontal deflection of color TV sets, suppliedwith transistors or SCR’S.
TDA4433 TV SIGNAL IDENTIFICATION CIRCUIT AND AFC INTERFACE
.
IDENTIFICATION OF TRUE TV STATIONS
.
LOW ONLY IMPEDANCE OUTPUT OF THE IDENTIFICATION SIGNAL
DIGITAL CONTROLSIGNAL FOR AUTOMATIC SEARCH AND AFC OPERATION
THERMAL COMPENSATION OF THE VOLTAGE REGULATOR.
The TDA4433 is a monolithic integrated circuit in a 14 lead dual-in-line plastic package. It integrates the following functions :
- TV signal identificator - Sync. separator - Threshold detector - Digital Interface - Voltage regulator.
TV Signal Identification Circuit
The circuit recognizes only TV signals by checking logically during one line the coincidence between the horizontal flyback pulse and the pulse detected by a sync. separator. The signal identification is carried out by charging the capacitor connected to pin 5 ; when the capacitor voltage overcomes a fixed threshold voltage, a Schmitt trigger switches and enables the AFC control. If a TV signal is recognized, the capacitor is slightly charged every line and its voltage reaches the thresholdafter a number of line which is defined by the value of the capacitor itself. The sensitivity of the identification circuit, hence the number of lines required to charge the capacitor, can be adjusted by means of the resistor connected between pin 11 and ground. When the identification has been made, a signal (level L) is available at pin 10. Threshold Circuit The circuit detects 3 ranges of AFC voltage and in combination with the TV signal identification circuit drives the electronic switches.
The TDA4433 has two separate outputs which can have only two states, high (H) or low (L). The outputs at pin 2 and at pin 6 remain at a low level with no video signal input or with a video signal not identified as a true TV signal. Both pin 2 and pinare open collector outputs and must be pulled-up to the positive supply voltage by external resistors. Voltage Regulator The circuit can deliver 1 mA and it can be used as D/A converter reference to supply fine tuning voltage.
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