Obsolete Technology Tellye !

True Televisions have the CRT Tube !! Welcome to the Obsolete Technology Tellye Web Museum. Here you will see a TV Museum showing many Old Tube Television sets all with the CRT Tube, B/W ,color, Digital, and 100HZ Scan rate, Tubes technology. This is the opportunity on the WEB to see, one more time, what real technology WAS ! In the mean time watch some crappy lcd picture around shop centers (but don't buy them, or money lost, they're already broken when new) !!!

Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical Obsolete technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.

Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:
- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....

Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !
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©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of Engineer Frank Sharp. NOTHING HERE IS FOR SALE !
All posts are presented here for informative, historical and educative purposes as applicable within Fair Use.

Monday, April 3, 2023

PHILIPS 14PT1356 CHASSIS L01.2E AA INTERNAL VIEW

PHILIPS L01 chassis Circuit Description

The PHILIPS L01 chassis is a global TV chassis for the model year 2001 and is used for TV sets with screen sizes from 14” - 21” (small screen) to 21” - 32” (large screen). The standard architecture consists of a Main panel, a Picture Tube panel, a Side I/O panel (not al executions) and a Top Control panel. The Main panel consists primarily of conventional components with hardly any surface mounted devices.

The functions for video processing, microprocessor (μP) and teletext (TXT) decoder are combined in one IC (TDA958xH), the so-called Ultimate One Chip (UOC). This chip is (surface) mounted on the copper side of the main panel.with PHILIPS UOC BASED CHASSIS development,

The Ultimate One Chip Television provides manufacturers with a single chip, global TV concept with a wide range of options using advanced proven technologies for both mixed-signal and digital processes.
By integrating the core functions of picture and sound decoding, digital processing and teletext and on-screen display into a single package, the Ultimate One Chip Television reduces the number of peripheral devices required. It allows the manufacturer to design a single chassis for a world family of television receivers. The same chassis can be used for different size tubes, for single and multiple transmission standard receivers (PAL/NTSC/SECAM), and can provide a range of facilities including stereo sound and different teletext standards.

The analog circuitry, built in Philips' BiMOS process technology, is primarily concerned with the colour decoding and other picture and sound processing. The digital circuitry, built with Philips' CMOS technology, looks after on screen display using a microprocessor core and specialist caption decoder and teletext circuitry. Also included as part of the digital circuitry is one time programmable (OTP) memory and up to 2K RAM. The process technologies are both regarded as amongst the most advanced in the industry, providing higher levels of integration and lower levels of power consumption than competitive processes.
The Ultimate One Chip Television requires lower power at start up, for operation and for standby, than other solutions currently available, providing the opportunity for 'green' sets. The TV signal processor includes a single, automatic search, PAL/NTSC or multi-standard decoder, with a multi-standard IF circuit incorporating an alignment free PLL (Phase Loop Lock) demodulator. Other features include multi-standard FM sound, with a choice of mono or stereo, an audio switch, which removes the need for separate external band-pass filters, and an automatic volume levelling circuit. The design was carried out initially at two of Philips Semiconductors design centres, with Southampton, UK, carrying out digital design and software development and Nijmegen, Netherlands responsible for analog design. The design team in Taiwan has since become involved in tailoring the design for specific applications.

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to television technology, and more particularly to providing television functionality on a single integrated circuit chip.
2. Background
Television systems have become increasingly complex as consumers continue to demand greater functionality and performance from television sets. Furthermore, the miniaturization of television systems demands that while complexity is increasing, that the size of electronic circuitry to support this complexity and performance must be reduced. At the same time, market forces continue to drive prices lower for television sets. Current electronic circuitry to support the functionality needed to receive audio and video signals that are either analog or digital and process those signals to provide a signal suitable for display on a television often consist of several integrated circuits. Furthermore, additional functionality related to value added features, such as teletext or e-commerce often requires additional integrated circuits.
What is needed is a system for providing television functionality and ancillary functionality on a single integrated chip to reduce costs and support the continued miniaturization of electronics for televisions.

The present invention provides a cost effective approach for implementing television functionality on a single integrated circuit chip (referred to herein as “TV on a Chip” or TVOC). A TVOC includes functionality to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All or substantially all functionality provided can be provided on a single integrated circuit. TVOC includes one or more of a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces.
The present invention addresses the conflicting consumer demands of television system miniaturization and reducing the cost of televisions.

The PHILIPS L01 is divided into 2 basic systems, i.e. mono and stereo sound. While the audio processing for the mono sound is done in the audio block of the UOC, an external audio processing IC is used for stereo sets. The tuning system features 100 video channels with on-screen display. The main tuning system uses a tuner, a microcomputer, and a memory IC mounted on the main panel. Also, in some type numbers, an FM radio is implemented with 40 pre-set channels. The microcomputer communicates with the memory IC, the customer keyboard, remote receiver, tuner, signal processor IC and the audio output IC via the I2C bus. The memory IC retains the settings for favourite stations, customer-preferred settings, and service/factory data. The on-screen graphics and closed caption decoding are done within the microprocessor, and then sent to the signal processor IC to be added to the main signal. The chassis uses a Switching Mode Power Supply (SMPS) for the main voltage source. The chassis has a ‘hot’ ground reference on the
primary side and a cold ground reference on the secondary side of the power supply and the rest of the chassis.

In mono sets, the signal goes via the SAW filter (position 1004 in case of QSS demodulation and 1003 in case of Intercarrier demodulation), to the audio demodulator part of the UOC IC7200. The audio output on pin 48 goes directly, via buffer 7943, to the audio amplifier (AN7523 at position 7902). The volume level is controlled at this IC (pin 9) by a ‘VolumeMute’ control line from the microprocessor. The audio signal from IC7902 is then sent to the speaker/ headphone output panel.
The video signal-processing path consists of the following
parts:
• RF signal processing.
• Video source selection.
• Video demodulation.
• Luminance/Chrominance signal processing.
• RGB control.
• RGB amplifier
The processing circuits listed above are all integrated in the UOC TV processor. The surrounding components are for the adaptation of the selected application. The I2C bus is for defining and controlling the signals.

RF Signal Processing:
The incoming RF signal goes to the tuner (pos. 1000), where the 38.9 MHz IF signal is developed and amplified. The IF signals then exits the tuner from pin 11 to pass through the SAW filter (position 1002 in case of QSS demodulation and 1003 in case of Intercarrier demodulation). The shaped signal is then applied to the IF processor part of the UOC (pos. 7200). Tuner AGC (Automatic Gain Control) will reduce the tuner gain and thus the tuner output voltage when receiving strong RF signals. Adjust the AGC take-over point via the Service Alignment Mode (SAM). The tuner AGC starts working when the video-IF input reaches a certain input level and will adjust this level via the I2C bus. The tuner AGC signal goes to the tuner (pin 1) via the open collector output (pin 22) of the UOC. The IC also generates an Automatic Frequency Control (AFC) signal that goes to the tuning system via the I2C bus, to provide frequency correction when needed. The demodulated composite video signal is available at pin 38 and then
buffered by transistor 7201.

Video Source Selection
The Composite Video Blanking Signal (CVBS) from buffer 7201 goes to the audio carrier trap filters (1200 and 1201) to remove the audio signal. The signal then goes to pin 40 of IC7200. The internal input switch selects the following input signals:
• Pin 40: terrestrial CVBS input
• Pin 42: external AV1 CVBS input
• Pin 44: external Side I/O CVBS or AV2 Luminance (Y) input
• Pin 45: external AV2 Chrominance (C) input

Once the signal source is selected, a chroma filter calibration is performed. The received colour burst sub-carrier frequency is used for this. Correspondingly, the chroma band pass filter for PAL processing or the cloche filter for SECAM processing is switched on. The selected luminance (Y) signal is supplied to the horizontal and vertical synchronisation processing circuit and to the luminance processing circuit. In the luminance- processing block, the luminance signal goes to the chroma trap filter. This trap is switched 'on' or 'off', depending on the colour burst detection of the chroma calibration circuit. The group delay correction part can be switched between the BG and a flat group delay characteristic. This has the advantage that in multi-standard receivers no compromise has to be made for the choice of the SAW filter.

Video Demodulation
The colour decoder circuit detects whether the signal is a PAL, NTSC or SECAM signal. The result is made known to the auto system manager. The PAL/NTSC decoder has an internal clock generator, which is stabilised to the required frequency by using the 12 MHz clock signal from the reference oscillator of the microcontroller/teletext decoder. The base-band delay line is used to obtain a good suppression of cross colour effects. The Y signal and the delay line outputs U and V are applied to the luminance/chroma signal processing part of the TV processor.

Luminance/Chrominance Signal Processing
The output of the YUV separator is fed to the internal YUV switch, which switches between the output of the YUV separator or the external YUV (for DVD or PIP) on pins 51-53. Pin 50 is the input for the insertion control signal called ‘FBL-1’. When this signal level becomes higher than 0.9 V (but less than 3 V), the RGB signals at pins 51, 52 and 53 are inserted into the picture by using the internal switches.

Also some picture improvement features are implemented in
this part:
• Black stretch This function corrects the black level of incoming signals, which have a difference between the black level and the blanking level. The amount of extension depends upon the difference between actual black level and the darkest part of the incoming video signal level. It is detected by means of an internal capacitor.
• White stretch This function adapts the transfer characteristic of the luminance amplifier in a non-linear way depending on the average picture content of the luminance signal. It operates in such a way that maximum stretching is obtained when signals with a low video level are received. For bright pictures, stretching is not active.
• Dynamic skin tone correction This circuit corrects (instantaneously and locally) the hue of those colours which are located in the area in the UV plane that matches the skin tone. The correction is dependent on the luminance, saturation and distance to the preferred axis. The YUV signal is then fed to the colour matrix circuit, which converts it to R, G and B signals. The OSD/TXT signal from the microprocessor is mixed with the main signal at this point, before being output to the CRT board (pins 56, 57 and 58).

RGB Control
The RGB control circuit enables the picture parameters contrast, brightness and saturation to be adjusted, by using a combination of the user menus and the remote control. Additionally automatic gain control for the RGB signals via cut- off stabilisation is achieved in this functional block to obtain an accurate biasing of the picture tube. Therefor this block inserts the cut-off point measuring pulses into the RGB signals during the vertical retrace period. The•••following additional controls are used: Black current calibration loop Because of the 2-point black current stabilisation circuit, both the black level and the amplitude of the RGB output signals depend on the drive characteristics of the picture tube. The system checks whether the returning measuring currents meet the requirements, and adapt the output level and gain of the circuit when necessary. After stabilisation of the loop, the RGB drive signals are switched on. The 2-point black level system adapts the drive voltage for each cathode in such
a way that the two measuring currents have the right value. This is done with the measurement pulses during the frame flyback. During the first frame, three pulses with a current of 8 μA are generated to adjust the cut off voltage. During the second frame, three pulses with a current of 20 μA are generated to adjust the ‘white drive’. This has as a consequence, that a change in the gain of the output stage will be compensated by a gain change of the RGB control circuit. Pin 55 (BLKIN) of the UOC is used as the feedback input from the CRT base panel. Blue stretch This function increases the colour temperature of the bright scenes (amplitudes which exceed a value of 80% of the nominal amplitude). This effect is obtained by decreasing the small signal gain of the red and green channel signals, which exceed this 80% level. Beam current limiting A beam current limiting circuit inside the UOC handles the contrast and brightness control for the RGB signals. This prevents the CRT from being overdriven, which could
otherwise cause serious damage in the line output stage. The reference used for this purpose is the DC voltage on pin 54 (BLCIN) of the TV processor. Contrast and brightness reduction of the RGB output signals is therefore proportional to the voltage present on this pin. Contrast reduction starts when the voltage on pin 54 is lower than 2.8 V. Brightness reduction starts when the voltage on pin 54 is less than 1.7 V. The voltage on pin 54 is normally 3.3 V (limiter not active). During set switch ‘off’, the black current control circuit generates a fixed beam current of 1 mA. This current ensures that the picture tube capacitance is discharged. During the switch-off period, the vertical deflection is placed in an over-scan position, so that the discharge is not visible on the screen.

RGB Amplifier
From outputs 56, 57 and 58 of IC7200, the RGB signals are applied to the integrated output amplifier (7330) on the CRT panel. Via the outputs 7, 8 and 9, the picture tube cathodes are driven. The supply voltage for the amplifier is +200 V and is derived from the line output stage.

PHILIPS TDA93XX series TV signal processor-Teletext decoder with embedded m-Controller

GENERAL DESCRIPTION
The various versions of theTDA935X/6X/8X series combine the functions of a TV signal processor together with a m-Controller and US Closed Caption decoder. Most versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1or 10 page text. The ICs are intended to be used in economy television receivers with 90° and 110° picture tubes. The ICs have supply voltages of 8 V and 3.3 V and they are mounted in S-DIP envelope with 64 pins.

TV-signal processor
· Multi-standard vision IF circuit with alignment-free PLL
demodulator
· Internal (switchable) time-constant for the IF-AGC circuit
· A choice can be made between versions with mono
intercarrier sound FM demodulator and versions with
QSS IF amplifier.
· The mono intercarrier sound versions have a selective
FM-PLL demodulator which can be switched to the
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz).
The quality of this system is such that the external
band-pass filters can be omitted.
· Source selection between ‘internal’ CVBS and external
CVBS or Y/C signals
· Integrated chrominance trap circuit
· Integrated luminance delay line with adjustable delay
time
· Asymmetrical ‘delay line type’ peaking in the luminance
channel
· Black stretching for non-standard luminance signals
· Integrated chroma band-pass filter with switchable
centre frequency
· Only one reference (12 MHz) crystal required for the
m-Controller, Teletext- and the colour decoder
· PAL/NTSC or multi-standard colour decoder with
automatic search system
· Internal base-band delay line
· RGB control circuit with ‘Continuous Cathode
Calibration’, white point and black level off set
adjustment so that the colour temperature of the dark
and the light parts of the screen can be chosen
independently.
· Linear RGB or YUV input with fast blanking for external
RGB/YUV sources. The Text/OSD signals are internally
supplied from the m-Controller/Teletext decoder
· Contrast reduction possibility during mixed-mode of
OSD and Text signals
· Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
· Vertical count-down circuit
· Vertical driver optimized for DC-coupled vertical output
stages
· Horizontal and vertical geometry processing
· Horizontal and vertical zoom function for 16 : 9
applications
· Horizontal parallelogram and bow correction for large
screen picture tubes
· Low-power start-up of the horizontal drive circuit

m-Controller
· 80C51 m-controller core standard instruction set and
timing
· 1 ms machine cycle
· 32 - 128Kx8-bit late programmed ROM
· 3 - 12Kx8-bit Auxiliary RAM (shared with Display and
Acquisition)
· Interrupt controller for individual enable/disable with two
level priority
· Two 16-bit Timer/Counter registers
· WatchDog timer
· Auxiliary RAM page pointer
· 16-bit Data pointer
· IDLE and Power Down (PD) mode
· 14 bits PWM for Voltage Synthesis Tuning
· 8-bit A/D converter
· 4 pins which can be programmed as general I/O pin,
ADC input or PWM (6-bit) output
Data Capture
· Text memory for 1 or 10 pages
· In the 10 page versions inventory of transmitted Teletext
pages stored in the Transmitted Page Table (TPT) and
Subtitle Page Table (SPT)
· Data Capture for US Closed Caption
· Data Capture for 525/625 line WST, VPS (PDC system
A) and Wide Screen Signalling (WSS) bit decoding
· Automatic selection between 525 WST/625 WST
· Automatic selection between 625 WST/VPS on line 16
of VBI
· Real-time capture and decoding for WST Teletext in
Hardware, to enable optimized m-processor throughput
· Automatic detection of FASTEXT transmission
· Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
· Signal quality detector for video and WST/VPS data
types
· Comprehensive teletext language coverage
· Full Field and Vertical Blanking Interval (VBI) data
capture of WST data
Display
· Teletext and Enhanced OSD modes
· Features of level 1.5 WST and US Close Caption
· Serial and Parallel Display Attributes
· Single/Double/Quadruple Width and Height for
characters
· Scrolling of display region
· Variable flash rate controlled by software
· Enhanced display features including overlining,
underlining and italics
· Soft colours using CLUT with 4096 colour palette
· Globally selectable scan lines per row (9/10/13/16) and
character matrix [12x10, 12x13, 12x16 (VxH)]
· Fringing (Shadow) selectable from N-S-E-W direction
· Fringe colour selectable
· Meshing of defined area
· Contrast reduction of defined area
· Cursor
· Special Graphics Characters with two planes, allowing
four colours per character
· 32 software redefinable On-Screen display characters
· 4 WST Character sets (G0/G2) in single device (e.g.
Latin, Cyrillic, Greek, Arabic)
· G1 Mosaic graphics, Limited G3 Line drawing
characters
· WST Character sets and Closed Caption Character set
in single device

FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR
Vision IF amplifier The vision IF amplifier can demodulate signals with positive and negative modulation. The PLL demodulator is completely alignment-free. The VCO of the PLL circuit is internal and the frequency is fixed to the required value by using the clock frequency of the m-Controller/Teletext decoder as a reference. The setting of the various frequencies (38, 38.9, 45.75 and 58.75 MHz) can be made via the control bits IFA-IFC in subaddress 27H. Because of the internal VCO the IF circuit has a high immunity to EMC interferences. QSS Sound circuit (QSS versions) The sound IF amplifier is similar to the vision IF amplifier and has an external AGC decoupling capacitor. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved. The AM sound demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics. The AM signal is supplied to the output (pin 44) via the volume control. It is possible to get the AM output signal (not controlled on amplitude) on the QSS intercarrier output. The selection is made by means of the AM bit in subaddress 29H. Another possibility is that pin 35 is transferred to external audio input pin and pin 32 to (non-controlled) AM output pin. This can be realised by means of the setting the control bits CMB0 and CMB1 in subaddress 22H. FM demodulator and audio amplifier (mono versions) The FM demodulator is realised as narrow-band PLL with external loop filter, which provides the necessary selectivity without using an external band-pass filter. To obtain a good selectivity a linear phase detector and a constant input signal amplitude are required. For this reason the intercarrier signal is internally supplied to the demodulator via a gain controlled amplifier and AGC circuit. The nominal frequency of the demodulator is tuned to the required frequency (4.5/5.5/6.0/6.5 MHz) by means of a calibration circuit which uses the clock frequency of the m-Controller/Teletext decoder as a reference. The setting to the wanted frequency is realised by means of the control bits FMA and FMB in control byte 29H. When required an external sound band-pass filter can be inserted in front of the narrow-band PLL. In that case pin 32 has to be switched to sound IF input by means of the bits SIF (subaddress 21H) and CMB0/CMB1 (subaddress 22H). When the sound IF input is selected the subcarrier output (90° versions) or AVL function (110° versions) are not available. From the output status bytes it can be read whether the PLL frequency is inside or outside the window and whether the PLL is in lock or not. With this information it is possible to make an automatic search system for the incoming sound frequency. This can be realised by means of a software loop which switches the demodulator to the various frequencies and then select the frequency on which a lock condition has been found. The deemphasis output signal amplitude is independent of the TV standard and has the same value for a frequency deviation of ±25 kHz at the 4.5 MHz standard and for a deviation of ±50 Khz for the other standards. The audio control circuit contains an audio switch and volume control. In the mono intercarrier sound versions the Automatic Volume Levelling (AVL) function can be activated. The pin to which the external capacitor has to be connected depends on the IC version. For the 90° types the capacitor is connected to the EW output pin (pin 20). For the 110° types a choice must be made between the AVL function and a sub-carrier output for comb filter applications. This choice is made via the CBM0 and CMB1bits (in subaddress 22H). When the AVL is active it automatically stabilises the audio output signal to a certain level. The signal on the deemphasis pin (28) can be supplied to the SCART connector via a buffer stage. It is also possible to use this pin as additional audio input. In that case the internal signal must, of course, be switched off. This can be realised by means of the sound mute bit (SM in subaddress 29H). When the IF circuit is switched to positive modulation the internal signal on the deemphasis pin is automatically muted.

Video switches
The video switch has one input for an external CVBS or Y/C signal. The switch configuration is given in Fig.40. The selected CVBS signal can be supplied to pin 38, the IF video output. The selection between both signals is realised by means of the SVO bit in subaddress 22H. The video ident circuit can be connected to the incoming ‘internal’ video signal or to the selected signal. This ident circuit is independent of the synchronisation and can be used to switch the time-constant of the horizontal PLL depending on the presence of a video signal (via the VID bit). In this way a very stable OSD can be realised. Because of the availability of the Y/C input and the subcarrier output an external comb-filter can be applied. In that case an external video switch (or comb-filter with integrated switch) must be used. The subcarrier output is combined with a 3-level output switch (0 V, 4 V and 8 V). The output level and the availability of the subcarrier signal is controlled by the CMB1 and CMB0 bits. The output can be used to switch sound traps etc. It is also possible to use this pin for the connection of the AVL capacitor, external sound IF input or as AM output. The possibilities are illustrated in table 1. Synchronisation circuit The IC contains separator circuits for the horizontal and vertical sync pulses and a data-slicing circuit which extracts the digital teletext data from the analog signal. The horizontal drive signal is obtained from an internal VCO which is running at a frequency of 25 MHz. This oscillator is stabilised to this frequency by using a 12 MHz signal coming from the reference oscillator of the m-Controller/Teletext decoder. The horizontal drive is switched on and off via the soft start/stop procedure. This function is realised by means of variation of the TON of the horizontal drive pulses. In addition the horizontal drive circuit has a ‘low-power start-up’ function. The vertical synchronisation is realised by means of a divider circuit. The vertical ramp generator needs an external resistor and capacitor. For the vertical drive a differential output current is available. The outputs must be DC coupled to the vertical output stage. In the types which are intended for 90° picture tubes the following geometry parameters can be adjusted:
· Horizontal shift
· Vertical amplitude
· Vertical slope
· S-correction
· Vertical shift

The types which are intended to be used in combination with 110° picture tubes have an East-West control circuit in stead of the AVL function. The additional controls for these types are: · EW width · EW parabola width · EW upper and lower corner parabola correction · EW trapezium correction · Vertical zoom and in some versions: · horizontal parallelogram and bow correction. Chroma and luminance processing The chroma band-pass and trap circuits (including the SECAM cloche filter) are realised by means of gyrators and are tuned to the right frequency by comparing the tuning frequency with the reference frequency of the colour decoder. The luminance delay line and the delay cells for the peaking circuit are also realised with gyrators. The circuit contains a black stretcher function which corrects the black level for incoming signals which have a difference between the black level and the blanking level. Colour decoder The ICs can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need external reference crystals but has an internal clock generator which is stabilised to the required frequency by using the 12 MHz clock signal from the reference oscillator of the m-Controller/Teletext decoder. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the colour killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO-bit (Forced Colour On) in subaddress 21H. The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 20H) prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, viz: the divided 12 MHz reference frequency (obtained from the m-Controller) which is used to tune the PLL to the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode. The base-band delay line (TDA 4665 function) is integrated. This delay line is also active during NTSC to obtain a good suppression of cross colour effects. The demodulated colour difference signals are internally supplied to the delay line. RGB output circuit and black-current stabilization In the RGB control circuit the signal is controlled on contrast, brightness and saturation. The ICs have a linear input for external RGB signals. It is possible to use this input for the insertion of YUV signals. Switching between RGB and YUV can be realised via the YUV-bit in subaddress 2BH. The signals for OSD and text are internally supplied to the control circuit. The output signal has an amplitude of about 2 Volts black-to-white at nominal input signals and nominal settings of the various controls. To obtain an accurate biasing of the picture tube the ‘Continuous Cathode Calibration’ system has been included in these ICs. A black level off set can be made with respect to the level which is generated by the black current stabilization system. In this way different colour temperatures can be obtained for the bright and the dark part of the picture. The black current stabilization system checks the output level of the 3 channels and indicates whether the black level of the highest output is in a certain window (WBC-bit) or below or above this window (HBC-bit). This indication can be read from the status byte 01 and can be used for automatic adjustment of the Vg2 voltage during the production of the TV receiver. During switch-off of the TV receiver a fixed beam current is generated by the black current control circuit. This current ensures that the picture tube capacitance is discharged. During the switch-off period the vertical deflection is placed in an overscan position so that the discharge is not visible on the screen.

SOFTWARE CONTROL
The CPU communicates with the peripheral functions using Special function Registers (SFRs) which are addressed as RAM locations. The registers for the Teletext decoder appear as normal SFRs in the m-Controller memory map and are written to these functions by using a serial bus. This bus is controlled by dedicated hardware which uses a simple handshake system for software synchronisation. For compatibility reasons and possible re-use of software blocks, the I2C-bus control for the TV processor is organised as in the stand-alone TV signal processors. The TV processor registers cannot be read, so when the content of these registers is needed in the software, a copy should be stored in Auxiliary RAM or Non Volatile RAM.

Notes
1. When the 3.3 V supply is present and the m-Controller is active a ‘low-power start-up’ mode can be activated. When
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal TOFF and
the TON grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
4. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
5. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the m-Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. Measured at 10 mV (RMS) top sync input signal.
8. Via this pin (38) both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
9. So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.49. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.

Adjustment of geometry control parameters
The deflection processor offers 5 control parameters for
picture alignment, viz:
· S-correction
· vertical amplitude
· vertical slope
· vertical shift
· horizontal shift.
The 110° types offer in addition:
· EW width
· EW parabola width
· EW upper/lower corner parabola
· EW trapezium correction.
· Vertical zoom
· Horizontal parallelogram and bow correction for some
versions in the range
It is important to notice that the ICs are designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and therefore not available). For a particular combination of picture tube type, vertical output stage and EW output stage it is determined which are the required values for the settings of S-correction,EW parabola/width ratio and EW corner/parabola ratio. These parameters can be preset via the I2C-bus, and do not need any additional adjustment. The rest of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV-set adjustments. The vertical shift control is meant for compensation of off sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in first order approximation proportional to the value of the off set, and to the square of the S-correction needed. The necessity to use the vertical shift alignment depends on the expected off sets in vertical output stage and picture tube, on the required value of the S-correction, and on the demands upon vertical linearity. For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SBL bit HIGH. In this mode the RGB-outputs are blanked during the second half of the picture. There are 2 different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed. The top of the picture is placed by adjustment of the vertical amplitude, and the bottom by adjustment of the vertical slope. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrical with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the right setting and should not be changed. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1F). Then the top of the picture is placed by adjustment of the vertical amplitude and the bottom by adjustment of the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjustment of the EW width and the horizontal shift. Finally (if necessary) the left- and right-hand sides of the picture are aligned in parallel by adjusting the EW trapezium control. To obtain the full range of the vertical zoom function the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom DAC at position 19 HEX.

SCAVEM (if present)

Synchronisation
Inside IC7200 (part D), the vertical and horizontal sync-pulses
are separated. These ‘H’ and ‘V’ signals are synchronised with
the incoming CVBS signal. They are then fed to the H- and V-
drive circuits and to the OSD/TXT circuit for synchronisation of
the On Screen Display and Teletext (or Closed Caption)
information.

Deflection
Horizontal Drive
The horizontal drive signal is obtained from an internal VCO, which is running at twice the line frequency. This frequency is divided by two, to lock the first control loop to the incoming signal. When the IC is switched ‘on’, the ‘Hdrive’ signal is suppressed until the frequency is correct. The ‘Hdrive’ signal is available at pin 30. The ‘Hflybk’ signal is fed to pin 31 to phase lock the horizontal oscillator, so that TS7462 cannot switch ‘on’ during the flyback time. The ‘EWdrive’ signal for the E/W circuit (if present) is available on pin 15, where it drives transistor 7400 to make linearity corrections in the horizontal drive. When the set is switched on, the ‘+8V’ voltage goes to pin 9 of IC7200. The horizontal drive starts up in a soft start mode. It starts with a very short TON time of the horizontal output transistor. The TOFF of the transistor is identical to the time in normal operation. The starting frequency during switch on is therefore about 2 times higher than the normal value. The ‘on’ time
is slowly increased to the nominal value in 1175 ms. When the nominal value is reached, the PLL is closed in such a way that only very small phase corrections are necessary. The ‘EHTinformation’ line on pin 11 is intended to be used as a ‘X-ray’ protection. When this protection is activated (when the voltage exceeds 6 V), the horizontal drive (pin 30) is switched 'off' immediately. If the ‘H-drive’ is stopped, pin 11 will become low again. Now the horizontal drive is again switched on via the slow start procedure. The ‘EHTinformation’ line (Aquadag) is also fed back to the UOC IC7200 pin 54, to adjust the picture level in order to compensate for changes in the beam current. The filament voltage is monitored for ‘no’ or ‘excessive’ voltage. This voltage is rectified by diode 6447 and fed to the emitter of transistor TS7443. If this voltage goes above 6.8 V, transistor TS7443 will conduct, making the ‘EHT0’ line ‘high’. This will immediately switch off the horizontal drive (pin 30) via the slow stop procedure.
The horizontal drive signal exits IC7200 at pin 30 and goes to TS7462, the horizontal driver transistor. The signal is amplified and coupled to the base circuit of TS7460, the horizontal output transistor. This will drive the line output transformer (LOT) and associated circuit. The LOT provides the extra high voltage (EHT), the VG2 voltage and the focus and filament voltages for the CRT, while the line output circuit drives the horizontal deflection coil.

Vertical Drive
A divider circuit performs the vertical synchronisation. The vertical ramp generator needs an external resistor (R3245, pin 20) and capacitor (C2244, pin 21). A differential output is available at pins 16 and 17, which are DC-coupled with the vertical output stage. To avoid damage of the picture tube when the vertical deflection fails, the ‘V_GUARD’ output is fed to the beam current limiting input. When a failure is detected, the RGB- outputs are blanked. When no vertical deflection output stage is connected, this guard circuit will also blank the output signals. These ‘V_DRIVE+’ and ‘V_DRIVE-‘ signals are applied to the input pins 1 and 2 of IC 7471 (full bridge vertical deflection amplifier). These are voltage driven differential inputs. As the driver device (IC 7200) delivers output currents, R3474 and R3475 convert them to voltage. The differential input voltage is compared with the voltage across measuring resistor R3471 that provides internal feedback information. The voltage across this measuring
resistor is proportional to the output current, which is available at pins 4 and 7 where they drive the vertical deflection coil (connector 0222) in phase opposition. IC 7471 is supplied by +13 V. The vertical flyback voltage is determined by an external supply voltage at pin 6 (VlotAux+50V). This voltage is almost totally available as flyback voltage across the coil, this being possible due to the absence of a coupling capacitor (which is not necessary, due to the ‘bridge’ configuration).

Deflection Corrections
The Linearity Correction A constant voltage on the horizontal deflection coil should result in a sawtooth current. This however is not the case as the resistance of the coil is not negligible. In order to compensate for this resistance, a pre-magnetised coil L5457 is used. R3485 and C2459 ensure that L5457 does not excite, because of its own parasite capacitance. This L5457 is called the 'linearity coil'.

The Mannheim Effect
When clear white lines are displayed, the high-voltage circuit is heavily loaded. During the first half of the flyback, the high voltage capacitors are considerable charged. At that point in time, the deflection coil excites through C2465. This current peak, through the high-voltage capacitor, distorts the flyback pulse. This causes synchronisation errors, causing an oscillation under the white line. During t3 - t5, C2490//2458 is charged via R3459. At the moment of the flyback, C2490//2458 is subjected to the negative voltage pulses of the parabola as a result of which D6465 and D6466 are conducting and C2490//2458 is switched in parallel with C2456//2457. This is the moment the high-voltage diodes are conducting. Now extra energy is available for excitation through C2465 and the line deflection. As a consequence, the flyback pulse is less distorted.

The S-Correction
Since the sides of the picture are further away from the point of deflection than from the centre, a linear sawtooth current would result in a non-linear image being scanned (the centre would be scanned slower than the sides). For the centre-horizontal line, the difference in relation of the distances is larger then those for the top and bottom lines. An S-shaped current will have to be superimposed onto the sawtooth current. This correction is called finger-length correction or S-correction. C2456//2457 is relatively small, as a result of which the sawtooth current will generate a parabolic voltage with negative voltage peaks. Left and right, the voltage across the deflection coil decreases, and the deflection will slow down; in the centre, the voltage increases and deflection is faster. The larger the picture width, the higher the deflection current through C2456//2457. The current also results in a parabolic voltage across C2484//2469, resulting in the finger length correction proportionally increasing
with the picture width. The east/west drive signal will ensure the largest picture width in the centre of the frame. Here the largest correction is applied.

East/West Correction
In the PHILIPS L01, there are three types of CRTs, namely the 100o, 110o and wide screen CRTs. The 100o CRT is raster- correction-free and does not need East/West correction. The 110o 4:3 CRT comes with East/West correction and East/ West protection. The wide screen TV sets have all the correction of the 110 4:3 CRT and also have additional picture format like the 4:3 format, 16:9, 14:9, 16:9 zoom, subtitle zoom and the Super-Wide picture format A line, written at the upper- or lower side of the screen, will be larger at the screen centre when a fixed deflection current is used. Therefore, the amplitude of the deflection current must be increased when the spot approaches the centre of the screen. This is called the East/West or pincushion correction. The ‘Ewdrive’ signal from pin 15 of IC7200 takes care for the correct correction. It drives FET TS7400. It also corrects breathing of the picture, due to beam current variations (the EHT varies dependent of the beam current). This correction is derived from the ‘
EHTinformation’ line. Two protections are built-in for the E/W circuit: over-current and over-voltage protection. See paragraph Power Supply. Panorama The panorama function is only used in 16:9 sets. This is a function to enable the 4:3 and Super-Wide feature. It drives the ‘Bass_panorama’ line, to activate relay 1400. When this relay is switched on, the capacitors 2453//2454 are added in parallel to the default S-correction capacitors 2456//2457. This results in an increased capacitance, a lower resonance frequency of the line deflection coil and the S-correction capacitors and therefore a less steep S-corrected line deflection current. Rotation (only present in widescreen sets) To cope with the different earth magnetism situations in the world, a rotation coil is added in widescreen sets. This coil is controlled by the rotation circuitry (see diagram A15). The amount of frame rotation is user controlled via the the PWM output (pin 77) of the UOC. With the tilt setting at ‘-10’, the PWM duty cycle is 0.1 (
leftmost tuning). With the setting at ‘+10’, the duty cycle is 0.9 (rightmost tuning). The output of amplifier IC7171 is a DC-voltage in the range from 0 (user setting = -10), via 6 V (user setting = 0) to 12 V (user setting = +10).

Power Supply

The supply is a Switching Mode Power Supply (SMPS). The frequency of operation varies with the circuit load. This ‘Quasi- Resonant Flyback’ behaviour has some important benefits compared to a ‘hard switching’ fixed frequency Flyback converter. The efficiency can be improved up to 90%, which results in lower power consumption. Moreover the supply runs cooler and safety is enhanced. The power supply starts operating when a DC voltage goes from the rectifier bridge via T5520, R3532 to pin 8. The operating voltage for the driver circuit is also taken from the ‘hot’ side of this transformer. The switching regulator IC7520 starts switching the FET ‘on’ and ‘off’, to control the current flow through the primary winding of transformer 5520. The energy stored in the primary winding during the ‘on’ time is delivered to the secondary windings during the ‘off’ time. The ‘MainSupply’ line is the reference voltage for the power supply. It is sampled by resistors 3543 and 3544 and fed to the input of the regulator 7540/
6540. This regulator drives the feedback optocoupler 7515 to set the feedback control voltage on pin 3 of 7520. The power supply in the set is ‘on’ any time AC power goes to the set.

GENERAL DESCRIPTION
The GreenChipTMII is the second generation of green Switched Mode Power Supply (SMPS) controller ICs operating directly from the rectified universal mains. A high level of integration leads to a cost effective power supply with a very low number of external components. The special built-in green functions allow the efficiency to be optimum at all power levels. This holds for quasi-resonant operation at high power levels, as well as fixed frequency operation with valley switching at medium power levels. At low power (standby) levels, the system operates at reduced frequency and with valley detection. If burst mode operation is applied, the standby power level can even be reduced to below 1 W. The proprietary high voltage BCD800 process makes direct start-up possible from the rectified mains voltage in an effective and green way. A second low voltage BICMOS IC is used for accurate, high speed protection functions and control. Highly efficient, reliable supplies can easily be designed using the GreenChipTMII controller.

The TEA1507 is the controller of a compact flyback converter, with the IC situated at the primary side. An auxiliary winding of the transformer provides demagnetization detection and powers the IC after start-up. The TEA1507 operates in multi modes. The next converter stroke is started only after demagnetization of the transformer current (zero current switching), while the drain voltage has reached the lowest voltage to prevent switching losses (green function). The primary resonant circuit of primary inductance and drain capacitor ensures this quasi-resonant operation. The design can be optimized in such a way that zero voltage switching can be reached over almost the universal mains range. To prevent very high frequency operation at lower loads, the quasi-resonant operation changes smoothly in fixed frequency PWM control. At very low power (standby) levels, the frequency is controlled down, via the VCO, to a minimum frequency of about 6 kHz. Typically, 3 Watts can be achieved for a 75 W converter with an output power of 100 mW.

Derived Voltages
The voltages supplied by the secondary windings of T5520 are: • ‘MainAux’ for the audio circuit (voltage depends on set ••execution, 3.3 V and 3.9 V for the microprocessor and ‘MainSupply’ for the horizontal output (voltage depends on set execution, see table below). Other supply voltages are provided by the LOT. It supplies +50 V (only for large screen sets), +13 V, +8 V, +5 V and a +200 V source for the video drive. The secondary voltages of the LOT are monitored by the ‘EHTinformation’ lines. These lines are fed to the video processor part of the UOC IC7200 on pins 11 and 34. This circuit will shut ‘off’ the horizontal drive in case of over- voltage or excessive beam current.

Degaussing
When the set is switched on, the degaussing relay 1515 is immediately activated as transistor 7580 is conducting. Due to the RC-time of R3580 and C2580, it will last about 3 to 4 seconds before transistor 7580 is switched off. Basic IC Functionality For a clear understanding of the Quasi-Resonant behaviour, it is possible to explain it by a simplified circuit diagram (see Figure below). In this circuit diagram, the secondary side is transferred to the primary side and the transformer is replaced by an inductance LP. CD is the total drain capacitance including the resonance capacitor CR, parasitic output capacitor COSS of the MOSFET and the winding capacitance CW of the transformer. The turns ratio of the transformer is represented by n (NP/NS).

In the Quasi-Resonant mode each period can be divided into 4 different time intervals, in chronological order: Interval 1: t0 < t < t1 primary stroke At the beginning of the first interval, the MOSFET is switched ‘on’ and energy is stored in the primary inductance (magnetisation). At the end, the MOSFET is switched ‘off’ and the second interval starts. Interval 2: t1 < t < t2 commutation time In the second interval, the drain voltage will rise from almost zero to VIN+n•(VOUT +VF). VF is the forward voltage drop of de diode that will be omitted from the equations from now on. The current will change its positive derivative, corresponding to VIN/LP , to a negative derivative, corresponding to -n•VOUT /LP. Interval 3: t2 < t < t3 secondary stroke In the third interval, the stored energy is transferred to the output, so the diode starts to conduct and the inductive current IL will decrease. In other words, the transformer will be demagnetised. When the inductive current has become zero the next interval begins.
Interval 4: t3 < t < t00 resonance time In the fourth interval, the energy stored in the drain capacitor CD will start to resonate with the inductance LP. The voltage and current waveforms are sinusoidal waveforms. The drain voltage will drop from V IN+n•VOUT to VIN-n•VOUT. Frequency Behaviour The frequency in the QR-mode is determined by the power stage and is not influenced by the controller (important parameters are LP and CD). The frequency varies with the input voltage VIN and the output power POUT. If the required output power increases, more energy has to be stored in the transformer. This leads to longer magnetising tPRIM and demagnetising tSEC times, which will decrease the frequency. See the frequency versus output power characteristics below. The frequency characteristic is not only output power-, but also input voltage dependent. The higher the input voltage, the smaller tPRIM, so the higher the frequency will be.

Start-up Sequence
When the rectified AC voltage VIN (via the centre tap connected to pin 8) reaches the Mains dependent operation level (Mlevel: between 60 and 100 V), the internal ‘Mlevel switch’ will be opened and the start-up current source is enabled to charge capacitor C2521 at the VCC pin as shown below. The ‘soft start’ switch is closed when the VCC reaches a level of 7 V and the ‘soft start’ capacitor CSS (C2522, between pin 5 and the sense resistor R3526), is charged to 0.5 V. Once the VCC capacitor is charged to the start-up voltage VCC- (11 V), the IC starts driving the MOSFET. Both internal startcurrent sources are switched ‘off’ after reaching this start-up voltage. Resistor RSS (3524) will discharge the ‘soft start’ capacitor, such that the peak current will slowly increase. This to prevent ‘transformer rattle’. During start-up, the VCC capacitor will be discharged until the moment that the primary auxiliary winding takes over this voltage.

The moment that the voltage on pin 1 drops below the ‘under voltage lock out‘ level (UVLO = ± 9 V), the IC will stop switching and will enter a safe restart from the rectified mains voltage.
Operation
The supply can run in three different modes depending on the
output power:
• Quasi-Resonant mode (QR) The QR mode, described above, is used during normal operation. This will give a high efficiency.
• Frequency Reduction mode (FR) The FR mode (also called VCO mode) is implemented to decrease the switching losses at low output loads. In this way the efficiency at low output powers is increased, which enables power consumption smaller than 3 W during stand-by. The voltage at the pin 3 (Ctrl) determines where the frequency reduction starts. An external Ctrl voltage of 1.425 V corresponds with an internal VCO level of 75 mV. This fixed VCO level is called VVCO,start . The frequency will be reduced in relation to the VCO voltage between 75 mV and 50 mV (at levels larger than 75 mV, Ctrl voltage < 1.425V, the oscillator will run on maximum frequency foscH = 175 kHz typically). At 50 mV (VVCO,max) the frequency is reduced to the minimum level of 6 kHz. Valley switching is still active in this mode.
• Minimum Frequency mode (MinF) At VCO levels below 50 mV, the minimum frequency will remain on 6 kHz, which is called the MinF mode. Because of this low frequency, it is possible to run at very low loads without having any output regulation problems.

Safe-Restart Mode
This mode is introduced to prevent the components from being destroyed during eventual system fault conditions. It is also used for the Burst mode. The Safe-Restart mode will be entered if it is triggered by one of the following functions:
• Over voltage protection,
• Short winding protection,
• Maximum ‘on time’ protection,
• VCC reaching UVLO level (fold back during overload),
• Detecting a pulse for Burst mode,
• Over temperature protection.
When entering the Safe-Restart mode, the output driver is immediately disabled and latched. The VCC winding will not charge the VCC capacitor anymore and the VCC voltage will drop until UVLO is reached. To recharge the VCC capacitor, the internal current source (I(restart)(VCC) ) will be switched ‘on’ to initiate a new start-up sequence as described before. This Safe-Restart mode will persist until the controller detects no faults or burst triggers.

Standby
The set goes to Standby in the following cases:
• After pressing the ‘standby’ key on the remote control.
• When the set is in protection mode.

In Standby, the power supply works in ‘burst mode’. Burst mode can be used to reduce the power consumption below 1 W at stand-by. During this mode, the controller is active (generating gate pulses) for only a short time and for a longer time inactive waiting for the next burst cycle. In the active period the energy is transferred to the secondary and stored in the buffer capacitor CSTAB in front of the linear stabiliser (see Figure below). During the inactive period, the load (e.g. microprocessor) discharges this capacitor. In this mode, the controller makes use of the Safe-Restart mode.

The system enters burst mode standby when the microprocessor activates the ‘Stdby_con’ line. When this line is pulled high, the base of TS7541 is allowed to go high. This is triggered by the current from collector TS7542. When TS7541 turns ‘on’, the opto-coupler (7515) is activated, sending a large current signal to pin 3 (Ctrl). In response to this signal, the IC stops switching and enters a ‘hiccup’ mode. This burst activation signal should be present for longer than the ‘burst blank’ period (typically 30 μs): the blanking time prevents false burst triggering due to spikes. Burst mode standby operation continues until the microcontroller pulls the ‘Stdby_con’ signal low again. The base of TS7541 is unable to go high, thus cannot turn ‘on’. This will disable the burst mode. The system then enters the start- up sequence and begins normal switching behaviour. For more detailed description of one burst cycle, three time are defined: t1: Discharge of V CC when gate drive is active During the first interval,
energy is transferred, which result in a ramp- up of the output voltage (VSTAB) in front of the stabiliser. When enough energy is stored in the capacitor, the IC will be switched ‘off’ by a current pulse generated at the secondary side. This pulse is transferred to the primary side via the opto coupler. The controller will disable the output driver (safe restart mode) when the current pulse reaches a threshold level of 16 mA into the Ctrl pin. A resistor R1 (R3519) is placed in series with the opto coupler, to limit the current going into the Ctrl pin. Meanwhile the VCC capacitor is discharged but has to stay above VUVLO . t2: Discharge of VCC when gate drive is inactive During the second interval, the VCC is discharged to VUVLO. The output voltage will decrease depending on the load. t3: Charge of VCC when gate drive is inactive The third interval starts when the UVLO is reached. The internal current source charges the VCC capacitor (also the soft start capacitor is recharged). Once the V CC capacitor is
charged to the start-up voltage, the driver is activated and a new burst cycle is started.

Protection Events
The SMPS IC7520 has the following protection features: Demagnetisation sense This feature guarantees discontinuous conduction mode operation in every situation. The oscillator will not start a new primary stroke until the secondary stroke has ended. This is to ensure that FET 7521 will not turn on until the demagnetisation of transformer 5520 is completed. The function is an additional protection feature against:
• saturation of the transformer,
• damage of the components during initial start-up,
• an overload of the output.
The demag(netisation) sense is realised by an internal circuit that guards the voltage (Vdemag) at pin 4 that is connected to VCC winding by resistor R1 (R3522). The Figure below shows the circuit and the idealised waveforms across this winding.

Over Voltage Protection
The Over Voltage Protection ensures that the output voltage will remain below an adjustable level. This works by sensing the auxiliary voltage via the current flowing into pin 4 (DEM) during the secondary stroke. This voltage is a well-defined replica of the output voltage. Any voltage spikes are averaged by an internal filter. If the output voltage exceeds the OVP trip level, the OVP circuit switches the power MOSFET ‘off’. Next, the controller waits until the ‘under voltage lock out‘ level (UVLO = ± 9 V) is reached on pin 1 (VCC). This is followed by a safe restart cycle, after which switching starts again. This process is repeated as long as the OVP condition exists. The output voltage, at which the OVP function trips, is set by the demagnetisation resistor R3522.

Over Current Protection
The internal OCP protection circuit limits the ‘sense’ voltage on pin 5 to an internal level.

Over Power Protection
During the primary stroke, the rectified AC input voltage is measured by sensing the current drawn from pin 4 (DEM). This current is dependent on the voltage on pin 9 of transformer 5520 and the value of R3522. The current information is used to adjust the peak drain current, which is measured via pin ISENSE.

Short Winding Protection
If the ‘sense’ voltage on pin 5 exceeds the short winding protection voltage (0.75 V), the converter will stop switching. Once VCC drops below the UVLO level, capacitor C2521 will be recharged and the supply will start again. This cycle will be repeated until the short circuit is removed (safe restart mode). The short winding protection will also protect in case of a secondary diode short circuit. This protection circuit is activated after the leading edge blanking time (LEB). LEB time The LEB (Leading Edge Blanking) time is an internally fixed delay, preventing false triggering of the comparator due to current spikes. This delay determines the minimum ‘on’ time of the controller.

Over Temperature protection
When the junction temperature exceeds the thermal shutdown temperature (typ. 140o C), the IC will disable the driver. When the VCC voltage drops to UVLO, the VCC capacitor will be recharged to the V(start) level. If the temperature is still too high, the V CC voltage will drop again to the UVLO level (Safe-Restart mode). This mode will persist until the junction temperature drops 8 degrees typically below the shutdown temperature. Mains dependent operation enabling level To prevent the supply from starting at a low input voltage, which could cause audible noise, a mains detection is implemented (Mlevel). This detection is provided via pin 8, that detects the minimum start-up voltage between 60 and 100 V. As previous mentioned, the controller is enabled between 60 and 100 V. An additional advantage of this function is the protection against a disconnected buffer capacitor (CIN). In this case, the supply will not be able to start-up because the VCC capacitor will not be charged to the start-up voltage.

Controls:
The microprocessor part of the UOC has the complete control and teletext on board. User menu, Service Default Mode, Service Alignment Mode and Customer Service Mode are generated by the μP. Communication to other ICs is done via the I2C-bus.

2I C-Bus
The main control system, which consists of the microprocessor part of the UOC (7200), is linked to the external devices (tuner, NVM, MSP, etc) by means of the I2C-bus. An internal I2C-bus is used to control other signal processing functions, like video processing, sound IF, vision IF, synchronisation, etc.

User Interface
There are two control signals, called ‘KEYBOARD_protn’ and ‘IR’. Users can interact either through the Remote Control transmitter, or by activation of the appropriate keyboard buttons. The PHILIPS L01 uses a remote control with RC5 protocol. The incoming signal is connected to pin 67 of the UOC. The 'Top Control' keyboard, connected to UOC pin 80, can also control the set. Button recognition is done via a voltage divider. The ‘KEYBOARD_protn’ line, also serves to detect faults in the E/W circuit, which would require the μP to shut down the set (by forcing the power supply in standby mode). The front LED (6691) is connected to an output control line of the microprocessor (pin 5). It is activated to provide the user information about whether or not the set is working correctly (e.g., responding to the remote control or fault condition)

Sound Interface
There are three control signals, called ‘Volume_Mute’, ‘Treble_Buzzer_Hosp_app’ and ‘Bass_panorama’. The ‘Volume_Mute’ line controls the sound level output of the audio amplifier or to mute it in case of no video identification or from user command. This line also controls the volume level during set switch ‘on’ and ‘off’ (to prevent audio plop). The ‘Treble’ and ‘Bass’ lines have another functionality:

– The ‘Bass_panorama’ line is used to switch the panorama mode in widescreen sets (to fit 4:3 pictures into a 16:9 display, it is possible to apply a panoramic horizontal distortion, to make a screen-fitting picture without black sidebars or lost video).

– The ‘Treble_Buzzer_Hosp_app’ is used in ITV applications for other feautures, and in widescreen sets to enable the ‘Tilt’ feature (via R3172 on diagram A8) in the deflection part.

In- and Output Selection
For the control of the input and output selections, there are three lines:
• STATUS1 This signal provides information to the microprocessor on whether a video signal is available on the SCART1 AV input and output port.
– 0 to 2 V: INTERNAL 4:3
– 4.5 to 7 V: EXTERNAL 16:9
– 9.5 to 12 V: EXTERNAL 4:3

• STATUS2 This signal provides information to the microprocessor on whether a video signal is available on the SCART2 AV input and output port (signal is low). For sets with an SVHS input, it provides the additional information if a Y/C or CVBS source is present (signal is high). The presence of an external Y/C source makes this line ‘high’ while a CVBS source makes the line ‘low’. – 0 to 2 V: INTERNAL 4:3 – 4.5 to 7 V: EXTERNAL 16:9

•
– 9.5 to 12 V: EXTERNAL 4:3
SEL-MAIN-FRNT-RR This is the ‘source select control’
signal from the microprocessor. This control line is under
user control or can be activated by the other two control
lines.
Power Supply Control The microprocessor part is supplied with 3.3 V and 3.9 V both derived from the ‘MainAux’ voltage via a 3V3 stabiliser (7560) and a diode.
Two signals are used to control the power supply:
• Stdby_con This signal is generated by the microprocessor when over-current takes place at the ‘MainAux’ line. This is done to enable the power supply into standby burst mode, and to enable this mode during a protection. This signal is ‘low’ under normal operation conditions and goes to ‘high’ (3.3 V) under ‘standby’ and ‘fault’ conditions.

• POWER_DOWN This signal is generated by the power supply. Under normal operating conditions this signal is ‘high’ (3.3 V). During ‘standby’ mode, this signal is a pulse train of approx. 10 Hz and a ‘high’ duration of 5 ms. It is used to give information to the UOC about the fault condition in the Audio amplifier supply circuit. This information is generated by sensing the current on the ‘MainAux’ line (using voltage drop across R3564 to trigger TS7562). This signal goes ‘low’ when the DC-current on the ‘MainAux’ line exceeds 1.6 - 2.0 A. It is also used to give an early warning to the UOC about a power failure. Then the information is used to mute the sound amplifier to prevent a switch off noise and to solve the switch-off spot.

Tuner IF
Pin 3 of the UOC (SEL-IF-LL’_M-TRAP), is an output pin to switch the SAW-filter to the appropriate system.
• If UOC pin 3 is ‘low’, the selected system is:
– West Europe: PAL B/G, I, SECAM L/L’
– East Europe: PAL B/G
– Asia Pacific: NTSC M
• If UOC pin 3 is ‘high’, the selected system is:
– West Europe: SECAM L’, L’-NICAM
– East Europe: PAL D/K
– Asia Pacific: PAL B/G, D/K, I
Note: For West Europe, two separate SAW filters (1002 and 1004) are used for video and audio (Quasi Split Sound demodulation). For East Europe, one SAW filter (1003) is used for both (Intercarrier demodulation).

Protection Events
Several protection events are controlled by the UOC:
• BC protection, to protect the picture tube from a too high beam current. The UOC has the capability of measuring the normal back level current during the vertical flyback. So if for some reason the CRT circuit is malfunctioning (i.e. high beam current), the normal black current will be out of the 75 μA range, and the UOC will trigger the power supply to shut down. However, this is a high beam-current situation, the TV screen will be bright white before the set is shut down.
• I2C protection, to check whether all I2C IC's are functioning. In case one of these protections is activated, the set will go into ‘standby’. The ‘on’ and ‘standby’ LEDs are controlled via the
UOC.

Protections
If a fault situation is detected an error code will be generated and if necessary, the set will be put in the protection mode. Blinking of the red LED at a frequency of 3 Hz indicates the protection mode. In some error cases, the microprocessor does not put the set in the protection mode. The error codes of the error buffer can be read via the service menu (SAM), the blinking LED procedure or via ComPair. The DST diagnose functionality will force the set into the Service-standby, which is similar to the usual standby mode, however the microprocessor has to remain in normal operation completely. To get a quick diagnosis the chassis has three service modes implemented:

• The Customer Service Mode (CSM).
• The Service Default Mode (SDM). Start-up of the set in a predefined way.
• The Service Alignment Mode (SAM). Adjustment of the set via a menu and with the help of test patterns.
See for a detailed description paragraphs Deflection and Power Supply.

Repair Tips
Below some failure symptoms are given, followed by a repair
tip.
• Set is dead and makes hiccuping sound ‘MainSupply’ is available. Hiccuping stops when de- soldering L5561, meaning that problem is in the ‘MainSupply’ load. No output voltages at LOT, no horizontal deflection. Reason: line transistor 7460 is defective.

• Set is dead, and makes no sound
Check power supply IC7520. Result: voltage at pins 1, 3, 4, 5 and 6 are about 180 V and pin 8 is 0 V. The reason why the voltage on these pins is so high is because the output driver (pin 6) has an open load. That is why MOSFET TS7521 is not able to switch. Reason: feedback resistor 3523 is defective. Caution: be careful measuring on the gate of TS7521; circuitry is very high ohmic and can easily be damaged! (first connect ground to measuring equipment, than the gate).

• Set is in hiccup mode and shuts down after 8 s.

•Blinking LED (set in SDM mode) indicates error 5. As it is unlikely that μP ‘POR’ and ‘+8V protection’ happen at the same time, measure the ‘+8V’. If this voltage is missing, check transistor TS7480.
Set is non-stop in hiccup mode
Set is in over current mode; check the secondary sensing (opto coupler 7515) and the ‘MainSupply’ voltage. Signal ‘Stdby_con’ must be logic low under normal operation conditions and goes to high (3.3 V) under standby and fault conditions.

Set turns on, but without picture and sound The screen shows snow, but OSD and other menus are okay. Blinking LED procedure indicates error 10, so problem is expected in the tuner (pos. 1000). Check presence of supply voltages. As ‘Vlotaux+5V’ at pin 6 and 7 are okay, ‘VT_supply’ at pin 9 is missing. Conclusion: resistor 3460 or 3488 is defective.

Set turns on, but with a half screen at the bottom. Sound is okay Blinking LED (set in SDM mode) indicates error 2. Check ‘Vlotaux+13V’ and ‘+50V’. If they are okay, problem is expected in the vertical amplifier IC7471. Measure with a scope the waveform on pin 17 of the UOC. Measure also at pin 1 of IC7471. If here the signal is missing, a defective resistor R3244 causes the problem.

Other References:
EP1405397    2007-02-07            CURRENT MODE CONTROLLED SWITCHED MODE POWER SUPPLY
GB2438464A    2007-11-28            Regulating the output of a switch mode power supply
WO2008104919A1    2008-09-04            LOAD CURRENT DETECTION IN ELECTRICAL POWER CONVERTERS
WO2010015999A1    2010-02-11            CONVERTER WITH CONTROLLED OUTPUT CURRENT

Other References:
NXP B.V. (Eindhoven, NL)
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