- PAL DEKODER STEPEN 3880880 with TDA3560
- RGB AMPLIFIER STEPEN 3860358
- VERTIKAL STEPEN 3860336
- MF STEPEN 3863825 WITH TDA2541
- TONSKI STEPEN 3236758 WITH TBA120U AND TBA800U
- HOR OSC 3236816
- HORIZONTALNI IZLAZNI STEPEN 3860314 BU208
- POWER SUPPLY 6703154 BU326
- TUNING CONTROL SYSTEM UB819-B (Policom Italy). with SGS M293B1 and SGS M104B1
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
BU208(A)
Silicon NPNnpn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.
DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.
APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C
THE TBA800, TBA810 AUDIO integrated circuits:
AUDIO integrated circuits are being increasingly used in television chassis and certainly represent the simplest approach to improving the audio side of a TV set. A number of such i.c.s have appeared during the 70's.
The main difference between them being that the TBA800 is a somewhat higher voltage, lower current device. The TBA800 is used in the current Grundig and ASA 110° colour chassis while the Finlux 110' colour chassis uses a TBA810. In each of these chassis the audio i.c. is driven from a TBA120 intercarrier sound i.c. The TBA800 and TBA810S can also be used as the field output stage in 110' monochrome chassis with c.r.t.s of up to l7in. and as the field driver stage in larger screen monochrome sets.
The
TBA800 is designed to provide up to 5W into a 16 Ohm load when operated
from a 24V supply. It is encapsulated in the type cf quad -in -line
case shown in Fig. I: the tabs at the centre are to assist in cooling
the device and must be earthed. The TBA800 can be operated from power
supply voltages up to the absolute maximum permissible value of 30V. It
is best to regard 24V as being the upper limit however in order to
provide an adequate safety margin and prevent possible damage during
voltage surges. The minimum power supply voltage recommended by the
manufacturers is 5V, but the power output is then less than 0-5W. The
quiescent current taken by the TBA800 is typically 9mA from a 24V
supply-no device of this type should draw more than 20mA. When an input
signal is applied the current increases considerably- up to about 1.5A
at full power. Two circuits for use with the TBA800 are shown in Figs. 2
and 3 and give comparable performance. The circuit shown in Fig. 2 is somewhat simpler but thatshown in Fig. 3 enables one side of the loudspeaker to be connected to chassis. The input resistance of the TBA800 is quite high (typically 5 MOhm) but a resistor must be connected between the input pin 8 and chassis otherwise the out- put stage will not operate with the correct bias. In the circuits shown the volume control VR1 provides this function: the bias current that flows through it is typically 1 microA (maximum 5 microA). The average voltage at the output pin 12 is half the supply potential. The loudspeaker must be capacitively coupled therefore and the low frequency response will be worse as this capacitor is decreased in value. The output coupling capacitor C4 in Fig. 2 also provides the bootstrap connection to pin 4. In Fig. 3 an additional capacitor (C9) is required for this purpose.
In both circuits the value of R1 controls the amount of feedback and thus the gain. The output signal is fed back to pin 6 via an internal 7 kOhm resistor. If R1 is reduced in value the gain will increase but the frequency response will be affected and the distortion will rise. With the component values shown the voltage gain of both circuits is typically 140 (43dB) which is quite adequate for most audio applications. R3 in Fig. 3 is necessary only if the power supply voltage is fairly low (less than about 14V).
C2 smooths the power supply input and C1 is connected between pin 1 and chassis to provide r.f. decoupling and help prevent instability. If mains hum is present on the supply line with the circuit shown in Fig. 3 capacitor C8 should be included between pin 7 and chassis. The circuits shown have a level frequency response (within ±3dB) between about 40Hz and 20kHz. If you wish to reduce the upper 3dB level to about 8kHz C5 can be increased to about 560pF. The total harmonic distortion provided by these circuits remains fairly constant at about 0.5% until the power output reaches 3W: it then rises rapidly with power level as shown in Fig. 4.
The
TBA800 can be operated from a 13V supply to feed up to 2.5W into an 80
load or from a 17V supply to feed the same power into a 160 load without
an additional heatsink. If more output power is required the cooling
tabs must be connected to a heatsink. Two methods of mounting the TBA800
are shown in Figs. 5 and 6. In Fig. 5 the device is inserted into a
circuit board and a heatsink is soldered to the same points as the tabs:
this has the disadvantage that the heatsink extends above the board
though on the other hand the whole board can be used for the
construction of the circuit. In Fig. 6 the tabs are soldered directly to
a suitable area of copper on the board: this method has the
disadvantage that about two square inches of the board are not available
for component mounting. It is generally best to make soldered
connections to the pins of the device since this ensures good heat
dissipation with minimum unwanted feedback. Observe the usual heat
precautions when soldering. The pins can however be carefully bent so
that they will fit into a 16 -pin dual -in -line socket.The TBA810S has the same type of encapsulation as the TBA800 and the connections are also as shown in Fig. 1 except that there is no internal connection to pin 3. An alternative version, the TBA810AS, has two horizontal tabs with a hole in each (see Fig. 7) so that a heatsink can be bolted on. Some readers may find it easier to bolt a heatsink to a TBA810AS than to solder the TBA810S tabs. TBA810 devices can provide 7W of audio power to a 40 loudspeaker when operated from a I6V supply. Fig. 8 shows the change in maximum output power with different supply voltages. As a 4.5W output can be obtained with a 12V supply the TBA810 is much more suitable than the TBA800 for use with battery operated equipment. The TBA810 can provide output currents up to 2.5A.
Two circuits for use with TBA810 devices are shown in Figs. 9 and 10: they are very similar to the circuits shown in Figs. 2 and 3 though some of the capacitor values are larger because of the lower output impedance. The two circuits have comparable performance but that shown in Fig. 10 gives somewhat better results at low supply voltages (down to 4V). In either circuit R2 may be replaced with a 100k0 volume control. The bias current flowing in the pin 8 circuit is typically
0-4 microA and the input resistance 5M 0 (the value of R2 must be much less however to ensure correct bias.
The gain decreases as the value of R1 is increased for the same reason as with the TBA800. The values of R1, C3 and C7 affect the high -frequency response. With the values shown the response is level within ±3dB from about 40Hz to nearly 20kHz. Fig. 11 shows values of C3 plotted against R1 where the frequency is 3dB down at 10kHz and 20kHz and C7 is five times C3. The output distortion with these circuits is about 0.3% for outputs up to 3W rising to about 1% at 4W, 3% at 5W and 9% at 6W with a 14.4V supply voltage. The voltage gain is typically 70 times (37dB). Although this value is half that obtained with the TBA800 the input voltage required to produce a given output power is about the same for both types. This is because a smaller output voltage is required to drive a 40 load at a certain power level than is required to drive a 160 load.
The TBA810S may be mounted in the same way as the TBA800. One way of mounting the TBA810AS is shown in Fig. 12. It is simpler however to bolt flat heatsinks to the tabs.
Devices of this type will be destroyed within a fraction of a second if the power supply is accidentally con- nected with reversed polarity. When experimenting therefore it is wise to include a diode in the positive power supply line to prevent any appreciable reverse current flowing in the event of incorrect power supply connection. The diode can be removed once the circuit has been finalised. The TBA800 is likely to be destroyed if the output is accidentally shorted to chassis. The TBA810S and TBA810AS however are protected from damage in the event of such a short-circuit even if this remains for a long time (but note that the earlier TBA8I0 and TBA810A versions did not contain internal circuitry to provide this protection). The TBA800 is not protected against overheating but the TBA810S and TBA810AS incorporate a thermal shutdown circuit.
For this reason the heat- sinks used with the TBA810S and TBA810AS can have a smaller safety factor than those used with the TBA800. If the silicon chip in a TBA810S or TBA810AS becomes too hot the output power is temporarily reduced by the internal thermal shutdown circuit. As with all high -gain amplifiers great care should be taken to keep the input and output circuits well separated otherwise oscillation could occur. The de- coupling capacitors should be soldered close to the i.c. -especially the 0 1pF decoupling capacitor in the supply line (this should be close to pin I).
Field Output Circuit:
GELOSO TVC14" MODELLO G.14032 CHASSIS 3880319 UNITS VIEW. Switching power supply, especially for a T.V. receiving apparatus:
1. Switch mode power supply means, especially for a television receiver, having a working winding (5), a switching transistor (6), a back-coupling winding (7) and a control switch (11) on the primary side of a divided transformer (1), and also having rectifiers (15, 16, 20) for the production of the drive voltages (U1, U2, U3) on the secondary side of the transformer (1), characterized by the following features : (a) Connected to a winding (19) there is a thyristor (24) which is poled in the permitted direction for the voltage at the winding (19) arising during the current conducting phase of the switching transistor (6). (b) One of the drive voltages (U2) is applied to the control electrode of the thyristor (24) with such magnitude that the thyristor (24) remains blocked in the normal working state and fires on the occurrence of an inadmissible rise of the drive voltage (U3).
GELOSO TVC14" MODELLO G.14032 CHASSIS 3880319 UNITS VIEW. Schaltnetzteil
(ZANUSSI BS394 SWITCH MODE POWER SUPPLY), IN GERMAN:
2. Netzteil nach Anspruch 1, dadurch gekennzeichnet, dass die Betriebsspannung (U3) ·uber einen Spannungsteiler (25,26) an die Steuerelektrode des Thyristors (24) angelegt ist.
3. Netzteil nach Anspruch 1, dadurch gekennzeichnet, dass die Wicklung (19) eine Sekund·arwicklung des Trenntransforma tors (1) ist.
Description:
Schaltnetzteil, insbesondere f·ur einen Fernsehempf·anger
Bei Ger·aten der Nachrichtentechnik wie z.B. einem Fernsehempf·anger ist es bekannt, die f·ur die einzelnen Stufen notwendigen Betriebsspannungen mit einem Schaltnetzteil aus der Netzspannung zu erzeugen (Funkschau 1975, Heft 5, Seite 40-43). Ein Schaltnetzteil erm·oglicht die f·ur den Anschluss ·ausserer Ger·ate und f·ur die Massnahmen zur Schutzisolierung vorteilhafte galvanische Trennung der Empf·angerschaltung vom Netz. Da ein Schaltnetzteil mit einer gegen·uber der Netzfrequenz hohen Frequenz von ca. 30 kHz arbeitet, kann der zur galvanischen Trennung dienende Trenntransformator gegen·uber einem Netztrafo f·ur 50 Hz wesentlich kleiner und leichter ausgebildet sein. Durch mehrere Wicklungen oder Wicklungsabgriffe und angeschlossene Gleichrichter k·onnen auf der Sekund·arseite des Trenntransformators Betriebs~ spannungen unterschiedlicher Gr·osse und Polarit·at erzeugt werden.
Ein solches Schaltnetzteil enth·alt eine Regelschaltung zur Stabilisierung der Amplitude der auf der Sekund·arseite erzeugten Betriebsspannungen. In dieser Regelschaltung wird eine durch Gleichrichtung der Impulsspannung am Trafo gewonnene Stellgr·osse erzeugt und mit einer Bezugsspannung verglichen. In Abh·angigkeit von der Abweichung wird der Schaltzeitpunkt des auf der Prim·arseite vorgesehenen elektronischen Schalters so gesteuert, dass die Amplitude der erzeugten Betriebsspannungen konstant bleibt.
Bei einem solchen Schaltnetzteil kann die genannte Regelschaltung z.B. durch ein fehlerhaftes Bauteil ausfallen. Die Regelung der Amplitude der erzeugten Betriebsspannungen ist dann unkontrolliert. Die Betriebsspannungen k·onnen dann auf den doppelten oder dreifachen Wert ansteigen. Dadurch besteht die Gefahr, dass das Schaltnetzteil oder die an die Betriebsspannungen angeschlossenen Verbraucher wie z.B. der Heizfaden der Bildr·ohre oder der Zeilenendstufentransistor zerst·ort werden. Der Anstieg der Betriebsspannungen kann dar·uberhinaus einen Anstieg der im Fernsehempf·anger erzeugten Hochspannung und dadurch eine R·ontgenstrahlung ausl·osen.
Es ist auch ein Schaltnetzteil bekannt (DE-OS 27 27 332), bei dem zum Schutz gegen einen zu starken Anstieg der erzeugten Betriebsspannungen aus der Impulsspannung an der Prim·arseite des Trafos eine Stellgr·osse gewonnen wird, die beim ·Uberschreiten eines Schwellwertes den R·uckkopplungsweg unwirksam steuert. Durch die Unterbrechung des R·uckkopplungsweges kann das Schaltnetzteil nicht mehr schwingen, so dass in erw·unschter Weise auch keine Betriebsspannungen mehr erzeugt werden. Diese Schaltung erfordert jedoch eine Vielzahl von Bauteilen und ist daher relativ teuer.
Der Erfindung liegt die Aufgabe zugrunde, eine sicher wirkende Schutzschaltung mit verringertem Schaltungsaufwand gegen
die oben
beschriebenen Gefahren zu schaffen.
Diese Aufgabe wird durch die im Anspruch 1 beschriebene Erfindung gel·ost. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteranspr·uchen beschrieben.
Die Erfindung beruht auf folgender ·Uberlegung: Der Schalttransistor auf der Prim·arseite wird von der prim·arseitigen R·uckkopplungswicklung w·ahrend seiner stromleitenden Phase mit einem Basisstrom angesteuert. Wenn jetzt eine Sekund·arwicklung w·ahrend dieser stromleitenden Phase stark belastet, z.B. ·uber den Thyristor kurzgeschlossen wird, bricht auch die Spannung an der prim·arseitigen R·uckkopplungswicklung zusammen. Diese Wicklung kann dann f·ur den Schalttransistor nicht mehr einen f·ur den leitenden Betrieb ausreichenden Basis strom liefern. Das Schaltnetzteil schwingt dann nicht mehr, so dass die sekund·arseitigen Betriebsspannungen in erw·unschter Weise zusammenbrechen. Der schaltungstechni- sche Aufwand ist gering. Er besteht vorzugsweise aus einem Thyristor und zwei Widerst·anden.
Ein Ausf·uhrungsbeispiel der Erfindung wird anhand der Zeichnung erl·autert. Darin zeigen Figur 1 ein erfindungsgem·ass ausgebildetes Schaltnetzteil und Figur 2 Kurven zur Erl·auterung der Wirkungsweise. Dabei zeigen die kleinen Buchstaben, an welchen Punkten in Figur 1 die Spannungen gem·ass Figur 2 stehen.
Das Schaltnetzteil gem·ass Figur 1 enth·alt auf der Prim·arseite des Trenntransformators 1 den Netzgleichrichter 2, den Ladekondensator 3, den Strom-Messwiderstand 4, die Prim·arwicklung 5 den Schalttransistor 6, die zur Schwingungserzeugung dienende R·uckkopplungswicklung 7, den zur Steuerung des Schalttransistors 6 dienenden Thyristor 8, die Regelwicklung 9, den zur Erzeugung der Regelspannung dienenden Gleichrichter 10 sowie die zur Stabilisierung der Betriebsspannungen dienende Regelschaltung 11 mit dem Transistor 12 und der eine Referenzspannung lieferndenZenerdiode 13. Die Sekund·arwicklung 14 liefert ·uber den Gleichrichter 15 eine erste Betriebsspannung U1 von 150 V. Ein Abgriff der Wicklung 14 liefert ·uber den Gleichrichter 16 eine zweite Betriebsspannung U2 von 12 V f·ur einen Fernbedienungsempf·anger.
Eine weitere Sekund·arwicklung 19 liefert ·uber den Gleichrichter 20 eine dritte Betriebsspannung U3 von 12 V. Die Polung der Wicklungen 14,19 und der Gleichrichter 15,16,20 ist derart, dass die Gleichrichter 15,16,20 w·ahrend der Sperrphase des Schalttransistors 6 durch die sekund·arseitig auftretenden Impulsspannungen leitend gesteuert sind und die angeschlossenen Ladekondensatoren aufladen.
An das untere Ende der Wicklung 19 ist zus·atzlich der Thyristor 24 angeschlossen. An die Steuerelektrode b des Thyristors 24 ist die Betriebs spannung U2 ·uber den Spannungsteiler 25,26 angelegt.
Die Wirkungsweise der Schaltung wird anhand der Figur 2 erl·autert. Es sei angenommen, dass das Schaltnetzteil im Zeitpunkt tl in Betrieb genommen wird. Mit der Diode 21 wird aus der Netzspannung am Punkt d ein positiver Impuls erzeugt. Dieser gelangt ·uber den Kondensator 23 auf die Basis des Schalttransistors 6 und steuert diesen leitend. Dadurch beginnt das Schaltnetzteil zu schwingen, wobei die Schwingung durch die R·uckkopplungswicklung 7
aufrechterhalten wird. Am Punkt a entsteht dann eine m·aanderf·ormige
Wechselspannung mit einer Frequenz von etwa 25-30 kHz.
Die daraufhin in den Sekund·arwicklungen 14,19 erzeugten Impulse erzeugen in der beschriebenen Weise die Betriebsspannungen U1,U2,U3. Der Spannungsteiler 25,26 ist so bemessen, dass der Thyristor 24 gesperrt bleibt, d.h. die Spannung am Punkt 6 jst kleiner als 0,7 V. Der Thyristor 24 hat dann keine Wirkung. Dir Amplitude der Spannungen Ui,U2,U3 wird ·uber die Regelschaltung 11 stabilisiert.
Es sei jetzt angenommen, dass durch einen Fehler in der Regelschaltung 11, z.B. durch Ausfall eines Bauteiles, die Regelung zur Stabilisierung der Betriebsspannungen U1,U2,U3 nicht mehr wirkt und diese Betriebsspannungen stark ansteigen. Dadurch steigt auch die Spannung am Punkt b an.
Im Zeitpunkt t2 erreicht diese Spannung den Wert von 0,7 V, so dass der Thyristor 24 z·undet. Der untere Teil der Wicklung 19 ist jetzt praktisch kurzgeschlossen. Das Netzteil ist dadurch sekund·arseitig so stark belastet, dass die R·uck kopplungswicklung 7 keinen ausreichenden Basisstrom zur Steuerung des Schalttransistors 6 in seine stromleitende Phase mehr liefert. Im Zeitpunkt t2 bricht die Schwingung des Schaltnetzteiles ab, so dass auch die Wechselspannung am Punkt a auf null abf·allt. Den Ladekondensatoren der Gleichrichter 15,16,20 wird kein Strom mehr zugef·uhrt, so dass die Betriebspannungen U1,U2,U3 nicht weiter ansteigen k·onnen, sondern entsprechend den wirksamen Entladezeitkonstanten abfallen. Das Schaltnetzteil w·urde auf diese Weise an sich beliebig lange ausgeschaltet bleiben.
Im Zeitpunkt t3 erscheint am Punkt b der n·achste aus der Netzspannung gewonnene Startimpuls, der den Schalttransistor 6 wieder leitend steuert, so dass die Wechselspannung am Punkt a wieder auftritt. Das Schaltnetzteil geht also in einen getakteten Betrieb ·uber, bei dem die ·ubertragene Leistung entsprechend dem Zeitverh·altnis zwischen Einschaltphase und Ausschaltphase der Spannung am Punkt a betr·achtlich verringert ist. Die Betriebsspannungen U11U2,U3 k·onnen nicht mehr unzul·assig hohe Werte annehmen.
- GELOSO TVC14" MODELLO G.14032 CHASSIS 3880319 UNITS VIEW. LINE DEFLECTION OUTPUT UNIT WITH BU208A (Ei) This p.c.b. amplifies the pulse sequence at line frequency and drives a circuit operating as
an ON-OFF switch for supplying the deflection current to the horizontal yoke. It also
receives the parabolic signal which acts on the diodes modulator for E/W correction.
Series was featuring a Simplified BU208A transitor horizontal deflection section replacing all Thyristor horizontal timebase based circuits.
A horizontal deflection circuit makes a sawtooth
current flow through a deflection coil. The current
will have equal amounts of positive and negative
current. The horizontal switch transistor conducts
for the right hand side of the picture. The damper
diode conducts for the left side of the picture.
Current only flows through the fly back capacitor
during retrace time.
For time 1 the transistor is turned on. Current
ramps up in the yoke. The beam is moved from the
center of the picture to the right edge. Energy is
stored on the inductance of the yoke.
E=I2L/2
For time 2 the transistor is turned off. Energy
transfers from the yoke to the flyback capacitor. At
the end of time two all the energy from the yoke is
placed on the flyback capacitor. There is zero
current in the yoke and a large voltage on the
capacitor. The beam is quickly moved from the
right edge back to the middle of the picture.
During time 3 the energy on the capacitor flows
back into the yoke. The voltage on the flyback
capacitor decreases while the current in the yoke
builds until there is no voltage on the capacitor. By
the end of time 3 the yoke current is at it's
maximum amount but in the negative direction.
The beam is quickly deflected form the center to the
left edge.
Time 4 represents the left hand half of the picture.
Yoke current is negative and ramping down. The
beam moves from the left to the center of the
picture.
The current that flows when the horizontal switch is
closed is approximately:
Ipk ≅ Vcc T / Ldy
Ipk = collector current
T = 1/2 trace time
Ldy = total inductance (yoke + lin coil + size coil)
note:The lin coil inductance varies with current.
______
Tr ≅ 3.14 √ L C
The current that flows during retrace is produced by
the C and L oscillation. The retrace time is 1/2 the
oscillation frequency of the L and C.
I2L /2 ≅ V2C /2 or I2L = V2C As stated earlier the energy in the yoke moves to the
flyback capacitor during time 2.
V= the amount of the flyback pulse that is above the
supply voltage.
D.C. annualizes is inductors are considered
shores, capacitors are open and generally
semiconductors are removed. The voltage at the
point “B+” is the supply voltage. The collector
voltage of Q1 is also at the supply voltage. The
voltage across C2 is equal to the supply voltage.
When we A.C. annualize this circuit we will find
that the collector of Q1 has a voltage that ranges
from slightly negative to 1000 volts positive. The
average voltage must remain the same as the D.C.
value.
In the A.C. annualizes of the circuit, the
inductance of the yoke (DY) and the inductance of
the flyback transformer are in parallel. The
inductance of T2 is much larger than that if the
DY. This results is a total system inductance of
about 10% to 20% less than that of the DY it’s
self.
The voltage across the Q1 is a half sinusoid pulse during the flyback or retrace period and close to zero at
all other times. It is not possible or safe to observe this point on an oscilloscope without a proper high
frequency high voltage probe. Normally use a 100:1 probe suitable for 2,000V peak. The probe must have
been high frequency calibrated recently.
HORIZONTAL SIZE / E/W AMPLITUDE - CORRECTION CIRCUIT:
There are several different methods of adjusting horizontal size.
SIZE COIL
Add a variable coil to the yoke current path
causes the total inductance to vary with the coils
setting.
The yoke current is related to supply voltage,
trace time and total inductance. This method
has a limited range!
The horizontal section uses a PWM to set the
horizontal size. One DAC sets the horizontal
size and another DAC sets the pincushion and
trap.
The Raster Centering (D.C. centering) is
controlled by a DAC.
On small monitors the retrace time is fixed. On
large monitors or wide frequency range monitors
two different retrace times are available. The flyback time is set by the micro computer by selecting two
different flyback capacitors. At slow frequencies the longer retrace time is selected.
Different S corrector capacitor values are selected by the micro computer. At the highest frequency the
smallest capacitor is selected.
SPLIT DIODE MODULATOR
This horizontal circuit consists of two parts. D1, C1, C2 and DY are the components as described above.
D2, C3, C4 and L1 are a second “dummy” horizontal section that does not cause deflection current. By the
D.C. analyzing this circuit the voltage across C2 + C4 must equal the supply voltage (B+). Deflection
current in the DY is related to the supply voltage minus the voltage across C4. For a maximum horizontal
size the control point must be held at ground. This causes the dummy section to not operate and the DY
section will get full supply voltage. If the control point is at 1/3 supply then the DY section will be
operating at 2/3 supply.
Note: The impedance of (D1,C1,C2 and DY) and (D2,C3,C4 and L1) makes a voltage divider. If the
control point is not connected then there is some natural voltage on C4. Most split diode monitors are built
to pull power from the dummy section through L2 to ground. A single power transistor shunts from the
control point to ground. It is true that power can be supplied from some
other supply through L2 to rise the voltage on C4. For maximum range a
bi-directional power amplifier can drive the control point.
The most exciting feature if the split diode modulator is that the flyback pulse, as seen by the flyback
transformer, is the same size at all horizontal size settings.
HORIZONTAL SWITCH/DAMPER DIODE
On the right hand side of the screen, the H. switch transistor conducts current through the deflection yoke.
This current comes from the S correction capacitors, which have a charge equal to the effective supply
voltage. The damper diode allows current for the left hand side of the screen to flow back through the
deflection yoke to the S capacitors.
FLYBACK CAPACITOR
The flyback capacitor connects the hot side of the yoke to ground. This component determines the size and
length of the flyback pulse. ‘Tuning the flyback capacitor’ is done to match the timing of the flyback pulse
to the video blanking time of the video signal. The peak flyback voltage on the horizontal switch must be
set to less that 80% if the Vces specification. The two conditions of time and voltage can be set by three
variables (supply voltage, retrace capacitor and yoke inductance) .
S CAPACITOR
The S capacitors corrects outside versus center linearity in the horizontal scan. The voltage on the S cap
has a parabola plus the DC horizontal supply. Reducing the value of S cap increases this parabola thus
reducing the size of the outside characters and increasing the size of the center characters.
S Capacitor value: Too low: picture will be squashed towards edges.
Too high: picture will be stretched towards edges.
By simply putting a capacitor in series with each coil, the sawtooth waveform is
modified into a slightly sine-wave shape. This reduces the scanning speed near the
edges where the yoke is more sensitive. Generally the deflection angle of the electron
beam and the yoke current are closely related. The problem is the deflection angle
verses the distance of movement on the CRT screen does not have a linear effect.
BASE DRIVE CURRENT
The base drive resistor determines the amount of
base drive. If the transistor is over driven the Vsat
looks very good, but the current fall time is poor.
If the base current is too small the current fall time is very fast. The problem is that the transistor will have many volts across C-E when closed.
The best condition is found by placing the transistor in the heaviest load condition. Adjust the base resistor for the least power consumption then increase the base drive a small amount. This will slightly over drive the base.
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.
DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.
APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C.
The PHILIPS TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
PHILIPS 14CT3405 CAMPIGLI CHASSIS KT3 TRD Video signal processing circuit for a color television receiver PHILIPS TDA3560: In a video signal processing circuit for a color television receiver, a brightness setting, which is operative for external color signals as well as for internal color signals and which does not produce a color shift, can be obtained by combining with the luminance signal (Y) a level shift signal (H) the amplitude of which is adjustable by the brightness setting and by employing in each color channel two clamping circuits, the first one of which clamps a first reference level (RL1) in the external color signal (ER, EG, EB) onto a combination of the level shift signal and the internal color signal (R, G, B) and the second clamping circuit clamps a second reference leve (RL2) which occurs in the sum signal of the internal and the external color signal when the level shift signal has zero value, onto the cutoff level of the relevant electron gun of a picture display tube.
1. A video signal
processing circuit for a color television receiver having inputs for a
luminance signal, for color difference signals and for external color
signals, comprising respective matrix circuits for combining the
respective color difference signals with the luminance signal to form
respective color signals, respective first clamping circuits for
clamping the respective external color signals onto the respective color
signals, respective combining circuits for combining the respective
clamped external color signals with the respective color signals,
respective second clamping circuits for clamping the outputs of the
respective combining circuits onto a predetermined level, and a
brightness setting circuit, characterized in that the first clamping
circuits act on a first reference level in said respective external
color signals occurring in a first group of periods and the second
clamping circuits act on a second reference level occurring in a second
group of periods which differ from the periods of the first group, while
the brightness setting circuit is an amplitude setting circuit for a
level shift signal, which is combined with the luminance signal prior to
processing the color difference signals, with which the relative
position of the second reference level with respect to the remaining
portion of the luminance signal is adjustable.
2. A video signal processing circuit as claimed in claim 1, characterized in that the respective first and second clamping circuits are operative alternately and every other line flyback period.
You can see the complexity of the tellye even only from the wiring around it.
TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET
DESCRIPTION
The TDA2593 isa circuit intended for the horizontal
deflectionof color TVsets, suppliedwith transistors
or SCR’S.
.LINE OSCILLATOR(two levels switching)
.PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE
Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity)
.PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATORVOLTAGE
Ø2
.COINCIDENCE DETECTOR PROVIDING A
LARGE HOLD-IN-RANGE .FILTER CHARACTERISTICS AND GATE
SWITCHING FOR VIDEO RECORDER APPLICATION
.NOISE GATED SYNCHRO SEPARATOR
.FRAME PULSE SEPARATOR
.BLANKING AND SAND CASTLE OUTPUT
PULSES
.HORIZONTAL POWER STAGE PHASE LAGGING
CIRCUIT
.SWITCHING OF CONTROL OUTPUT PULSE
WIDTH
.SEPARATED SUPPLY VOLTAGE OUTPUT
STAGE ALLOWING DIRECT DRIVE OF
SCR’S CIRCUIT .SECURITY CIRCUIT MAKES THE OUTPUT
PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.
Bei Ger·aten der Nachrichtentechnik wie z.B. einem Fernsehempf·anger ist es bekannt, die f·ur die einzelnen Stufen notwendigen Betriebsspannungen mit einem Schaltnetzteil aus der Netzspannung zu erzeugen (Funkschau 1975, Heft 5, Seite 40-43). Ein Schaltnetzteil erm·oglicht die f·ur den Anschluss ·ausserer Ger·ate und f·ur die Massnahmen zur Schutzisolierung vorteilhafte galvanische Trennung der Empf·angerschaltung vom Netz. Da ein Schaltnetzteil mit einer gegen·uber der Netzfrequenz hohen Frequenz von ca. 30 kHz arbeitet, kann der zur galvanischen Trennung dienende Trenntransformator gegen·uber einem Netztrafo f·ur 50 Hz wesentlich kleiner und leichter ausgebildet sein. Durch mehrere Wicklungen oder Wicklungsabgriffe und angeschlossene Gleichrichter k·onnen auf der Sekund·arseite des Trenntransformators Betriebs~ spannungen unterschiedlicher Gr·osse und Polarit·at erzeugt werden.
Ein solches Schaltnetzteil enth·alt eine Regelschaltung zur Stabilisierung der Amplitude der auf der Sekund·arseite erzeugten Betriebsspannungen. In dieser Regelschaltung wird eine durch Gleichrichtung der Impulsspannung am Trafo gewonnene Stellgr·osse erzeugt und mit einer Bezugsspannung verglichen. In Abh·angigkeit von der Abweichung wird der Schaltzeitpunkt des auf der Prim·arseite vorgesehenen elektronischen Schalters so gesteuert, dass die Amplitude der erzeugten Betriebsspannungen konstant bleibt.
Bei einem solchen Schaltnetzteil kann die genannte Regelschaltung z.B. durch ein fehlerhaftes Bauteil ausfallen. Die Regelung der Amplitude der erzeugten Betriebsspannungen ist dann unkontrolliert. Die Betriebsspannungen k·onnen dann auf den doppelten oder dreifachen Wert ansteigen. Dadurch besteht die Gefahr, dass das Schaltnetzteil oder die an die Betriebsspannungen angeschlossenen Verbraucher wie z.B. der Heizfaden der Bildr·ohre oder der Zeilenendstufentransistor zerst·ort werden. Der Anstieg der Betriebsspannungen kann dar·uberhinaus einen Anstieg der im Fernsehempf·anger erzeugten Hochspannung und dadurch eine R·ontgenstrahlung ausl·osen.
Es ist auch ein Schaltnetzteil bekannt (DE-OS 27 27 332), bei dem zum Schutz gegen einen zu starken Anstieg der erzeugten Betriebsspannungen aus der Impulsspannung an der Prim·arseite des Trafos eine Stellgr·osse gewonnen wird, die beim ·Uberschreiten eines Schwellwertes den R·uckkopplungsweg unwirksam steuert. Durch die Unterbrechung des R·uckkopplungsweges kann das Schaltnetzteil nicht mehr schwingen, so dass in erw·unschter Weise auch keine Betriebsspannungen mehr erzeugt werden. Diese Schaltung erfordert jedoch eine Vielzahl von Bauteilen und ist daher relativ teuer.
Der Erfindung liegt die Aufgabe zugrunde, eine sicher wirkende Schutzschaltung mit verringertem Schaltungsaufwand gegen
die oben
beschriebenen Gefahren zu schaffen.Diese Aufgabe wird durch die im Anspruch 1 beschriebene Erfindung gel·ost. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteranspr·uchen beschrieben.
Die Erfindung beruht auf folgender ·Uberlegung: Der Schalttransistor auf der Prim·arseite wird von der prim·arseitigen R·uckkopplungswicklung w·ahrend seiner stromleitenden Phase mit einem Basisstrom angesteuert. Wenn jetzt eine Sekund·arwicklung w·ahrend dieser stromleitenden Phase stark belastet, z.B. ·uber den Thyristor kurzgeschlossen wird, bricht auch die Spannung an der prim·arseitigen R·uckkopplungswicklung zusammen. Diese Wicklung kann dann f·ur den Schalttransistor nicht mehr einen f·ur den leitenden Betrieb ausreichenden Basis strom liefern. Das Schaltnetzteil schwingt dann nicht mehr, so dass die sekund·arseitigen Betriebsspannungen in erw·unschter Weise zusammenbrechen. Der schaltungstechni- sche Aufwand ist gering. Er besteht vorzugsweise aus einem Thyristor und zwei Widerst·anden.
Ein Ausf·uhrungsbeispiel der Erfindung wird anhand der Zeichnung erl·autert. Darin zeigen Figur 1 ein erfindungsgem·ass ausgebildetes Schaltnetzteil und Figur 2 Kurven zur Erl·auterung der Wirkungsweise. Dabei zeigen die kleinen Buchstaben, an welchen Punkten in Figur 1 die Spannungen gem·ass Figur 2 stehen.
Das Schaltnetzteil gem·ass Figur 1 enth·alt auf der Prim·arseite des Trenntransformators 1 den Netzgleichrichter 2, den Ladekondensator 3, den Strom-Messwiderstand 4, die Prim·arwicklung 5 den Schalttransistor 6, die zur Schwingungserzeugung dienende R·uckkopplungswicklung 7, den zur Steuerung des Schalttransistors 6 dienenden Thyristor 8, die Regelwicklung 9, den zur Erzeugung der Regelspannung dienenden Gleichrichter 10 sowie die zur Stabilisierung der Betriebsspannungen dienende Regelschaltung 11 mit dem Transistor 12 und der eine Referenzspannung lieferndenZenerdiode 13. Die Sekund·arwicklung 14 liefert ·uber den Gleichrichter 15 eine erste Betriebsspannung U1 von 150 V. Ein Abgriff der Wicklung 14 liefert ·uber den Gleichrichter 16 eine zweite Betriebsspannung U2 von 12 V f·ur einen Fernbedienungsempf·anger.
Eine weitere Sekund·arwicklung 19 liefert ·uber den Gleichrichter 20 eine dritte Betriebsspannung U3 von 12 V. Die Polung der Wicklungen 14,19 und der Gleichrichter 15,16,20 ist derart, dass die Gleichrichter 15,16,20 w·ahrend der Sperrphase des Schalttransistors 6 durch die sekund·arseitig auftretenden Impulsspannungen leitend gesteuert sind und die angeschlossenen Ladekondensatoren aufladen.
An das untere Ende der Wicklung 19 ist zus·atzlich der Thyristor 24 angeschlossen. An die Steuerelektrode b des Thyristors 24 ist die Betriebs spannung U2 ·uber den Spannungsteiler 25,26 angelegt.
Die Wirkungsweise der Schaltung wird anhand der Figur 2 erl·autert. Es sei angenommen, dass das Schaltnetzteil im Zeitpunkt tl in Betrieb genommen wird. Mit der Diode 21 wird aus der Netzspannung am Punkt d ein positiver Impuls erzeugt. Dieser gelangt ·uber den Kondensator 23 auf die Basis des Schalttransistors 6 und steuert diesen leitend. Dadurch beginnt das Schaltnetzteil zu schwingen, wobei die Schwingung durch die R·uckk
opplungswicklung 7
aufrechterhalten wird. Am Punkt a entsteht dann eine m·aanderf·ormige
Wechselspannung mit einer Frequenz von etwa 25-30 kHz.Die daraufhin in den Sekund·arwicklungen 14,19 erzeugten Impulse erzeugen in der beschriebenen Weise die Betriebsspannungen U1,U2,U3. Der Spannungsteiler 25,26 ist so bemessen, dass der Thyristor 24 gesperrt bleibt, d.h. die Spannung am Punkt 6 jst kleiner als 0,7 V. Der Thyristor 24 hat dann keine Wirkung. Dir Amplitude der Spannungen Ui,U2,U3 wird ·uber die Regelschaltung 11 stabilisiert.
Es sei jetzt angenommen, dass durch einen Fehler in der Regelschaltung 11, z.B. durch Ausfall eines Bauteiles, die Regelung zur Stabilisierung der Betriebsspannungen U1,U2,U3 nicht mehr wirkt und diese Betriebsspannungen stark ansteigen. Dadurch steigt auch die Spannung am Punkt b an.
Im Zeitpunkt t2 erreicht diese Spannung den Wert von 0,7 V, so dass der Thyristor 24 z·undet. Der untere Teil der Wicklung 19 ist jetzt praktisch kurzgeschlossen. Das Netzteil ist dadurch sekund·arseitig so stark belastet, dass die R·uck kopplungswicklung 7 keinen ausreichenden Basisstrom zur Steuerung des Schalttransistors 6 in seine stromleitende Phase mehr liefert. Im Zeitpunkt t2 bricht die Schwingung des Schaltnetzteiles ab, so dass auch die Wechselspannung am Punkt a auf null abf·allt. Den Ladekondensatoren der Gleichrichter 15,16,20 wird kein Strom mehr zugef·uhrt, so dass die Betriebspannungen U1,U2,U3 nicht weiter ansteigen k·onnen, sondern entsprechend den wirksamen Entladezeitkonstanten abfallen. Das Schaltnetzteil w·urde auf diese Weise an sich beliebig lange ausgeschaltet bleiben.
Im Zeitpunkt t3 erscheint am Punkt b der n·achste aus der Netzspannung gewonnene Startimpuls, der den Schalttransistor 6 wieder leitend steuert, so dass die Wechselspannung am Punkt a wieder auftritt. Das Schaltnetzteil geht also in einen getakteten Betrieb ·uber, bei dem die ·ubertragene Leistung entsprechend dem Zeitverh·altnis zwischen Einschaltphase und Ausschaltphase der Spannung am Punkt a betr·achtlich verringert ist. Die Betriebsspannungen U11U2,U3 k·onnen nicht mehr unzul·assig hohe Werte annehmen.
- GELOSO TVC14" MODELLO G.14032 CHASSIS 3880319 UNITS VIEW. LINE DEFLECTION OUTPUT UNIT WITH BU208A (Ei) This p.c.b. amplifies the pulse sequence at line frequency and drives a circuit operating as
an ON-OFF switch for supplying the deflection current to the horizontal yoke. It also
receives the parabolic signal which acts on the diodes modulator for E/W correction.
Series was featuring a Simplified BU208A transitor horizontal deflection section replacing all Thyristor horizontal timebase based circuits.
A horizontal deflection circuit makes a sawtoothcurrent flow through a deflection coil. The current
will have equal amounts of positive and negative
current. The horizontal switch transistor conducts
for the right hand side of the picture. The damper
diode conducts for the left side of the picture.
Current only flows through the fly back capacitor
during retrace time.
For time 1 the transistor is turned on. Current
ramps up in the yoke. The beam is moved from the
center of the picture to the right edge. Energy is
stored on the inductance of the yoke.
E=I2L/2
For time 2 the transistor is turned off. Energy
transfers from the yoke to the flyback capacitor. At
the end of time two all the energy from the yoke is
placed on the flyback capacitor. There is zero
current in the yoke and a large voltage on the
capacitor. The beam is quickly moved from the
right edge back to the middle of the picture.
During time 3 the energy on the capacitor flowsback into the yoke. The voltage on the flyback
capacitor decreases while the current in the yoke
builds until there is no voltage on the capacitor. By
the end of time 3 the yoke current is at it's
maximum amount but in the negative direction.
The beam is quickly deflected form the center to the
left edge.
Time 4 represents the left hand half of the picture.
Yoke current is negative and ramping down. The
beam moves from the left to the center of the
picture.
The current that flows when the horizontal switch is
closed is approximately:
Ipk ≅ Vcc T / Ldy
Ipk = collector current
T = 1/2 trace time
Ldy = total inductance (yoke + lin coil + size coil)
note:The lin coil inductance varies with current.
______
Tr ≅ 3.14 √ L C
The current that flows during retrace is produced by
the C and L oscillation. The retrace time is 1/2 the
oscillation frequency of the L and C.
I2L /2 ≅ V2C /2 or I2L = V2C As stated earlier the energy in the yoke moves to the
flyback capacitor during time 2.
V= the amount of the flyback pulse that is above the
supply voltage.
D.C. annualizes is inductors are consideredshores, capacitors are open and generally
semiconductors are removed. The voltage at the
point “B+” is the supply voltage. The collector
voltage of Q1 is also at the supply voltage. The
voltage across C2 is equal to the supply voltage.
When we A.C. annualize this circuit we will find
that the collector of Q1 has a voltage that ranges
from slightly negative to 1000 volts positive. The
average voltage must remain the same as the D.C.
value.
In the A.C. annualizes of the circuit, the
inductance of the yoke (DY) and the inductance of
the flyback transformer are in parallel. The
inductance of T2 is much larger than that if the
DY. This results is a total system inductance of
about 10% to 20% less than that of the DY it’s
self.
The voltage across the Q1 is a half sinusoid pulse during the flyback or retrace period and close to zero at
all other times. It is not possible or safe to observe this point on an oscilloscope without a proper high
frequency high voltage probe. Normally use a 100:1 probe suitable for 2,000V peak. The probe must have
been high frequency calibrated recently.
HORIZONTAL SIZE / E/W AMPLITUDE - CORRECTION CIRCUIT:
There are several different methods of adjusting horizontal size.
SIZE COILAdd a variable coil to the yoke current path
causes the total inductance to vary with the coils
setting.
The yoke current is related to supply voltage,
trace time and total inductance. This method
has a limited range!
The horizontal section uses a PWM to set the
horizontal size. One DAC sets the horizontal
size and another DAC sets the pincushion and
trap.
The Raster Centering (D.C. centering) is
controlled by a DAC.
On small monitors the retrace time is fixed. On
large monitors or wide frequency range monitors
two different retrace times are available. The flyback time is set by the micro computer by selecting two
different flyback capacitors. At slow frequencies the longer retrace time is selected.
Different S corrector capacitor values are selected by the micro computer. At the highest frequency the
smallest capacitor is selected.
SPLIT DIODE MODULATORThis horizontal circuit consists of two parts. D1, C1, C2 and DY are the components as described above.
D2, C3, C4 and L1 are a second “dummy” horizontal section that does not cause deflection current. By the
D.C. analyzing this circuit the voltage across C2 + C4 must equal the supply voltage (B+). Deflection
current in the DY is related to the supply voltage minus the voltage across C4. For a maximum horizontal
size the control point must be held at ground. This causes the dummy section to not operate and the DY
section will get full supply voltage. If the control point is at 1/3 supply then the DY section will be
operating at 2/3 supply.
Note: The impedance of (D1,C1,C2 and DY) and (D2,C3,C4 and L1) makes a voltage divider. If the
control point is not connected then there is some natural voltage on C4. Most split diode monitors are built
to pull power from the dummy section through L2 to ground. A single power transistor shunts from the
The most exciting feature if the split diode modulator is that the flyback pulse, as seen by the flyback
transformer, is the same size at all horizontal size settings.
HORIZONTAL SWITCH/DAMPER DIODE
On the right hand side of the screen, the H. switch transistor conducts current through the deflection yoke.This current comes from the S correction capacitors, which have a charge equal to the effective supply
voltage. The damper diode allows current for the left hand side of the screen to flow back through the
deflection yoke to the S capacitors.
FLYBACK CAPACITOR
The flyback capacitor connects the hot side of the yoke to ground. This component determines the size and
length of the flyback pulse. ‘Tuning the flyback capacitor’ is done to match the timing of the flyback pulse
to the video blanking time of the video signal. The peak flyback voltage on the horizontal switch must be
set to less that 80% if the Vces specification. The two conditions of time and voltage can be set by three
variables (supply voltage, retrace capacitor and yoke inductance) .
S CAPACITOR
The S capacitors corrects outside versus center linearity in the horizontal scan. The voltage on the S cap
has a parabola plus the DC horizontal supply. Reducing the value of S cap increases this parabola thus
reducing the size of the outside characters and increasing the size of the center characters.
S Capacitor value: Too low: picture will be squashed towards edges.
Too high: picture will be stretched towards edges.
By simply putting a capacitor in series with each coil, the sawtooth waveform is
modified into a slightly sine-wave shape. This reduces the scanning speed near the
edges where the yoke is more sensitive. Generally the deflection angle of the electron
beam and the yoke current are closely related. The problem is the deflection angle
verses the distance of movement on the CRT screen does not have a linear effect.
BASE DRIVE CURRENT
The base drive resistor determines the amount of
base drive. If the transistor is over driven the Vsat
looks very good, but the current fall time is poor.
If the base current is too small the current fall time is very fast. The problem is that the transistor will have many volts across C-E when closed.
The best condition is found by placing the transistor in the heaviest load condition. Adjust the base resistor for the least power consumption then increase the base drive a small amount. This will slightly over drive the base.
BU208(A)
Silicon NPNnpn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.
DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.
APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C.
The PHILIPS TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control isa linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast controlThe contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is acti
vated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
PHILIPS 14CT3405 CAMPIGLI CHASSIS KT3 TRD Video signal processing circuit for a color television receiver PHILIPS TDA3560: In a video signal processing circuit for a color television receiver, a brightness setting, which is operative for external color signals as well as for internal color signals and which does not produce a color shift, can be obtained by combining with the luminance signal (Y) a level shift signal (H) the amplitude of which is adjustable by the brightness setting and by employing in each color channel two clamping circuits, the first one of which clamps a first reference level (RL1) in the external color signal (ER, EG, EB) onto a combination of the level shift signal and the internal color signal (R, G, B) and the second clamping circuit clamps a second reference leve (RL2) which occurs in the sum signal of the internal and the external color signal when the level shift signal has zero value, onto the cutoff level of the relevant electron gun of a picture display tube.
1. A video signal
processing circuit for a color television receiver having inputs for a
luminance signal, for color difference signals and for external color
signals, comprising respective matrix circuits for combining the
respective color difference signals with the luminance signal to form
respective color signals, respective first clamping circuits for
clamping the respective external color signals onto the respective color
signals, respective combining circuits for combining the respective
clamped external color signals with the respective color signals,
respective second clamping circuits for clamping the outputs of the
respective combining circuits onto a predetermined level, and a
brightness setting circuit, characterized in that the first clamping
circuits act on a first reference level in said respective external
color signals occurring in a first group of periods and the second
clamping circuits act on a second reference level occurring in a second
group of periods which differ from the periods of the first group, while
the brightness setting circuit is an amplitude setting circuit for a
level shift signal, which is combined with the luminance signal prior to
processing the color difference signals, with which the relative
position of the second reference level with respect to the remaining
portion of the luminance signal is adjustable. 2. A video signal processing circuit as claimed in claim 1, characterized in that the respective first and second clamping circuits are operative alternately and every other line flyback period.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals, and for external color signals, comprising a matrix circuit for combining a color difference signal with the luminance signal to form a color signal, a first clamping circuit for clamping an external color signal onto the corresponding color signal, a combining circuit for combining a clamped external color signal with the corresponding color signal, a second clamping circuit acting on an output signal of the combining circuit and a brightness setting circuit.
A video
signal processing circuit of the type defined above is described in
Philip Data Handbook for Integrated Circuits, Part 2, May, 1980 as IC
TDA3560. The brightness setting, which is common for internal and
external video signals, is obtained by means of a common direct current
level setting of the second clamping circuits. The settings of the three
electron guns of a picture display tube coupled to the outputs of the
video signal processing circuit are changed to an equal extent by this
direct current level setting as a result whereof, due to the mutual
differences in the efficiency of the phosphors of the picture display
tube, a color shift may occur at a brightness adjustment. It is an
object of the invention to prevent this.
SUMMARY OF THE INVENTION
According to the invention, a video signal processing circuit of the type defined in the preamble is therefore characterized in that the first clamping circuit acts on a first reference level occurring in a first group of periods and the second clamping circuit acts on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
Owing to the measure in accordance with the invention, the common setting of the brightness for internal video signals is maintained and a color shift is prevented from occurring at a brightness setting.
DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be further described by way of example with reference to the accompanying drawings.
In the drawings:
FIG. 1 illustrates, by means of a block schematic circuit diagram, a video signal processing circuit in accordance with the invention; and
FIG. 2 shows some waveforms such as they may occur in the circuit shown in FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In
FIG. 1, an external red color signal ER' is applied to an input 1, a
red color difference signal (R-Y) to an input 3, an external green color
signal EG' to an input 5, a luminance signal Y to an input 7, a green
color difference signal (G-Y) to an input 9, an external blue color
signal EB' to an input 11, a blue color difference signal (B-Y) to an
input 13 and a synchronizing signal S to an input 15.
The luminance signal at the input 7 is shown in FIG. 2 as a waveform 207. In the line flyback periods this luminance signal has a black level Z which, for simplicity, is assumed to occur in all cases during the whole line flyback period but which may, of course, alternatively occur during only a portion of that line flyback period.
The luminance signal Y is applied to an input 17 of a combining circuit 19. To a further input 21 thereof, a level shift signal H is applied which, via an amplitude setting circuit 23, is obtained from an output 25 of a pulse generator 27, to an input 29 of which the synchronizing signal S is applied.
The level shift signal H is shown in FIG. 2 as a waveform 221 which in this case has a zero amplitude every other line flyback period and at other times an amplitude which depends on the setting of the amplitude setting circuit 23.
The respective color
difference signals (R-Y), (G-Y) and (B-Y) at the respective inputs 3, 9
and 13, are applied to inputs 31, 33 and 35, respectively, of matrix
circuits 37, 39 and 41, respectively, to respective inputs 43, 45 and 47
of which the combination Y+H of the luminance signal (Y) and the level
shift signal (H) is applied, and from respective outputs 49, 51 and 53,
the red (R) and green (G) and blue (B) color signals are obtained. FIG. 2
shows the red color signal of said color signals as a waveform 249.
The respective external color signals ER', EG' and EB' at the respective inputs 1, 5 and 11 are applied to respective inputs 61, 63 and 65 of respective combining circuits 67, 69 and 71 via respective capacitors 55, 57 and 59. Further inputs 73, 75 and 77, respectively, of the combining circuits 67, 69 and 71, respectively, are connected to the outputs 49, 51 and 53, respectively, of the matrix circuits 37, 39 and 41, respectively, and receive the red, green and blue color signals, respectively.
Arranged between the inputs 61 and 73, 63 and 75, and 65 and 77, respectively, there are first clamping circuits 79, 81 and 83, respectively, which, under the control of a pulse signal K1 coming from an output 84 of the pulse generator 27, clamps a first reference level RL1 in the respective external color signals ER', EG' and EB' onto the respective color signals R, G and B, as a result of which the respective clamped external color signals ER, EG and EB at the respective inputs 61, 63 and 65 of the combining circuits 67, 69 and 71 are produced, the signal level ER at the input 61 of the combining circuit 67 being shown in FIG. 2 as the waveform 261. The pulse signal K1 is shown in FIG. 2 as the waveform 284.
At respective outputs 85, 87 and 89 of the combining circuits 67, 69 and 71, respectively, there are now produced signals which are the sums of the respective clamped external color signals ER, EG and EB and the respective color signals R, G and B. Via respective capacitors 91, 93 and 95, said sum signals (ER+R), (EG+G) and (EB+B), respectively, are applied to respective inputs 97, 99 and 100 of respective video output amplifiers 102, 104 and 106, respective outputs 108, 110 and 112 of which being connected to respective cathodes of a picture display tube 114.
Second clamping circuits 116, 118 and 120, respectively, which are rendered operative by a pulse signal K2 coming from an output 122 of the pulse generator 27 and whereby a second reference level RL2 in the signals at the respective inputs 97, 99 and 100 is adjusted to a fixed potential, zero potential here, are connected to the respective inputs 97, 99 and 100 of the respective video output amplifiers 102, 104 and 106. This is shown in FIG. 2 by means of the waveform 297 for the signal (ER+R) at the input 97 of the video output amplifier 102. For the sake of clearness, the luminance signal (Y) and the red color difference signal (R-Y) are assumed to have zero values.
The picture display tube 114 has a deflection circuit 124 which is controlled by signals coming from outputs 126 and 128, respectively, of the pulse generator 27.
On the basis of FIG. 2, it will now be demonstrated that the brightness of the color signals as well as of the external color signals is adjustable by means of the amplitude setting circuit 23, more specifically in such a ratio, occurring at the picture display tube 114, that no color shift is produced.
If a luminance signal Y and a color difference signal
(R-Y) are produced and the external color signal ER' has zero value, the
signal at the output 49 of the matrix circuit 37 has the waveform 249
and likewise the signal at the input 97 of the video output amplifier
108, as during the occurrence of the signal K2 (waveform 222), the
second clamping circuit 116 has adjusted the second reference level RL2
to zero, which corresponds to the cutoff level of the relevant cathode
of the picture display tube 114. Outside the periods in which signal is
clamped to the second reference level RL2, the black level,
shown in the waveform 249 by means of a dashed line, of the color signal
at the input 97 of the video amplifier is determined by the amplitude
of the level shift signal H, which, in response to the video output
amplifier gain factors which are adapted to the efficiencies of the
phosphors of the picture display tube, are applied in the relevant
signal paths to the cathodes of the picture display tube 114 to said
cathodes in such an amplitude ratio that no color shift can be produced.
If there is an external color signal but no luminance and color
difference signals (Y=O, R-Y=O, G-Y=O, B-Y=O), then a signal is produced
at the input 97 of the video output amplifier 102 which has the
waveform 297 and which, during the occurrence of the second reference
level RL2, is clamped onto zero by the second clamping
circuit 116 by means of the clamping pulses K2 and which consequently
corresponds to the cutoff level of the relevant cathode of the picture
display tube 114. During the occurrence of the first reference level RL1
in the signal ER', the first clamping circuit 79 clamps the signal ER
(waveform 261) at the input 61 of the combining circit 61 onto the
output signal of the matrix circuit 37 during the occurrence of the
clamping pulses K1 (waveform 284). Now this output signal has the
waveform 221, as R-Y and Y have zero values. From the waveform 297, it
now appears that the signal ER+R, which in this case is equal to ER+H,
has, outside the periods in which the second reference level RL2
occurs in the waveform 297, a black level which is indicated by means
of a dashed line and is determined by the amplitude of the level shift
signal H. Also now this amplitude is applied in the proper ratio to the
cathodes of the picture display tube 114 by the video output amplifier
gain factors which are adapted to the efficiencies of the phosphors of
the picture display tube 114, so that no color shift can be produced.
It will be obvious that it is not imperative that the clamping pulses K1 and K2 be produced alternately and every other line flyback period. If so desired, the clamping pulses K1 may, for example, occur in a number of line trace periods of the field trace which are located outside the visible picture plane, and the clamping pulses K2 may occur in the line flyback periods. The clamping pulses K2 must be produced in the period in which the level shift signal causes the second reference level RL2 and the clamping pulses K1 outside said periods and in the periods the first level reference level RL1 occurs.
In the above-described embodiment the clamping circuits are provided in the form of short-circuiting switches which are arranged subsequent to capacitors which have for their function to block direct current signals. It will be obvious, that, if so desired, clamping circuits in the form of control circuits may alternatively be used and that in that event, if so desired, blocking the direct current component by a capacitor may be omitted.
If so desired, instead of an adder circuit 19, an insertion circuit may be employed by means of which, in the appropriate periods of the luminance signal, when the signal K2 is produced the reference level Z then present, is replaced by a new level which is influencable by the brightness setting .
The invention relates to a video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals, and for external color signals, comprising a matrix circuit for combining a color difference signal with the luminance signal to form a color signal, a first clamping circuit for clamping an external color signal onto the corresponding color signal, a combining circuit for combining a clamped external color signal with the corresponding color signal, a second clamping circuit acting on an output signal of the combining circuit and a brightness setting circuit.
A video
signal processing circuit of the type defined above is described in
Philip Data Handbook for Integrated Circuits, Part 2, May, 1980 as IC
TDA3560. The brightness setting, which is common for internal and
external video signals, is obtained by means of a common direct current
level setting of the second clamping circuits. The settings of the three
electron guns of a picture display tube coupled to the outputs of the
video signal processing circuit are changed to an equal extent by this
direct current level setting as a result whereof, due to the mutual
differences in the efficiency of the phosphors of the picture display
tube, a color shift may occur at a brightness adjustment. It is an
object of the invention to prevent this. SUMMARY OF THE INVENTION
According to the invention, a video signal processing circuit of the type defined in the preamble is therefore characterized in that the first clamping circuit acts on a first reference level occurring in a first group of periods and the second clamping circuit acts on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
Owing to the measure in accordance with the invention, the common setting of the brightness for internal video signals is maintained and a color shift is prevented from occurring at a brightness setting.
DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be further described by way of example with reference to the accompanying drawings.
In the drawings:
FIG. 1 illustrates, by means of a block schematic circuit diagram, a video signal processing circuit in accordance with the invention; and
FIG. 2 shows some waveforms such as they may occur in the circuit shown in FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In
FIG. 1, an external red color signal ER' is applied to an input 1, a
red color difference signal (R-Y) to an input 3, an external green color
signal EG' to an input 5, a luminance signal Y to an input 7, a green
color difference signal (G-Y) to an input 9, an external blue color
signal EB' to an input 11, a blue color difference signal (B-Y) to an
input 13 and a synchronizing signal S to an input 15. The luminance signal at the input 7 is shown in FIG. 2 as a waveform 207. In the line flyback periods this luminance signal has a black level Z which, for simplicity, is assumed to occur in all cases during the whole line flyback period but which may, of course, alternatively occur during only a portion of that line flyback period.
The luminance signal Y is applied to an input 17 of a combining circuit 19. To a further input 21 thereof, a level shift signal H is applied which, via an amplitude setting circuit 23, is obtained from an output 25 of a pulse generator 27, to an input 29 of which the synchronizing signal S is applied.
The level shift signal H is shown in FIG. 2 as a waveform 221 which in this case has a zero amplitude every other line flyback period and at other times an amplitude which depends on the setting of the amplitude setting circuit 23.
The respective color
difference signals (R-Y), (G-Y) and (B-Y) at the respective inputs 3, 9
and 13, are applied to inputs 31, 33 and 35, respectively, of matrix
circuits 37, 39 and 41, respectively, to respective inputs 43, 45 and 47
of which the combination Y+H of the luminance signal (Y) and the level
shift signal (H) is applied, and from respective outputs 49, 51 and 53,
the red (R) and green (G) and blue (B) color signals are obtained. FIG. 2
shows the red color signal of said color signals as a waveform 249. The respective external color signals ER', EG' and EB' at the respective inputs 1, 5 and 11 are applied to respective inputs 61, 63 and 65 of respective combining circuits 67, 69 and 71 via respective capacitors 55, 57 and 59. Further inputs 73, 75 and 77, respectively, of the combining circuits 67, 69 and 71, respectively, are connected to the outputs 49, 51 and 53, respectively, of the matrix circuits 37, 39 and 41, respectively, and receive the red, green and blue color signals, respectively.
Arranged between the inputs 61 and 73, 63 and 75, and 65 and 77, respectively, there are first clamping circuits 79, 81 and 83, respectively, which, under the control of a pulse signal K1 coming from an output 84 of the pulse generator 27, clamps a first reference level RL1 in the respective external color signals ER', EG' and EB' onto the respective color signals R, G and B, as a result of which the respective clamped external color signals ER, EG and EB at the respective inputs 61, 63 and 65 of the combining circuits 67, 69 and 71 are produced, the signal level ER at the input 61 of the combining circuit 67 being shown in FIG. 2 as the waveform 261. The pulse signal K1 is shown in FIG. 2 as the waveform 284.
At respective outputs 85, 87 and 89 of the combining circuits 67, 69 and 71, respectively, there are now produced signals which are the sums of the respective clamped external color signals ER, EG and EB and the respective color signals R, G and B. Via respective capacitors 91, 93 and 95, said sum signals (ER+R), (EG+G) and (EB+B), respectively, are applied to respective inputs 97, 99 and 100 of respective video output amplifiers 102, 104 and 106, respective outputs 108, 110 and 112 of which being connected to respective cathodes of a picture display tube 114.
Second clamping circuits 116, 118 and 120, respectively, which are rendered operative by a pulse signal K2 coming from an output 122 of the pulse generator 27 and whereby a second reference level RL2 in the signals at the respective inputs 97, 99 and 100 is adjusted to a fixed potential, zero potential here, are connected to the respective inputs 97, 99 and 100 of the respective video output amplifiers 102, 104 and 106. This is shown in FIG. 2 by means of the waveform 297 for the signal (ER+R) at the input 97 of the video output amplifier 102. For the sake of clearness, the luminance signal (Y) and the red color difference signal (R-Y) are assumed to have zero values.
The picture display tube 114 has a deflection circuit 124 which is controlled by signals coming from outputs 126 and 128, respectively, of the pulse generator 27.
On the basis of FIG. 2, it will now be demonstrated that the brightness of the color signals as well as of the external color signals is adjustable by means of the amplitude setting circuit 23, more specifically in such a ratio, occurring at the picture display tube 114, that no color shift is produced.
If a luminance signal Y and a color difference signal
(R-Y) are produced and the external color signal ER' has zero value, the
signal at the output 49 of the matrix circuit 37 has the waveform 249
and likewise the signal at the input 97 of the video output amplifier
108, as during the occurrence of the signal K2 (waveform 222), the
second clamping circuit 116 has adjusted the second reference level RL2
to zero, which corresponds to the cutoff level of the relevant cathode
of the picture display tube 114. Outside the periods in which signal is
clamped to the second reference level RL2, the black level,
shown in the waveform 249 by means of a dashed line, of the color signal
at the input 97 of the video amplifier is determined by the amplitude
of the level shift signal H, which, in response to the video output
amplifier gain factors which are adapted to the efficiencies of the
phosphors of the picture display tube, are applied in the relevant
signal paths to the cathodes of the picture display tube 114 to said
cathodes in such an amplitude ratio that no color shift can be produced.
If there is an external color signal but no luminance and color
difference signals (Y=O, R-Y=O, G-Y=O, B-Y=O), then a signal is produced
at the input 97 of the video output amplifier 102 which has the
waveform 297 and which, during the occurrence of the second reference
level RL2, is clamped onto zero by the second clamping
circuit 116 by means of the clamping pulses K2 and which consequently
corresponds to the cutoff level of the relevant cathode of the picture
display tube 114. During the occurrence of the first reference level RL1
in the signal ER', the first clamping circuit 79 clamps the signal ER
(waveform 261) at the input 61 of the combining circit 61 onto the
output signal of the matrix circuit 37 during the occurrence of the
clamping pulses K1 (waveform 284). Now this output signal has the
waveform 221, as R-Y and Y have zero values. From the waveform 297, it
now appears that the signal ER+R, which in this case is equal to ER+H,
has, outside the periods in which the second reference level RL2
occurs in the waveform 297, a black level which is indicated by means
of a dashed line and is determined by the amplitude of the level shift
signal H. Also now this amplitude is applied in the proper ratio to the
cathodes of the picture display tube 114 by the video output amplifier
gain factors which are adapted to the efficiencies of the phosphors of
the picture display tube 114, so that no color shift can be produced. It will be obvious that it is not imperative that the clamping pulses K1 and K2 be produced alternately and every other line flyback period. If so desired, the clamping pulses K1 may, for example, occur in a number of line trace periods of the field trace which are located outside the visible picture plane, and the clamping pulses K2 may occur in the line flyback periods. The clamping pulses K2 must be produced in the period in which the level shift signal causes the second reference level RL2 and the clamping pulses K1 outside said periods and in the periods the first level reference level RL1 occurs.
In the above-described embodiment the clamping circuits are provided in the form of short-circuiting switches which are arranged subsequent to capacitors which have for their function to block direct current signals. It will be obvious, that, if so desired, clamping circuits in the form of control circuits may alternatively be used and that in that event, if so desired, blocking the direct current component by a capacitor may be omitted.
If so desired, instead of an adder circuit 19, an insertion circuit may be employed by means of which, in the appropriate periods of the luminance signal, when the signal K2 is produced the reference level Z then present, is replaced by a new level which is influencable by the brightness setting .
TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SETDESCRIPTION
The TDA2593 isa circuit intended for the horizontal
deflectionof color TVsets, suppliedwith transistors
or SCR’S.
.LINE OSCILLATOR(two levels switching)
.PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE
Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity)
.PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATORVOLTAGE
Ø2
.COINCIDENCE DETECTOR PROVIDING A
LARGE HOLD-IN-RANGE .FILTER CHARACTERISTICS AND GATE
SWITCHING FOR VIDEO RECORDER APPLICATION
.NOISE GATED SYNCHRO SEPARATOR
.FRAME PULSE SEPARATOR
.BLANKING AND SAND CASTLE OUTPUT
PULSES
.HORIZONTAL POWER STAGE PHASE LAGGING
CIRCUIT
.SWITCHING OF CONTROL OUTPUT PULSE
WIDTH
.SEPARATED SUPPLY VOLTAGE OUTPUT
STAGE ALLOWING DIRECT DRIVE OF
SCR’S CIRCUIT .SECURITY CIRCUIT MAKES THE OUTPUT
PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.
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