SONG IC UNIT (CONTROL TUNING REMOTE VST) 8222.280.2132.3
LINEAR FUNCTIONS (LINEAR FUNCTIONS AND SEARCH BAR GENERATION) 482221220588
8222 280 2139.1 SEARCH UNIT (PERFORMS SEARCH DRIVING SONG IC WITH VIDEO IDENTIFICATION AND FINE TUNING AUTOMATICALLY)
SUPPLY 4822 212 20302
MATRIX 3122 133 31460
CHROMA 4822 212 20306
SOUND 4822 212 20599
MULTISTABILIZER 4822 212 20304
IF AMPLIFIER 4822 212 20309
3122 133 31490
E/W + 29 /32/225V SUPPLY 4822 212 20305
SYNCRONIZATION 3122 133 31470
IF DETECTOR 3122 133 30480
FRAME DEFLECTION 20AX 4822 212 20303
TDA2581 CONTROL CIRCUIT FOR SMPS
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
PHILIPS 26C858 / 38Z CHASSIS K12 (20AX) E/W CORRECTION Circuit arrangement in an image display apparatus for (horizontal) line deflection:
Line deflection circuit in which the deflection coil is east-west modulated. In order to cancel an east-west dependent horizontal linearity defect the inductance value of the linearity correction coil is made independent of the field frequency, for example by means of a compensating current. In an embodiment this current is supplied by the shunt coil of the east-west modulator.
1. Circuit arrangeme
nt for use with a line deflection coil, said circuit comprising a generator means adapted to be coupled to said coil for producing a sawtooth line-deflection current through said line deflection coil, said deflection current having a field-frequency component current, a horizontal linearity correction coil adapted to be coupled in series with said deflection coil and including an inductor having a bias-magnetized core, and means for making the inductance value of the linearity correction coil substantially independent of the field frequency component current. 2. Circuit arrangement as claimed in claim 1, wherein said making means includes a current supply source means for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the compensating current having a field-frequency variation. 3. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is opposite to the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have the same direction. 4. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is the same as the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have opposite directions. 5. Circuit arrangement as claimed in claim 2, wherein said correction coil further comprises an additional winding disposed on the core, said additional winding being coupled to said supply source means to receive the compensating current. 6. Circuit arrangement as claimed in claim 5, further comprising modulator means for modulating the line deflection current with said field frequency component, said modulator including a compensation coil coupled in series with said additional winding. 7. Horizontal linearity correction coil comprising a core made of a magnetic material and bias-magnetized by at least one permanent magnet, and an additional winding disposed on the core. 8. Image display apparatus including a circuit arrangement as claimed in claim 1. The invention relates to a circuit arrangement in an image display apparatus for (horizontal) line deflection, which apparatus also includes a circuit arrangement for (vertical) field deflection, provided with a generator for generating a sawtooth line-frequency deflecting current through a line deflection coil and with a modulator for field-frequency modulation of this current, the deflection coil being connected in series with a linearity correction coil in the form of an inductor having a bias-magnetized core.
By means of the linearity correction coil the linearity error due to the ohmic resistance of the deflection circuit is corrected. The sign of the bias magnetisation is chosen so that it is cancelled by the deflection current at the beginning of the deflection interval, so that the inductance of the correction coil is a maximum, whereas the voltage drop across the deflection coil then is a minimum. This voltage drop is adjustable by adjustment of the starting inductance of the correction coil. During the deflection interval the core gradually becomes saturated so that the inductance of, and the voltage drop across, the correction coil decrease. Thus the linearity error can be cancelled exactly at the beginning of the interval, that is to say on the left on the screen of the image display tube, and with a certain approximation at other locations.
In image display tubes using a large deflection angle, raster distortion, which generally is pincushion-shaped, of the image displayed occurs. This distortion can be removed in the horizontal direction, the so-called east-west direction, by means of field-frequency modulation of the line deflection current, the envelope in the case of pincushion-shaped distortion being substantially parabolic so that the amplitude of the line deflection current is a maximum at the middle of the field deflection interval.
It was found in practice that the said two corrections are not independent of one another, that is to say the adjustment of the east-west modulation affects horizontal linearity. As long as the modulation depth is not excessive, a satisfactory compromise can be found. However, in display tubes having a deflection angle of 110° and particularly in colour display tubes in which the deflection coils have a converging effect also, it is difficult to find such a compromise. A tube of this type is described in "Philips Research Reports," volume Feb. 14, 1959, pages 65 to 97; the distribution of the deflection field is such that throughout the display screen the landing points of the electron beams coincide without the need for a converging device. Owing to this field distribution, however, the pin-cushion-shaped distortion in the image displayed in the east-west direction is greater than in comparable display tubes of another type. Hence there must be east-west modulation of the line deflection current to a greater depth. It is true that under these conditions horizontal linearity can correctly be adjusted over a given horizontal strip after the east-west modulation has been adjusted correctly, i.e., for a rectangular image, but it is found that in other parts of the display screen a serious linearity error remains. When vertical straight lines are displayed as straight lines in the right-hand part of the screen, they are displayed as curved lines in the left-hand part.
It is an object of the present invention to remove the said defect so that horizontal linearity can satisfactorily be adjusted throughout the screen, and for this purpose the circuit arrangement according to the invention is characterized in that it includes means by which the inductance of the linearity correction coil is made substantially independent of the field frequency.
The invention is based on the recognition that the defect to be removed is due to a field-frequency variation of the said inductance because the latter is current-dependent. According to a further recognition of the invention the circuit arrangement is characterized in that it includes a current supply source for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the current being field-frequency modulated. The circuit arrangement according to the invention may further be characterized in that an additional winding is provided on the core of the linearity correction coil and is traversed by the compensating current. A circuit arrangement in which the modulator for modulating the line deflection current includes a compensation or bridge coil may according to the invention be characterized in that the additional winding is connected in series with the said coil.
The invention also relates to a linearity correction coil for use in a line deflection circuit having a core which is made of a magnetic material and is bias magnetized by at least one permanent magnet, which coil is characterized in that an additional winding is provided on the core.
Embodiments of the invention will now be described by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is the circuit diagram of a known circuit arrangement for line deflection in which the line deflection current is east-west modulated,
FIG. 2 shows the distorted image which is displayed on the screen when the circuit arrangement of FIG. 1,
FIG. 3 is a graph explaining the observed defect, and
FIGS. 4 and 7 show embodiments of the circuit arrangement according to the invention by which this defect can be cancelled.
FIG. 1 is a greatl
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG.
To the base of transistor Tr line-frequency switching pulses are supplied. In known manner the said series combination is connected to the supply voltage source during the deflection interval (the trace time), diode D and transistor Tr conducting alternately. During the retrace time these elements are both cut off. Under these conditions the current i y is a sawtooth current. The coil L, which has a saturable ferrite core which is bias-magnetized by means of at least one permanent magnet, serves to correct the linearity of the current i y during the trace time, whilst the capacitance of the capacitor C t is chosen so that the currenct i y is subjected to what is generally referred to as S correction. During the retrace time, at point A pulses are produced the amplitude of which is much higher than that of the voltage V b and would be constant in the absence of modulation source M. Information from the field deflection circuit, not shown, of the image display apparatus and line retrace pulses, the latter for example by means of a transformer, are supplied in known manner to modulation source M. Amplitude-modulated line retrace pulses having a field-frequency parabolic envelope, as indicated in the FIG., are produced at point B. During the line trace time the voltage at point B is zero. Thus the current i y is given the desired field-frequency modulated form which is also shown in FIG. 1.
The amplitude of the envelope in point B at the beginning and at the end of the field trace time and the amplitude of this envelope at the middle of the said time can both be adjusted so that the image displayed on the display screen of the display tube (not shown) has the correct substantially rectangular form. If, however, the required modulation depth is comparatively large, a linearity error of the line deflection is produced which cannot be removed by means of the correction coil L.
FIG. 2 shows the image of a pattern of vertical straight lines as it is displayed on the screen with the correction coil L adjusted so that horizontal linearity is satisfactory along and near the central horizontal line. In FIG. 2 the defect is exaggerated. It is found that horizontal linearity is defective in other areas of the screen so that the vertical lines are displayed correctly in the right-hand half of the screen but as curves in the left-hand path, the defect increasing as the line is farther to the left.
This phenomenon can be explained with reference to FIG. 3. In this FIG. the inductance L of the linearity correction coil is plotted as a function of the magnetic field strength H. In the absence of current, H has a value H 0 owing to the bias magnetization. If an approximately linear sawtooth current i (t) as shown in the b
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t .
Because owing to the east-west modulation the amplitude of current i(t) varies, the amplitude of L(t) also varies. This implies a field-frequency variation of L which is non-linear. This variation is undesirable. In the case of a small variation of the amplitude of current i(t) the variation of L(t) can be more or less neglected, but this is no longer possible when the amplitude of current i(t) varies greatly owing to the east-west modulation. L(t) varies according to different curves. FIG. 3 shows two of such curves and also illustrates the fact that the undesirable variation of L(t) is greatest at the beginning of the trace time and smallest at the end thereof.
FIG. 4 shows a circuit arrangement in which the defect described can be corrected. On the core of the correction coil L of the circuit of FIG. 1 an additional winding L 2 is provided. Winding L 2 is connected to a current source which produces a compensating current i 2 which has a line-frequency sawtooth variation and a field-frequency amplitude modulation. The envelope here also is parabolic, however, with a shape opposite to that of deflection current i y , that is to say having a minimum at the middle of the field trace time. The direction of current i 2 and the winding sense of winding L 2 relative to that of coil L are chosen so that the magnetic field produced in the core by winding L 2 has the same direction as the field produced by coil L. Hence the two field strengths are added. The amplitude of current i 2 and the turns number of winding L 2 can be chosen so that current i y flows through inductances the total value of which is not dependent upon the field frequency. The curve L(t) of FIG. 3 remains substantially unchanged. Consequently the undesirable field-frequency modulation is removed without variation of the bias magnetization, which would have been varied if current i 2 were a field-frequency current. Obviously the same result can be achieved by a choice such of the direction of current i 2 and of the winding sense of winding L 2 that the two field strengths are subtracted one from the other, whilst the curvature of the envelope of current i 2 has the same direction as that of the envelope of current i y .
The current source of FIG. 4 may be formed in known manner by means of a modulator in which a line-frequency sawtooth signal is field-frequency modulated, the envelope being parabolic. FIG. 5 shows a circuit arrangement in which current i 2 is produced by the modulation source which provides the east-west correction. In FIG. 5, the source M of FIG. 1 comprises a diode D', a coil L' and two capacitors C' r and C' t , which elements constitute a network of the same structure as the network formed by elements D, L y , C r and C t . The capacitor C' t is shunted by a modulation source V m which supplies a field-frequency parabolic voltage having a minimum at the middle of the field trace time.
With the exception of the linearity correction means to be described hereinafter, the circuit arrangement of FIG. 5 was described in more detail in U.S. Pat. No. 3,906,305. Hence it will be sufficient to mention that the capacitances of capacitors C r and C' r and of a capacitor C 1 connected between junction point A and earth and the inductance of coil L' are chosen so that the three sawtooth currents flowing through L y , L' and L 1 have the same retrace time. The capacitances of capacitors C t and C' t , which are large, are ignored. When voltage V b is constant, current i y is subjected to the desired east-west modulation having the form shown in FIG. 1.
Coil L y is connected in series with correction coil L, and winding L 2 is connected in series with coil L'. FIG. 5 shows that the current flowing through winding L 2 has the same waveform as the current i 2 of FIG. 4, for its envelope has the same shape as the voltage supplied by source V m . By a suitable choice of the number of turns of winding L 2 it can be ensured that the linearity correction remains the same for every line during the field trace time.
Modified embodiments of the circuit arrangement of FIG. 5 can also be used. FIG. 6 shows such a modified embodiment in which the capacitive voltage divider C r , C' r of FIG. 5 is replaced by an inductive voltage divider by means of a tapping on coil L 1 . A capacitor C 2 is included between the tapping and the junction point of diodes D and D', whilst capacitor C' t here forms part of two networks C t , L y and C' t , L' traversed by a sawtooth current. In FIG. 6 modulation source V m is connected via a choke coil L 3 to the junction point of D, D', C 2 and
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 .
Other east-west modulators are known in which the step of FIGS. 5 and 6 can be used. An example is the modulator described in the publication by Philips, Electronic Components and Materials: "110° Colour television receiver with A66-140X standard-neck picture tube and DT 1062 multisection saddle yoke," May 1971, pages 19 and 20, which modulator also comprises two diodes and a compensation coil L', which are arranged in a slightly different manner. In another example the east-west modulator and the line deflection generator are included in a bridge circuit whilst they are decoupled from one another by means of a bridge coil which has the same function as coil L' in FIGS. 5 and 6. In these circuit arrangements coil L and winding L 2 may be arranged in the same manner as in FIG. 6. The same applies to an east-west modulator using a transductor the operating winding of which is in series with the deflection coil.
In the abovedescribed embodiments of the circuit arrangement according to the invention the compensating current i 1 is provided by transformer action. In the embodiment of FIG. 7 the current source which supplies the current i 2 is connected in parallel with correction coil L, i.e., without an auxiliary winding. In this embodiment the east-west modulation is achieved not by means of a modulator, but by means of the fact that the supply voltage V b is the super-position of a field-frequency parabolic voltage on the direct voltage. In this known manner the supply source also is the modulator.
It will be seen that in the embodiments of FIGS. 4, 5 and 6 current i 2 counteracts the east-west modulation of deflection current i y . It was found in practice, however, that this counteraction is slight.
PHILIPS 26C858 / 38Z CHASSIS K12 (20AX) Line oscillator synchronizing circuit:
A television receiver having a line synchronizing circuit wherein gate pulses for keying the synchronizing signal are derived from the oscillator signal, the gate pulses being positioned, by means of an auxiliary phase control loop, substantially symmetrical relative to
an edge of a reference signal also derived from the oscillator signal. The auxiliary control loop also eliminates the influence of phase variations occurring in the line deflection circuit.1. A television receiver having a line deflection circuit and a line synchronizing circuit, said line synchronizing circuit comprising a controllable oscillator, a signal derived therefrom being applicable to said line deflection circuit; a pulse generator coupled to said oscillator for deriving pulse-shaped gate signals; a coincidence detector; means for applying said pulse-shaped gate signals and pulse-shaped line synchronizing signals to said coincidence detector; a first phase discriminator coupled to said coincidence detector for determining the phase difference between said line synchronizing signal and a reference signal derived from said oscillator signal; a first low-pass filter for smoothing the output voltage from said first phase discriminator, said controllable oscillator being coupled to said first low-pass filter whereby the output therefrom controls the frequency and/or phase of said controllable oscillator; a second phase discriminator for determining the interval between the center instant of a pulse of said pulse-shaped gate signal and the center instant of an edge occurring in said reference signal; a second low-pass filter for smoothing the output voltage from said second phase discriminator; and means for controlling the center instant of the edge in said reference signal using the output from said second low-pass filter; wherein said line synchronizing circuit further comprises gate means having a first input terminal for receiving the output from said pulse generator and a second input terminal for receiving an output signal from said line deflection circuit, said gate means also having an output terminal for generating the gate pulses for said coincidence detector and said second phase dis
BACKGROUND OF THE INVENTION
The invention relates to a television receiver comprising a line synchronizing circuit and also comprising a line deflection circuit, the line synchronizing circuit comprising a controllable oscillator for generating an oscillator signal applicable to the line deflection circuit and being provided with means for applying a pulse-shaped line synchronizing signal and a pulse-shaped gate, which which is derived from the oscillator signal by means of a pulse generator, to a coincidence stage, an output terminal of which is connected to a first phase discriminator for determining the phase difference between the synchronizing signal and a reference signal which is also derived from the oscil
lator signal, the line synchronizing circuit being further provided with a first low-pass filter for smoothing the output voltage of the first phase discriminator, the frequency and/or phase of the oscillator being controllable by the first smoother voltage thus obtained, with a second phase discriminator for determining the interval between the center instant of a gate pulse and the center instant of an edge occurring in the reference signal, and with a second low-pass filter for smoothing the output voltage of the second phase discriminator, the center instant of said edge being controllable by means of the second smoothed voltage thus obtained. Such a line synchronizing circuit is disclosed in Applicant's Dutch Patent Application No. 7511633 (PHN.8169). In this known circuit a second phase control loop, which comprises the second discriminator and the second low-pass filter ensures that said two instants substantially coincide so that the gate pulses are substantially symmetrical relative to the edge of the reference signal. Consequently, the gate pulses may be of a very short duration, so that the insensitivity to noise is increased. The output signal of the circuit can be applied to the line deflection circuit ensuring that its phase is fixed relative to that of the received line synchronizing pulses.
It may, however, happen that phase variations occur in the line deflection circuit, for example because the turn-off time of a switch, usually a power transistor, present in said circuit is not constant. In order to reinstate the desired fixed phase relation between the deflection and the received synchronizing pulses, it is proposed in said patent application to apply the output signal of the present circuit first to a phase discriminator in which it is compared in known manner to a signal originating from the deflection circuit. This implies a third phase control loop. Consequently, the synchronizing circuit becomes complicated and more difficult to be implemented in integrated form.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a synchronizing circuit comprising only two phase-controlled loops and, to this end, the receiver according to the invention is characterized by a gate having a first input terminal for receivng the output signal of the pulse generator and a second input terminal for receiving an output signal of the line deflection circuit and having an output terminal for applying the gate pulses thus obtained to the coincidence state and to the second phase discriminator.
DESCRIPTION OF THE DRAWINGS
The invention will be further explained by way of non-limitative example with reference to the accompanying figures in which
FIG. 1 shows a block diagram of an implementation of a portion of a television receiver according to the invention and
FIGS. 2 and 3 show wave forms which may be used therein.
In FIG. 1 reference numeral 1 denotes the input terminal of the line synchronizing circuit. Line synchronizing pulses, having the line repetition frequency f H , i.e., for example, 15,625 or 15,750 Hz, are present at the input terminal. These pulses are derived, in known manner in the television receiver, not shown, of which the circuit forms part, from the received signal in a synchronizing-separation stage and are applied to an input terminal of an AND-gate 2. FIG. 2a shows the variation versus the time of these pulses. Herein the symbol T H denotes the line period, i.e. approximately 64 μs.
FIG. 2b shows the variation of gate pulses which are applied to another input terminal of gate 2 and which are generated in the circuit in a manner still to be explained hereafter. FIG. 2b shows each gate pulse symmetrically relative to the center instant t o of the corresponding line synchronising pulse of FIG. 2a. As known this pulse has a duration of, for example, 4.5 to 5 μs. The gate pulses have a somewhat longer duration of, for example, 7.7 μs. The output signal of gate 2 is applied to a controllable switch 3. If the pulses at the inputs of gate 2, as in FIG. 2, occur at least partly simultaneously, then switch 3 is made conductive for the duration of that portion of the line synchronizing pulses.
Switch 3 is supplied with a line frequency reference signal which is generated in a manner still to be explained hereafter and which is shown in FIG. 2c. In the synchronized state it has a falling edge at instant t o and a rising edge at an instant which is, for example, in the center of the time interval between instant t o and the corresponding instant t 1 one cycle later.
In these circumstances the voltage shown in FIG. 2d is present at the output terminal of switch 3. After smoothing by means of a low-pass filter 4, a d.c. voltage is produced which is supplied to a voltage controlled oscillator 5, whose frequency and/or phase is adjusted hereby. Switch 3 behaves as a phase discriminator by means of which the falling edge of the signal of FIG. 2c is adjusted to the center instant t o of the pulse of FIG. 2a. If the frequency of the signal of FIG. 2c deviates from the value f H , then the phase difference between this signal and that of FIG. 2a varies continuously. The control voltage supplied
to oscillator 5 is then an a.c. voltage, namely until the two frequencies are equal again, wherafter the control voltage is a d.c. voltage.
Oscillator 5 is also supplied with a d.c. voltage V o of, for example, 3 V on which the control voltage just mentioned is superimposed. Voltage V o may correspond to the nominal frequency of the line synchronizing pulses in accordance with the television standard for which the television receiver is suited. In the described implementation, however, the signal generated by oscillator 5 has, in the nominal case, a frequency 2f H which is double the line frequency. This signal is applied to a frequency divider circuit 6 in which the frequency is divided by the number of lines per picture in the relevant standard, being, for example, 625 or 525. A field frequency signal of, for example, 50 or 60 Hz, is available at an output terminal of divider circuit 6 in the synchronized state of the line phase-controlled loop, which signal can be applied to a field synchronizing circuit of known type.
The sawtooth signal shown in FIG. 3a is derived from the signal of oscillator 5, the sawtooth signal being applied to a pulse generator 7. By means of a d.c. voltage level V 1 which is applied to generator 7 and which is generated in a manner still to be explained, the sawtooth signal is converted in this generator into a pulse-shaped signal (FIG. 3b). The leading edges of these pulses and the rising edges in FIG. 3a occur simultaneously; while the instant of occurrence of the trailing edges of the pulses is determined by the value of voltage V 1 . These pulses are applied to a frequency dividing circuit 8 which, for example, is a binary divider circuit of known type, for example a master-slave flip-flop. The output signals thereof have the line frequency f H . The signal at an output terminal Q s thereof (see FIG. 3c) changes levels each time a falling edge occurs in the signal of FIG. 3b, while the signal at an output terminal Q m of circuit 8 (see FIG. 3d) changes levels each time a rising edge occurs in the signal of FIG. 3b. This implies that the signal of FIG. 3b is fixed relative to the time axis while the position of the signal of FIG. 3c depends on the value of voltage V 1 .
The signal at terminal Q m is the signal which is applied as a reference signal to switch 3, while the signal at terminal Q s is applied to a pulse shaper 9. The output signal thereof has the variation which is suitable for being applied, possibly via a driver stage, to a line output stage 10. Stage 10 supplies a line frequency current to the deflection coil, not shown, for the horizontal deflection in the picture display tube. Stage 10 comprises a switch usually a power transistor, whose turn-on time is relatively short, while its turn-off time is considerable, namely in the order of 10 μs. This is caused by the fact that the charge carriers, which are present in an excess in the saturated transistor, must first be removed. As known, the turn-off time depends on variations in the load of stage 10, for example the beam current in the picture display tube. In known manner, the adverse influence of such variations can be compensed for, for example by including a phase-controlled loop between oscillator 5 and the output of stage 10, this loop comprising a phase discriminator, a low-pass filter as well as an oscillator or a phase-shifting network. A signal originating from the output of stage 10 is used as a reference signal for this loop. Dutch Patent Application No. 7103465 (PHN.5499) discloses such a phase-controlled loop. A compensation is effected in the circuit of FIG. 1 in a different manner, which will be explained in the further course of this description.
The sawtooth voltage of FIG. 3a is also applied to a pulse generator 11 in which the sawtooth signal is converted into the pulse-shaped signal of FIG. 3e by means of a d.c. voltage V 2 applied thereto. The rising edges thereof occur simultaneously with those of FIG. 3a while the falling edges occur at the instants at which the sawtooth signal attains the value V 2 . In this manner the frequency of these pulses would have the double line frequency 2f H . However, the signal at the terminal Q m of divider circuit 8 is also applied to generator 11, thus, each rising edge of this signal cuts off generator 11. Other line frequency signals, for example line flyback pulses originating from stage 10, can also be used for this same purpose. The pulses obtained are applied to an input terminal of an OR-gate 12.
FIG. 3f shows line flyback pulses present in output stage 10, for example across a winding of a transformer thereof. For simplicity they are depicted as sine-shaped waves. They occur from approximately the instant at which the switch in stage 10 is switched-off, that is to say a time 96 after the occurrence of a falling edge of signal Q s (FIG. 3c) which time τ may be variable, while the duration of these pulses is substantially constant. The pulses of FIG. 3f are applied to an input terminal of an AND-gate 13, while another input terminal is connected to terminal Q m of the frequencies divider 8. The output terminal of gate 13 is connected to an input terminal of gate 12.
From FIGS. 3d and 3f it appears that the output signal of gate 13 has a leading edge from a time τ after the occurrence of a falling edge of signal Q s , and a trailing edge at the instant at which a falling edge of signal Q m occurs. The output signal of gate 12 has a leading edge at the same instant at which the leading edge of the output signal of gate 13 occurs and a trailing edge at the same instant at which the trailing edge of generator 11 occurs. The pulses at the output terminal of gate 12 are shown in FIG. 3g and are the gate pulses of FIG. 2b which are applied to gate 2. The leading edges thereof occur at instants which depend on the delay τ produced in output stage 10, while the instants at which the trailing edges occur depend only on the, optionally adjustable, voltage V 2 . These pulses do not contain any information concerning the signal Q m , in spite of the fact that Q m is one of the input signals of gate 13, which information is, for the rest not necessary. Said input signal is only used for removing the portion of the pulse of FIG. 3f occurring after the falling edge of signal Q m . The same result can be achieved by means of, for example, a bistable multivibrator, the output signal of which has a leading edge at the same instant as the flyback pulse and a trailing edge at the same instant as the signal of generator 11.
A phase discriminator 14, implemented as a controllable switch, is supplied with the reference signal at the output terminal Q m of divider circuit 8 (FIG. 3d) as well as with the gate pulses originating from gate 12. Switch 14 conducts during the occurrence of the gate pulses and its output voltage is smoothed by a low-pass filter 15.
The smoothed voltage obtained, as well as a d.c. voltage V 3 , derived from the supply voltage of the circuit, are supplied to a differential amplifier 16. The output voltage thereof is the voltage V 1 which is supplied to pulse generator 7. As a result thereof the duration of the pulses of FIG. 3b and, consequently, also the position along the time axis of the edges of signal Q s , depend on the value of the smoothed voltage. Elements 7 to 16 inclusive constitute an auxiliary control loop which operates so that each gate pulse of FIG. 3g remains symmetrical relative to the edge of the reference signal of FIG. 3d and, consequently, also relative to the center instant of the synchronizing pulse of FIG. 2a. This determines the duration of the gate pulse. Since, if the duration of the synchronizing pulse is 4.7 μs while the duration of the flyback pulse is 12 μs and if the interval between the starting instant of the flyback pulse (that is to say that of the blanking pulse in the received video signal) and the starting instant of the synchronizing pulse is equal to 1.5 μs, then the period of time between the leading edge in FIG. 2b and instant t o is equal, in the ideal case, to 1.5 +(4.7/2)=3.85 μs. Due to the action of voltage V 2 in stage 11 and of the auxiliary control loop, the trailing edge in FIG. 2b occurs 3.85 μs after instant t o , so that the duration of the gate pulse is 7.7 μs. In practice the pulse will be somewhat longer but it is obvious that, due to this rather short period of time, it is ensured that the sensitivity of the circuit to noise and disturbances is low, which especially holds for disturbances caused by reflection.
The final state of the auxiliary control loop is attained after a time which is independent of the frequency of oscillator 5, while the auxiliary control loop cannot experience an adverse influence from noise and disturbances. The time constant of filter 15 can therefore be chosen at will. Dutch Patent Application No. 7511633 (PHN.8169) describes all this more extensively. Because, however, the variations of delay τ can be rapid, this time constant must be many times smaller, for example ten times as small as that of filter 4.
If the frequency of oscillator 5 varies, for example due to a variation in the supply voltage, or if the frequency of the received line synchronisation pulses varies, for example because a switch-over to another transmitter is effected, the oscillator 4 is so adjusted by the operation of the control loop formed by elements 3 to 8 inclusive that the situation indicated in FIG. 2 occurs. This implies that the waveforms of the FIGS. 3a, 3b, 3c, 3d and 3e are shifted along the time axis until the leading edges of the pulses of FIG. 3a occur at the center instants of the synchronizing pulses of FIG. 2a. In this way it is ensured that also the trailing edges of the pulses of FIG. 3e and, consequently, also those of the gate pulses of FIGS. 3g and 2b are fixed relative to the synchronizing pulses.
If now the delay τ between the falling edge of the signal of FIG. 3c and the starting instant of the flyback pulse of FIG. 3f vary and/or if a shift of the gate pulses of FIG. 3g occurs relative to the reference signal of FIG. 3d as a result of spread in the properties of the various components and/or of inequalities of the transition times in the various transistors etc., then the pulse generator 7 is so adjusted by the operation of auxiliary control loop 7 to 16 inclusive that the situation shown in FIG. 3d occurs. In this situation the input voltage, originating from filter 15, of differential amplifier 16 is substantially equal to the voltage V 3 . Prior to the occurrence of this situation, said voltages deviate from one another, so that voltage V 1 varies. As a result, the position of the trailing edges of the pulses of FIG. 3b and, consequently, also the position of the edges of the signal Q s of FIG. 3 c change. Thus, the signal Q s is shifted along the time axis until the flyback pulses of FIG. 3f are fixed relative to the synchronizing pulses of FIG. 2a. Therefore, it is ensured, by means of the auxiliary control loop, that the influence of variations in time τ are considerably reduced and that the gate pulses shift only a little relative the reference signal, so that they may be of a short duration.
As in the previously mentioned Dutch Patent Application No. 7511633, the d.c. voltage V o , which is supplied to oscillator 5 in the absence of a control voltage originating from filter 4 and cause the oscillator to generate a signal having the nominal frequency, may be derived from the output voltage of filter 15. Also a pulse may be derived from one of the signals of FIG. 2 or FIG. 3, for example the sawtooth signal of FIG. 3a, for keying out the color synchronizing signal, which pulse may also be used for stabilising the black level. A coincidence detector may be used with which it is possible to reinstate the at least partly simultaneous occurrence of the gate pulses and the synchronizing pulses. In the case of non-coincidence, the gate pulses assume a longer duration, or the supply load for the gate pulses to gate 2 is interrupted, while the loop gain of control loop 3 to 8 inclusive is increased. As known, the locking-in property of the loop is improved by means of this switch-over.
As this loop gain cannot be infinitely large, the situation shown in FIG. 2 does not as a rule occur, that is to say there always remains a residual error. This means that the edge of the reference signal of FIG. 2c occurs, in the nominal state, at an instant which slightly deviates from instant t o , so that the voltage supplied to oscillator 5 slightly deviates from the value V o . The circuit of FIG. 1 is improved in this respect.
The control voltage which is supplied to oscillator 5 is also supplied to an amplifier 17. The output voltage thereof is the voltage V 2 which is supplied to pulse generator 11. Amplifier 17 is so dimensioned that the abovementioned error is corrected. If the error is, for example, such that the falling edge of the signal of FIG. 2c occurs somewhat too early relative to instant t o then amplifier 17 must have a gain of such a value and such a sign that voltage V 2 in FIG. 3a increases by a suitable value. This cause the falling edges in FIG. 3e and, consequently, in FIG. 3g to be shifted to the left. Due to the operation of the auxiliary control loop, when the gate pulses of FIG. 3g are substantially symmetrical in the synchronized state relative to instant t o , the rising edges in FIG. 3g are shifted to the right so that the gate pulses are given a shorter duration. The consequence of the outlined shift is that the flyback pulses occur somewhat later than is the case in FIG. 3f, so that also the signal Q s of FIG. 3c is shifted to the right. This means an identical shift of the falling edges of the signal of FIG. 3b and, consequently, a decrease of voltage V 1 . In this manner a small error is introduced in the auxiliary control loop so that the flyback pulses are slightly shifted relative to the reference signal, whose position along the time axis does not depend on voltage V 1 but, as a consequence of which, with a suitable design of amplifier 17, the flyback pulses are fixed relative to the synchronizing pulses. The center instant of a flyback pulse thus occurs at instant t o . A certain value can be assigned to voltage V 2 in the absence of a control voltage at the input terminal of amplifier 17; the duration of the gate pulses is adjusted by this setting. It will be obvious that a similar adjustment can also be applied in the case amplifier 17 is not present.
The foregoing discusses the idealised wave forms of FIGS. 2 and 3. It is obvious that both the leading and trailing edges in, for example, FIG. 2b and the edges in, for example, FIG. 2c have in practice no infinitely steep slope but a kind of sawtooth shape. Consequently, the symmetry aimed at means that the center instants of the pulses in FIG. 2b and of the edges in FIG. 2c occur substantially simultaneously, wherein center instant must be understood to mean in the first-mentioned case the instant located in the center of the time interval between which the signal is higher than half its maximum value and in the second case the instant at which half of the maximum value is achieved.
During the locking-in of the auxiliary control loop the position of the gate pulses varies in the described circuit along the time axis while that of the reference signal remains unchanged. It is clear that an implementation can be realised in which the position of the gate pulses is not affected
by the control, while the position of the reference signal varies.
With the exception of capacitors which are part of filters 4 and 15, the described circuits can be integrated in a semiconductor body. In the preceding the oscillator has in the nominal state double the line frequency. It will be obvious that this is not essential for the invention, that is to say the invention can also be used if the nominal frequency is the line frequency or another multiple thereof.
PHILIPS CHASSIS K12 (20AX) SONG IC Tuning COLORED BAR SCREEN display for a television receiver:
1. In a television (TV) receiver which receives TV signals in at least one frequency band which has a plurality of TV channel signals included in lower- and upper-frequency portions thereof separated by a gap, including
tuning means for developing a tuning signal to select one of said TV channel signals and for developing band signals to indicate the one of said lower- and upper-frequency portions which includes said selected one TV channel signal, wherein said tuning signal varies between first and second magnitudes for ones of said TV channel signals in each of said lower- and upper-frequency portions, and wherein said tuning signal can have similar magnitudes for different ones of said TV channel signals,
processing and display means for displaying a TV picture responsive to said selected one TV channel signal, and
tuning indicator means responsive to a control signal for developing a tuning indication of said selected one TV channel signal;
electronic control apparatus for developing said control signal in response to said tuning signals and to said band signals to have different magnitudes corresponding to different ones of said plurality of TV channel signals, comprising:
divider means for developing a proportioned tuning signal in response to said tuning signal;
offsetting means for developing an offsetting signal in response to said band signals, said offsetting signal having a magnitude corresponding to the one of said lower- and upper-frequency portions which includes said selected one TV channel signal; and
combining means, coupled to said divider means and to said offsetting means, for combining said proportioned tuning signal developed by said dividing means and said offsetting signal developed by said offsetting means to develop said control signal.
2. The control apparatus of claim 1 wherein said dividing means comprises first voltage divider means receiving said tuning signal at a first end thereof and receiving a reference signal at a second end thereof for developing said proportioned tuning signal at an intermediate connection thereof. 3. The control apparatus of claim 2 wherein said dividing means further comprises:second voltage divider means receiving said tuning signal at a first end thereof and receiving said reference signal at a second end thereof for developing said proportioned tuning signal at an intermediate connection thereof;
a terminal; and
switch means for selectively connecting the intermediate connection of said first voltage divider means to said terminal when said selected one TV channel signal is included in said lower-frequency portion and for selectively connecting the intermediate connection of said second voltage divider means to said terminal when said selected one TV channel signal is included in said upper-frequency portion.
amplifying means for developing said control signal at an output terminal thereof and having at least one input terminal; and
means for applying said proportioned tuning signal and said offsetting signal to the input terminal of said amplifying means.
7. The control apparatus of claim 1 wherein said combining means comprises:amplifying means for developing said control signal at an output terminal thereof and having first and second input terminals; and
means for applying said proportioned tuning signal and said offsetting signal to the first and second input terminals, respectively, of said amplifying means.
tuning means responsive to a tuning signal for selecting one of said TV channel signals and responsive to band signals for selecting the one of said lower- and upper-frequency portions which includes said selected one TV channel signal, wherein said tuning signal varies between first and second magnitudes for ones of said TV channel signals in each of said lower- and upper-frequency portions, and wherein said tuning signal can have similar magnitudes for different ones of said TV channel signals, and
processing and display means for displaying a TV picture responsive to said selected one TV channel signal;
apparatus comprising:
a source for supplying a first control signal;
divider means for developing a porportioned control signal in response to said first control signal;
offsetting means for developing an offsetting signal in response to said band signals, said offsetting signal having a magnitude corresponding to the one of said lower- and upper-frequency portions which includes said selected one TV channel signal;
combining means, coupled to said divider means and to said offsetting means, for combining said proportioned control signal developed by said dividing means and said offsetting signal developed by said offsetting means to develop a second control signal;
tuning indicator means responsive to an indicating signal for developing a tuning-indicating display on said display means, the position of said tuning-indicating display on said display means corresponding to the magnitude of said indicating signal;
means for applying one of said first and second control signals to said tuning means as said tuning signal; and
means for applying the other one of said first and second control signals to said tuning indicator means as said tuning-indicating signal.
12. The apparatus means of claim 11 wherein said tuning indicator means comprises bar generating means for developing a bar display as said tuning-indicating display, said bar generating means including:delaying means for developing a pulse signal controllably delayed in response to said other one of said first and second control signals; and
means for applying said pulse signal to said display means to produce said bar display thereon.
13. The apparatus of claim 12 wherein said bar generating means further includes a panel proximate said display means and upon which indicia of channels of said TV channel signals are provided, the indicia of a particular channel being located on said panel according to the position of said bar display indication corresponding to said particular channel.The present invention relates to tuning indicators for television receivers and, in particular, for displaying an apparently continuous tuning indication where the tuning band is in fact discontinuous.
The VHF-TV frequency band, including channels 2-13, is perceived by most viewers as being a single TV band even though it is in fact partitioned into lower and upper frequency portions including channels 2-6 and 7-13, respectively, which are separated by a gap. Voltage controlled tuning systems for such TV receivers employ a tuning voltage which varies over substantially the same range of magnitude from a lower to a higher voltage for each of the frequency portions of the VHF band. Accordingly, conventional channel indicators responsive to the magnitude of the tuning voltage partition the frequency bands to avoid ambiguity in the channel indication.
Tuning indicators of that sort include a display of a vertical or horizontal bar on a TV screen where the position of the bar, horizontally or vertically, respectively, provides an approximate indication of channel selection. The bar position is determined from the magnitude of the tuning voltage. Because tuning voltage is ambiguous as between the lower and upper portions of the VHF-TV band, band partitioning and some auxiliary indication is necessary to unambiguously indicate the selected channel.
Such channel indicators might be confusing to some viewers because the display partitions the VHF-TV band contrary to the viewers' perception of a single VHF-TV band. In addition, where the viewer must manually select the band in which tuning is to be accomplished, the tuning process can become more complex and inconvenient due to the increased number of bands. Moreover, the controls necessary as a result of partioning the VHF band into separate bands tends to unnecessarily increase the cost of the TV receiver.
Some TV receivers have employed mechanical tuning potentiometers having segmented resistance elements and/or segmented conductive rings positioned for developing tuning voltage, band indicating signals or display control signals. Such mechanical potentiometers are disadvantageously complex and expensive unlike the electronic apparatus described herein.
Therefore, there is a need for a tuning indicator which provides an unambiguous, approximate indication of the TV channel selected but which does not entail substantial additional complexity or cost. Such display is particularly advantageous when employed in conjunction with a low-cost scanning-type tuning system in a low cost TV receiver.
The foregoing problems are overcome when the present invention is employed in a TV receiver including a tuning device for developing a tuning signal to select one TV signal and for developing band signals to indicate the one of the lower and upper portions of a frequency band which includes the selected TV signal. The tuning signal varies between first and second magnitudes for each of the upper and lower portions of the frequency band. A processing device displays a TV picture responsive to the selected signal and a tuning indicator is responsive to a control signal for developing a tuning indication of the selected TV signal. Control apparatus which develops the control signal to cause the displayed indication to appear as if the lower and upper portions of the frequency band were substantially continuous comprises a divider for proportioning the tuning signal when the selected TV signal is in the lower and upper portions, a device responsive to the band signals for generating an offsetting signal when the selected TV signal is included in one of the lower and upper portions, and a device for combining the proportioned tuning signal and the offsetting signal to develop the control signal.
In the drawing:
FIG. 1 is a schematic block diagram of a TV receiver including the present invention;
FIG. 2 is a view of a television display;
FIGS. 3, 5 and 6 are diagrams partially in schematic and partially in block form of apparatus useful in the TV receiver of FIG. 1; and
FIG. 4 is a graphical representation of characteristics associated with the TV receiver of FIG. 1.
In the TV receiver shown in FIG. 1, TV signals are received through antenna ANT by tuning system 10 for TV signals including, e.g., channels 2-13 in the VHF-TV frequency band and channels 14-83 in the UHF-TV frequency band. Tuning system 10 develops band signals V-LO-VHF, V-HI-VHF and V-
UHF to select the one of the lower VHF, upper VHF or UHF bands, respectively, in which the selected TV signal channel is included. Tuning system 10 further develops tuning voltage VT in response to which it specifically tunes the selected TV signal in that band. IF signals from tuning system 10 are applied to IF processor 12 which develops automatic fine tuning (AFT) and automatic gain control (AGC) signals for controlling tuning system 10 and further develops a composite video signal.
Sound processor 14 develops from the composite video signal audio program information which is reproduced by loudspeaker LS.
Video processor 16 develops video signals in response to the composite video signal. In a color TV receiver in particular, video processor 16 develops blue (B), red (R) and green (G) color video signals responsive to the chrominance information in the composite video signal, each of which color video signals further includes luminance information. Kine drivers 18 couple the B, R and G color video signals to corresponding electrodes of kine display tube 20 upon which color picture information is displayed.
Sync separator 22 develops vertical synchronization signal VS which is applied to vertical deflection circuits 24 for developing periodic vertical deflection signals for driving the vertical deflection portion of yoke 30. Horizontal synchronization signal HS developed by sync separator 22 is conventionally applied via phantom path HS' for synchronizing horizontal oscillator 26 which drives horizontal deflection circuits 28 for developing periodic horizontal deflection signals in the horizontal portion of yoke 30.
A picture program display is developed on the screen of kine 20 in response to the B, R and G color video signals and the vertical and horizontal deflection signals. The TV receiver thus far described is conventional and an and an exemplary receiver is described in detail in RCA Television Service Data, Chassis CTC-107, File 1981 C-2 and Supplement 1981 C-2-S2, published by RCA Corporation, Consumer Electronics, Indianapolis, Indiana, which data is incorporated herein by reference.
Bar display generator 44 develops an on-screen tuning displa
y. In FIG. 2, TV picture program information 70 is displayed on TV screen 60. A tuning indication, for example, vertical bar 62 is also displayed on screen 60, at least at selected times. Channel numerals 66 for VHF-TV channels 2-13 and channel numerals 68 for UHF-TV channels 14-83 are provided on panel 64 proximate to screen 60. Bar 62 is moved leftward and rightward so that its position relative to channel numerals 66 and 68 indicates the channel number of the selected TV channel. So that bar 62 appears uniform and accentuated, picture information 70 is blanked on the portion of screen 60 where bar 62 is displayed. This is indicated in FIG. 2 by the gap in picture 70 where it intersects with bar 62.
In the VHF-TV band, channels 2-6 (54-88 MHz) are separated from channels 7-13 (174-216 MHz) by a gap (88-174 MHz). Tuning voltage VT developed by tuning system 10 varies between about 0.5-2 volts for voltage level V1 and 20-30 volts for voltage level V2, or about a 20-30 volt range, as illustrated by the graphical representation of FIG. 4a. VT characteristics 102 for the lower portion of the VHF-TV band, 104 for the upper portion thereof, and 106 for the UHF-TV band are ambiguous with respect to the channel selected. However, by employing VT in conjunction with band signals V-LO-VHF, V-HI-VHF and V-UHF in accordance with the present invention, a non-ambiguous tuning indication, such as that of control voltage VC shown in FIG. 4b, is obtainable. Control voltage VC is developed within bar generator 44 for controlling the position of bar 62 on screen 60 as described in detail below.
Bar display generator 44 is described in detail with reference to FIG. 3. Tuning voltage VT is proportioned by voltage dividers R1, R3 and R5 shown by way of example as potentiometers. The proportioned VT signals at the intermediate points of R1, R3 and R5, at which their wiper arms are positioned, are respectively coupled to node N1 through switches S1, S3 and S5. S1, S3 and S5 are rendered respectively conductive by bandswitch signals V-LO-VHF, V-HI-VHF and V-UHF when the selected TV signal is included in the lower VHF, upper VHF or UHF bands, respectively.
In similar fashion, offsetting potentials are developed at node N2 when the potential at the respective wiper arms of potentiometers R2, R4 and R6, developed from operating potential +V, is coupled to node N2 by switches S2, S4 and S6. S2, S4 and S6 are rendered respectively conductive by the aforementioned band signals.
Amplifier DA combines the proportioned tuning voltage at node N1 and the offsetting voltage at N2 to develop a control signal VC which is coupled through diode D to the control terminal of variable one-shot (monostable multivibrator) 80. Amplifier DA modifies the proportioned tuning voltage at N1 by a factor -RF/RI and the offsetting voltage at N2 by a factor [1+(RF/RI)], where RI and RF are the values of resistances RI and RF.
In particular, where bar generator 44 of FIG. 3 employs a CD4098B dual monostable multivibrator COS/MOS integrated circuit, available from RCA Solid-State Division, Somerville, N.J., for one-shots 80 and 82, control signal VC has about a 1.5 volt range as developed at diode D. Switches S1-S6 employ CD4016B quad bilateral switch COS/MOS integrated circuits also available from RCA Solid-State Division. The greatest magnitude control signal VC is voltage VL in FIG. 4b which positions bar 62 near the left edge of screen 60; and decreases therefrom move bar 62 towards the right. At VC equal to voltage VR, bar 62 is at the right edge of screen 62.
For low VHF channels 2-6, control voltage VC follows characteristic 112 of FIG. 4b. Potentiometer R2 is adjusted to develop VC=VL to position bar 62 at numeral "2" of indicia 66 when channel 2 is selected. With channel 6 selected, potentiometer R1 is adjusted to proportion VT to develop VC of value so that bar 62 as at numeral "6" of indicia 66. For high VHF channels 7-13, control voltage VC follows characteristic 114. R4 is adjusted so that the offsetting potential developed at N2 causes control voltage VC at diode D to be of value VL less offsetting voltage VOS so that bar 62 is positioned at numeral "7" (not shown) of indicia 66 when channel 7 is selected. With channel 13 selected, R2 is adjusted to develop VC=VR to position bar 62 at numeral "13".
For UHF channels 14-83, VC follows characteristic 116. R6 is adjusted to develop VC=VL to position bar 62 at numeral "14" of indicia 68 when channel 14 is selected; R5 is adjusted to develop VC=VR to position bar 62 at numeral "83" with channel 83 selected.
Variable one-shot 80 develops a trigger pulse signal at its output connection. The beginning of the trigger pulse signal substantially coincides with the synchronization pulse received from sync substitutor 48; the ter
mination of the trigger pulse signal is delayed from that synchronization pulse by a time period determined by the magnitude of the control signal received from the cathode of diode D. The delay time is shorter than the period of the horizontal deflection signal. Resistor RX and capacitor CX are connected between +V and ground, and determine the maximum duration of the trigger pulse. The control signal reduces that duration by restricting the range of voltage over which CX is charged and discharged.
One-shot 82 produces a pulse signal at its output connection which commences at the termination of the trigger signal from one-shot 80 and which has a duration directly controlled by a signal from control source CS. Commonly, control source CS supplies a fixed magnitude control signal so that the pulse signal from one-shot 82 is of substantially constant time duration and is substantially shorter than the period of the horizontal deflection signal. The bar pulse signal from one-shot 82 is desirably of about 0.6 microseconds duration to determine the width of the bar display and is generated between about 2 and 58 microseconds after a synchronization signal is received from 48 so to position the bar display between the left- and right-hand edges of the displayed picture. That bar pulse signal is developed and applied to an input of AND gate 84 irrespective of whether a bar is to be displayed or not.
When a tuning indication is to be displayed, a BAR ON signal is applied to the other input of AND gate 84 so that the bar pulse signal developed by one-shot 82 is coupled to node N3. The bar pulse is applied to common-emitter NPN driver transistor T1 via its base resistor RB1 and is coupled through resistor RC1 as a BLANKING signal. By way of example, that BLANKING signal can be connected to the base of vertical blank transistor Q702 shown in FIG. 21 of the CTC-107 Service Data referred to above. Alternatively, the BLANKING signal can be inverted and applied to TP 806 also shown in FIG. 21 thereof.
When the TV channel selected for viewing is in either the upper or lower portion of the VHF band, the appropriate one of band signals V-LO-VHF and V-HI-VHF are applied through OR-gate 87 to an input of AND gate 88 so that the bar pulse signal at node N3 passes via resistor RB3, driver transistor T3 and resistor RC3 to develop a RED color video signal to produce a red-colored bar display. Similarly, if the selected TV channel is in the UHF band, band signal V-UHF is applied to an input of AND gate 86 so that bar pulses from N3 causes resistor RC2, driver T2 and resistor RC2 to develop GREEN color video signals to produce a green-colored bar display. By way of example, the RED color video signal can be applied to the emitter of RED driver transistor Q5001 and the GREEN color video signal can be applied to the emitter of GREEN driver transistor Q5002, both shown in FIG. 22 of the CTC-107 Service Data referred to above.
The bar display can be inhibited under certain conditions so that degradation of its appearance does not occur. For example, signal VS applied via AND gate 89 inhibits both RED and GREEN color video signals during vertical retrace. By way of further example, the RED and GREEN color video signals are inhibited by AND gate 91 in response to band change signal BC when the tuning system changes from one band to another, such as between the VHF and UHF bands, and in response to mid-band reset signal MBR when the tuner changes over the gap between channels 6 and 7 in the VHF band. As a result, the position of the bar display is not changed in a confusing manner due to transients of tuning voltage VT or of the bandswitch voltages when the tuning system changes between bands or between portions of the VHF band.
A bar tuning display is desired whenever tuning is being performed and for a short time, for example, four seconds, thereafter, as well as on viewer demand. To that end, one-shot 42 in FIG. 1 develops the BAR ON signal for a four-second period responsive to a RECALL signal developed, for example, by the viewer depressing a pushbutton. While channel tuning is in process, horizontal synchronization signals HS are unavailable from received TV signals. Sync validity detector 40 compares the average level of received synchronization signal HS against a threshold level to develop a SYNC VALID indication which is present during tuning. One-shot 42 develops the BAR ON signal continuously so long as SYNC VALID signal is applied and for four seconds after the SYNC VALID signal is removed when valid synchronization signals are detected.
To avoid bar display tuning indication 62 from being jagged or erratic owing to the absence of an adequate sync signal, sync substitutor 48 ensures that appropriate synchronization signals are always applied to horizontal oscillator 26. To that end, oscillator 46 develops secondary horizontal synchronization signals SHS at the standard horizontal frequency of 15,575 Hz which are applied to sync substitutor 48, as are received horizontal synchronization signals HS when they are present. With respect to the detailed diagram of sync substitutor 48 shown as part of FIG. 3, SYNC VALID signal is applied to AND gate 92, and is inverted and applied as SYNC VALID signal to AND gate 94. As a result, synchronization signal HS is applied to NOR gate 96 when HS is present and valid, and synchronization signal SHS is applied to NOR gate 96 when HS is not present or not valid. NOR gate 96, resistor RC 4 and inverting buffer amplifier transistor T4 together comprise an OR gate to generate synchronization signals applied to horizontal oscillator 26.
FIG. 5 shows a modification of the embodiment described above in relation to FIG. 3. R2, R4, R6, S2, S4 and S6 has been eliminated and replaced by potentiometer R15. R15 is adjusted so that the voltage developed at its wiper is applied to the non-inverting (+) connection of amplifier DA so that DA develops VC=VL. Network 120A serves the same function as potentiometers R1 and R2 of FIG. 3. Tuning voltage VT
is proportioned substantially by R20, R21 and R22. R20 is adjusted for positioning bar 62 in like manner to that described above for R1. Bias voltage +VB is applied through resistors R23 and R24 to switch S1. R23 is adjustable for setting VC=VR for positioning bar 62 as was described above for resistor R2. Switch S1 is rendered conductive by band signal V-LO-VHF when the selected TV channel is in the lower VHF-TV band.
Networks 120B and 120C are similar to network 120A and are employed for positioning bar 62 when the selected channel is in the upper portion of the VHF-TV band and in the UHF-TV band, respectively. However, with respect to network 120B, the variable resistor corresponding to R23 of 120A is employed for developing an offsetting potential; variable resistor R23 is adjusted to establish VC=VL-VOS when channel 7 is selected.
With an embodiment of the sort shown in FIG. 5 connected to an RCA CTC-107 TV receiver, with RI=RF=100 kilohms, with diode D comprising two 1N914 diodes in series, and with DA being an LM358 operational amplifier available from National Semiconductor Corp., Santa Clara, CA., the following voltages were measured:
| TABLE I |
| ______________________________________ |
| TV Band Low VHF High VHF UHF |
| ______________________________________ |
Channel No. 2 6 7 13 14 83 Control Voltage VC 3.1 2.5 2.2 1.5 3.0 1.6 Tuning Voltage VT 0.9 16.1 7.3 20.4 0.7 20.3 Combined Pro- 1.8 2.4 2.5 3.4 1.9 3.3 portional VT & Offsetting Voltage at N1 Voltage at DA+ 2.5 2.5 2.5 2.5 2.5 2.5 |
| ______________________________________ |
Examination of the data listed in Table I reveals striking similarities between the values of VC and VT under differing conditions. Specifically, the respective values of VC and VT are substantially the same when either channel 2 or 14 is selected. Moreover, the respective values of VC and VT with channel 13 or 83 selected are also substantially the same. Taking advantage of these similar values permits additional simplification of bar generator 44, such as that shown in the embodiment of FIG. 6.
FIG. 6 shows an embodiment modified from that described in relation to FIG. 5 in that networks 120A, 120B and 120C, and switches S1, S3 and S5 are replaced by resistors R10-R14 and switch S7. Tuning voltage VT is proportioned by the voltage divider comprising resistors R10 and R11 so that the change in VC is substantially VL-VR. When the selected channel is in the VHF frequency band, signal V-UHF is applied rendering switch S7 conductive to connect resistance R14 between node N1 and ground. The additional proportioning introduced by the voltage divider including R12 and R14 further attenuates VT so that the changes in control voltage VC are proportioned for characteristics 112 and 114 as compared to 116 in FIG. 4b. R14 is shown as a variable resistor for adjusting VC=VR.
When the selected channel is in the UHF-TV band, V-UHF is not applied so that S7 is nonconductive and VT is attenuated substantially by R10 and R11 for proportioning characteristic 116 of control voltage VC. When the selected channel is in the upper portion of the VHF-TV band, band voltage V-HI-VHF is applied through resistance R13 to develop an offsetting voltage which is combined at node N1 with the proportioned VT voltage. R13 is adjusted so that control voltage VC is offset by VOS from VL. It is equally satisfactory that signal V-UHF be developed by inverting band signal V-UHF or by combining V-LO-VHF and V-HI-VHF such as by a diode-ORing circuit.
Modifications are contemplated to the present invention which should be limited in scope solely by the claims following. For example, the present invention is equally satisfactory whether used in conjunction with black and white or color TV receivers and may employ either a horizontal or vertical bar type display of tuning information. Moreover, it is equally satisfactory that the tuning information be conveyed by the position of a contrasting bar as described herein or by varying the length of such bar, in which case the variable end of the bar would indicate the selected channel by its correspondence with numerials of indicia 66 and 68 on panel 64.
Although the embodiments of bar generator 44 of FIGS. 3, 5 and 6 have been described as developing an offsetting voltage when the selected TV channel is in the upper portion of the VHF-TV band so that a characteristic of the sort shown in FIG. 4b will obtain, it is equally satisfactory that offsetting potential be developed when the selected channel is in the lower portion of the VHF-TV band. In that case, the offsetting potential would be of polarity sense to shift characteristic 102 in voltage relative to characteristic 104 such that combined characteristics 112 and 114 result.
Additionally, it is equally satisfactory that the present invention be employed in conjunction with a display separate from the TV screen. For example, with a plurality of light-emitting diodes (LED) linearly arrayed, the variable time delay pulse developed by one-shot 80 can be employed to determine the number of LEDs illuminated. The illuminated LEDs appear as the equivalent of a "bar" of variable length the end of which corresponds to numerals on indicia 66 and 68 to indicate the selected channel.
While control source CS of FIG. 3 is described as supplying a fixed control signal to one-shot 82, it is equally satisfactory that CS supply a control signal variable in response to another parameter to be displayed. For example, the strength of the received signal which is readily determinable from the magnitude of AGC voltage developed by IF processor 12 can be applied to CS to vary the width of bar 62.
Additionally, to provide a limited and more precise adjustment for the proportioned tuning voltages and offsetting voltages discussed above in relation to FIG. 3, each of potentiometers R1-R6 could be reduced in resistance value and reconnected with a respective fixed resistance connected in series with each of its respective ends.
A television tuning device having a circuit for continuously scanning at least one frequency band. Scanning can take place at two speeds and controls are provided for starting and stopping the scanning procedure. The scanning speed is automatically changed from high speed to low speed when a television channel is detected to allow ample time for scanning to be stopped manually. Alternatively, the scanning may be stopped automatically.
A station finder which switches to automatic frequency control during automatic finding in case of reception of
1. A receiver tuning circuit for a tuner comprising means for detecting the presence of a received signal having an input means for coupling to said tuner; a search tuning circuit having a capacitor means for a tuning voltage for said tuner, and an automatic frequency control circuit coupled to said capacitor, said tuning circuit and said automatic frequency control circuit charging said capacitor when activated; an operating device means coupled to said detecting means and said search tuning circuit for activation of said search tuning circuit and for subsequent deactivation of said search tuning circuit and activation of said automatic frequency control circuit upon detection of a received signal; and time constant circuit means coupled between said detecting means and said operating device means for repeatedly activating said search tuning circuit and deactivating said automatic frequency control circuit a selected time after said search tuning circuit has been deactivated. 2. A receiver tuning circuit as claimed in claim 1, wherein said operating device has a supply lead and the time constant circuit is coupled to the supply lead of the operating device. 3. A receiver tuning circuit as claimed in claim 1, wherein the detection circuit is coupled to an output of a frequency detector and includes a means for preventing pulling in on the same transmitter upon activation of said search tuning circuit.
The invention relates to a receiver tuning circuit including a search tuning circuit which can be activated by a control device in which the search tuning circuit is automatically switched off when a received station is detected by a detection circuit and an automatic frequency control circuit is switched on, and in which a time constant circuit changes the state of the receiver tuning circuit after a certain time.
A receiver tuning circuit of the kind described above is known from German Offenlegungsschrift 2,023,352 which after activation of the search tuning stops the search action when a transmitter transmitting a pilot signal is received and switches on an automatic frequency control circuit. The search tuning circuit must again be activated when the received transmitter is not desired. When a transmitter without a pilot signal is received, the search tuning circuit switches over to a slowed down searching action and the automatic frequency control remains switched off. The tuning circuit includes a time constant circuit which renders the detection circuit for the pilot signal inactive some time after the finder has been activated so that the circuit can then pull in on transmitters without a pilot signal.
This known tuning circuit is only suitable for special receivers. An object of the invention is to provide a tuning circuit which is more suitable for other receiver types.
To this end a receiver tuning circuit of the kind described in the preamble according to the invention is characterized in that the time constant circuit is incorporated in the tuning circuit in such a manner that again and again it switches on the search tuning circuit a certain time after having automatically switched it off and switches off the automatic frequency control as long as the search tuning circuit is maintained operative with the aid of the operating device.
By using the step according to the invention a receiver is obtained which upon activation of the search tuning circuit receives without distortion transmitter after transmitter each during a time determined by the time constant circuit. The search tuning can be rendered inactive with the aid of the operating device after the desired station has been found. The tuning circuit is very suitable for radio or television receivers for domestic use.
1. A television tuning device comprising a circuit scanning means for continuously scanning at least one band of receivable frequencies, manual control means for starting and stopping said scanning, a terminal means for applying a switch signal to said scanning means for switching from a first band-scanning speed to a second band-scanning speed lower than the first, and detection means for detecting the presence of a television channel by comparing received synchronization signals with local signals generated in the television receiver and for applying a switch signal to said terminal means for switching from said first band-scanning speed to said second band-scanning speed in the presence of said switch signal so that the band scanning continues at said second band-scanning speed until the manual control means stops the scanning.
2. A television tuning device according to claim 1, further comprising scanning stopping means for stopping the scanning automatically when a television channel has been correctly tuned in, speed reducing means for reducing band-scanning speed, and said detection means comprising first and second detecting means for detecting the presence of a television channel which act in sequence one after another for supplying to said speed reducing means control signals at successive instants so as to increase the effective time interval during which said scanning stopping means may operate.
3. A device according to claim 2, further comprising controlling means for controlling the tuning frequency of the receiver automatically for optimum tuning, said controlling means being activated or de-activated by said switch signal provided by the said detection means for detecting the presence of a television channel.
4. A device according to claim 1, in which said band-scanning circuit means includes means for generating scanning signals at increasing speed starting from the instant scanning commences, and means for stopping and restarting scanning when the presence of a television channel is detected so that scanning continues at the same speed as when it commenced.
5. A device according to claim 1, in which said detecting means includes a coincidence detector means for detecting coincidence between the synchronization signals received and picture tube deflection signals generated inside the television receiver.
6. A device according to claim 1, in which said manual control means includes two push-buttons, one for controlling commencement of band scanning from the lowest to the highest frequencies and the other for controlling commencement of band scanning in the opposite direction and in which scanning commences on pressing one of said buttons and stops upon release of the same button.
7. A device according to claim 3, in which said first detecting means for detecting the presence of a television channel includes a detector means for detecting coincidence between the synchronization signals of the received signal and picture tube deflection signals generated in the television receiver and said second detecting means includes a threshold comparator means for receiving the output signal of said controlling means and processing means for supplying by means of processing means a signal for stopping band scanning.
8. A device according to claim 7, in which said processing means are operative to supply a signal for restarting band scanning at the same speed at which it was commenced.
9. A device according to claim 7, in which said processing means includes a series circuit comprising a disabling circuit which receives the output signals of said first and second detecting means, a Flip Flop, and an exclusive OR logic circuit, which stop the scanning operation and prevent it from being continued until a new scanning-start signal is received from said controlling means and such as to reset the Flip Flop.
10. A device according to claim 9, further comprising means for resetting said series circuit when the receiver is turned on to prevent scanning from being commenced until the scanning-start signal is sent.
Description:
The present invention relates to a television tuning device, comprising a circuit for continuously scanning at least one band of receivable frequencies, and having control means for starting and stopping the said scanning procedure and a terminal for applying a switch signal for switching from a first band-scanning speed to a second band-scanning speed slower than the first.
The name usually applied to a unit consisting of circuits of this type for selecting and memorising a given number of preferred channels is "station memory".
Many types of station memories are already being sold on the market which can be divided into two main groups: those with automatic and those with manual television channel searching.
The automatic types are fitted with electronic searching circuits which locate television channels automatically when started by the user. This is done by scanning a given band (VHF or UHF, for example) and stopping on the located channel. Data relative to the located channel can then be memorised by the user in a memory circuit and the same channel recalled whenever required by simply pressing a button which recalls the said data from the memory and supplies it to the channel selection circuit.
This type of circuit is also fitted with components which sense, during search, if a television channel has been tuned into and disable automatic searching to prevent television band scanning from continuing. Most of these circuits are fitted with a phase detector which senses the coincidence between the sync signals received and those regenerated in the receiver (in particular, the flyback signal).
Manual station memories, on the other hand, are fitted with controls which, when activated by the user, start a device for scanning a given television band. These controls also stop the said device when required by the user. When the user sees the required channel appear on the screen, the device is stopped to disable search and enable the channel to be memorised in the appropriate circuit.
In these cases, the simplest way of starting and stopping the search is to fit the circuits with a button which, when pressed, supplies a search-start signal and, when released, stops the searching operation. For best tuning, two buttons are usually provided for band scanning in both directions.
Both the types discussed up to now present drawbacks. In the case of automatic station memories, for example, tuning quality depends on correct operation of all the search-stop circuits and the automatic tuning circuit (AFC=automatic frequency control). Even in cases where these circuits are operating correctly, tuning could still be impaired by noise or amplitude distortion on the received signal.
Tuning quality on manual station memories, on the other hand, depends on the tuning ability of the user. Television receivers can be manipulated by anybody not all of whom are gifted with this ability. A further drawback of manual station memories is that the user has very little time in which to decide whether the received channel is the right one and to estimate tuning quality. If the whole television band is to be sca
nned in a reasonable length of time (let us say, the UHF band in one minute) band-scanning speed needs to be fairly high. Consequently, if the user is not quick enough in sending out the search-stop control signal, it is more than likely that the control will be sent when the required television channel has been overshot. If, by chance, there are two channels close to one another, the searching device may even stop on the second of the two, thus confusing the user who will not know which of the two channels he has tuned into.The aim of the present invention is to provide a tuning device to overcome these problems.
With this aim in view, the present invention provides a television tuning device comprising a circuit for continuously scanning at least one band of receivable frequencies, manual control means for starting and stopping the said scanning procedure, a terminal for applying a switch signal for switching from a first band-scanning speed to a second band-scanning speed lower than the first, and detection means for detecting the presence of a television channel by comparing the received sync signals with local signals generated in the television receiver, and applying a switch signal to the said terminal for switching from the said first scanning speed to the said second scanning speed in the presence of the said switch signal, so that the band scanning continues at said lower speed until the manual control means produce the stopping scanning procedure.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 shows a block and circuit diagram of an exemplary television tuning device according to the invention; and
FIG. 2 shows the internal structure of exemplary integrated circuits used in the diagram of FIG. 1.
In the diagram, an input terminal receives an input signal from a freque
ncy discriminating circuit, which forms part of a known automatic frequency control (AFC) circuit, the input signal being applied to a known Schmitt trigger circuit, generally designated 2. The output of circuit 2 is connected to a first input of a circuit 3 which has two outputs, one connected to set input S and one to reset input R of Flip Flop circuit 4. Input S of the said Flip Flop is also connected to a first input of an exclusive OR logic circuit 5 and a first output of a control circuit 6 which has a second output connected to input R of circuit 4 and an input connected to a terminal of a first push-button 7 the other terminal of which is grounded.Number 8 represents an input for receiving line sync signals obtained in the known way from sync separating circuits, the signals being applied to a first input of a coincidence detecting circuit 10 the second input of which is connected to receive a line flyback pulse 9, obtained from the horizontal deflection circuits. The output of circuit 10 is connected to a signal translation circuit 11, the second input of circuit 3 and an output 12 which can be sent to activate the AFC circuits on the set. ON reset circuit 13 has a first output connected to the second input of circuit 5, which is also connected to the output of circuit 4 through disconnecting resistor 22, and a second output connected to the control input of circuit 3, which is also connected to the output of circuit 5 through resistor 14. The output of EX-OR circuit 5 is also connected to the input of matching stage 15 the output of which is connected to a second push-button 16 and a first control input (UP) of a tuning detection and memorising circuit 17. This has a second control (down) input connected to a third push-button 18. A detection speed switch input is connected to the output of circuit 11. Input 21 can be connected, in the known way, to a station keyboard, outputs 19 and 20 representing respectively the tuning voltage to be sent to the tuning circuit and the channel indication to be sent to an appropriate display, using known methods. Push-buttons 16 and 18 are the same as push-button 7 and therefore have their second terminals grounded.
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NPN transistors BC 148B PNP transistors BC 158B Diodes 1N4148 NOR gates 1/4 F4001 (+ A supply) NAND gates 1/4 F4011 (+ A supply) + A 5V + B 12.5V + C 33V
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The circuit operates as follows:
When one of the buttons on the television panel connected to inputs 21 of circuit 17 is pressed, the corresponding memory register in circuit 17 (I.C. Ser. No. 76,720) is activated to give a voltage at output 19 corresponding to the tuning voltage of a given television channel memorised previously. If a video signal is present, the horizontal deflection circuits on the set are synchronized by the sync signals in the received signal, coincidence detector circuit 10 supplies a high output voltage so that the AFC circuit comes into operation, controlled by output 12 for optimum tuning. In this case, the voltage at the output of stage 15 is high and circuit 17 undertakes no further operations to detect other emitting stations. The voltage at the output of EX-OR stage 5 is also high so that the circuit at gate 3 is kept closed, a situation which persists until one of the control buttons is pressed. By pressing other keys on the board, it is possible to tune into other stations memorised previously in the same way as described already. If there is no television signal present for the key pressed, circuit 10 detects no coincidence, its output remains low and the AFC circuit does not come into operation.
A third mode of operation is possible in which searching and memorising are performed automatically. When button 7 is pressed, low and high voltages are applied, through circuit 6, to the set and reset inputs of Flip Flop 4 respectively so as to force the output to zero. Two zeroes are thus applied to EX-OR circuit 5 so as to create a low voltage at its output. In this way, the voltage at the output of circuit 15 moves to zero and circuit 17 starts searching upwards exactly in the same way as when button 16 was pressed. After a given interval, determined by resistor 14 and the condenser at the control input of circuit 3, this gate circuit opens so that the signals at its inputs can be sent to the inputs of Flip Flop 4. During the search, in the absence of any stations, the output of circuit 10 is low while that of trigger circuit 2 is high. This results in a 1 at the reset input and a 0 at the set input of the Flip Flop so that the output of circuit 15 remains low and the search is continued. As soon as a station is approached, on the video carrier side, given the searching direction chosen, the horizontal deflection circuits are synchronized with the signal, the coincidence detector supplies a high output and the AFT circuits become activated through output 12 to reduce searching speed (circuits 11 and 17).
The reset input of the Flip Flop moves to zero but the output remains unchanged and the search continues at low speed. Over time, the AFC voltage at input 1 describes a curve in the form of an S, that is it starts at zero, rises to a maximum, returns to zero (optimum tuning), reaches a minimum and then returns to zero.
When the threshold of trigger 2 is reached, the latter switches, that is, its output becomes low, Flip Flop inputs S and R become 1 and 0 and switching commences. For a time period equal to the delay of the Flip Flop, a 1-0 condition exists at the input of the EX-OR circuit so that its output presents a positive peak which stops searching for an instant. After the Flip Flop switches (high output) a 1-1 condition exists at the EX OR input so that the output becomes low and searching continues at minimum speed. When the falling AFC voltage crosses the trigger threshold again, the trigger output becomes high causing it to switch. Two zeroes are present at the Flip Flop input, therefore its output remains at 1 with a 1 and 0 at the EX OR input. The result is its output becomes high, searching is stopped on the required station and this tuning condition memorised automatically in circuit 17. Following the delay determined by resistor 14, gate circuit 3 closes and the tuning condition reached can no longer be disturbed. For searching to be continued, button 7 must be pressed after which the cycle is repeated in the same way.
FIG. 2 shows the details of the integrated circuits used in the circuit of FIG. 1. The I.C. type Ser. No. 76,727 provides a clock signal to the other I.C. Ser. No. 76,720. This circuit features an oscillator which is controlled by an exte
rnal crystal coupled to pins 2 and 3. A pair of cascaded divide-by-two flip-flops provide the proper clock signal at pin 4. A D-type flip-flop, which provides waveform shaping, is coupled to pin 4, and has both Q and Q output signals applied to pins 13 and 14 respectively. Two additional cascaded divide-by-two flip-flops are coupled to the Q output of the D-type flipflop and provide buffered output signals on pins 6 and 9 for driving a LED display (not shown). Two keyboard scanning output signals are provided at pins 5 and 10 which are in synchronization with the LED output signals at pins 6 and 9 but are narrowed and delayed to avoid edge coincidence glitches.The station memory is Texas Instrument integrated circuit of the type Ser. No. 76,720 which receives the clock signal at its pin 9 and applies it to 12 bit synchronous counter. Pins 15 to 18 and 1 correspond to the input terminal 21 of the present invention and are intended to carry a five bit code identifying the manually selected channel. The signals are applied to 5 to 20 line decoder which in turn applies signals to a 12 bit tuning voltage RAM. The pins 10 and 11 are the up and down frequency scanning controls shown in FIG. 1 and the VHF/UHF pin 13 is also scanning speed controlled. The scanning is effected by transferring the data of the prevailing channel into the transparent counter and modifying this data under the control of the tuning program generator, the counter being clocked up or down at rate determined by the tuning timer and the countdown frequency select circuit. When one or the other buttons connected to the pins 10 and 11 is depressed, the count is incremented initially at a slower rate, the rate increasing gradually until it reaches a miximum level determined by the signal applied to pin 13.
The advantages of the circuit according to the present invention will be clear from the description given. First and foremost, as compared with known solutions, is the extra time allowed to the user for stopping the search when this is done manually. This is possible with no increase in the time taken for a complete band to be scanned. A further advantage is the possibility of two types of search: automatic and manual. The advantages of both operating modes are thus combined in one device to provide the best results. In particularly delicate cases, the user can leave aside automatic searching and perform the operation manually. A further advantage is that, when operating automatically the circuit described is provided with two circuits which, as optimum tuning is approached, both slow down band-scanning speed one after the other to facilitate operation of the automatic searching-stop 2/3 circuit and recognition of correct tuning. One last advantage is that the arrangement described is particularly simple and economical considering the functions it performs. To those skilled in the art it will be clear that variations can be made to the circuit described without, however, departing from the scope of the present invention as defined in the claims. Of these we shall mention just a few. For example, the possibility of using only one type of search, e.g. manual. Another variation could be to use a different type of station memory, for example another of the "dedicated" integrated circuits available on the market or a station memory circuit made using a microprocessor. It should be pointed out that the circuits shown in the blocks on the diagram are only a few of the many types capable of performing the functions required and that numerous variations can be made to them.
"Fernseh-Portable mit Suchlauf-Automatik", Funkschau, vol. 45, No. 13, Jun. 22, 1973, Munich, Germany, pp. 469-472.
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