SINUDYNE 22256 CADMO 22" TELECOMPUTER CHASSIS PROFESSIONAL 5000 INTERNAL VIEW.

The SINUDYNE CHASSIS PROFESSIONAL 5000 is a unique example of modularity.

The units are fitted like "cards" above and under the chassis structure divided by power parts and signal parts.

The chassis was introducing the use of the MOTOROLA TDA3300 instead of the PHILIPS VIDEO COMBINATION used in previous PROFESSIONAL 2000 CHASSIS with even a redesigned horizontal output unit.





SINUDYNE 22256 CADMO 22" TELECOMPUTER CHASSIS PROFESSIONAL 5000 Switched mode power supply

Supply is based on TDA4600 (SIEMENS).

Power supply Description based on TDA4601d (SIEMENS)

TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.

Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.

Description:

The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.

Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.









TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC

DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).




SINUDYNE 22256 CADMO 22" TELECOMPUTER - VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)

TDA3300 3301 TV COLOR PROCESSOR

This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).

Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.

The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.

It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.

90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.

ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.

4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.

Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.

Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.


SINUDYNE 22256 CADMO 22" TELECOMPUTER CHASSIS PROFESSIONAL 5000 Digital phase locked loop tuning system / PLL FREQUENCY SYNTHESIZER:

A phase locked loop circuit for use in an automatic frequency synthesizing system. The system includes a programmer circuit which is responsive to a channel number input signal and generates a first digital control signal which is representative of the selected channel number and a second digital control signal which is representative of a predetermined group of channel numbers. A programmable divider is controlled by the programming circuit and generates a digital output signal which causes the phase locked loop circuit to generate a desired system output frequency corresponding to the selected channel number input signal. The phase locked loop circuit includes automatic fine tuning and manual fine tuning features.


1. A digital phase locked loop tuning system responsive to a local oscillator signal for producing a frequency synthesized digital output signal which is utilized to control the frequency of the local oscillator, the local oscillator having a plurality of frequencies associated therewith corresponding, respectively, to a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups with each channel in a particular channel group being separated from an adjacent channel in the particular channel group by a predetermined frequency spacing of the local oscillator, comprising:
programming means responsive to an input signal representing a selected channel number of a particular channel group for generating a first digital control signal having a value corresponding to the selected channel number and for generating a second digital control signal representative of said particular channel group, said second digital control signal being a constant predetermined value for all of said channel numbers that are within said group; and
programmable divider means coupled to said programming means being responsive to said first, second digital control signals and the local oscillator signal, in a local oscillator mode, for generating the digital output signal which is representative of a desired frequency corresponding to said selected channel number, said programmable divider means including means for dividing the local oscillator signal by first and second factors, said first factor being related to the frequency separation between local oscillator signals by an integral number, the local oscillator signal being divided by said first factor during a first interval for a first number of periods of the output signal and being divided by said second factor for a second number of periods of the output signal, said first number of periods being related to the number of the channel selected, said second number being related to the channel group within which the selected channel lies.


2. Phase locked loop system according to claim 1, wherein said programming means including means coupled to said programming means for receiving an MFT signal and being responsive to said MFT signal for altering said first and second digital control signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered system output frequency.

3. Phase locked loop system according to claim 2, wherein said programming means includes first terminal means coupled to said programming means for receiving an AFT control signal, and first logic means responsive to the input signal and the AFT control signal for generating the first digital control signal.

4. Phase locked loop system according to claim 3, wherein said programming means includes second logic means coupled to said first logic means and responsive to the AFT control signal for generating the second digital control signal.

5. Phase locked loop system according to claim 4, wherein said second logic means includes group decoder means coupled to said first logic means.

6. Phase locked loop circuit means according to claim 5, wherein said second logic means includes memory means coupled to said group decoder means and to said first terminal means.

7. Phase locked loop system according to claim 6, wherein said second logic means includes second terminal means for receiving an MFT signal, and up/down counter latch means coupled to said memory means and to said second terminal means for altering said first and second digital control signals in response to said MFT signal.

8. Phase locked loop system according to claim 7, wherein said second logic means includes adder means coupled to said up/down counter latch means to said memory means.

9. Phase locked loop system according to claim 3, wherein said first logic means includes channel number generator means coupled to said first terminal means and responsive to said input signal.

10. Phase locked loop system according to claim 9, wherein said channel number generator means includes first and second data selector means coupled to said first terminal means, and adder means coupled to said second data selector means and to said up/down counter latch means.

11. Phase locked loop system according to claim 1, wherein said means for dividing the local oscillator signal includes programmable counter means for generating a modulus control output signal, and variable modulus prescaler divider means coupled to and responsive to said programmable counter means, said variable modulus prescaler divider means dividing the local oscillator signal by said first and second factors.

12. Phase locked loop system according to claim 11, wherein said programmable counter means includes third data selector means coupled to receive said first and second digital control signals and said modulus control signal.

13. Phase locked loop system according to claim 12, wherein said programmable counter means includes a programmable counter coupled to said third data selector means and to said variable modulus prescaler divider means.

14. Phase locked loop system according to claim 13, wherein said programmable counter means includes look ahead circuit means coupled to said programmable counter, and divide by two circuit means coupled to said look ahead circuit means for generating said modulus control output signal.

15. Phase locked loop tuning system according to claim 1 including digital automatic fine tuning (AFT) means wherein:
said programmable divider means includes switching means responsive to an AFT control signal to inhibit the local oscillator signal to said programmable divider means and to provide an input signal thereto of a different frequency than the local oscillator signal; and
said programming means including logic means responsive to said AFT control signal for altering said first and second digital control signals to predetermined values to cause the phase locked loop tuning system to be operable in an automatic fine tuning mode.


16. Phase locked loop tuning system of claim 15 wherein said programmable divider means includes:
programmable counter means for generating first and second modulus control signals; and
dual modulus prescaler means responsive to said first modulus control signal for dividing the local oscillator signal in said local oscillator mode and said input signal of a different frequency in said automatic fine tuning mode by said first factor which is equal to the integer six and being responsive to said second modulus control signal for dividing said local oscillator signal and said input signal of a different frequency by said second factor which is equal to the integer five respectively.


17. Phase locked loop tuning system of claim 16 wherein said signal of a different frequency is an intermediate frequency signal provided by the tuning system and supplied to said switching means.

18. In a phase locked loop tuning system for receiving a channel number input signal and a local oscillator signal having groups of selectable frequencies wherein the frequency spacing between each adjacent local oscillator frequency within a single group is uniform, the improvement comprising programmable divider means for generating a digital output signal representative of a desired tuning system output frequency including variable modulus prescaler divider means having a prescaler division ratio being equal to P = S/Y' for dividing the local oscillator frequency by said prescaler division ratio during a first interval for a first number of periods of the digital output signal and for dividing the local oscillator frequency by a second prescaler division ratio during a second interval for a second number of periods, said second ratio being related to said first ratio, where S is the frequency spacing between each adjacent local oscillator frequency within a single group (i), Y_i =D_i -X_i S, where D_i is said desired tuning system output frequency within said selected group; X_i =D_i /S rounded off to the nearest integer; Y' is chosen such that Y_i /Y' is an integer and S/Y' is an integer and Y' is the smallest value of all values of Y_i.

19. In a receiver including a tuning apparatus for providing a plurality of local oscillator signals each corresponding to a respective one of a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups wherein each channel is separated from an adjacent channel in the respective channel group by a predetermined frequency spacing, a phase locked loop tuning system for producing a frequency synthesized output signal for controlling the frequency of the local oscillator, comprising:
variable modulus divider means for selectively dividing the frequency of the local oscillator signal by first and second factors in response to a modulus control signal to provide an output signal, said first factor being related to the frequency separation between local oscillator signals by an integral number; and
programmable means for generating said modulus control signal to cause said variable modulus divider means to divide by said first factor during a first interval for a first number of periods of said output signal and to divide by said second factor during a second interval for a second number of periods of said output signal, said first number of periods being related to the number of the channel selected, said second number of periods being related to the channel group corresponding to the selected channel.


20. The phase locked loop tuning system of claim 19 wherein said programmable means includes:
programming means responsive to a selected channel input signal for producing first and second digital output signals, said first digital output signal being related to the selected channel number plus one of two constant values which are determined in accordance within which channel group the selected channel input signal lies, said second digital signal being a constant value for all selected channels within a channel group; and
programmable divider means responsive to said first and second digital output signals from said programming means for providing said variable modulus control signal and the frequency synthesized output signal.


21. The phase locked loop tuning system of claim 20 wherein said programming means includes automatic fine tuning (AFT) means responsive to a AFT control signal being applied thereto when the receiver is placed in an AFT mode wherein:
said variable modulus divider means is caused to receive a input signal different from the local oscillator signal;
said programming means being responsive to the AFT control signal for altering said first and second digital signals such that the receiver is finely tuned to the frequency of the received signal applied to the receiver.


22. The phase locked loop tuning system of claim 21 wherein said programming means includes means for receiving a manual fine tuning (MFT) signal for altering said first and second digital output signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered output signal.

23. The phase locked loop tuning system of claim 19 wherein the one of said first and second factors is an even number and the other is an odd number.

24. The phase locked loop tuning system of claim 23 wherein said first factor is the integer six and said second factor is the integer five.

Description:

BACKGROUND OF THE INVENTION
This invention relates to digital tuning systems, and more particularly, to a simplified digital phase locked loop (PLL) tuning system incorporating unique digital automatic fine tuning and manual fine tuning schemes.
Since the appearance of varactor tuners for television, many tuning address schemes have evolved for controlling them. PLL techniques have maintained a performance advantage but have suffered a cost disadvantage due to complexity, the high frequencies involved, the need for automatic fine tuning and in some localities, the need for a manual fine tuning arrangement. With the advances that have taken place in semiconductor technology in the last several years, the high operating frequencies no longer present a significant problem.
Prior art PLL systems for use in television tuners have not yet been able to incorporate an automatic fine tuning feature, nor have they been able to incorporate a manual fine tuning system which would enable the PLL tuning system to be intentionally offset in predetermined increments. Television sets normally have an automatic fine tuning (AFT) feature, but this is normally incorporated as a separate circuit which is not directly incorporated into the television tuner.

An additional disadvantage of prior art PLL systems which are designed for use in a television tuner environment is that they are highly complex and relatively expensive. In order to convert the channel number input into the proper digital control signals for the PLL, a relatively large ROM having a capacity on the order of 82 words by 12 bits was required. The best prior art PLL tuning systems require two high speed programmable counters which greatly increase the system complexity. This together with the large ROM which the system required, greatly decreased the cost effectiveness of the system so that commercial manufacturers were able to use these prior art PLL systems only in their most expensive commercial television receivers.
Therefore, it is a feature of this invention to provide a digital PLL tuning system which incorporates design techniques that vastly simplify the complexity of the PLL while at the same time allowing the system to meet the latest needs of a television tuning system or any other PLL tuning system which is addressed by a channel number.
It is another feature of this invention to provide a digital PLL tuning system that has the ability to automatically tune nonprecise station frequencies and the ability to be manually fine tuned.
It is yet another feature of the present invention to provide a digital PLL tuning system having only a single high speed programmable counter and requiring a ROM capacity of only 5 words by 9 bits.
It is still another feature of this invention to provide a digital PLL tuning system which performs the automatic fine tuning feature by utilizing the PLL tuning system as a digital discriminator.
It is yet another feature of this invention to provide a digital PLL tuning system incorporating a manual fine tuning (MFT) arrangement which is capable of intentionally offsetting the local oscillator frequency of a TV tuner in one megahertz steps or of offsetting TV IF frequency in steps of 125 kilohertz.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention includes a phase locked loop circuit means for an automatic frequency synthesizing system. The phase locked loop circuit means includes programming means which is responsive to an input signal representing a selected channel number for generating a first digital control signal representative of the selected channel number and for generating a second digital control signal representative of a predetermined group of channel numbers. A programmable divider means is coupled to the first and second digital control signals and generates a digital output signal representative of a desired system output frequency corresponding to the selected channel number.
The phase locked loop circuit means further includes an automatic fine tuning feature for fine tuning the phase locked loop output frequency to the exact frequency of the received signal. The system further includes a manual fine tuning provision which allows the phase locked loop operating frequency to be intentionally offset in predetermined increments.