Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.


Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....
Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !
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©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of
Engineer Frank Sharp. NOTHING HERE IS FOR SALE !

Tuesday, October 2, 2012

PHILIPS 17CE1230 MATISSE CHASSIS CP90 INTERNAL VIEW.






























































































The PHILIPS CHASSIS CP90 was fitted from 15 to 21 Inches television sets in many various models types.

It was reliable except for the Line deflection output EHT Transformer which was failing often, and for some dry joints around the power parts and of course the NiCd backup battery.

I've noticed that if they were hardly used (10 or more hours per day) the were more reliable than one used few or less hours a day.

The PHILIPS CHASSIS CP90 is indeed compact and seems simple, but is not so simple as is.

Some times repairing it can be time consuming work and you have to know how it runs.


TDA3561A PAL decoderGENERAL DESCRIPTION
The TDA3561A is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.

APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.




PHILIPS 17CE1230 MATISSE CHASSIS CP90 Switched-mode self oscillating supply voltage circuit:POWER SUPPLY (PHILIPS SOPS - Self Oscillating Power Supply)

A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or a load connected to the output voltage. The circuit comprises a first controllable switch connected in series with a transformer winding and a second controllable switch for turning-off the first switch. The conduction period of the first switch is controlled by means of a control voltage present on a control electrode of the second switch. The circuit can be switched-over to a stand-up state in which the energy supplied to the load is reduced to zero. A starting network is connected between the input voltage and the second switch so that the current therein flows through the second switch during the period of time this switch conducts and does not flow to the control electode of the first switch in the stand-by state.

1. A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage, comprising a transformer having a primary and a feedback winding, a first controllable switch connected in series with the primary winding, the series arrangement thus formed being coupled between terminals for the input voltage, a second controllable switch coupled via a turn-off capacitor to the control electrode of the first switch to turn it off, means coupling the feedback winding to said control electrode, a transformer winding being coupled via a rectifier to an output capacitor having terminals which supply the output voltage, an output voltage-dependent control voltage being present on a control electrode of the second switch for controlling the conduction period of the first switch, the circuit being switchable between an operating state and a stand-by state in which relative to the operating state the supply energy supplied to the load is considerably reduced, a starting network connected to a terminal for the input voltage, means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off, a connection which carries current during the conduction period for the second controllable switch being provided between the starting network and said second switch, and means providing a connection between the starting network and the control electrode of the first switch, which connection does not carry current in the stand-by state.

2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.

3. A supply voltage circuit as claimed in claim 2, characterized in that the second controllable switch comprises a thyristor having a main current path included in the control electrode connection of the first controllable switch, said thyristor having a first control gate electrode for adjusting the turn-off instant of the first switch and a second control electrode to which the starting network and the resistor are connected.

4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.

Description:
The invention relates to a switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage. This circuit comprises a transformer having a primary and a feedback winding and a first controllable switch arranged in series with the primary winding. The series arrangement thus formed is coupled between the terminals of the input voltage. A second controllable switch which is coupled via a turnoff capacitor to the control electrode of the first switch to turn it off. The feedback winding is coupled to this control electrode and the primary winding is coupled via a rectifier to an output capacitor the terminals of which are the terminals for the output voltage. An output voltage-dependent control voltage is present on a control electrode of the second switch for controlling the conduction period of the first switch. The circuit is switchable between an operating state and a stand-by state in which relative to the operating state the energy supplied to the load is considerably reduced, and the circuit further comprises a starting network connected to a terminal for the input voltage.
Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
In the stand-by state the transistor is non-conducting in a large part of the period of the generated oscillation so that little energy is stored in the transformer. However, the starting resistor is connected via a diode to the second controllable switch, which is a thyristor. As the sum of the voltages across these elements is higher than the base-emitter threshold voltage of the transistor, the diode and the thyristor cannot simultaneously carry current. This implies that current flows through the starting resistor to the base of the transistor via the feedback winding after a capacitor connected to the feedback winding has been charged.
The invention has for its object to provide an improved circuit of the same type in which in the stand-by state the supply energy applied to the load is reduced to zero. The prior art circuit cannot be improved in this respect without the use of mechanical switches, for example relays. According to the invention, the switched-mode self-oscillating supply voltage circuit does not comprise such relays and is characterized in that it further comprises means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off. A connection which carries current during the conduction period of the second controllable switch is provided between the starting network and said second switch while a connection present between the starting network and the control electrode of the first switch does not carry current in the stand-by state.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.


The invention will now be further described by way of example with reference to the accompanying drawing, which shows a basic circuit diagram of a switched-mode self-oscillating supply voltage circuit.


The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V B of, for example, 300 V. Voltage V B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2. The series arrangement of a diode D1 and a 2.2 Ohm-limiting resistor R3 is arranged between the other terminal of capacitor C2 and the other end of winding L2 and the series arrangement of a resistor R4 of 12 Ohm and a diode D2 is arranged between the same end of winding L2 and the emitter of transistor Tr1. A 150 nF capacitor C3 is connected in parallel with diode D2. The anode of diode D1 is connected to that end of winding L2 which is not connected to capacitor C2, while the anode of diode D2 is connected to the emitter of transistor Tr1. In the FIGURE the winding sense of windings L1 and L2 is indicated by means of dots.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because of the feedback the described circuit oscillates independently as soon as the steady state is achieved. It will be described hereinafter how this state is obtained. During the time transistor Tr1 conducts the current flowing through the resistor R1 increases linearly. The resistor R4 then partly determines the base current of transistor Tr1. Capacitor C4 and resistor R7 form a voltage source the voltage of which is subtracted from the voltage drop across resistor R1. As soon as the voltage on the base of transistor Tr3 is equal to approximately 0.7 V this transistor becomes conductive, as a result of which the thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive and remains so. Across capacitor C2 there is a negative voltage by means of which transistor Tr1 is turned off. The inverse base current thereof flows through thyristor Tr2, Tr3. This causes charge to be withdrawn from capacitor C2, while the charge carriers stored in transistor Tr1 are removed with the aid of inductance L3. As soon as the collector current of transistor Tr1 has been turned off, the voltage across winding L2 reverses its polarity, which current recharges the capacitor. Now the voltage at the junction of components C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish.
Secondary windings L4, L5 and L6 are provided on the core of transformer T with the indicated winding senses. When transistor Tr1 is turned off, a current which recharges a smoothing capacitor C5, C6 or C7 via a rectifier D3, D4 or D5 flows through each of these windings. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in the FIGURE, are, for example, portions of a television receiver.
In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flows via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V B and to a Zener diode Z1 which has a positive voltage of approximately 7.5 V, while the base is unconnected. The other end of diode Z1 is connected to ground. A light-emitting diode D8, whose cathode is connected to the collector of an npn-transistor Tr5, is optically coupled to transistor Tr4. By means of a potentiometer R11 the base of transistor Tr5 can be adjusted to a d.c. voltage which is derived from the voltage V 0 of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V 1 of approximately 13 V. A resistor R12 is also connected to voltage V 1 , the other end of the resistor being connected to the emitter of transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage of approximately 7.5 V and to a smoothing capacitor C10. The other ends of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can be generated by means of a transformer connected to the electric AC supply and a rectifier, which are not shown for the sake of simplicity, more specifically for a remote control to which constantly supply energy is always applied, even when the majority of the components of the receiver in what is referred to as the stand-by state are not supplied with supply energy.
A portion of voltage V 0 is compared with the voltage of diode Z2 by means of transistor Tr5. The measured difference determines the collector current of transistor Tr5 and consequently the emitter current of transistor Tr4. This emitter current produces across resistor R6 a voltage drop whose polarity is the opposite of the polarity of the voltage source formed by resistor R7 and capacitor C4. Under the influence of this voltage drop the turn-on instant of thyristor Tr2, Tr3 is controlled as a function of voltage V 0 . If, for example, voltage V 0 tends to decrease owing to an increasing load thereon and/or in response to a decrease in voltage V B , then the collector current of transistor Tr5 decreases and consequently also the said voltage drop. Thyristor Tr2, Tr3 is turned on at a later instant than would otherwise be the case, causing transistor Tr1 to be cut-off at a later instant. The final value of the collector current of this transistor is consequently higher. Consequently, the ratio of the time interval in which transistor Tr1 is conductive to the entire period, commonly referred to as the duty cycle, increases, while the frequency decreases.
The circuit is protected from overvoltage. This is ensured by a thyristor which is formed by a pnp-transistor Tr6 and an npn-transistor Tr7. The anode of a diode D9 is connected to the junction of components R3 and C2 and the cathode to the base of transistor Tr6 and to the collector of transistor Tr7. The base of transistor Tr7, which base is connected to the collector of transistor Tr6, is connected via a zener diode Z3 to a voltage which, by means of a potentiometer R13 is adjusted to a value derived from the voltage across capacitor C7. The emitter of transistor Tr6 also is connected to the voltage of capacitor C7, more specifically via a resistor R14 and a diode D10. If this voltage increases to above a predetermined value then thyristor Tr6, Tr7 becomes conductive. Since the emitter of transistor Tr7 is connected to ground, the voltage at its collector becomes very low, as a result of which diode D9 becomes conductive, which keeps transistor Tr1 in the non-conducting state. This situation is maintained as long as thyristor Tr6, Tr7 continues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
The circuit comprises a 1 MOhm starting resistor R16, one end of which is connected to the base of transistor Tr2 and the other end to the conductor which carries the voltage V B . Upon turn-on of the circuit current flows through resistors R16 and R5 and through capacitor C2, which has as yet no charge, to the base of transistor Tr1. The voltage drop thus produced across resistor R5 keeps transistor Tr2, and consequently also transistor Tr3, in the non-conductive state, while transistor Tr1 is made conductive and is maintained so by this current. Current also flows through winding L2. In this manner the circuit can start as energy is built up in transformer T.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state.
If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur. If in the operating state transistor Tr1 conducts while thyristor Tr2, Tr3 is cut-off, then the current flows through resistor R16 in the same manner as it flows during the start to the base of transistor Tr1, but has relatively little influence as the base current caused by the energy stored in winding L2 is many times larger. If both transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the current through resistor R16 flows through components R5, C2, L2, R4, C3 and R1. In this stand-by state capacitor C2 has indeed substantially no negative charge any longer but, in spite thereof, transistor Tr1 cannot become conductive since no current flows to its base. It will furthermore be noted that the circuit is protected in the event that thyristor Tr2, Tr3 has an interruption. Namely, in such a case the circuit cannot start.
In the foregoing a circuit is described which may be considered to be a switched-mode supply voltage circuit of the parallel ("flyback") type. It will be obvious that the invention may alternatively be used in supply voltage circuits of a different type, for example converters of the type commonly referred to as up-converters. It will also be obvious that transistor Tr1 may be replaced by an equivalent switch, for example a gate-turn-off switch.


TDA2579B Horizontal/vertical synchronization circuit




GENERAL DESCRIPTION
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth



FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
Standard TV-norm
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 < 1.2 V)
In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height
is achieved.
Video tape recorders in feature mode
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.

The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated
via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at
count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by
adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of
the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage
a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).
The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value
of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends.
The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is
discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and
ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current
source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a
typical voltage of » 7.5 volts. The recommended operating current range is 10 to 75 mA. The resistance at pin R4 should
be 100 to 770 kW. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired
value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current
measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback
voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and
AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.
The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a
fully DC coupled feedback circuit is possible.
Vertical guard
The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level
on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output
signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard
levels specified refer to the zener diode reference voltage source level.
Driver output
The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately
170 W. The output pin is also connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins 5,6,7,8 and 18)
The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of
the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level value
is stored in the capacitor at pin 6.

Black level detector
A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with
a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC
conditions at input pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and
ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced
and separation of the vertical sync pulse is improved.
Noise level detector
An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a
built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at
the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated.
A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below
19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated
by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the
“acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant.
When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync
pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.

Phase detector
The phase detector circuit is connected to pin 8. This circuit consists of 3 separate phase detectors which are activated
depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. For normal and fast time
constants all three phase detectors are activated during the vertical blanking period, this with the exception of the
anti-top-flutter pulse period, and the separated vertical sync-pulse time. As a result, phase jumps in the video signal
related to the video head, take over of video recorders are quickly restored within the vertical blanking period. At the end
of the blanking period the phase director time constant is increased by 1.5 times. In this way there is no requirement for
external VTR time constant switching, and so all station numbers are suitable for signals from VTR, video games or home
computers.
For quick locking of a new TV station starting from a noise only signal condition (normal time constant) a special circuit
is incorporated. A new TV station which is not locked to the horizontal oscillator will result in a voltage decrease below
0.1 V at pin 18. This will activate a frame period counter which switches the phase detector to fast for 3 frame periods
during the vertical scan period.
The horizontal oscillator will now lock to the new TV-station and as a result, the voltage on pin 18 will increase to
approximately 6.5 V. When pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is switched OFF and the
divider is set to the large window. In general the mute signal is switched OFF within 5 ms (pin C18 = 47 nF) after reception
of a new TV-signal. When the voltage on pin 18 reaches a level of 5 V, usually within 15 ms, the frame counter is switched
OFF and the time constant is switched from fast to normal during the vertical scan period.

If the new TV station is weak, the sync-noise detector is activated. This will result in a change over of pin 18 voltage from
6.5 V to »10 V. When pin 18 exceeds the level of 7.8 V the phase detector is switched to slow time constant and gated
sync pulse condition. The current is also reduced during the vertical blanking period by 1 mA. When desired, most
conditions of the phase detector can also be set by external means in the following way:
a. Fast time constant TV transmitter identification circuit not active, connect pin 18 to earth (pin 9).
b. Fast time constant TV transmitter identification circuit active, connect a resistor of 220 kW between pin 18 and ground.
This condition can also be set by using a 3.6 V stabistor diode instead of a resistor.
c. Slow time constant, (with exception of frame blanking period), connect pin 18 via a resistor of 10 kW to + 12 V, pin 10.
In this condition the transmitter identification circuit is not active.
d. No switching to slow time constant desired (transmitter identification circuit active), connect a 6.8 V zener diode
between pin 18 and ground.

Supply (pins 9, 10 and 16)
The IC has been designed such that the horizontal oscillator and output stage can start operating by application of a very
low supply current into pin 16.
The horizontal oscillator starts at a supply current of approximately 4 mA. The horizontal output stage is forced into the
non-conducting stage until the supply current has a typical value of 5 mA. The circuit has been designed so that after
starting the horizontal output function a current drop of » 1 mA is allowed. The starting circuit has the ability to derive the
main supply (pin 10) from the horizontal output stage. The horizontal output signal can also be used as the oscillator
signal for synchronized switched mode power supplies. The maximum allowed starting current is 9.7 mA (Tamb = 25 °C).
The main supply should be connected to pin 10, and pin 9 should be used as ground. When the voltage on pin 10
increases from zero to its final value (typically 12 V) a part of the supply current of the starting circuit is taken from pin 10
via internal diodes, and the voltage on pin 16 will stabilize to a typical value of 9.4 V.
In a stabilized condition (pin V10 > 10 V) the minimum required supply current to pin 16 is » 2.5 mA. All other IC functions
are switched on via the main supply voltage on pin 10. When the voltage on pin 10 reaches a value of » 7 V the horizontal
phase detector circuit is activated and the vertical ramp on pin 3 is started. The second phase detector circuit and burst
pulse circuit are started when the voltage on pin 10 reaches the stabilized voltage value of pin 16 which is typically 9.4 V.
To close the second phase detector loop, a flyback pulse must be applied to pin 12. When no flyback pulse is detected
the duty factor of the horizontal output stage is 50%.
For remote switch-off pin 16 can be connected to ground (via a npn transistor with a series resistor of » 500 W) which
switches off the horizontal output.
Horizontal oscillator, horizontal output transistor, and second phase detector (pins 11, 12, 14 and 15)
The horizontal oscillator is connected to pin 15. The frequency is set by an external RC combination between pin 15 and
ground, pin 9. The open collector horizontal output stage is connected to pin 11. An internal zener diode configuration
limits the open voltage of pin 11 to » 14.5 V.
The horizontal output transistor at pin 11 is blocked until the current into pin 16 reaches a value of » 5 mA.
A higher current results in a horizontal output signal at pin 11, which starts with a duty factor of » 40% HIGH.
The duty factor is set by an internal current-source-loaded npn emitter follower stage connected to pin 14 during starting.
When pin 16 changes over to voltage stabilization the npn emitter follower and current source load at pin 14 are switched
OFF and the second phase detector circuit is activated, provided a horizontal flyback pulse is present at pin 12.
When no flyback pulse is detected at pin 12 the duty factor of the horizontal output stage is set to 50%.
The phase detector circuit at pin 14 compensates for storage time in the horizontal deflection output stage. The horizontal
output pulse duration is 29 ms HIGH for storage times between 1 ms and 17 ms (flyback pulse of 12 ms). A higher storage
time increases the HIGH time. Horizontal picture shift is possible by forcing an external charge or discharge current into
the capacitor at pin 14.

Mute output and 50/60 Hz identification (pin 13)
The collector of an npn transistor is connected to pin 13. When the voltage on pin 18 drops below 1.2 V
(no TV-transmitter) the npn transistor is switched ON.
When the voltage on pin 18 increases to a level of » 1.8 V (new TV-transmitter found) the npn transistor is switched OFF.
Pin 13 has also the possibility for 50/60 Hz identification. This function is available when pin 13 is connected to pin 10
(+ 12 V) via an external pull-up resistor of 10 to 20 kW. When no TV-transmitter is identified the voltage on pin 13 will be
LOW (< 0.5 V). When a TV-transmitter with a divider ratio > 576 (50 Hz) is detected the output voltage of pin 13 is HIGH
(+ 12 V).
When a TV-transmitter with a divider ratio < 576 (60 Hz) is found an internal pnp transistor with its emitter connected to
pin 13 will force this pin output voltage down to » 7.6 V.
Sandcastle output (pin 17)
The sandcastle output pulse generated at pin 17, has three different voltage levels. The highest level, (10.4 V), can be
used for burst gating and black level clamping. The second level (4.5 V) is obtained from the horizontal flyback pulse at
pin 12, and is used for horizontal blanking. The third level (2.5 V) is used for vertical blanking and is derived via the
vertical divider system. For 50 Hz the blanking pulse duration is 44 clock pulses and for 60 Hz it is 34 clock pulses started
from the vertical divider reset. For TV-signals which have a divider ratio between 622 and 628 or between 522 and 528
the pulse is started at the first equalizing pulse. With the 50/60 Hz information the burst-key pulse width is switched to
improve the behaviour in multi-norm concepts.



- IF DEM + AMPL with TDA3541
DESCRIPTION
The TDA3541;Q are integrated IF
amplifier and demodulator circuits for colour or black/white
television receivers, the TDA8340;Q is for application with
n-p-n tuners and the TDA8341;Q for p-n-p tuners.

The TDA8340;Q and TDA8341;Q are pin-compatible
successors with improved performance to types
TDA2540/2541;Q and TDA3540/3541;Q.
Features
· Full range gain-controlled wide-band IF amplifier
· Linear synchronous demodulator with excellent
intermodulation performance
· White spot inverter
· Wide-band video amplifier with noise protection
· AFC circuit with AFC on/off switching and
sample-and-hold function
· Low impedance AFC output
· AGC circuit with noise gating
· Tuner AGC output for n-p-n tuners (TDA8340) or p-n-p
tuners (TDA8341)
· External video switch for switching-off the video output
· Reduced sensitivity for high sound carriers
· Integrated filter to limit second harmonic IF signals
· Wide supply voltage range
· Requires few external components

An automatic fine tuning (AFT) circuit is provided which generates an AFT control signal in response to a video intermediate frequency (I.F.) signal. The I.F. signal is supplied to the inputs of two buffer amplifiers, which couple signals of like phase relationship to two inputs of a discriminator network. The discriminator network is tuned to the desired frequency of the video I.F. signal, and is responsive to the buffered I.F. signals for causing respective signal voltages to be developed at its inputs which vary differentially in magnitude in response to the frequency deviation of the I.F. signals from the desired I.F. frequency. The differentially related signals are detected by two peak detector networks for use as AFT control signals. The buffer amplifiers and peak detectors may be conveniently fabricated on a single I.C. chip. The discriminator network is coupled to the buffer amplifiers by two external I.C. terminals.
------------------------------



CHASSIS CP90 TELETEXT UNIT 311910861001 4822 21222614

SAA
5231 PHILIPS
SAA5241P/B PHILIPS
TMM2016BP-15 TOSHIBA

The teletext Unit was generally an extra addon to purchase apart except for the TXT model which it have had included directly.








SAA5231 Teletext video processor:

GENERAL DESCRIPTION
The SAA5231 is a bipolar integrated circuit intended as a successor to the SAA5030. It extracts Teletext Data from the
video signal, regenerates Teletext Clock and synchronizes the text display to the television syncs. The integrated circuit
is intended to work in conjunction with CCT (Computer Controlled Teletext), EUROM or other compatible devices.
Features
· Adaptive data slicer
· Data clock regenerator
· Adaptive sync separator, horizontal phase detector and 6 MHz VCO forming display phase locked loop (PLL)

The function is quoted against the corresponding pin number.
1. Synch output to TV
Output with dual polarity buffer, a load resistor to 0 V or + 12 V selects positive-going or negative-going syncs.
2. Video input level select
When this pin is LOW a 1 V video input level is selected. When the pin is not connected it floats HIGH selecting a
2,5 V video input level.
3. HF filter
The video signal for the h.f.-loss compensator is filtered by a 15 pF capacitor connected to this pin.
4. Store h.f.
The h.f. amplitude is stored by a 1 nF capacitor connected to this pin.
5. Store amplitude
The amplitude for the adaptive data slicer is stored by a 470 pF capacitor connected to this pin.
6. Store zero level
The zero level for the adaptive data slicer is stored by a 22 nF capacitor connected to this pin.
7. External data input
Current input for sliced teletext data from external device.
Active HIGH level (current), low impedance input.
8. Data timing
A 270 pF capacitor is connected to this pin for timing of the adaptive data slicer.
9. Store phase
The output signal from the clock phase detector is stored by a 100 pF capacitor connected to this pin.
10. Video tape recorder mode (VCR)
Signal input to command PLL into short time constant mode. Not used in application circuit Fig.4a or Fig.4b.
11. Crystal
A 13,875 MHz crystal, 2 x data rate, connected in series with a 15 pF capacitor is applied via this pin to the oscillator
and divide-by-two to provide the 6,9375 MHz clock signal.
12. Clock filter
A filter for the 6,9375 MHz clock signal is connected to this pin.
13. Ground (0 V)
14. Teletext clock output (TTC)
Clock output for CCT (Computer Controlled Teletext).
15. Teletext data output (TTD)
Data output for CCT.
16. Supply voltage VCC (+ 12 V typ.)
17. Clock output (F6)
6 MHz clock output for timing and sandcastle generation in CCT.
18. Oscillator output (6 MHz)
A series resonant circuit is connected between this pin and pin 20 to control the nominal frequency of the VCO.
19. Filter 2
A filter with a short time constant is connected to this pin for the horizontal phase detector. It is used in the video
recorder mode and while the loop is locking up.

20. Oscillator input (6 MHz)
See pin 18.
21. Filter 1
A filter with a long time constant is connected to this pin for the horizontal phase detector.
22. Sandcastle input pulse (PL/CBB)
This input accepts a sandcastle waveform, which is formed from PL and CBB from the CCT.
Signal timing is shown in Fig.5.
23. Pulse timing resistor
The current for the pulse generator is defined by a 68 W resistor connected to this pin.
24. Pulse timing capacitor
The timing of the pulse generator is determined by a 220 pF capacitor connected to this pin.
25. Video composite sync output (VCS)
The output signal is for CCT.
26. Black level
The black level for the adaptive sync separator is stored by a 68 nF capacitor connected to this pin.
27. Composite video input (CVS)
The composite video signal is input via a 2,2 mF clamping capacitor to the adaptive sync separator.
28. Text composite sync input (TCS)/Scan composite sync input (SCS)
TCS is input from CCT or SCS from external sync circuit. SCS is expected when there is no load resistor at pin 1.
If pin 28 is not connected the sync output on pin 1 will be the composite video input at pin 27, internally buffered.


PHILIPS 17CE1230 MATISSE CHASSIS CP90 Teletext decoder with improved processor which determines the beginning and end of a teletext page:


 As shown in FIG. 2, a teletext decoder has a multi-page memory (MEM) comprising a plurality of memory portions (CH0 to CH3) in which individual pages can be stored on a priority basis. The numbers of selected pages are entered into page request registers (PR0 to PR3) and when the number of a selected page is detected by the relevent one of page comparators (PC0 to PC3) a found bit (FB) is produced by the relevant one of flip-flops (FB0 to FB3) and recorded in the memory portion allotted to the selected page by processor means (PM). In order to ensure that the end of a selected page can also be detected, one of the memory portions is allotted to store every page received so that a found bit is always produced at the end of a selected page stored in another memory portion. The processor means (PM) uses this latter found bit to signify detection of the end of the selected page.

 1. A teletext decoder for teletext information comprising a plurality of different pages each of which is identified by a respective page number, said teletext decoder comprising:
processor means,
a multi-page memory having a plurality of memory portions for storing the different pages on a priority basis,
means for selecting given ones of the different pages by their respective page number in preparation for storing in the memory portions according to an allotment by the processor means, and
means responsive to the respective page number of a page selected by the selecting means to store a found signal corresponding to a memory portion allotted to the page selected by the selecting means,
wherein the processor means is operable;
to allot a particular memory portion for storing a first page,
to cause the selection means to select the first page in preparation for storing the first page in said particular memory portion,
to detect a beginning of storing of the first page selected by the selecting means in response to a first stored found signal
to detect a beginning of storing of a second page selected by said selecting means in response to a second stored found signal, and
to detect an end of storing of the first page by changing the state of the first found signal in response to the second found signal.


2. The teletext decoder of claim 1 wherein the processor means is operable to test for the first and second found signals.

3. The teletext decoder of claim 1 wherein each memory portion includes a respective single bit location for storing a respective found signal in the form of a single bit, the single bit having one logic value when the processor means has allotted such memory portion to one of the different pages, which one page has not been found after being selected by the selecting means, the single bit having a second logic value when the one page has been found.

4. The teletext decoder of claim 3 wherein the processor means is operable to change a value of the single bit from the second logic value to the first logic value when a currently selected page is allotted to the respective memory portion.

5. The teletext decoder of claim 1 wherein the processor means is operable to set flags therein representing a respective beginning and end of storage of the page selected by the selecting means.

6. A teletext decoder as claimed in claim 5, characterised in that each of said flags is a single bit which is given one logic value when it is set and the opposite logic value when it is cleared.

7. The teletext decoder of claim 1 wherein the processor means is operable to allot first and second particular memory portions to first and second first pages; and
to cause the first and second particular memory portions to store the first and second first pages alternately, so that the first particular memory portion retains the first first page while the second particular memory portion stores the second first page, with beginning and ends of the first and second first pages being detected between the first and second first pages using first and second first stored found signals.


8. The teletext decoder of claim 7, wherein the processing means is operable to determine from a logic value of a single flag bit which of the first and second particular memory portions is to store a next page selected by the selecting means and which is to retain a current page selected by the selecting means.

9. The teletext decoder of claim 8 wherein said first particular memory portion is accorded a higher priority than said second particular memory portion; and
said single flag bit is associated with said first particular memory portion, so that said second particular memory portion automatically stores the next page when said single flag bit determines that said first particular memory portion is not to store the next page.


10. A method for identifying an end of a teletext page which is one of a plurality of different teletext pages, the method comprising the following steps: (a) allotting a first portion of a multi-page memory to a first teletext page;
(b) selecting a first teletext page;
(c) when the first page is found, first storing a first found signal and the first teletext page in the first portion;
(d) second storing a second found signal and a second teletext page in a second portion of the multi-page memory;
(e) identifying a beginning of the second page in response to the second stored found signal; and
(f) identifying an end of the first page by changing a state of the stored first found signal in response to the second stored found signal.


11. A method for identifying an end of a teletext page comprising the following steps in the order given: (a) receiving a plurality of teletext pages;
(b) allotting a first portion of multi-page memory to a first one of the teletext pages;
(c) first finding the first one of the teletext pages;
(d) first storing a first logic value for a first found signal in the first portion, to indicate that the first one of the teletext pages is being either stored or sought;
(e) second storage the first one of the teletext pages in the first portion;
(f) second finding a second one of the teletext pages;
(g) third storing the first logic value for a second found signal in a second portion of the multi-page memory, to indicate that the second one of the teletext pages is being either stored or sought; and
(g) setting the first found signal to a second logic value, to indicate that the end of the first one of the teletext pages has been reached, in response to the first logic value of the second found signal;
whereby the end of the first one of the teletext pages is identified without embedding an end of page signal in the first teletext page and without loss of the first teletext page.


12. The method of claim 11 wherein (a) the first and third storing steps are performed by hardwired data acquisition circuits; and
(b) the setting step is performed by software in a processor.


13. The method of claim 11 further comprising the step of acquiring a control page.

14. The method of claim 11 further comprising the step of maintaining internal flags in a processor, which internal flags represent ends of teletext pages, in response to the found signals.


15. The method of claim 11 further comprising the steps of (a) allocating first, second, third, and fourth page locations of the multi-page memory to a control page, a first data page, a second data page, and a trash page, respectively;
(b) selecting the control, first and second data pages; and
(c) selecting a range of trash pages.


16. The method of claim 15 further comprising the steps of (a) alternating acquisition of the first and second data pages, and
(b) using a beginning of the trash page to signify an end of any other page.


Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to teletext decoders for receiving, storing and processing teletext information which is transmitted as digitally coded data and comprises a plurality of different pages each of which is identified by a respective page number. Transmissions of teletext information are in television signals in television lines where no picture signals representing normal television picture information are present. These television lines are referred to as data-lines.
2. Related Art
The document "Broadcast Teletext Specification", September 1976, published jointly by the British Broadcasting Corporation, Independent Broadcasting Authority and British Radio Equipment Manufacturers' Association, discloses a specification for transmitting teletext information in 625-line television systems.
In the above-identified document "Broadcast Teletext Specification", a quantity of teletext information to be considered as an entity is termed a page and will be so termed herein. All of the pages which are available are normally transmitted in a recurrent cycle, with or without up-dating page information, as appropriate. At a teletext decoder any page can be selected, and the digitally coded data representing the page information is then acquired by the teletext decoder from the cyclic transmission and is stored in a page memory of the teletext decoder for as long as the page is required. A teletext decoder may have a multi-page memory having a plurality of memory portions in which individual pages can be stored. These memory portions may be used on a priority basis, that is, if two (or more) memory portions are allotted to store the same selected page, then priority logic in the decoder allows only one portion to receive the page in preference to the other(s).
The pages are organised into different magazines (or groups) and each page consists of up to 24 data rows. The first data row (Row 0) of each page is termed a page-header and contains inter alia the page number. The transmission of each page begins with, and includes, its page-header and ends with, and excludes, the next page-header which is transmitted in respect of a page in the same magazine. Thus, it is assumed that all of the data rows containing the relevant magazine number which are transmitted between two such successively transmitted different page-headers belong to the page having the first page-header.
Proposals for enhancing the teletext specification given in the "Broadcast Teletext Specification" document are given in the document "World System Teletext Technical Specification", March 1985, compiled by the Department of Trade and Industry. One of these enhancement proposals concerns the provision of a conditional access teletext service in which teletext message information in data pages is scrambled prior to transmission, and can only be received as useful information by a teletext decoder having an appropriate descrambling key. Such a descrambling key is itself transmitted as encrypted teletext information in the data page concerned, whilst other keys which are provided to regulate the conditional access to transmitted teletext message information are transmitted in encrypted control pages. Decryption therefore has also to be performed within the teletext decoder.
The reception and processing of the scrambled data pages and the encrypted control pages necessitates the use of a type of teletext decoder which includes processor means for carrying out the descrambling and decryption. The actual reception of the data pages and control pages can be carried out by dedicated hardware circuits of the teletext decoder, albeit under the control of the processor means.
A problem that has been encountered in the realisation of a teletext decoder of this type is that the processor means needs to know when acquisition of a selected teletext page (control or data) has been completed before descrambling or decryption, as the case may be, of the teletext page can commence. This problem occurs because although the aforementioned page-header feature provides a specific page-found indication from which a `page-found` signal can be produced directly to signify the start of a selected page, this feature does not provide a specific end-of-page indication at the end of the transmitted page from which an end-of-page signal can be produced directly at the end of a transmitted page.

SUMMARY OF THE INVENTION
It is an object of the present invention to provide a teletext decoder of the type set forth above which includes means for determining when all of the teletext information contained in selected page has been received by the teletext decoder.
According to the invention a teletext decoder for teletext information comprising a plurality of different pages each of which is identified by a respective page number, comprises:
processor means,
a multi-page memory having a plurality of memory portions in which individual pages can be stored on a priority basis,
means for selecting pages by their page number for storage in memory portions allotted by the processor means, and
means responsive to the receipt of the page number of a selected page to record a found signal in respect of the memory portion allotted to that page, which teletext decoder is characterised in that said processor means is operable:
to allot a particular memory portion for the storage of any received page,
to cause the selection means to select all the received pages of said plurality for storage in said particular memory portion,
to signify the beginning of the storage of an individually selected page in another memory portion in response to the presence of a found signal in respect of that memory portion, and
to signify the end of the storage of the selected page in response to the presence of a found signal in respect of said particular memory portion.
By causing any received page to be accepted and stored in said particular memory portion, it is ensured that a found signal is always produced at the end of an individually selected page, which found signal thus becomes an effective end of page signal for the selected page.
Because of the priority logic in the docoder, a page which is individually selected and has a memory portion allotted to it will be stored in that memory portion rather than in said particular memory portion. It therefore follows that when two different immediately adjacent pages are individually selected, each will have a respective memory portion allotted to it for storage therein and neither will be stored in said particular page.
Thus, in carrying out the invention, it is preferable to arrange the operation of the processor means such that the presence of a found signal is looked for in respect of both said particular memory portion and each other memory portion that may be allotted to an immediately following individually selected page.
Conveniently, the found signal is a single, found, bit which is stored in the memory portion to which it pertains, this found bit having one logic value when a page to which its memory portion has been allotted has not been found following its selection, and this found bit having the opposite logic value when the page number for that page has been received.
In order that the found bit pertaining to said particular memory portion is always at said one logic value prior to the receipt of the page number for the page immediately following a selected page, the processor means may be arranged to write a found bit of said one logic value into said particular memory portion each time the presence of a found bit of said opposite logic value is detected in the memory portion allotted to an individually selected page.
The beginning and end of the storage of an individually selected page can be signified in the processor means by the setting therein of respective flags. These flags may be respective single bits which are given one logic value when they are set and the opposite logic value when they are cleared .

BRIEF DESCRIPTION OF THE DRAWING
In order that the invention may be fully understood reference will now be made by way of example to the accompanying drawings, of which:
FIG. 1 is a block diagram of a teletext decoder in which the invention can be embodied;
FIG. 2 is a block diagram showing elements of the teletext decoder of FIG. 1;
FIG. 3 is a flow chart showing operations of the processing means of the teletext decoder in the performance of the invention; and
FIG. 4 is a timing diagram showing the time relationships of various of the steps in the flow chart of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to the drawings, the teletext decoder shown in FIG. 1 has a front end 1 for receiving an incoming television signal VS. This front end 1 comprises the usual amplifying, tuning and i.f. detector circuits and is under tuning control of processor means 2. The demodulated video signal VS' produced at the output of the front end 1 is applied to a video processor circuit 3 which performs data slicing for retrieving teletext data pulses D from the video signal VS'. The video processor circuit 3 also produces input data clock pulses C from the data pulses D. The data pulses D are fed together with the clock pulses C to a data acquisition circuit 4 which is operable to feed selected groups D/G of the data pulses to a memory 5 as address, message and control information. The memory 5 has a capacity for storing at least four pages, comprising a plurality of data rows, in respective memory portions which are hereinafter referred to as "chapters". A page and row format according to the aforementioned "Broadcast Teletext Specification" is assumed.
The processor means 2 is operable in accordance with select signals applied to it from a user interface device 6 to control channel selection and which pages, as composed of the selected groups D/G of the data pulses, are acquired by the data acquisition circuit 4. The processor means 2 is further operable to read out from the memory 5 the control and message information which has been acquired. The message information is used to drive a character generator 7 which produces R,G,B, component signals for utilisation. A timing circuit 8 provides timing signals on connections t1, t2 and t3 for the circuit elements 4, 5 and 7. These circuit elements and the timing circuit 8 are accessed by the processor means 2 via an interface circuit 9. The operation of the timing circuit 8 is synchronised with the received video signal VS by a composite pulse signal VCS which contains the line and field synchronising pulses which are separated from the demodulated video signal VS' in the video processor circuit 3.
The operation of the processor means 2 may also be under the control of a remote terminal or computer which has access to the teletext decoder via a suitable two-way link 10 and interface 11, for instance an RS232 external link. Acquired teletext information can then be transmitted over this external link for utilisation remotely. Channel and page selection may also be effected from a remote terminal rather than by the interface device 6.
The processor means 2 can be a commercially available microcomputer; e.g. from the MAB 8400 Series (Philips). The circuit element can be the integrated circuit VIP2 type 5230 (Mullard); the circuit elements 4, 5 and 8 can be the integrated circuit EURO CCT type SAA 5240 (Mullard); and the interface circuit 9 can be a so-called I2 C bus.

The block diagram of FIG. 2 shows elements of the data acquisition circuit (4 - FIG. 1) of the teletext decoder. An 8-bit shift register SR/8 has the received teletext data pulses D clocked into it by the clock pulses C. In the aforementioned "Broadcast Teletext Specification", each teletext data row includes for byte synchronisation an 8-bit framing code. This framing code is looked for by a framing code detector FCD and when it is found, this indicates the start of proper data on a data-line and a `start` signal ST is applied by the detector FCD to a data bit counter BC. The bit counter BC is clocked by the clock pulses C and counts the teletext data pulses as they are clocked into the shift register SR/8. Various decodes from the bit counter BC provide pulses to other parts of the data acquisition circuit at certain times during the data-line. One of these decodes provides a signal (≉8) every eight clock pulses, and is used to clock the data pulses into an 8-bit latch LA. The serial teletext data pulse stream is thus broken up into 8-bit words. The 8-bit words are fed to a Hamming and parity checker HPC. Seven of the eight bits of words from the latch LA form data bytes of teletext information TI to be stored in the relevant chapters of a page memory MEM (5 - FIG. 1). This memory MEM has four chapters CH0 and CH3 for storing respective pages. The eighth bit is a parity bit, which is not stored but is used by the Hamming and parity checker HPC to test for odd parity in the words. The first two 8-bit words after the framing code on each data-line are used to define row and magazine addresses, which are protected by Hamming codes. The checker HPC effects Hamming correction for one bit errors and Hamming detection of two bit errors and produces two 4-bit corrected words of which 5 bits define row addresses and the remaining 3 bits define magazine addresses. These two addresses are clocked into respective row and magazine address latches. However, for the sake of simplicity there is shown in FIG. 2 only the row address latch RL which is clocked by row pulses RA from the bit counter BC to latch in successive 5-bit row addresses.
The row address output RAO from the latch RL identifies in various chapters the row addresses where the teletext information TI is to be stored in the memory MEM. The row address output RAO is also applied to a detector DRO which can detect the address of Row 0. When Row 0 (i.e. a page-header) is detected, the detector DRO produces a signal which `sets` (s) a flip-flop PHR (page header received). The resulting signal from the flip-flop PHR `enables` (e) a group of four page comparators PC0 to PC3, `resets` (rs) a group of four flip-flops CPHR0-CPHR3 (correct page header received), and `activates` (a) a write element WC via an OR-gate OWC. When activated, the element WC produces a `write` signal WS which enables a memory interface and control element MCE to permit data (TI) in a detected page-header (Row 0) to be written into one of the chapters of the memory MEM. The particular one of four chapters concerned is determined by the processor means PM (2 - FIG. 1) by a chapter `select` signal CHS which is applied to the element MCE from the processor means PM via the bus I2 C (9 -FIG. 1).
Associated with the page comparators PC0 to PC3 are respective page request registers PRO to PR3 into which the page numbers PN of selected pages are entered by the processor means PM. As already mentioned, a page may be selected directly from a user interface device (6 - FIG. 1). A page may also be selected by the processor means 2 in accordance with control information contained in a previously acquired page. When a page number is entered into one of the registers PRO to PR3 an associated one of four flip-flops PBLF0 to PBLF3 (page being looked for) is set (s) and a PBLF bit of logic value `1` is entered into the associated one of the memory chapters CH0 to CH3.
Each page-header (Row 0) contains a Hamming protected page number which is compared in each of the comparators PC0 to PC3 with any page number that has been entered into the registers PR0 to PR3. If there is correspondence between any of the compared page numbers the or each comparator concerned `sets` (s) the associated one of the four flip-flops CPHR0 to CPHR3. The resulting output signal from a set one of these flip-flops `activates` (a) the write control element WC via the OR-gate OWC for all the following data-lines that cohtain the data rows of the selected page, until receipt of the next page-header (Row 0) causes the flip-flops which are set to be reset by the flip-flop PHR and thereby terminate the writing action. A reset pulse RS is applied to the flip-flop PHR at the end of every data-line by the bit counter BC. The activation of the write control element WC is in respect of an output signal from any of the flip-flops CPHR0 to CPHR3, but a priority detector PD to which these output signals are applied determines on a pre-selected priority basis into which memory chapter the selected page is to be written in the event that more than one of the flip-flops CPHR0 to CPHR3 signifies that a correct page header has been received.
The output signals from the set flip-flops CPHR0-CPHR3 are also used to `reset` (rs) a respective one of the four flip-flops PBLF0 to PBLF3. This results in the relevant PBLF bit being changed from a logic value `1` to a logic value `0`. Finally, the output signals from the flip-flops CPHR0-CPHR3 reset (rs) respective flip-flops FB0 to FB3 to provide found bits FB of `0` logic value which are stored in the relevant memory chapter. These found bits FB and the bits PBLF are used by the processor means PM for data acquisition control. The bits PBLF are changed between the logic values `1` and `0` values as the flip-flops PBLF0 to PBLF3 are `set` and `reset` by the circuit action. However, this is not the case for the bits FB which, as stored, are only given the logic value `0` by the circuit action. A bit FB can only be changed to the logic value `1` by the processor means PM setting the relevant one of the flip-flops FB0 to FB3 using a setting signal SS. Three situations concerning the logic values of the bits FB and PBLF can be determined. Firstly, there is a normal situation in which a page has been received and all relevant control functions have been dealt with by the processor means PM. This is indicated by PBLF =0 and FB =1 (written by the processor means PM). Second, after a page has been requested and is being searched for, PBLF =1 and FB =1. Third, when a page has been received but the processor means PM has not yet observed the fact, this is indicated by PBLF =0 and FB =0.
When the processor means PM has dealt with any actions which are necessary on receipt of a page, it changes the relevant found bit FB to a logic value `1`. This then acts as a flag to signify to control software that such actions have been taken and it need not process that page again. Each time the page is subsequently received the found bit FB will be reset to the logic value `0`, indicating to the processor means PM that action may be required (e.g. the page may be updated). If no special action is to be taken by the control software on receipt of a page there is no need for the processor means PM to set the found bit FB to a logic `1`, and this bit will remain at the logic value `0` after the first reception of a page.
It can be seen from the foregoing description of the operation of the data acquisition circuit that the processor means PM can determine from the relevant bit PBLF whether or not a requested page is being looked for, as determined by the logic value `0` or `1` value of this bit, and it can determine from the logic value `0` of the found bit FB when a requested page has been found. The processor means PM cannot, however, determine when all the data rows of a found page have been received because the logic value of the found bit FB is not changed by the data acquisition circuit in response to receipt of a subsequent page header, which provides the assumption that all the data rows of the previous page have been sent.
In accordance with the present invention, the control software of the processor means PM is organised so as to give an end-of-page indication. Such an indication has been found to be necessary when dealing with scrambled and encrypted teletext pages. The flow chart of FIG. 3 illustrates the control software which provides the end-of-page detection. For the purposes of the following description of the software control, it will be assumed that different teletext pages in a hexadecimal page number range 700 to 7FF are to be received by the teletext decoder, and that the processor means PM always allots the memory chapter CH0 for storing a control page (e.g. page 700), the memory chapters CH1 to CH2 for storing data pages, (e.g. 701, 702 . . . ), and the memory chapter CH3 for storing any page 7xx, :n this number range. The processor means PM allots the memory chapters CH1 and CH2 alternately for the storage of selected data pages, by alternating the entry of individually selected data page numbers into the page request registers PR1 PR2. The page request register PR3 has all the page numbers of the range entered into it by the processor means PM.
In the flow chart of FIG. 3, the various boxes and the legends contained therein specify the control software programme steps as follows:
F1: STRT - this is an instruction to enter the programme.
F2: TIM 0/F? -- this is an instruction to determine whether (Y) or not (N) a timer has timed-out.
(The purpose of the timer is to set a flag once every 20ms - i.e. once per television field - to identify the start of each vertical blanking interval. The timer is automatically reset after each interval, to remove the flag, and commences a new time-out period.
F3: CPpf? - this is an instruction to determine whether (Y) or not (N) a flag CPpf in the processor means PM has is set (=1) or cleared (=0). (When a control page CP is currently being acquired in the memory chapter CH0, as signified by FB/CP =0, this flag CPpf =1).
F4: FB/DP-TP - this step is entered into when the flag CPpf is set, and is an instruction requiring the processor means PM to get the found bit FB from the chapter memory CH1 (or CH2 as will be discussed) and also from the chapter memory CH3.
F5: FB=0? - this is an instruction to determine whether either of the found bits FB which have been obtained are at logic value `0`.
(When FB/DP1 =0 (or FBDP2 =0) in the chapter memory CH1 (or CH2) this signifies that a data page DP is stored or is being stored therein. Likewise, when FB/TP =0 in the chapter memory CH3 this signifies that another (trash) page TP is stored or is being stored therein. When either of these found bits FB has a logic value `1` this signifies that the control page CP is still being acquired).
F6: EXT - this is an instruction to exit the programme when the control page CP is still being acquired.
F7: DPpf? - this step is entered into when step F3 determines that the flag CPpf =0, and is an instruction for determining whether (Y) or not (N) a flag DPpf in the processor means PM is set (=1) or cleared (=0). (When a data page DP is currently being acquired in the memory chapter CH1 (or CH2), as signified by FB/DP1 =0 (or FB/DP2 =0), this flag DPpf =1).
F8 FB/CP-TP - this step is entered into when the flag DPpf is set, and is an instruction requiring the processor means PM to get the found bit FB/CP from the chapter memory CH0 and also the found bit FB/TP from the chapter memory CH3.
F9: FB=0? - this is an instruction to determine whether either of the found bits FB which have been obtained are at logic value `0`.
(When FB/CP =0 in the chapter memory CH0 this signifies that a control page CP is stored or is being stored therein. Likewise, when FB/TP =0 in the chapter memory CH3 this signifies that another (trash) page TP is stored or is being stored therein. When either of these found bits FB has a logic value `1` this signifies that the data page DP is still being acquired).
F10: EXT - this is an instruction to exit the programme when the data page DP is still being acquired.
F11: CLR CPpf - when step F5 determines that the found bit FB in SET CPepd either chapter memory CH1 (or CH2) or chapter memory and CH3 has a logic value `0` this WR FB/CP instruction F11 is entered into and requires the processor means PM to clear the flag CPpf, to set another flag CPepd, and to write a bit of logic value `1` for the found bit FB/CP in the chapter memory CH0. (The clearing of the flag CPpf signifies that the control page is no longer being acquired and the setting of the flag CPepd signifies that the entire control page has been received. The bit FB/CP =1 in the chapter memory CH0 signifies that the control software action for receiving the control page has been completed).
F12: CLR DPpf - this instruction corresponds to the instruction in SET DP epd step F11 but it is carried out in respect of a data
WR FB/DP page DP1 (or DP2) when either FB/CP =0 in the memory chapter CH0, or FB/TP =0 in the memory chapter CH3 as determined by step F9.
F13: FB/DP=0? - this is an instruction to determine whether the found bit FBDP1 (or FB/DP2) obtained by step F4 in the memory chapter CH1 (or CH2) is at logic value `0`. If it is not, then the programme is exited at step F14. If this found bit is at logic value `0`, signifying that a data page is being stored in the relevant chapter memory, step F15 is entered into.
F14: EXT - this is an instruction to exit the programme as just mentioned.
F15: SET DPpf - this instruction requires the processor means PM to CLR DPepd set the flag DPpf, to clear another flag DPepd, and WR FB/TP to write a bit of logic value `1` for the found bit FB/TP in the chapter memory CH3. (The setting of the flag DPpf signifies that a data page is being acquired and the clearing of the flag DPepd prepares for the subsequent setting of this latter flag when the entire data page has been received. The bit PB/TP is set to 0 in response to the next page header when it is received to provide an end-of-page indication for the page immediately preceding that page header).
F16: EXT - this is an instruction to exit the programme. F17: FB/CP=0? - this is an instruction to determine whether the found bit FB/CP obtained by step F8 in the memory chapter CH0 is at logic value `0`. If it is not, then the programme is exited at step F18. If this found bit is at logic value `0`, signifying that a control page CP is being stored in the chapter memory CH0, step F19 is entered into.
F18: EXT - this is an instruction to exit the programme as just mentioned.
F19: SET CPpf - this instruction corresponds to the instruction in CLR CPepd step F15 but it is carried out in respect of the WR FB/TP control page CP.
F20: FB/DP-CP - this is an instruction requiring the processor means PM to get the found bits FB from the chapter memories CH1 (or CH2) and CH0.
F21: FB/CP=0? - this step coresponds to step F17 and leads into step F19 when FB =0 in the chapter memory CH0.
F22: FB/DP=0? - this step corresponds to step F13 and leads into step F15 when FB =0 in the chapter memory CH1 (or CH2).
F23/24: EXT - these are instructions to exit the programme.
The overall operation of the flow chart of FIG. 3 may be summarised, as follows, with reference to the timing diagrams of FIG. 4. Diagram (a) represents a teletext transmission in which the blocks RO--RN signify successive data rows. Each block RO signifies a page header row of which five, PH1 to PH5, are shown. The data rows RO(PH1) to RN contain data for a control page CP, the data rows RO(PH2) to RN contain data for a data page DP, the data rows RO(PH3) to RN contain data for a trash page TP, the data rows RO(PH4) to RN contain data for a second data page DP, and the page header RO(PH5) is for a second control page CP.
Diagram (b) shows the output logic levels from the flip-flop PHR. The output logic levels from each of the flip-flops FB0 to FB3 which form the found bits FB are represented by diagrams (c), (d) and (e), respectively.
At the time that the page header RO(PH1) is received both the flags CPpf and DPpf are cleared, so that step F20 is entered via steps F3 and F7 to obtain FB/DP and FB/CP in step F20. Step F19 is then entered into because step F21 detects FB/CP =0. Because CPpf =1 is now detected by step F3, steps F4 and F5 are entered periodically. When the page-header R0(PH2) has been received, FB/DP =0 to allow step F11 to be entered to set the flag CPepd which signifies that all the data rows of the control page CP have been received. Because the page-header RO(PH2) relates to the data page DP, step F15 is entered via step F13 to set the flag DPpf. With the flag CPpf reset and the flag DPpf set, step F8 is entered into via steps F3 and F7. When the page-header RO (PH3) has been received, FB/TP =0 to allow step F12 to be entered into via steps F8 and F9 to set the flag DPepd which signifies that all the data rows of the data page DP have been received. Both the flags CPpf and DPpf are now reset again so that steps F20, F21 and F22 are entered via steps F3 and F7 and are passed through without any change because FB/CP =1 and FB/DP =1. When the page-header RO(PH4) has been received, FB/DP =0 to allow step F15 to be entered into via step F22 to set the flag DPpf. When the page-header RO(PH5) has been received, step F12 is entered into via steps F8 and F9 to set the flag DPepd to signify that all the second data page DP has been received. Because FB/CP =0, step F19 is next entered into from step F17 to set the flag CPpf.
It can be seen from the foregoing that whenever the page header for a control page or a data page is received, as detected by the logic value `0` of the found bit in the relevant memory chapter, the processor means writes a found bit of logic value `1` into the memory chapter allocated to the trash page. A found bit of logic value `1` will also be stored in the memory chapter for a control page or a data page prior to such pages being received. When the next page header for either a control page or a data page is received, this causes the relevant found bit to be changed to the logic value `0` which is detected by the processor means to set the end-of-page detector flag in respect of the preceding page. If the next page-header is not for a control page or a data page, then the data acquisition circuit will accept the page-header as belonging to a trash page to change the found bit for this trash page to logic value `0` and this again will be detected by the processor means to set the end-of-page detector flag in respect of the preceding page. Depending on the page-header sequence the found bit for the fresh page may already be of logic value `1` when a logic value `1` is written to it.
The flow chart of FIG. 3 also includes a multi-instruction step F25: CPL ACQb, HOL SP, ACQ DP. This instruction step serves to make the two memory chapters CH1 and CH2 available alternately for storing the next acquired data page, even though both these chapters are always allotted to store this page. CPL ACQb is a complement instruction to change the value of a flag ACQb between logic value `1` and `0` to cause the processor means to carry out the other steps of the programme in respect of the two memory chapters in turn as they become available alternately. HOL SP and AQC DP are instructions which identify in the processor means which memory chapter is holding a previously acquired data page (i.e. a shadow page SP) and which memory chapter is being used to acquire the next data page (DP). When the flag ACQb =1, the memory chapter CH1 is used to acquire the next data page and the memory chapter CH2 holds the shadow page. When the flag ACQb =0, the memory chapter CH1 holds the shadow page and the memory chapter CH2 is used to acquire the next data page. Because of the priority detector PD of the data acquisition circuit, the chapter CH1 will normally be chosen before chapter CH2 to store the next received data page. Therefore, it only becomes necessary to use the single flag ACQb to select the "hold" or "acquire" function of the memory chapter CH1, because the memory chapter CH2 will then automatically have the alternate function. Because of the toggling action in respect of alternate data pages, the instruction WR FB/DP in step F12 is now carried out after step F25.



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