This Chassis SCC-231B-A is developed on 2 main panels boards.
- Deflections + Supply board on the central bottom.
- Signal board on the left side vertical mounted.
uPC1365C Luminance and Chrominance combination ASIC - Chroma Processor Circuit - PAL Chrominance & Luminance Processor
SONY Digitally controlled tuner with automatic fine tuning:
A tuning system for digitally controlled electronically tuned tuner with automatic fine tuning (AFT) constantly operable to hold the tuner at a predetermined optimum frequency setting, especially a television channel. A reversible counter provides the digital signal to control the tuning of the tuner and is, itself, deliberately shifted from one setting to another by pulses from a source, such pulses being applied to the UP input terminal of the counter as the up-tuning pulses to shift the tuner frequency higher. Pulses from the same source are also used as down-tuning pulses when applied to the DOWN input terminal of the tuning pulses to a lower frequency supplied to two AFT AND circuits. One output logic up-tuning instruction signal EU of the AFT circuit enables the up-tuning AFT AND circuit only in a certain sub-range below the desired frequency. The other output logic down-tuning instruction signal ED of the AFT circuit enables the other AFT AND circuit only in a certain sub-range above the desired frequency. Consequently, deliberate application of up-or-down-tuning pulses to the UP or DOWN terminals changes the count as desired, being only partially counteracted by the lower frequency, AFT-controlled pulses to the opposite counter terminal.
1. A channel selecting apparatus comprising an electronically tuned tuner, a reversible counter having an UP input terminal and a DOWN input terminal to receive pulses to cause said counter to count UP and DOWN, respectively, digital-to-analog converter means connected to said counter to receive digital count from the latter and to convert the same to an analog signal to control the tuning of said tuner, an automatic fine tuning circuit comprising means to generate automatic fine tuning control signals when said tuner is tuned within an automatic fine tuning range centered about a channel frequency, said signals including an up-tuning control signal when said tuner is tuned within said range but below the channel frequency in that range and a down-tuning control signal when said tuner is tuned within said range between the channel frequency in that range and an upper frequency of that range, a source of first pulses having a predetermined frequency, first connection means for selectively channeling said first pulses to said UP and DOWN input terminals of said counter for bringing said tuner from one channel to another, a source of second pulses having a frequency lower than that of said first pulses, and second connection means for selectively channeling said second pulses to said UP and DOWN input terminals, said automatic fine tuning circuit being connected to said second connection means to cause said second connection means to transmit said second pulses to said UP input terminal in response to said up-tuning control signal and to transmit said second pulses to said DOWN input terminal in response to said down-tuning control signal.
2. The channel selecting apparatus of claim 1 in which said first connection means comprises:
first and second AND circuits both connected to receive said first pulses from said source thereof, said first AND circuit being connected to said UP input terminal and said second AND circuit being connected to said DOWN input terminal; and
selective means to enable either of said AND circuits to allow the passage therethrough of said first pulses to the respective UP or DOWN input terminal.
3. The channel selecting apparatus of claim 2 in which said selective means comprises switch means to apply, selectively, a "1" signal to said first or said second AND circuit to enable that selected AND circuit to pass said first pulses to the respective UP or DOWN input terminal.
4. The channel selecting apparatus of claim 1 in which said means to produce said second pulses comprises a frequency divider connected to said source of said first pulses to divide the frequency of said first pulses to that of said second pulses.
5. The channel selecting apparatus of claim 4 in which said frequency divider is a divide-by-two frequency divider.
6. The channel selecting apparatus of claim 1 comprising first and second AND circuits both connected to said means to produce second pulses, said first AND circuit being connected to a terminal of said fine tuning circuit to receive said up-tuning control signal therefrom and said second AND circuit being connected to a second output terminal of said fine tuning circuit to receive said down-tuning control signal therefrom, said first AND circuit being connected to said UP input terminal to supply said second pulses thereto when said up-tuning control signal has a logic value of "1", and said second AND circuit being connected to said DOWN input terminal to supply said second pulses thereto when said down-tuning control signal has a logic value of "1".
7. The channel selecting apparatus of claim 6 comprising third and fourth AND circuits both connected to said source of first pulses;
first actuation means connected to said third AND circuit to apply a signal having a logic value of "1" to said third AND circuit, selectively, to allow said third AND circuit to conduct said first pulses therethrough;
second actuation means connected to said fourth AND circuit to supply selectively a signal having a logic value of "1" to make said fourth AND circuit conductive to said first pulses;
a first OR circuit having an output terminal connected to said UP input terminal of said counter and having input terminals connected to output terminals of said first and third AND circuits to transmit to said UP input terminal either said first pulses or said second pulses;
a second OR circuit having an output terminal connected to said DOWN input terminal of said counter and having input terminals connected to output terminals of said second and fourth AND circuits to supply to said DOWN input terminal said first or second pulses, the transmission of said first pulses through said third and fourth AND circuits being determined by said first and second actuation means, respectively and alternately, and the transmission of said second pulses through said first and second AND circuits being controlled by said up-tuning and down-tuning control signals, respectively, of said automatic fine tuning circuit independently of said actuation means.
The invention described hereinafter is related to the inventions described in the following U.S. applications:
U.S. Patent application Ser. No. 716,655, filed Aug. 23, 1976, now U.S. Pat. No. 4,085,371, issued Apr. 18, 1978;
U.S. Patent application Ser. No. 716,702, filed Aug. 23, 1976, now U.S. Pat. No. 4,085,372, issued Apr. 18, 1978;
U.S. Patent application Ser. No. 716,654, filed Aug. 23, 1976;
U.S. Patent application Ser. No. 717,477, filed Aug. 25, 1976, now U.S. Pat. No. 4,058,772, issued Nov. 15, 1977;
U.S. Patent application Ser. No. 740,753, filed Nov. 10, 1976;
U.S. Patent application Ser. No. 743,008, filed Nov. 18, 1976, now U.S. Pat. No. 4,079,420, issued Mar. 14, 1978;
U.S. Patent application Ser. No. 743,523, filed Nov. 19, 1976, now U.S. Pat. No. 4,079,320, issued Mar. 14, 1978.
Field of the Invention
This invention relates to a digitally controlled, electronic tuner that can be tuned to any of several different channels at different frequencies and which includes an automatic fine tuning (AFT) circuit to adjust the tuning precisely when the frequency to which the tuner is tuned is within a predetermined frequency range close to the exact desired frequency. In particular, the invention relates to a television signal tuner for a receiver having an AFT circuit to maintain the tuning at a selected frequency according to one of the available channels and further including means to overcome the effect of the AFT circuit when it is desired to shift the tuner to a different channel.
U.S. Pat. No. 4,085,371 describes a television receiver tuner in which the basic tuning is accomplished by controlling the voltage on the one or more varactors in the circuits to be tuned. Varactors are capacitors, the capacitance of which is determined by the magnitude of the direct voltage applied across the capacitor terminals. The tuning circuit includes a memory section that retains information in digital form according to the frequencies to which the tuner may be set. Such information may be generated in the overall circuit and applied to the memory section by a user of the television receiver, normally at the time the set is first placed in operation. Television channels are commonly identified by number and there are usually not more than a dozen or so channels at any one location. Thus a receiving set incorporating the electronic tuner of the aforesaid Pat. No. 4,085,371 is likely to be adjusted to receive each of the available channels in turn when the set is first placed in use. Thereafter tuning is simply accomplished by actuating a switch according to the desired channel.
However, because of aging factors in the circuit or environmental factors that affect the receiver, the initial tuning information stored in digital form may become incorrect after the lapse of an indeterminate time. If the memory section always instructs the varactor control circuit to apply a certain voltage to the varactor or to the multiple varactors according to the initial setting memorized in the memory circuit, the receiver might eventually be tuned to a frequency different from the desired channel. The difference would become increasingly apparent as fuzziness of image or perhaps distortion of sound. Accordingly, the aforesaid U.S. Pat. No. 4,085,371 defines an AFT circuit that begins to operate when the frequency to which the tuner is set is within a certain range of the exact frequency for a channel. The range may be, for example ±1.2 MHz. This range is further divided into a sub-range just above the exact desired frequency and extending out to +1.2MHz above the desired frequency and another sub-range that extends from the desired frequency to a frequency lower by 1.2 MHz. If the tuner is operating so that the carrier of the received signal falls within the upper sub-range, the AFT circuit applies pulse signals to adjust the tuning downwardly to the desired frequency. Conversely, if the carrier of the received signal is in the lower sub-range, a different signal is applied from the AFT circuit to shift the tuning upwardly to the desired frequency.
While the tuner has been referred to as being "set" at a frequency, that is somewhat incorrect; it is to be understood that the setting may be changing virtually continuously as the tuner is adjusted from one desired frequency to another. For example, if the tuner is set to receive channel 2 and the user decides to switch to channel 5, the tuner will be required to leave the proper setting for channel 2, pass through the upper sub-range of that channel, and pass through the lower and upper sub-ranges associated with channels 3 and 4 in succession in order to reach the lower sub-range and then the desired precise frequency of channel 5. The effect of the AFT circuit must be overcome in order to keep the voltage produced by the AFT circuit from locking the tuner at the frequency of channel 2 or the frequencies of channels 3 and 4.
It is a principal object of the present invention to provide a digital tuner having a control circuit that will, at all times, be capable of supplying an AFT control signal to effect both upward and downward tuning within a certain range of frequencies adjacent received frequencies, the control circuit further including means to supply signals to overcome the effect of the AFT signal.
It is a further object of the invention to generate the AFT control signal as pulses at a repetition rate lower than the repetition rate of the pulses supplied to effect deliberate shifting of the operating frequency of the tuner.
Further objects will become apparent from the following specification together with the related drawings.
In accordance with the present invention pulses are generated and are connected through a control circuit to a reference control counter to cause the counter either to count up or down. The digital output signal of the counter is applied to a digital-to-analog (D/A) converter that converts the digital count into an analog signal. This analog signal is applied to an electronic tuner to adjust voltage controlled means, such as one or more varactors therein, to determine the frequency to which the tuner is adjusted. This frequency may shift from instant to instant as the count in the counter changes either up or down.
An AFT circuit, which may include a frequency discriminator, is connected to the output of the tuner or to an intermediate frequency amplifier of the type that commonly follows the tuner in a cascade connection therewith. The AFT circuit is arranged to operate only within a certain band of frequencies. The center of this band is the carrier frequency of the signal applied to the AFT circuit. When the carrier of an incoming signal is in an upper sub-range above the center frequency of the discriminator, the AFT circuit generates a logic signal at the down-counting output terminal of the AFT circuit to effect downward tuning. When the carrier of the received signal at the input of the AFT circuit is in a lower sub-range below the desired frequency, the AFT circuit generates a logic signal at its up-counting output terminal to effect upward tuning of the electronic tuner.
The counter circuit is controlled by pulses received from a control circuit. These pulses may be applied either to the up-counting or the down-counting input circuit of the counter. Between the pulse generator and the up-counting and down-counting input terminals are two AND circuits, each connected in cascade with a respective OR circuit. The AND circuits are controlled, respectively, by logic signals which, in turn, are controlled by actuation of an up-counting or down-counting switch. The pulse signals applied from the pulse generator pass through one AND circuit to its associated OR circuit to the up-counting terminal when the switch to effect up-counting is actuated to enable that AND circuit. Conversely, signals from the pulse generator pass through the other AND circuit and its associated OR circuit to the down-counting terminal of the counter when the down-counting switch is actuated to enable the latter AND circuit.
Two other AND circuits have their output terminals connected to second input terminals of the aforementioned OR circuits, respectively. One of the latter AND circuits is connected to the down-counting output terminal of the AFT circuit to receive the logic signal therefrom to enable that AND circuit when the input signal to the AFT circuit is in the upper sub-range. Conversely, the other of the latter two AND circuits has an input terminal connected to the up-counting output terminal of the AFT circuit to be enabled by the logic signal therefrom when the frequency of the signal applied to the input of the AFT circuit is in the lower sub-range.
The other input terminal of the latter two AND circuits is connected to receive pulses from the pulse generator. However, in accordance with this invention, between the pulse generator and the latter two AND circuits is a frequency divider so that the pulses applied to the latter two AND circuits are at a sub-multiple frequency of the signals applied to the first two AND circuits. As a result, although the AFT circuit is constantly operating and supplies either an up-counting logic signal or a down-counting logic signal when the signal applied to its input is in the appropriate range, the resulting AFT pulses that attempt to bring the counter to a specific count value or to hold it at that count value will not be able to do so because the pulses that reach the counter by deliberate actuation of either the up-counting control switch or the down-counting control switch have a higher frequency that changes the count of the counter faster than the count can be pulled back to a previous condition.
FIG. 1 is a block diagram illustrating a channel selecting apparatus with AFT.
FIG. 2 is a block diagram illustrating, in greater detail, an up-down counter for generating channel identifying codes and a memory which are included in the apparatus of FIG. 1.
FIG. 3 is a detail block diagram of a pulse-width modulator which is included in the apparatus shown in FIG. 1.
FIGS. 4A-4E are waveform diagrams to which reference will be made in explaining the operation of the channel selecting apparatus of FIG. 1.
FIG. 5 is a schematic circuit diagram showing a portion of an automatic fine tuning circuit that is included in the apparatus according to this invention.
FIGS. 6A-6C and FIGS. 7A-7I are waveform diagrams to which reference will be made in explaining the automatic fine tuning operation of the channel selecting apparatus according to this invention.
FIG. 8 is a block diagram illustrating channel selecting apparatus according to this invention to overcome the effect of AFT when deliberately tuning from one channel to another.
FIGS. 9A and 9B are waveform diagrams illustrating AFT logic signals for effecting up-tuning and down-tuning, respectively.
FIG. 1 is a block diagram of a channel selecting circuit as claimed in the aforesaid companion case Ser. No. 716,654 but will be described here as an especially useful introduction to the present invention. It comprises a generator 10 of a clock pulse A o which is applied to a timing counter 20 for producing a circulating digital, or binary, code A 1 , A 2 , A 3 ---A 14 . A manually controllable sweep pulse generating circuit 30 is provided to produce either up-tuning pulses P U or down-tuning pulses P D to corresponding terminals of an up-down counter 40. In the programming mode of the apparatus, the counter 40 counts the pulses P U or P D to establish channel identification digital codes B 1 , B 2 , B 3 ---B 14 corresponding to the changing counts of the counter 40. These codes are recorded, or stored, at selected addresses in a memory 50.
Further, the channel selecting apparatus shown in FIG. 1 generally comprises a memory control circuit 60 for selectively establishing the programming mode of operation or a channel selecting mode of operation in which a channel identification digital code previously stored at a selected address in memory 50 is read out therefrom, as indicated at C 1 , C 2 , C 3 ---C 14 , and applied to counter 40 to establish the corresponding count in the latter. A manually controllable address selecting circuit 70 is provided for activating a selected address in the memory 50 for either recording a selected channel identification code or reading out a previously stored channel identification code from that address during the programming or channel selecting modes, respectively. A band-indicating signal-forming circuit 80 which, in the programming mode of operation, produces a signal indicating the band of the channel indicating code then being stored at a selected address of memory 50, with such band indicating signal also being stored at the respective address.
The channel selecting apparatus shown in FIG. 1 also generally comprises a D/A converter 90 that provides an analog control voltage for the varactor of a selected band in an electronic tuner 100. The analog control voltage corresponds to the count of the counter 40 as established by a channel identification digital code selectively read out of the memory 50 in the channel selecting mode of the apparatus. In the programming mode the analog voltage corresponds to the changing counts produced by the counter 40 when the latter counts tuning pulses from the generating circuit 30. A video intermediate frequency amplifier 110 receives the output of the tuner 100 and has its own output applied to a conventional video detector circuit as in the usual color television receiver.
The output of the video intermediate frequency amplifier 110 is also applied to an automatic fine tuning (AFT) circuit 120 which includes a frequency discriminator that responds to a video carrier wave in the output of the IF amplifier 110 to produce AFT logic signals from up-counting and down-counting outputs E U and E D . These logic signals are produced when the channel identification code then being applied to the converter 90 for establishing a receiving frequency in the channel selecting mode of the apparatus has to be modified upwardly or downwardly, respectively, for attaining precisely the correct receiving frequency for the respective channel. The discriminated outputs E U and E D are applied to the sweep pulse generating circuit 30. As will be hereinafter described in detail, the circuit 30 responds to the discriminated output E U or E D to provide tuning pulses to be counted by the counter 40 for modifying the channel identifying code applied therefrom to the converter 90 to obtain precisely the correct receiving frequency, that is, for achieving the desired AFT operation.
Further, a memory rewriting circuit 130 is provided in the channel selecting apparatus. As will be hereinafter described in detail, when the extent to which the channel identification code being read out of a selected address in the memory 50 to the counter 40 has to be modified to obtain the correct receiving frequency for the respective channel exceeds a predetermined amount, the rewriting circuit causes the writing of the modified channel identifying code at the selected address in place of the code originally stored thereat. In this way, the memory rewriting circuit 130 ensures that the channel identification codes stored in the memory 50 will not, in time, result in respective receiving frequencies that are outside the pull-in range of the AFT operation. Finally, the channel selecting apparatus comprises an AFT inhibit circuit 140 which is effective, as will be hereinafter described in detail, to prevent the AFT operation during the initial application of power to the apparatus and during operation of the address selecting circuit 70.
In the channel selecting apparatus as generally described above, the clock pulse A o from the generator 10 may have a frequency of, for example, 4 MHz resulting in a period τ of 0.25 μsec. In the timing counter 20, the clock pulse A o is counted to produce pulses A 1 , A 2 , A 3 ---A 14 which are frequency-divided in sequence so as to range from pulses A 1 that have a period of 0.5 μsec. and a pulse width of 0.25 μsec., to pulses A 14 that have a period of 4.096 m.sec. and a pulse width of 2.048 m.sec. The pulses A 1 , A 2 , A 3 ---A 14 form a 14-bit circulating digital code which changes its state 2 14 times, that is, 16,384 times, within the circulating or repeating period of T = 2 14 τ = 4.096 m. sec. (FIGS. 4A and B).
In the pulse generating circuit 30 as shown in FIG. 1, a fine up-tuning switch 31FU, a fine down-tuning switch 31FD, a coarse up-tuning switch 31CU and a coarse down-tuning switch 31CD are connected in series with respective resistors 32 1 , 32 2 , 32 3 and 32 4 , and such series circuits are connected in parallel between a voltage source +5V and ground. The switches 31FU, 31FD, 31CU and 31CD are normally open, as shown, to provide logic signals at the high logic level "1" at the junctions of such switches with the respective resistors 32 1 , 32 2 , 32 3 and 32 4 and the input terminals of inverters 33 1 , 33 2 , 33 3 and 33 4 . When any of the switches 31FU, 31FD, 31CU and 31CD are closed, a logic signal at the low logic level "0" is applied to the input terminals of the respective inverters 33 1 , 33 2 , 33 3 and 33 4 . The "1" or "0" logic controlled by the switches 31FU, 31FD, 31CU and 31DC are inverted by the corresponding inverters to first input terminals of NAND circuits 34 1 , 34 2 , 34 3 and 34 4 , respectively. The pulses A 14 having a period of 4.096 m. sec. are applied from the timing counter 20, as coarse tuning pulses, to second inputs of the NAND circuits 34 3 and 34 4 . The pulses A 14 are also applied to a frequency divider 35 to be divided, for example, by 64, to provide fine tuning pulses having a period of 262.144 m. sec., and such fine tuning pulses are applied to second inputs of the NAND circuits 34 1 and 34 2 .
The "1" or "0" logic signals controlled by the switches 31FU, 31FD, 31CU and 31CD are also all applied to a AND circuit 36 which has its output terminal connected through an inverter 37 to NAND circuits 38 1 and 38 2 . Each of the NAND circuits 38 1 and 38 2 also has the fine tuning pulses from the frequency divider 35 applied to it. Further, the separate outputs E U and E D from the AFT circuit 120 are applied to inverters 39 1 and 39 2 , respectively, which have their outputs applied to the NAND circuits 38 1 and 38 2 , respectively. The outputs of the NAND circuits 34 1 and 38 1 are applied to a NAND circuit 301, while the outputs of the NAND circuits 34 2 and 38 2 are similarly applied to a NAND circuit 302. The output of the NAND circuit 301 is applied through an inverter 303 to a NAND circuit 304 which also receives the output of NAND circuit 34 3 directly. The output of the NAND circuit 302 is similarly applied through an inverter 305 to a NAND circuit 306 which also receives the output of the NAND circuit 34 4 . The outputs of the NAND circuits 304 and 306 are respectively applied to the NAND circuits 308 and 309, each of which also receives an AFT inhibit pulse P G from circuit 140, and the outputs of the NAND circuits 308 and 309 are applied as up-tuning pulses P U and down-tuning pulses P D , respectively, to the counter 40. Further, the outputs of the NAND circuits 308 and 309 are connected to an OR circuit 310 for providing pulses P UD to the memory rewriting circuit 130.
As shown schematically in FIG. 2, the counter 40 may be a conventional 14-bit up-down counter having 14 flip-flops 41 1 , 42 2 ---41 14 which have their states of conductivity changed sequentially to effect up or down counting in response to the pulses P U or P D , respectively, to establish, at the end of a counting interval, the respective bits of sequentially changing 14-bit channel identification codes B 1 , B 2 ---B 14 . In the programming mode of operation, the channel identification codes are applied from the counter 40 to the memory 50 for writing or storage of a selected one of such codes at a selectively activated address in the memory. Simultaneously, the sequentially changing channel identification codes are also applied from the counter 40 to the digital-to-analog converter 90 to provide a correspondingly varied control voltage for the varactor in a selected band of the electronic tuner 100. The flip-flops 41 1 ---41 14 of the counter 40 are further adapted, in the channel selecting mode of operation, to have their respective states established by the respective bits C 1 -C 14 of a memorized channel identification code which are read out of a selectively activated address in the memory 50 to the AND circuits 42 1 -42 14 which also receive a load pulse P B during the channel selecting operation for passing the bits read out of the memory, as hereinafter described in detail, and which have their outputs respectively connected to the flip-flops 41 1 -41 14 , respectively.
As also shown in FIG. 2, the memory 50 may be made up of 16 memory units 51 1 , 51 2 ---51 16 at respective addresses in the memory 50, with the memory unit at each address being capable of storing 16 bits of digital information, that is, the 14 bits of a selected channel identification code from the counter 40 and 2-bits from an encoder 52 for the band indicating signal received from the circuit 80 for indicating whether the channel identified by the 14-bit digital code being stored at the respective address is a vhf or uhf channel, and, if it is a vhf channel, whether it is a low channel or a high channel in such broadcast band, respectively. Further, the memory 50 is schematically shown to include a decoder 53 which, in the programming and channel selecting modes of operation, receives the 2-bits of digital information representing the band of the channels identified by the 14-bit codes being applied to, or read out from, respectively, the memory units for providing a corresponding band identification signal applied to the electronic tuner 100 for selecting the corresponding band of the latter. Finally, the memory 50 also includes a decoder 54 which receives a 4-bit digital code from the address selecting circuit 70, as hereinafter described in detail. The 4-bit code is effective to activate or address the corresponding one of the memory units 51 1 , 51 2 ---51 16 . Preferably, the memory units of memory 50 are composed of non-volatile cells, such as, metal-nitride-oxide-silicon (MNOS) elements, so that the contents thereof, while being electrically alterable, are held unchanged during periods when the memory 50 is disconnected from a source of power.
Returning again to FIG. 1, it will be seen that the memory control 60 includes a mode change-over switch 61 having a movable contact that is manually actuable to engage fixed contacts a and b, selectively. The fixed contact a is connected to a voltage source +5V so that, when the movable contact of switch 61 engages the fixed contact a to establish the programming mode of operation, a signal P A at the high logic level "1" is obtained from switch 61. On the other hand, the fixed contact b of switch 61 is connected to ground so that, when the movable contact of switch 61 is engaged with the fixed contact b for establishing the channel selecting mode of operation, the signal P A is at the low logic level "0". The memory control 60 also has a normally open switch 62 which is connected in series with a resistor 62a between a voltage source +5V and ground. The signal P A from the mode change-over switch 61 is shown to be applied to one input of a NAND circuit 63 which has its other input connected through an inverter 64 with a junction in the connection between the switch 62 and resistor 62a. It will be apparent that, when the switch 62 is in its normally open position, as shown, the output of the inverter 64 will be at the low level "0", whereas, when the switch 62 is manually closed to effect a writing operation with the apparatus in its programming mode, the output of the inverter 64 will be at the high level "1". The output of the NAND circuit 63 is shown to be applied to a NAND circuit 66 along with a rewrite instruction signal P M from the circuit 130, and the output of the NAND circuit 66 is applied through an inverter 67 to an instruction signal forming circuit 65. When the output of the NAND circuit 63 or the instruction signal P M is at the low level "0", the circuit 65 supplies an erasing pulse P E and then a writing pulse P WR to the memory unit at a selected address in the memory 50 so as to erase the previously stored contents in such memory unit and, thereafter, to write in the selected memory unit the 14-bit channel identification code then being received from the counter 40 and the 2-bit code which represents the band of the channel identified by the code being written in the respective memory unit. On the other hand, when the output of the NAND circuit 63 or the instruction signal P M is at the high level "1", the instruction signal forming circuit 65 applies a read pulse P T to the memory unit 50 to read out the contents stored in the selected memory unit.
The band indicating signal forming circuit 80 is shown to include normally open switches S L , S H and S U which are connected in series with respective resistors 81 L , 81 H and 81 U between a voltage source +5V and ground. Junctions between switches S L , S H and S U and the respective resistors are connected to inverters 82 L , 82 H and 82 U , respectively, which have their outputs connected to first inputs of NAND circuits 83 L , 83 H and 83 U , respectively, while the second inputs of such NAND circuits receive the signal P A from the mode change-over switch 61. The outputs of the NAND circuits 83 L , 83 H and 83 U are applied to a band memory 84 which is effective to apply a band indicating signal P L , P H or P U to the encoder 52 in the memory 50 in response to a low level or "0" output from the NAND circuit 83 L , 83 H or 83 U , respectively. It will be apparent that, in the programming mode of operation established by engagement of the switch 61 with its fixed contact a to provide the signal P A with the high value "1", the output of any of the NAND circuit 83 L , 83 H or 83 U has the low value "0" only when the respective switch S L , S H or S U is manually closed to indicate that the channel identified by the 14-bit code to be written at a selected address in memory 50 is a low vhf channel, a high vhf channel or a uhf channel, respectively.
The address selecting circuit 70 of the illustrated channel selecting apparatus according to this invention includes 16 normally open address selecting switches S 1 , S 2 ---S 16 which are each selectively manually actuable to the closed condition for selecting a corresponding one of the 16 addresses or memory units in memory 50 to be activated during a programming operation or channel selecting operation of the apparatus. The address selecting circuit 70 is further shown to include neon tubes or other indicators N 1 , N 2 ---N 16 corresponding to the switches S 1 , S 2 ---S 16 , and address counter 71 which, in response to the closing of a selected one of the switches S 1 -S 16 , produces a corresponding 4-bit addressing code applied to the decoder 54 in the memory 50 for addressing the corresponding memory unit in the latter, and a decoder 72 which receives the coded output of the address counter 71 and, in response thereto, provides a "0" output signal on a respective one of 16 output lines L 1 , L 2 ---L 16 . The switches S 1 -S 16 are connected, at one side, in common, through series resistors 73 and 74 to ground, while the opposide sides of switches S 1 -S 16 are connected to lines L 1 -L 16 , respectively. Further, the lines L 1 -L 16 are connected through resistors 75 1 -75 16 , respectively, and a common resistor 76a with a voltage source +100V, while the neon tubes, or indicators, N 1 -N 16 are connected between the lines L 1 -L 16 , respectively, and the same voltage source +100V through a common resistor 76b. The junction between the series-connected resistors 73 and 74 is connected to the base electrode of a switching transistor 77 having its emitter electrode connected to ground and its collector electrode connected to a voltage source +V cc and to an inverter 78. The output of the inverter 78 is connected to one input of a NAND circuit 79 which, at its other input, receives the pulses A 9 produced by timing counter 20 and having a period of 0.128 m.sec. Finally, the output of the NAND circuit 79 is applied to the address counter 71 which is operative to count each "0" output of the NAND circuit 79.
In order to provide the load pulse P B to the AND circuits 42 1 -42 14 of the counter 40 to read out to the latter the channel identifying code C 1 -C 14 stored in a selected memory unit of memory 50 in the channel selecting mode of operation, an inverter 43 is included. This inverter receives the signal P A from the memory control 60 and has its output connected to one of the inputs of a NAND circuit 44. The other input of the NAND circuit 44 is connected to the output of a monostable multivibrator 45 triggered by a high collector output representing a logical "1" from the transistor 77 or from a transistor 46 of a time constant circuit 47. The output of the NAND circuit 44 is connected through an inverter 48 to AND circuits 42 1 -42 14 of the counter 40. The load pulse P B is produced when the output of the NAND circuit 44 is "0", that is, when the signal P A has the value "0" for the channel selecting mode of operation and the monostable multivibrator 45 is triggered to produce a pulse having the value "1" for a predetermined period of, for example, 50 m.sec. In the time constant circuit 47, the base electrode of the transistor 46 is connected between a capacitor 46a and a resistor 46b which are connected, in series, between the voltage source +V cc and ground, while the collector of transistor 46 is connected through a resistor 46c with the voltage source and the emitter electrode of transistor 46 is connected to ground. Therefore, when the apparatus is initially connected to a power source, the transistor 46 is made conductive and, hence its collector output is "0". After a predetermined lapse of time, for example 50 m.sec., the transistor 46 is turned off so that its collector output rises to the value "1" for triggering the monostable multivibrator 45 which then provides its output for the predetermined additional time of 50 m.sec.
The digital-to-analog converter 90 preferably includes a pulse-width modulator 91 operative to produce a chain of pulses at a predetermined repetition rate with the width of each of such pulses being dependent on the channel identifying code B 1 , B 2 ---B 14 obtained from the counter 40 either in response to the counting by the latter of the tuning pulses from the generating circuit 30 or in response to the read out of a channel identifying code stored at a selected address in the memory 50, and a low pass filter 92 which receives the chain of pulses from the modulator 91 to provide the analog control voltage for a varactor of the electronic tuner 100 in dependence on the modulated width of the pulses. More particularly, the pulse-width modulator 91 determines the pulse width of the chain of pulses applied to the low pass filter 92 in dependence on the absence of coincidence between the channel identifying code B 1 , B 2 ---B 14 obtained from the counter 40 and the circulating digital code A 1 , A 2 ---A 14 applied to the modulator 91 from the timing counter 20.
As shown in FIG. 3, the pulse-width modulator 90 includes 14 exclusive OR circuits 901, 902---914, each having first and second inputs which respectively receive the bits or pulses A 1 , A 2 ---A 14 of the circulating code and the bits B 1 , B 2 ---B 14 of the channel identifying code. The outputs of all of the exclusive OR circuits 901-914 are applied through an OR circuit 93 to the reset terminal R of a flip-flop 94 which has the pulse A 14 with a period of 4.096 m.sec. applied from timing counter 20 to the set terminal S of flip-flop 94. The flip-flop 94 is adapted to be set by the falling edge or side of each pulse A 14 so as to provide an output of value "1" at its output terminal Q, that is, to initiate an output pulse P W . The flip-flop 94 is reset to terminate the output pulse P W , that is, to return the output voltage to "0", in response to the falling edge or side of an output P O from the OR circuit 93.
As is apparent from FIGS. 4B-4E, an output pulse P W is initiated at the output Q of flip-flop 94 when the circulating code A 1 , A 2 ---A 14 returns from the state (11111111111111) to the state (00000000000000). So long as the circulating code A 1 , A 2 ---A 14 is not coincident in level with the channel identification code then being applied to pulse-width modulator 91, one or more of the exclusive OR circuits 901-914 produces an output "1" with the result that the output P O of the OR circuit 93 remains at the level "1" (FIG. 4B). Upon the coincidence of all buts of the circulating code A 1 , A 2 ---A 14 with the corresponding bits of the channel identification code B 1 , B 2 ---B 14 , which may occur at any count during each circulating period T of the circulating code, the outputs of all of the exclusive OR circuits 901-914 attain the value "0", with the result that the output P O of the OR circuit 93 falls from the value "1" to the value "0" so as to reset the flip-flop 94 and thereby return the output of the latter to the value "0". Thus, during each circulating period T of the circulating code A 1 , A 2 ---A 14 from the timing counter 20, an output pulse P W , that is, an output of the value "1", is obtained from the flip-flop 94 during the time interval between the return of the circulating code A 1 , A 2 ---A 14 from the state (11111111111111) to the state (00000000000000) and the coincidence of the circulating code with the channel identifying code B 1 , B 2 ---B 14 . Therefore, when a change is effected in the channel identification code B 1 , B 2 ---B 14 being applied to the pulse-width modulator 91, a corresponding change occurs in the width of the output pulse P w obtained from modulator 91 during each circulating period of the circulating code.
For example, as shown in the left-hand portions of FIGS. 4A-4E, if the channel identifying code B 1 , B 2 ---B 14 applied to pulse-width modulator 91 is (00000000000001) the output pulse P W produced during each circulating period of the circulating code A 1 , A 2 ---A 14 commences at the beginning of the circulating period, that is, when the circulating code returns from the state (11111111111111) to the state (00000000000000), and each such output pulse P W terminates at the commencement of the first pulse A 1 , at which time the circulating code (00000000000000) coincides with the received channel identifying code (00000000000001) to cause the output P O of the OR circuit 93 to fall from "1" to "0". Thus, the output pulse P W produced during each circulating period of the circulating code has a pulse width of τ. On the other hand, as shown in the middle portion of FIGS. 4A-4E, if the channel identifying code B 1 ,B 2 ---B 14 being received by the pulse-width modulator 91 is (00000000000010), the coincidence of that channel identification code with the circulating code A 1 ,A 2 ---A 14 occurs, during each circulating period of the circulating code, at the commencement of the pulse A 2 , so that the resulting output pulse P W obtained during each circulating period has a width of 2τ. Similarly, as shown at the right-hand portions of FIGS. 4A-4E, if the channel identification code B 1 ,B 2 ---B 14 received by the modulator 91 is (00000000000011), the coincidence of such channel identification code with the circulating code A 1 ,A 2 ---A 14 during each circulating period of the latter occurs at the commencement of the pulse A 1 appearing during the existence of the first pulse A 2 so that the resulting output pulse P W obtained during each circulating period has a pulse-width 3τ.
Thus, the output pulses P W produced by the modulator 91 during the successive circulating periods T of the circulating code A 1 , A 2 ---A 14 have their pulse-widths determined by the channel identification code B 1 , B 2 ---B 14 then being received by the modulator, and the low pass filter 92 is effective to smooth such output pulses P W from the modulator 91 and to deliver an analog or DC voltage having a value that corresponds to the switch of the pulses P W .
In the electronic tuner 100 a signal V H , V L or U received from the decoder 53 of the memory 50 selects either the high band or the low band of a vhf tuning section or the uhf tuning section, respectively, for operation. The frequency to be received is determined by the voltage controlled variable reactance element or varactor, such as a variable capacitance diode, of the selected tuning section. The voltage controlled element, in turn, is controlled by the analog, or DC, control voltage from the low pass filter 92, which is applied to the video intermediate frequency amplifier circuit 110.
The AFT circuit 120 is shown in more detail in FIG. 5. The AFT circuit comprises a conventional frequency discriminator circuit 121 which is connected to the output of the video IF amplifier 110 and provides an AFT voltage V T . As shown in FIG. 6A, the AFT voltage V T has a predetermined value V o when the video intermediate frequency f has the correct value f o , and the AFT voltage V T varies from the value V o in accordance with a generally S-shaped curve for values of the video intermediate frequency above and below the value f o . The AFT circuit 120 also comprises transistors 122A and 122B constituting a first differential amplifier, and transistors 123A and 123B constituting a second differential amplifier. Reference voltages V 1 and V 2 having values to satisfy the inequality V 1 > V o > V 2 are respectively applied to the base electrodes of the transistors 122A and 123A, while the AFT voltage V T from the circuit 121 is applied to the base electrodes of the transistors 122B and 123B. Further, the collector outputs of the transistors 122B and 123B are applied to the base electrodes of the transistors 124 and 125, respectively, and the collector output of the transistor 124 is applied, in turn, to the base electrode of a transistor 126. Finally, the collector output of the transistor 126 is delivered through a diode 127 to an output terminal 128U to provide the discriminated output E U at the latter, and the collector output of the transistor 125 is delivered through a diode 129 to an output terminal 128D to provide the discriminated output E D at the latter.
When the AFT voltage V T is larger than the reference voltage V 1 , that is, when the video intermediate frequency from amplifier 110 is less than (f o - Δf), transistors 122A and 122B are respectively non-conductive and conductive. Therefore, transistor 124 is non-conductive and the transistor 126 is conductive. As a result, the output voltage E U is "0", as shown in FIG. 6B. On the other hand, transistor 123B is conductive, which causes the transistor 125 to be non-conductive, so that the output voltage E D is "1", as shown in FIG. 6C.
If the video intermediate frequency from amplifier 110 is in the range between the frequencies (f o -Δf) and (f o + Δf), that is, within the proper tuning range, the AFT voltage from the circuit 121 is between V 1 and V 2 and, therefore, the transistor 123B remains conductive and the output E D continues to be "1". However, with V T being less than V 1 , the transistor 122B is non-conductive and, as a result, the transistor 126 is made non-conductive so that the output E U becomes "1".
Finally, when the AFT voltage V T from the frequency discriminating circuit 121 is less than V 2 , that is, when the video intermediate frequency from the amplifier 110 is greater than (f o + Δf), the output E U remains "1", but the transistor 123B becomes non-conductive, which makes the transistor 125 conductive, and as a result, the output E D becomes "0".
In the case of a channel selecting apparatus for a color television receiver, the reference voltages V 1 and V 2 of the AFT circuit 120 are suitably selected so that Δf will be about 50 kHz. In the correctly tuned condition, that is, when the frequency f is in the range between f o -50 kHz, the outputs E U and E D are both "1" and no correction is to be made in the binary code B 1 , B 2 ---B 14 applied to pulse width modulator 91 which determines the local oscillation frequency established in tuner 100. On the other hand, when f is less than f o -50 kHz, the resulting "0" state of discriminated output E U is effective to cause the pulse generating circuit 30 (FIG. 1) to provide up-tuning correction pulses which are counted by the counter 40 to modify the binary code B 1 , B 2 ---B 14 so as to raise the local oscillation frequency and thereby bring the receiver to the correctly tuned condition. Conversely, if the frequency f is greater than f o +50 kHz, the resulting "0" state of the output E D is effective, in the pulse generating circuit 30 to cause down-tuning correction pulses to be applied to the counter 40 so that the binary code B 1 , B 2 ---B 14 being applied from the counter 40 to the pulse width modulator 91 is modified to decrease the local oscillation frequency and thereby achieve the correctly tuned condition of the receiver. The upward-tuning and down-tuning pulses applied to the counter 40 in response to the "0" states of the AFT outputs E U and E D , respectively, are the fine tuning pulses from the frequency divider 35.
More particularly, reference to FIG. 1 will show that, when the output E U is "0", up-tuning pulses having the period of the fine tuning pulses from the frequency divider 35 are applied to the counter 40 by way of the circuit constituted by the inverter 39 1 , NAND circuits 38 1 and 301, inverter 303, and NAND circuits 304 and 308. On the other hand, when the output E D is "0", down-tuning pulses also having the period of the tine tuning pulses from the frequency divider 35 are applied to the counter 40 through the circuit constituted by the inverter 39 2 , NAND circuits 38 2 and 302, inverter 305, and NAND circuits 306 and 309. When any one of the switches 31FU, 31FD, 31CU and 31CD is manually closed, supplying up-tuning pulses or down-tuning pulses to the counter 40 from the circuit 30 in response to the closing of such switch is preferential. That is, the resulting signal applied to each of the NAND circuits 38 1 and 38 2 through the NAND circuit 36 and inverter 37 prevents the passage of any correction pulse through the NAND circuit 38 1 or 38 2 even though the output E U or E D may then be "0".
In order to inhibit or prevent the AFT operation of the channel selecting apparatus according to this invention during the operation of the address selecting circuit 70 for activating a selected one of the addresses or memory units in the memory 50 in a programming or channel selecting mode of the apparatus, the AFT inhibiting circuit 140 includes a NAND circuit 141 receiving the collector outputs of the transistors 46 and 77, a monostable multivibrator 142 which is triggered by the rising edge of the output from the NAND circuit 141, as shown in FIG. 7A to produce a positive pulse M 1 shown in FIG. 7B. The pulse M 1 has a width of, for example, 10 m.sec. The pulse M 1 is further applied to an inverter 143 to produce a negative inhibiting pulse P G shown in FIG. 7C. As previously mentioned, the pulse P G is applied to the NAND circuits 308 and 309 of the pulse generating circuit 30. Thus, during the existence or occurrence of the negative inhibit pulse P G , neither up-tuning nor down-tuning pulses can pass through the respective NAND circuit 308 or 309 to the counter 40.
The memory rewriting circuit 130 comprises a monostable multivibrator 131 which is triggered by the falling edge of an output M 1 pulse from the monostable multivibrator 142 to produce an output pulse M 2 , as shown in FIG. 7D. The falling edge of the pulse M 2 triggers a monostable multivibrator 132 to produce an output pulse M 3 , as shown in FIG. 7E and resets a counter 133. The up-tuning and down-tuning pulses P UD applied by the circuit 30 to the counter 40 are also applied through an OR circuit 310 to a NAND circuit 134 which also has applied thereto the output pulse M 2 of the monostable multivibrator 131. Further, the signal P A from the mode changeover switch 61 of the memory control circuit 60 is applied through an inverter 135 to the NAND circuit 134. Thus, the up-tuning and down-tuning pulses P UD are passed through the NAND circuit 134 to be counted by the counter 133 only upon the occurrence of the output pulse M 2 . This occurs when the inhibit pulse P G has been terminated to indicate that the operation of the address selecting circuit 70 for activating one of the memory units or addresses of the memory 50 has been completed, and further, only when the mode change-over switch 61 engages its fixed contact b to provide the signal or output P A with the value "0" for establishing the channel selecting mode of operation of the apparatus.
After each operation of the address selecting circuit 70 with the apparatus in its channel selecting mode so that the channel identifying code stored at the selected address of the memory 50 is read out to the counter 40 and the latter applies the corresponding binary code B 1 , B 2 ---B 14 to the pulse width modulator 91 to establish a respective receiving frequency, any operation of the AFT circuit 120 to cause circuit 30 to apply up-tuning or down-tuning pulses to the counter 40 for modifying the code B 1 , B 2 ---B 14 so as to obtain the correctly tuned condition also causes such up-tuning or down-tuning pulses to be counted by the counter 133. In the memory rewriting circuit 130, a decoder 136 is associated with the counter 133 and is operative, when the counter 133, after being reset by the rising side of the output pulse M 2 , has counted n upward or downward correcting pulses P UD (FIG. 7F), to provide an output "1" (FIG. 7G) on its output line L n by which a flip-flop 137 is set to provide an output pulse M 4 shown in FIG. 7H. The flip-flop 137 is reset by the falling side of the output pulse M 3 from the monostable multivibrator 132 so as to terminate the output pulse M 4 . Finally, the output pulses M 3 and M 4 are applied to a NAND circuit 138 which provides the rewriting instruction P M having the value "0", as shown in FIG. 7I, during the simultaneous occurrence of output pulses M 3 and M 4 . Application of the rewriting instruction P M to the NAND circuit 66 in the memory control circuit 60 with the apparatus in its channel selecting mode has substantially the same effect as closing the writing switch 62 when the apparatus is in its programming mode. In other words, the application of the rewriting instruction P M to the NAND circuit 66 causes the instruction signal forming circuit 65 to supply an erasing pulse P E and then a writing pulse P WR to the selected memory unit in the memory 50 so as to erase the channel identification code B 1 , B 2 ---B 14 previously stored in that memory unit and to write, in place of such channel identification code, the modified channel identification code which is then established by the counter 40 following the AFT operation. If, for example n+1 correction pulses are applied to the counter 40 in response to an AFT operation for achieving the correctly tuned condition when a channel identification code is read out of a selected one of the memory units of the memory 50, the resulting modified channel identification code is rewritten in the same memory unit in place of the original channel identification code. Of course, if less than n correction pulses are applied to the counter 40 in response to an AFT operation, the flip-flop 137 is not set and, therefore, the rewriting instruction P M is not obtained, with the result that the channel identification code originally written or programmed in the respective memory unit of memory 50 remains unchanged therein.
The above described channel selecting apparatus according to this invention operates as follows.
When it is desired to program the channel selecting apparatus, that is, to store at the various addresses in memory channel identification codes corresponding to various channels that are receivable in the region where the television receiver is located so that, thereafter, such channels can be received or selected merely by actuation of the switches S 1 -S 16 corresponding to the respective addresses, the mode change-over switch 61 is engaged with its fixed contact a for selecting the programming mode of operation. If it is desired, for example, to store at the address or memory unit 51 of the memory 50 a channel identification code corresponding to the receiving frequency for channel "one" in the Tokyo area of Japan, the address selecting switch S 1 is manually closed. Closing switch S 1 makes the transistor 77 in address selecting circuit 70 conductive so that the collector output of that transistor has the value "0". Thus, the output of the inverter 78 becomes "1" with the result that the NAND circuit 79 provides a "0" output on receiving each of the pulses A 9 from the timing counter 20. The address counter 71 counts each of the "0" outputs from the NAND circuit 79. When the resulting 4-bit code from the address counter 71 corresponds to the address or memory unit 51 1 selected by the closing of switch S 1 , the decoder 72 responds to such 4-bit code from address counter 71 to provide a "0" output on the corresponding output line L 1 . In response to such "0" output on line L 1 , transistor 77 is made non-conductive with the result that the output of the NAND circuit 79 remains at "1" and and the address counter 71 ceases counting. Accordingly, the 4-bit code corresponding to the switch S 1 is applied to the memory 50 for selecting or activating the address or memory unit 51 1 corresponding to the switch S 1 .
Since tuning information for channel "one" in the Tokyo area, which is a low vhf channel, is to be programmed in the memory unit 51 1 , the switch S L of the band indicating signal forming circuit 80 is closed to provide an output "1" from the respective inverter 82 L . Since the mode changeover switch 61 is engaged with its fixed contact a, its output P A is "1" and, therefore, the output of the NAND circuit 83 L becomes "0". The band memory 84 responds to such "0" output from the NAND circuit 83 L to provide the band selecting pulse P L which, through the encoder 52 and the decoder 53 of the memory 50, provides the signal V L for selecting the low band or channel of the vhf tuning section in tuner 100.
Having selected the address or memory unit of the memory 50 at which a channel identifying code is to be programmed and the band or section of tuner 100 which is appropriate for the channel to be programmed at the selected address, the pulse generating circuit 30 is made operative, for example, by manually actuating the coarse up-tuning switch 31CU and holding the latter in its closed position. The closing of the switch 31CU causes the associated inverter 33 3 to provide the output "1" to the NAND circuit 34 3 . Therefore, at each "0" state of the pulses A 14 from the timing counter 20, which pulses have a period of 4.096 m.sec., the NAND circuit 34 3 provides an output "1". Since the fine up-tuning switch 31FU is open, the output of its associated inverter 33 1 is "0" and the output of the respective NAND circuit 34 1 is "1". Therefore, the output of the NAND circuit 36 becomes "0" at every "1" output from the NAND circuit 34 3 , that is, at every "0" state of the pulses A 14 . Accordingly, an up-tuning pulse P U appears at the output of the inverter 37 at every "0" state of the pulses A 14 from the timing counter 20. Since such pulses A 14 have a relatively short period of 4.096 m.sec., the pulses P U appearing while the switch 31CU is held in its closed condition may be considered coarse up-tuning pulses which, when being counted by the counter 40, cause relatively rapid changes in the count of this counter. In other words, when counting the coarse up-tuning pules P U from the generating circuit 30, the count of the counter is changed, in sequence, in the upward direction to similarly change the resulting channel identification code B 1 , B 2 ---B 14 obtained from the counter 40 at every circulating period of the circulating code A 1 , A 2 ---A 14 from the timing counter 20, starting from the state (00000000000000), as shown in FIG. 4C. The changing channel identification code from the counter 40 and the circulating code from the timing counter 20 are applied to the pulse-width modulator 91 in the programming mode of operation. Since the circulating code A 1 , A 2 ---A 14 changes at every time τ =0.25 μsec., which is the width of the pulses A 1 , the width of the output pulse P W from the modulator 91 is increased by τ at every circulating period T of the circulating code starting from a pulse width of zero. Thus, so long as the switch 31CU of the pulse generating circuit 30 is held in its closed condition, the channel selecting, or control, voltage from the low pass filter 92 is increased progressively, for example, by about 2 m.V at every period T-4.096 m.sec. of the circulating code, the hence the receiving frequency establishing by tuner 100 increases progressively.
When a video picture being broadcast or transmitted by channel "one" appears on the screen of the television receiver, the coarse up-tuning switch 31CU is released by the operator so as to return to its normal open condition. Upon opening the switch 31CU, the supplying of the coarse up-tuning pulses P U to the counter 40 is terminated so that the counter 40 ceases its counting action and the channel identification code B 1 , B 2 ---B 14 then obtained from the counter 40 determines the approximate value of the receiving frequency of the tuner 100 for the desired channel. Thereafter, the fine up-tuning switch 31FU may be manually actuated and held in its closed condition to provide fine up-tuning pulses P U from the inverter 37, which fine up-tuning pulses have a repetition rate 1/64 of the rate of the coarse up-turning pulses by reason of the divider 35. In counting the fine up-tuning pulses, the counter 40 sequentially changes the resulting channel identification code B 1 , B 2 ---B 14 at every period 64T-262.144 m.sec. Thus, the width of the output pulses P W from pulse-width modulator 91 is increased by τ at every period 64T and, accordingly, the channel selecting or control voltage from low pass filter 92 is increased by about 2 mV at every period 64T for similarly changing the frequency to which the tuner 100 is turned. When the clarity of the picture on the screen of the television receiver indicates that fine tuning has been achieved in respect to the video signal broadcast by the desired channel, the switch 31FU is released to return to its open condition and thereby halt the supplying of the fine up-tuning pulses to the counter 40. Accordingly, the counter 40 stops counting with the resulting channel identification code B 1 , B 2 ---B 14 corresponding to a value of the analog control voltage applied from the D/A converter 90 to the tuner 100 corresponding to a receiving frequency for the fine-tuned reception of channel "one". Of course, in the illustrated embodiment of the invention, after the switch 31CU or the switch 31FU has been selectively closed to bring the received frequency established by the code B 1 , B 2 ---B 14 produced by the counter 40 to within the so-called pull-in range of the AFT circuit 120, the above described AFT operation may be relied upon to modify the code further to obtain the correctly tuned condition for the channel being programmed.
After the correctly tuned condition has been realized, either by selective actuation of the switches 31CU and 31FU, or by a combination of actuation of such switches and the AFT operation, the writing switch 62 is manually closed so that the associated inverter 64 provides the output "1". Since the mode change-over switch 61 remains engaged with its fixed contact a to provide the output P A with the value "1", the NAND circuit 63 provides the output "0". As a result of such "O" output from the NAND circuit 63, the instruction signal forming circuit 65 first supplies an erasing pulse P E to the memory 50 to erase any contents previously stored in the memory unit 51 1 selected by closing of switch S 1 . Then, the circuit 65 applies a writing pulse P WR to the memory unit 51 1 with the result that the channel identification code B 1 , B 2 ---B 14 established by the counter 40 for fine-tuning of channel "one" and the band identifying signal P L from the band memory 84 are then written in the respective cells of the memory unit 51 1 .
Following the programming of the memory unit 51 1 with a channel identification code and a band indicating code corresponding to channel "one", some or all of the other memory units 51 2 -51 16 of memory 50 may be similarly programmed with coded information corresponding to other vhf or uhf channels that are receivable in the region where the television receiver is located.
Although the programming of the channel selecting apparatus according to this invention has been described above as being effected by the sequential closing of the coarse up-tuning switch 31CU and the fine up-tuning switch 31FU, in which case, the coarse or fine up-tuning pulses P U are counted in the upward direction by the counter 40 for progressively increasing the frequency to which the tuner 100 is tuned. It will be apparent that the programming operations can be similarly effected by the successive closing of the coarse down-tuning switch 31DC and the fine down-tuning switch 31FD so that the counter 40 is made to count in the downward direction for progressively decreasing the frequency to which the tuner 100 is tuned. Whether the counter 40 is made to count in the upward direction or in the downward direction is merely dependent upon the relationship of the channel frequency which is to be programmed relative to the frequency of the channel which has been previously programmed and, in each case, the direction in which the counter 40 is made to count is selected so as to minimize the time required for the programming operation.
After the programming of the memory 50 has been completed, as described above, the mode change-over switch 61 is manually actuated to engage its fixed contact b and thereby to provide the output P A with the value "0" for establishing the channel selecting mode of operation for the apparatus. Since the writing switch 62 remains in its open position, the output of the associated inverter 64 is "0" and, accordingly, the NAND circuit 63 provides the output "1" to the instruction signal forming circuit 65 so that the latter supplies the reading pulse P R to the memory 50.
Preferably, when the power source for the channel selecting apparatus is initially turned on, the address counter 71 of address selecting circuit 70 is reset thereby so that the 4-bit code issuing from counter 71 will activate or address the memory unit 51 1 in the memory 50.
When the power source for the channel selecting apparatus is initially turned on, the transistor 46 in the time constant circuit 47 is made conductive so that its collector output is "0" for a predetermined period of, for example, 50 m.sec., whereupon the transistor 46 is made non-conductive and its collector output rises to the value "1". Such rise in the collector output of the transistor 46 triggers the monostable multivibrator 45 to provide an output pulse from the latter at the level "1" for the predetermined time of 50 m. sec. Since the output P A from the mode change-over switch 61 is "0" for the channel selecting mode of operation, the output from inverter 43 is "1" and, therefore, the output from the NAND circuit 44 is "0" for the predetermined time or period of the output pulse from the monostable multivibrator 45. Such "0" output from the NAND circuit 44 causes the inverter 48 to produce the output "1", that is, the load pulse P B for the period of the output pulse from the monostable multivibrator 45. The load pulse P B , when applied to AND circuits 42 1 -42 14 in the counter 40, allows the readout to the counter 40 from the memory unit 51 1 of the channel identification code C 1 , C 2 ---C 24 previously stored therein and which, in the example described above, represents channel "one" in the Tokyo area. At the same time, the band indicating code stored in the respective cells of the memory unit 51 1 is read out from the latter to the decoder 53 so that, in the described example, the signal V L is applied to the tuner 100 for selecting the low band of the vhf tuning section. During the existence of the load pulse P B , the bits C 1 -C 14 of the readout channel identification code are applied to the respective flip-flops 41 1 -41 14 of the counter 40 with the result that these flip-flops assume the states for providing the channel identification code B 1 -B 14 from the counter 40 to the pulse-width modulator 91 which, during programming, was determined to correspond to a control voltage for the tuner 100 suitable for fine tuning of the receiving frequency to that of channel "one". Therefore, upon the initial supplying of power to the channel selecting apparatus, the latter tunes the television receiver for the reception of the channel which has been programmed into the first address or memory unit 51 1 of memory 50.
Thereafter, if it is desired to receive a channel programmed in a memory unit of the memory 50 other than the first address or memory unit 51 1 , for example, if it is desired to receive channel "three" which has been programmed in the second memory unit 51 2 , the switch S 2 of the address selecting circuit 70 is manually closed and, as previously described in connection with the programming mode of operation, the address counter 71 counts the pulses A 9 until the 4-bit code from the address counter 71 addresses the second memory unit 51 2 for causing readout of the channel identification code and band indicating code stored in that memory unit during the programming of channel "three" in the memory unit 51 2 . When the code from the address counter 71 addresses the memory unit corresponding to the closed switch S 2 , the decoder 72 provides the signal "0" on the respective output line L 2 so that the transistor 77 is made non-conductive and its collector output rises from "0" to "1". Such rise in the collector output of the transistor 77 triggers the monostable multivibrator 45 and, as previously described, the output from the monostable multivibrator 45 results in the production of a load pulse P B from the inverter 48. In response to the load pulse P B , the channel identification code being read out of memory unit 51 2 correspondingly changes the states of the flip-flops of the counter 40 so that the latter provides the corresponding channel identification code B 1 , B 2 ---B 14 to the pulse width modulator 91. Therefore, the output pulse P W obtained from the modulator 91 during each circulating period of the circulating code A 1 , A 2 --A 14 has its width determined by the channel identification code so as to result in an analog control voltage from the low pass filter 92 to the tuner 100 sufficient to tune the latter to channel "three".
It will be apparent that the channels programmed in the other memory units 51 3 -51 6 may be similarly selectively received merely by manual closing of the corresponding address selecting switch S 1 -S 16 .
Although the memory 50 is initially programmed with correct channel identification codes B 1 , B 2 ---B 14 to set the varactor of the tuner 100 to the necessary values to tune to the respective channels, a shift from such correctly tuned condition may occur over a period of time due to a temperature drift, annual variation, or the like in the electronic tuning tuner 100. In other words, at some time after the programming of a memory unit in the memory 50 with a channel identification code, the tuner control voltage that results from the application of the programmed code to D/A converter 90 in the channel selecting mode of the apparatus may no longer set the tuner to receive the proper frequency of the respective channel. In that event, the AFT circuit 120 provides an output, E U or E D , according to the drift, to cause the circuit 30 to apply either upward or downward correcting pulses to the counter 40 to modify the channel identification code B 1 , B 2 ---B 14 applied from the counter 40 to the converter 90 increment by increment until the correctly tuned condition is restored.
It should be noted that the foregoing AFT operation in the channel selecting mode of the apparatus id delayed to commence a predetermined time after power is first applied to the apparatus, or after a selected one of the switches S 1 , S 2 ---S 16 is closed for selecting a respective one of the memory units in the memory 50 for readout of the channel identification code stored therein. More particularly, when the power source for the apparatus is initially turned on, or when one of the switches S 1 -S 16 is closed, the resulting collector output of transistor 46 or transistor 77, respectively triggers the monostable multivibrator 142 to provide the inhibit pulse P G for 10 m.sec. During that period of time, the inhibit pulse P G prevents upward or downward correction pulses from reaching the counter 40 even though the AFT circuit may then be providing the output E U or E D . Thus, the onset of the AFT operation is delayed until the address selecting circuit 70 has completed the previously described operations of selecting a memory unit 51, in the memory 50 in response to the initial connection of the apparatus to its power source or in response to the closing of one of switches S 1 -S 16 , and until the control voltage applied to the tuner 100 has attained a level corresponding to the channel identification code being read out of the selected memory unit. The foregoing delay in the onset of the AFT operation avoids the possibility that the AFT operation will seek to pull-in the local oscillation frequency at some region other than the desired normal tuned condition if the AFT operation is permitted when power is first applied to the apparatus or when the circuit 70 is changing over from the selection of one to another of the addresses in the memory 50.
When the AFT operation does occur with the apparatus in its channel selecting mode, the upward or downward correction pulses P UD applied to the counter 40 for modifying the code B 1 , B 2 ---B 14 applied from the latter to the D/A converter 90 to obtain the correctly tuned condition, are also counted by the counter 133. When the number of such upward or downward correction pulses reaches n, that is, when the frequency resulting from the channel identification code stored in the selected memory unit of the memory 50 is at least 50 kHz greater than or less than the local oscillation frequency for the normal or correct tuned condition, but still within the pull-in range of the AFT circuit, the memory rewriting circuit 130 provides the rewriting instruction P M . As previously described, such rewriting instruction causes the modified channel identification code B 1 , B 2 ---B 14 then produced by the counter 40 to be written in the selected memroy unit in place of the channel identification code previously written therein.
By reason of the above described rewriting operation, if the tuner 100 undergoes a progressive change in the relationship between its control varactor voltage and the frequency to which the tuner 100 is set, due to temperature drift, annual variation or the like, each periodic selection of each memory unit for selection of the respective channel causes the AFT operation to provide the correctly tuned condition and, if at any time, such AFT operation approaches the limits of its pull-in range, the code stored in the memory unit is replaced by a new code corresponding to the changed relationship between the control voltage and the actual frequency to which the tuner is tuned. This ensures that the pull-in range of the AFT circuit will not be exceeded.
Although the rewriting operation could be effected each time the channel identification code being read out of a memory unit is modified by the AFT operation, it is preferred that the rewriting operation occur only when the AFT correction exceeds a predetermined amount, as described above, particularly when the memory is composed of non-volatile memory cells, as such cells are, in general, limited as to number of times information can be rewritten therein.
In the illustrated embodiment of the invention, the control of the rewriting or memory refreshing operation is effected by directly counting the correction pulses P D resulting from the AFT operation, and performing the rewriting operation when the number of correction pulses exceeds a predetermined value. However, other means may be employed for controlling the rewriting or memory refreshing operation. For example, a buffer (not shown) may be provided separate from the counter 40 to store the channel identification code being read out of a selected memory unit, whereupon the contents of the counter 40, after the same are modified by an AFT operation, are compared with the contents stored in the buffer to cause the rewriting operation to occur when the compared contents differ from each other by at least a predetermined amount.
Further, the pulse width modulator 91 and the low-pass filter 92 provided in the illustrated embodiment for converting the digital channel identification codes into respective control voltages for the tuner 100 can be replaced by any other D/A converter, for example, consisting of switching elements and weighted resistors for achieving the same result.
It is further to be noted that the present invention avoids a serious problem encountered in effecting AFT operation in connection with an electronically tuned tuner employing a varactor as its tuning element. Such varactors or variable capacitance diodes have non-linear voltage-capacitance characteristics. In other words, as the receiving frequency is increased, progressively increasing changes in the control voltage are required to effect unit or incremental changes in the receiving frequency. Therefore, the change in the control voltage required to effect a predetermined change in the receiving frequency is different for each of the channels. Therefore, in the existing AFT circuits associated with the electronic tuning tuners, the correction or AFT sensitivity has had to be different or changed-over for each of the channels so that the construction of the AFT circuit becomes undesirably complex.
As distinguished form the foregoing in the channel selecting apparatus according to this invention, the AFT circuit 120 merely indicates by its discriminated outputs E U and E D the direction of the necessary change in the control voltage for achieving the correctly tuned condition. Therefore, the AFT operation can be simply and accurately performed in a wholly automatic fashion.
FIG. 8 is a circuit diagram of an electronic tuning system with a digital control circuit for an electronic tuner with AFT to maintain the frequency to which the tuner is tuned at the proper value for the desired channel. Means are provided in FIG. 8 to overcome the effect of the AFT circuit but without disabling or disconnecting that circuit.
In FIG. 1 the electronically tuned tuner 100 is controlled by a tuning voltage developed by the D/A circuit 90. This voltage is indicated in FIG. 8 as V c and is applied as a reverse bias voltage to the one or more variable capacitance diodes, or varactors, that determine the frequency to which the tuner 100 is tuned. The tuner may also be supplied with a band change-over signal in the same manner as the tuner 100 in FIG. 1 so that it can be switched to receive both the high and low channels of the vhf band and the channels in the uhf band. The tuner 100 in FIG. 8 is shown as part of a television receiver that includes the video IF amplifier 110 and a video detector 111, a video amplifier 112 and a cathode ray picture tube 113. The AFT circuit 120 is connected to the output of the IF amplifier 110 in the same manner as in FIG. 1, and the AFT circuit in FIG. 8 may be identical with the AFT circuit described in connection with FIGS. 5 and 6A-6C. A frequency discriminator 121 (FIG. 5) having an input versus output characteristic in the form of an S-shaped curve shown in FIG. 6A, produces an instruction signal E U when the output voltage of the discriminator circuit 121 is above the level V 1 . The AFT circuit also produces an instruction signal E D when the output voltage of the discriminator 121 is below the voltage V 2 . It has been explained originally in connection with FIG. 5 that the effective voltages E U and E D begin when there is a frequency difference Δf of ±50 kHz between the desired center frequency f o and the carrier of the received signal. Since the S-shaped response characteristic drops off after reaching its peak point, either the positive peak or the negative peak, at frequencies sufficiently distant from the frequency f o the output voltage of the discriminator 121 will be less than the voltage V 1 or greater than the voltage V 2 . The characteristic curve of the circuit is arranged so that the outer frequencies at which the AFT voltages are available are approximately ±1.2 mHz. Thus, as shown in FIG. 9, the signal E U has the value "0" below a frequency equal to f o - 1.2 mHz and a value "0" above a frequency f o - 50 kHz. Between the frequencies f o -1.2 mHz and f o -50 kHz, the value of the signal E U is "1".
Conversely, the output voltage of the frequency discriminator 121 in FIG. 5 is lower than the voltage V 2 only in the frequency sub-range between approximately f o +50 kHz and f o +1.2 mHz. At other points outside that sub-range the frequency signal E D has the value "0". These logic signals are illustrated in FIG. 9. It is appropriate to think of the entire AFT band between f o -1.2 mHz and f o +1.2 mHz as being the AFT range within which the AFT circuit 120 operates. This range is divided into one sub-range for the signal E U and another sub-range for the signal E D .
As in FIG. 1, the circuit in FIG. 8 includes a counter 40 for generating channel identification codes and a channel identification code memory 50. The relationship between the counter 40 and the memory 50 is described in detail in connection with FIG. 1.
The circuit also includes an address selecting section 700 that includes the address counter 71 and a decoder 72 in FIG. 1. The circuit 700 is controlled by address section switches S 1 -S N in a manner such as is shown in FIG. 1. In FIG. 1, the number n for the highest numbered switch is 16. The manner in which the switches S 1 -S N and the address selecting section 700 control the channel memory 50 corresponds to the manner in which the code memory 50 in FIG. 1 is controlled by the address counter 71 and the switches S 1 -S 16 and need not be described again in detail.
Briefly, when the receiver is put into use in a given region, certain of the switches S 1 -S N are closed, in turn, and the count is recorded in corresponding sections of the memory 50. According to each of the switches in each memory section the count, when converted into an analog signal by the D/A converter 90 becomes the analog voltage V c to control the tuner 100. Thereafter, each time one of the switches is closed, its particular memory section in the memory 50 is actuated and a count corresponding to the count stored in that memory section is applied to the D/A converter 90 to return the tuner to the desired channel.
The circuit in FIG. 8 further includes a channel memory counter circuit 60 which may be similar to the circuit 60 in FIG. 1 and which is controlled by a mode switch 61 and a writing or programming switch 62 that operates in the same manner as the switches 61 and 62 in FIG. 1. The channel memory counter circuit 60 controls the erasing, writing and reading signals to be applied to the memory 50 in accordance with whether the memory is being programmed (which requires erasure of any previous program at that memory section) or is being readout in the normal operation of the receiver after it has been programmed.
The section of the circuit in FIG. 8 that is different from the corresponding section of the circuit in FIG. 1 is the tuning pulse section 150. This section includes an uptuning switch 151U and a downtuning switch 151D, each of which is connected in series with its respective resistor between the positive power supply voltage +5V and ground. The common circuit point between the respective switches 151U and 151D and their series-connected resistors comprise input terminals to a pair of inverters 152 and 153, respectively. When the switches 151U and 151D are open, a "1" signal is applied to the corresponding inverter and when the switches are closed the "0" signal is applied. The output terminals of the inverters 152 and 153 are each connected to one input terminal of a corresponding AND circuit 154 and 155. The other input terminal of each of these AND circuits is connected to the output terminal of a pulse generator 156 that generates a pulse signal P 1 of a predetermined frequency F. The output of the pulse generator 156 is also connected to the input of a frequency divider 157, which in this case divides the frequency of the pulse P 1 by 2. The output terminals of the AND circuit 154 and 155 are connected, respectively, to one of the input terminals of a pair of OR circuits 158 and 159. The output terminal of the frequency divider 157 is connected to one input terminal of each AND circuits 160 and 161. The up-tuning signal E U from the AFT circuit 120 is connected to another input terminal of the AND circuit 160 and the output of this AND circuit is connected to another input terminal of the OR circuit 158, the output terminal of which is connected to the UP input circuit of the counter 40. A second input terminal of the AND circuit 161 is connected to the down-tuning output terminal to receive the down-tuning signal E D of the AFT circuit 120. The output terminal of the AND circuit 161 is connected to an input terminal of the OR circuit 159 and the output terminal of this OR circuit is connected to the DOWN terminal of the counter 40.
Pulse signals that reach the UP terminal of the counter 40 by way of the OR circuit 158 cause the counter to count UP. On the other hand, signals that reach the DOWN terminal of the counter 40 by way of the OR circuit 159 cause the counter to count DOWN. The pulse signals to be counted, in either case, are obtained from the pulse generator 156. These pulses are able to reach the OR circuit 158 if the AND circuit 154 has been enabled by a "1" at the output of the inverter 152 corresponding to closure of the switch 151U to produce a "0" at the input of that inverter. Similarly, pulse signals P 1 from the pulse generator 156 can reach the OR circuit 159 if the AND circuit 155 has been enabled by a "1" at the output of the inverter 153 due to a "0" at the input of that inverter. A "0" at the input of the inverter 153 is obtained by closure of the switch 151D.
When the memory 50 in FIG. 8 is to be programmed initially, the arm of the mode switch 61 is switched to the terminal connected to the +5V power supply voltage. This places the circuit 60 in position to write in a channel code in the memory 50. The address at which the code is to be written in is determined by closing one of the switches S 1 -S N . Then the code itself is generated by closing one or the other of the switches 151U or 151D. If it is assumed that the initial programming starts with the tuner 100 at its lowest frequency, the up-tuning switch 151U should be closed, thereby placing the AND circuit 154 in condition to allow the pulses P 1 to pass through this AND circuit and the OR circuit 158 to the UP input terminal of the counter 40. As the pulses cause the count in the counter 40 to increase, the output analog voltage of the D/A converter 90 changes to raise the frequency to which the tuner 100 is tuned. When the desired frequency is reached, the up-tuning switch 151U may be open, or in fact, when the tuning is below the desired frequency f o by about 1.2 mHz the up-tuning switch 151 can be open, the AFT circuit 120 can be allowed to tune the tuner 100 into the desired frequency f o .
The AFT circuit 120 generates the up-tuning signal E U that has a value starting at the edge of the subrange 1.2 mHz below f o . This signal having a value of "1" places the AND circuit 160 in condition to allow output pulses from the frequency divider 157 to pass through the AND circuit and the OR circuit 158 to the UP terminal of the counter 40. However, the frequency of the pulses that pass through the AND circuit 160 are lower than the frequency of the pulses P 1 by the frequency division ratio of the frequency divider 157. In the illustrated example, the pulses that pass through the AND circuit 160 have a frequency one-half that of the pulses that pass through the AND circuit 154. Thus the automatic fine tuning takes place somewhat more slowly than if the switch 151U were held closed until the exact frequency f o had been reached by the tuner 100, but the fine tuning is not so slow as to be objectionable.
Once the counter 40 reaches the count that causes the tuner 100 to be at the desired frequency, the writing switch 62 can be closed to record the proper count at the selected address determined by the particular switch S 1 -S N that has been closed. The process can then be repeated to tune in and record the count code of another channel at another address.
If it is assumed that the second channel code to be recorded corresponds to a channel at a higher frequency f o than the initially recorded code, the up-tuning switch 151U will again have to be closed to increase the count in the counter 40. However, the AFT circuit 120 is always in operation and as the counter 40 starts to count UP, the down-counting signal E D will become a "1" in the sub-range f o +50 kHz to f o +1.2 mHz. It is in order to allow the count in the counter 40 to progress upwardly and not be held back by the AFT signal E D (or downwardly and not be held back by the up-tuning signal E U ) that the pulses P 1 are frequency divided in the circuit 157. When the AFT 120 produces a "1" signal E D applied to the AND circuit 161 while the switch 151U is closed to allow pulses P 1 to reach the UP input terminal of the counter 40, the pulses that pass through the AND circuit 161 and the OR circuit 159 to the DOWN terminal of the counter will have a lower frequency than the up-counting pulses. Thus the pulses controlled by the AFT circuit 120 will not entirely be able to prevent the counter 40 from being shifted to a higher count (or, to a lower count if it is the switch 151D that is closed). Once the count in the counter 40 passes beyond the upper limit f o +1.2 mHz of the lower frequency channel, the count increases in speed corresponding to the frequency of the pulse signal P 1 until the next channel comes within the AFT range that extends from 1.2 mHz below the frequency f o of the next channel to 1.2 mHz above the frequency f o of that channel.
Although an illustrative embodiment of the invention has been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.
SONY Automatic pre-programming system for TV receiver/ Automatically presetting channel Program selecting system :
"A channel selecting system for use in a receiver having a voltage controlled tuning element which has an automatic channel presetting function which utilizes a pulse generator and a binary counter connected to the generator to count the pulses and to generate a binary coded output in accordance with the sum of the pulses. A digital-to-analog converter changes the binary coded output into a linearly increasing tuning sweep voltage which in turn conditions the voltage controlled tuning element to scan the frequency range of the tuner as the tuning voltage increases. As the frequencies are scanned, a detector, connected to the tuning element, senses the presence of a broadcast channel. When a channel is detected, the scan is interrupted and a binary memory is utilized to store the binary coded output which corresponds to the frequency of the detected broadcast channel. A control gate signal generator driven by the detector controls the pulse generator and memory such that the scan is continued until the entire frequency range has been scanned. Channel selection is accomplished by switch means actuatable to address the memory to read out a selected binary code output corresponding to the channel desired which causes the converter to generate a voltage to condition the tuning element to tune to the desired frequency. The voltage control tuning element may comprise several different elements, one for each of a plurality of different frequency ranges. Means are provided for selecting an appropriate tuner such that channels from any of the frequency ranges may be selected. "
An automatic tuning scheme for use in TV receivers includes a start/stop circuit which creates a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively, a tuning voltage generator which generates a gradually varying tuning voltage under control of the search start signal and search stop signal, and a memory circuit for storing the tuning voltage from the generator when desired. The tuning voltage stored in the memory circuit is supplied to a tuner including a well known voltage-sensitive capacitance diode.
1. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and the presence of a detected incoming signal, respectively, the presence of a detected incoming signal being determined at least in part in response to an output of said AFT detector;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from said tuning voltage generator means;
signal decision circuit means for determining whether the detected incoming signal is a true television signal including a television synchronizing signal by detecting the presence of the television synchronizing signal and the search stop signal, said signal decision circuit means providing a memory store instruction for the memory circuit means in the presence of the true television signal and providing a search re-start instruction for the start/stop circuit means in the absence of the true television signal, the tuning voltage stored in the memory circuit means being supplied to a tuner including a voltage-sensitive capacitance diode.
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the tuning voltage generator means
means for detecting the presence of synchronizing signals within the detected incoming signal;
noise skip circuit means which determines whether the detected synchronizing signal is a true synchronizing signal or noise and provides a search re-start instruction for the start/stop circuit means in the presence of noise; and
signal decision circuit means for determining whether there is a true television signal by counting the number of the true synchronizing signals derived from the noise skip circuit means and counting a predetermined number of the true synchronizing signals in a predetermined period of time, and then providing a memory store instruction for the memory circuit means in the presence of the true television signal and a search re-start instruction to the start/stop circuit means in the absence thereof, the tuning voltage stored in the memory circuit means being supplied to a tuner.
4. In an automatic tuning scheme for use in TV receivers including an AFT detector, which produces search start and stop signals upon receipt of a search start instruction and a detected incoming signal, a combination comprising:means for detecting the presence of synchronizing signals within the detected incoming signal;
noise skip circuit means for determining whether the synchronizing signal is a true synchronizing signal or noise and provides a search restart instruction to said tuning scheme in the presence of noise; and
means for adjusting a skip level in the noise skip circuit means in accordance with the intensity of the detected incoming signal.
5. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:start/stop circuit means which creates a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the generator, the tuning voltage stored in the memory circuit means being supplied to a tuner;
speed changer means for reducing the rate of variation in the tuning voltage derived from the tuning voltage generator means to enable a low speed searching operation slower than that of the normal searching operations when detecting an AFT detector output;
means for detecting the presence of synchronizing signals within the detected incoming signal; and
means for determining whether the synchronizing signal is a true synchronizing signal or noise and providing a search re-start instruction to said tuning scheme in the presence of noise.
6. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the tuning voltage generator means, the tuning voltage stored in the memory circuit means being supplied to a tuner; and
speed changer means for reducing the rate of variation in the tuning voltage derived from the tuning voltage generator means to enable a low speed searching operation slower than that of the normal searching operation when detecting an AFT detector output, the direction of variation of the tuning voltage being reversed in accordance with the polarity of the AFT detector output.
7. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the tuning voltage generator means, the tuning voltage stored in the memory circuit means being supplied to a tuner;
out-of-tuning detector means for supplying a search re-start signal to the start/stop circuit means when detecting the out-of-tuning condition;
means for detecting the presence of synchronizing signals within the detected incoming signal; and
means for determining whether the synchronizing signal is a true synchronizing signal or noise and providing a search re-start instruction to said tuning scheme in response thereto.
8. The automatic tuning scheme according to claim 7 wherein the out-of-tuning condition is sensed by comparing the AFT detector output to a given reference voltage. 9. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
means for detecting the presence of synchronizing signals within the detected incoming signal; and
means for determining whether the detected synchronizing signal is a true synchronizing signal or noise and providing a search re-start instructions to said tuning scheme in the presence of noise.
10. The automatic tuning scheme according to claim 9 further comprising alarm means enabled by the tuning instruction for notifying the operator of the automatic tuning operation. 11. The automatic tuning scheme according to claim 10 wherein said alarm means release alarm signals in the form of sound. 12. The automatic tuning scheme according to claims 3, 4, 5, 6, 7, or 9 wherein the reception of a true television signal is determined by the use of said true synchronizing signal and an AFT output.BACKGROUND OF THE INVENTION
The present invention relates to an automatic pre-programming tuning circuit which performs tuning operation automatically.
It is customary to perform the tuning operations in TV receivers while a viewer manually rotates a tuning knob. However, the tuning operation is bothersome particularly in case of the continuously varying tuning operation such as in UHF reception. Though tuning operation is considerably simpler in case of TV receivers of the recently developed touch control type or remote control type, it is difficult for a non-skilled person the to preset tuning operation, namely, to adjust the tuning frequencies for respective broadcasting stations before starting to watch a TV receiver.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an automatic tuning scheme which enables automatic preselectable tuning operation by sequentially memorizing tuning voltages of respective automatically selected broadcasting channels.
In its broadest aspect, an automatic tuning device of the present invention comprises a tuning voltage generator which generates a tuning voltage gradually variable during tuning operation, a memory circuit which receives the tuning voltage derived from the generator upon receipt of normal reception signals and memorizes a plurality of discrete tuning voltages each associated with a respective one of normal reception signal corresponding to a serviceable broadcasting station and means for picking up selectively one of the discrete tuning voltages from the memory circuit and supplying it to a tuner.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and attendant advantages of the present invention will be easily appreciated as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference numerals designate like part throughout the figures thereof, and wherein:
FIG. 1 is a schematic diagram of the automatic tuning apparatus embodying the present invention;
FIG. 2 is a more detailed circuit diagram of the automatic tuning apparatus shown in FIG. 1;
FIG. 3 is a schematic diagram of another embodiment of the present invention;
FIGS. 4 and 5 are a circuit diagram and a waveform diagram showing a noise skip circuit included in FIG. 3 embodiment;
FIG. 6 is an improvement in the noise skip circuit shown in FIGS. 4 and 5;
FIGS. 7 and 8 are embodiments effective to modify the searching speed in the automatic tuning apparatus;
FIGS. 9 through 11 are refresh means effective in the automatic tuning apparatus of the present invention;
FIG. 12 shows another embodiment including a memory skip circuit effective in the automatic tuning apparatus;
FIGS. 13 and 14 show alarm means effective in the automatic tuning apparatus.
DETAILED DESCRIPTION OF THE INVENTION
A basic circuit of a TV recei
ver having an automatic tuning scheme implemented with the present invention is shown in FIG. 1, which includes an antenna 1, a tuner 2, an intermediate frequency (IF) circuit 3, an automatic fine tuning (AFT) circuit 4, a video circuit 5, a synchronizing separator 6, a deflection circuit 7, a picture tube 8. According to the present invention, a start/stop circuit 9, a tuning voltage generator 10, a memory circuit 11 and a signal decision circuit 12 are further provided to form the automatic tuning scheme of the present invention.
It will be noted that the tuner 2 can be implemented with a well known electronic tuning circuit which includes a voltage-sensitive capacitance diode as disclosed in U.S. Pat. No. 3,233,179 entitled "AUTOMATIC FINE TUNNING CIRCUIT USING CAPACITANCE DIODES" issued on Feb. 1, 1966.
If the start/stop circuit 9 is given a search start command or au automatic tuning instruction prior to effecting of the preset tuning operation, then the start/stop circuit 9 will develop a search start pulse which is turn is supplied to the tuning voltage generator 10. Under the circumstance the tuning voltage generator 10 develops a sweep voltage or staircase voltage which is gradually rising or dropping during the automatic tuning operation. The sweep or staircase voltage is supplied as the tuning voltage to the tuning capacitance diode in the tuner 2 by way of the memory circuit 11. This implies that the reception frequency in the tuner 2 is gradually varied.
In this way, when the television signal of a specific broadcasting channel is received, the television video signal is derived from the IF circuit 3 and the synchronizing signal from the synchronizing separator 6. These signals are applied to the start/stop circuit 9. Meantime, the AFT detector output is derived from the AFT circuit 4 and supplied to the start/stop circuit 9.
More particularly, when the television signal is accurately received, the AFT detector output voltage will change in polarity so that the start/stop circuit 9 is permitted to develop a search stop pulse and the vertical synchronizing signal. In the given example the vertical synchronizing signal may serve as the search stop pulse. The search stop pulse is supplied to the tuning voltage generator 10, barring the generator 10 from developing the sweep or staircase voltage. The voltage at this moment remains unchanged since then and keeps being supplied as the tuning voltage to the tuner 2 via the memory circuit.
The vertical synchronizing signal derived from the start/stop circuit 9 is supplied to the signal decision circuit 12 to determine as to whether the signal being received is a normal or true television signal. If the affirmative answer is given, then the signal decision circuit 12 will issue a memory instruction which in turn is supplied to the memory circuit 11 so that the instantaneous tuning voltage derived from the generator 10 is stored within the memory circuit 11.
Contrarily, if a false synchronizing signal is derived from the start/stop circuit 9, then the signal decision circuit 12 reacts to it so that the circuit 12 issues a search re-start pulse. This is supplied to the start/stop circuit 9 to repeat the same procedure as when executing the first search start pulse. The procedure is repeated in this manner until the start/stop circuit 9 recognizes a true television vertical synchronizing signal or accurate reception is available by the tuner 2.
In other words, the memory instruction is not issued from the signal decision circuit 12 until the optimum reception state is guaranteed. Upon issuance of the memory instruction the instantaneous tuning voltage is stored in the memory circuit 11 and subsequently supplied to the tuner 2.
Once the preset tuning operation (i,e, the presetting of the optimum reception frequency) has been completed for the specific broadcasting channel, the tuning voltage stored in the memory circuit 11 will be automatically supplied to the tuner in response to release of a tuning instruction from an operational panel of the known touch control type or remote control type. The searching procedure is not required at this time.
It is obvious that the memory circuit 11 shown in FIG. 1 includes a predetermined number of memory elements the number of which corresponds to the number of serviceable broadcasting stations. The same searching or presetting procedure is repeated when it is desired to search and memorize a predetermined number of discrete tuning voltages prior to use of a TV receiver.
As noted earlier, when the search start instruction is given and the search start signal is released from the start/stop circuit 9, the tuning voltage generator 10 starts generating the sweep voltage (or the staircase voltage), which is supplied to the tuner 2 via the memory circuit 11 while showing a gradual variation. Alternatively, the gradually varying voltage may be supplied to the tuner 2 directly. If the search stop signal is derived from the start/stop circuit 9 upon receipt of the television signal, the sweep voltage generating function of the tuning voltage generator will come to a halt. The instantaneous tuning voltage supplied to the tuner 2 is held unchanged for a while.
At this time the signal decision circuit 12 decides whether the received signal is true or false. After confirming the presence of the true television signal, the memory instruction is issued for the memory circuit 11 so that the tuning voltage available from the tuning voltage generator 10 is held within the memory circuit 10 to complete the presetting of the optimum reception frequency for the specific television station.
On the contrary, when the signal decision circuit 12 does not sense the presence of the true television signal, the search re-start signal is issued for the start/stop circuit 9 to start the above mentioned operation again. Each time the memorizing operation or the tuning frequency presetting operation is completed in the memory circuit 11 for a specific one of broadcasting stations, the search start instruction is issued again for the start/stop circuit 9. Eventually, a plurality of discrete tuning voltages are stored in sequence in the memory circuit 9, completing the over-all loading operation of the discrete tuning voltages.
FIG. 2 shows a detailed way of implementation
of the present invention briefly described with respect to FIG. 1. When a search switch SW1 is turned on, a latch FF1 is placed to the set state with the Q output at a high level "H" and the Q output at a low level "L". A gate G3 is enabled such that clock pulses from a clock pulse generator 13 are sequentially supplied to a counter 14 to increment it at a high speed. The output of the counter 14 is supplied to a digital-to-analog converter 15 which converts the output of the counter 14 into a DC voltage correspondingly. This DC voltage is supplied as the tuning voltage to the tuner 2. Therefore, the gradually rising sweep voltage is transferred from the digital-to-analog converter 15 to the tuner 2 so that the reception frequency in the tuner 2 is gradually varied in the ascending order.
When the television signal of a specific broadcasting station is received, the television video signal is derived from the IF circuit 3 and the horizontal and vertical synchronizing signals are derived from the synchronizing separator 6. In the case where the detector output voltage from the AFT circuit 4 is positive, a gate G2 is enabled to place the latch FF1 into the reset state. At the moment the Q and Q outputs of the latch FF1 are respectively inverted into "L" and "H" levels. A gate G3 is disabled to stop supply of the clock pulses to the counter 14 so that the digital-to-analog converter 15 supplies the tuner 2 with the output voltage of a fixed value. In other words, the searching operation comes to a halt.
When the true television signal is being received, the horizontal synchronizing pulse derived from the synchronizing separator 6 is in phase with the flyback pulse derived from the deflection circuit 7. A transistor Tr1 is turned on in reponse to the horizontal synchronizing pulse with an increase in the emitter potential thereof. Gates G4 and G5 are enabled so that the vertical synchronizing pulse is supplied as the memory instruction to the memory circuit 11 via these gates G4 and G5. At this moment the output of the counter 14 is loaded into the first address of the memory circuit 11 in a digital fashion.
However, if the signal being received is not the true television signal, then the horizontal synchronizing pulse will neither be synchronous with the flyback pulse nor will the transistor Tr1 be turned on. Even though the vertical synchronizing pulse from the synchronizing separator 6 or the false synchronizing pulse forces the latch FF1 into the reset state, the gate G5 is never enabled but the gate G6 is enabled. The pulse transferred via the gate G6 is supplied as the search re-start pulse to the latch FF1 which then resorts to the reset state again to restart the searching procedure.
After the searching/memory operation has been completed for a specific one of broadcasting stations, the memory circuit 11 releases the search start pulse again, which is then supplied to the latch FF1 via the gate G1 to set the latch FF1.
The same operation is thus repeated. A different tuning voltage of the next suceeding station is digitally stored at the second address of the memory circuit 11. In this way, a predetermined number of discrete tuning voltages are digitally stored in sequence until the end of the presetting operation.
Once the presetting operation has been accomplished, all that is necessary for the operator to do is to select a desired one of channel selection switches 161 through 16n. Then, digital information indicative of the tuning voltage previously stored at its associated address of the memory circuit 11 is called forth in accordance with its associated selection codes within an address specifying circuit 17. The digital information is applied via the counter 14 to the digital-to-analog converter 15 which decodes it into the analog tuning voltage. The tuning voltage is supplied to the tuning capacitance diode included within the tuner 2.
FIG. 3 shows another example of the tuning scheme furth
er comprising a noise skip circuit. As described above, when the true television signal is received, the output from the AFT detector will change in polarity and upon such change the television synchronizing signal will be derived from the start/stop circuit 9. This synchronizing signal is supplied to a noise skip circuit 18 to decide whether or not this is the true television vertical synchronizing signal. Particularly when the true vertical synchronizing signal is confirmed, this is applied to the signal decision circuit 12 and simultaneously applied as the search stop pulse to the tuning voltage generator 10. Contrarily, when concluded as noise and not the synchronizing signal, this will be supplied as the re-start pulse to the start/stop circuit 9. This permits the recurring of the same operation as when the search start instruction is issued for the first time. In the given example, the vertical synchronizing signal obtained from the noise skip circuit 18 is utilized as the search stop pulse.
In this way the search stop pulse is developed from noise skip circuit 18 and sent to the tuning voltage generator 10, stopping the generator 10 from generating the sweep voltage. The instantaneous voltage is thereafter kept and sent to the tuner 2 via the memory circuit 11. Under these circumstances the signal decision circuit 12 determines again whether the vertical synchronizing signal developed from the start/stop circuit 9 is the true television synchronizing signal.
By way of example, the signal decision circuit 12 may be adapted to count the number of the synchronizing signals and determine whether a predetermined number of the synchronizing signals are present during a given period of time. If the true synchronizing signal is sensed, then the signal decision circuit 12 will release the memory instruction, permitting the memory circuit 11 to store the tuning voltage supplied from the generator 10.
Nevertheless, even if the noise skip circuit 18 delivers the false synchronizing signal inadvertently, the signal decision circuit 12 never overlooks it so that the circuit 12 issues the search re-start pulse. The start/stop circuit 9 receives such pulse to repeat the above mentioned operation. In other words, the operation is repeated to assure the optimum reception condition until the true television synchronizing signal is available from the start/stop circuit 9 and the noise skip circuit 18. The memory instruction will be issued immediately after the optimum reception condition is reached.
Details of the noise skip circuit 18 are shown in FIG. 4. This is split into three major portions: an integration circuit portion 21 consisting of resistors R1 and R2 and capacitors C1 and C2 ; a noise detection circuit portion 22 consisting of transistors Q1, Q2 and Q3, a diode D1 and so on; and a synchronizing signal amplifier portion 23 consisting of a transistor Q4 and so on. Assume now that the true television synchronizing signal (with negative polarity) as viewed from FIG. 5 a is derived from the start/stop circuit 9. This signal is integrated with the integration circuit portion 21 as shown in FIG. 5 b . The base bias voltage of the first stage transistor Q1 in the noise detector portion 22 is fixed, say at approximately 0.3 volts, by the resistors R3, R4 and R5 and the diode D1. Thus, this signal at the positive polarity side is extremely shallow and the transistor Q1 is placed into the cut off state as long as the genuine vertical synchronizing signal is derived. The remaining transistors Q2 and Q3 are also placed into the cut off state. Therefore, the noise detector portion 22 does not deliver the output signal or the search stop pulse. The vertical synchronizing pulse as shown in FIG. 5 c is applied to the base of the transistor Q4 via the capacitor C3 for amplification. The vertical synchronizing signal with the positive polarity as shown in FIG. 5 d is developed at the collector of the transistor Q4 and supplied to the signal decision circuit 12 and as the search stop pulse to the tuning voltage generator 10.
On the other hand, if the noise signal, for example, as shown in FIG. 5 e is
derived from the start/stop circuit 9, then this will be integrated with the integration circuit portion 21. The result is shown in FIG. 5 f , which has both positive and negative polarity components. Since the positive polarity component is well above the conduction level (say, 0.6 volts) of the transistor Q1, the transistor Q1 is turned on whenever an the transistors Q2 and Q3 are also turned on. The signal appearing at the emitter of the transistors Q3 is shown in FIG. 5 h and returned as the search re-start pulse to the start/stop circuit 9.
By the action of the noise skip circuit 18. Whether the signal derived from the start/stop circuit 9 is the true synchronizing signal or noise is determined by the positive voltage level of that signal. Then, the synchronizing signal is supplied to the signal decision circuit 12 and the tuning voltage generator 10, while the noise is supplied as the search re-start pulse to the start/stop circuit. As shown in FIG. 6, a skip level adjusting variable resistor VR1 installed in the noise detector portion 22 makes the above mentioned positive voltage level freely variable. It also becomes possible to supply the noise as the search re-start pulse to the start/stop circuit 9 when the normal television synchronizing signal is received but relatively strong noise is superimposed thereon.
Within the tuning scheme having the noise skip circuit, there is no opportunity inadvertently the tuning voltage generator 10 with the search stop instruction due to noise. In addition, only broadcasting stations with comparatively strong television signals can be preset in sequence while skipping ones with comparatively weak television signals. Although in the illustrated example the noise skip level is manually variable through the use of the variable resistor VR1, it is noted that the skip level can be varied in response to the intensity of the television signals being received by applying an AGC voltage thereto.
Details of modifications in the start/stop circuit 9 and the tuning voltage generator 10 are shown in FIG. 7 wherein the search speed is variable.
Provided that the search start instruction or the search restart pulse is supplied via an OR gate 34 to a reset input terminal of an R-S type latch 33, the latch 33 will be in the reset state so that the Q output thereof assumes a "H" level to enable an AND gate 35. Another latch 39 of the R-S type 39 is also placed into the reset state in response to the search start instruction or the search re-start pulse. The Q oupu
t of the latch 39 assumes a "L" level and the Q output assumes a "H" level, enabling an AND gate 40. At this time clock pulses of, for example, 320 Hz are generated via an AND gate 40, an OR gate 47 and an AND gate 35 from a high speed clock pulse generator 36 and supplied to a counter 42 in the tuning voltage generator 10. The count of the counter 42 varies sequentially at a relatively high rate and is converted through a digital-to-analog converter 43. As a consequence, the converter 43 develops a gradually rising or dropping DC voltage, which is supplied to the tuner 2 via the memory circuit 11. A rate of variations in the tuning voltage derived from the generator 43 is relatively high and the searching procedure is carried out at a high speed.
While a specific television signal is received, the detector output is derived from the AFT circuit 4 and the vertical synchronizing signal is derived from the synchronizing separator 6. When an AFT negative output detector 44 senses the AFT detector output of the negative polarity, the output of the detector 44 increases to a "H" level. The AND gate 45 is enabled so that the vertical synchronizing signal is supplied to a set input terminal of the R-S type latch 39. The latch 39 is placed into the set state with the Q output thereof having a "H" level and the Q output thereof having a "L" level. The AND gate 40 is disabled concurrently with the enabling of the AND gate 46. Under these circumstances clock pulses of, for example, 160 Hz from a low speed clock pulse generator 47 are supplied to the counter 42 via the AND gate 46, the OR gate 41 and the AND gate 35. The counter 42 performs the counting operation at a low speed. A rate of variations in the tuning voltage or the DC voltage obtainable from the digital-to-analog converter 43 is reduced to one-half its initial rate and the searching procedure is carried out at a low speed.
If the polarity of the AFT detector output changes from negative to positive during the low speed searching operation, then the output of an AFT positive output detector will increase to a "H" level. The AND gate 38 is enabled and the vertical synchronizing signal is supplied via the AND gates 38 and 48 to the set input terminal of the R-S type latch 33 (the AND gate 48 is now enabled because of the Q output of the latch 39 at a "H" level). The latch 33 is therefore set. As a result, the Q output of the latch 33 changes to a "L" level to disable the AND gate 35. The counter 42 is supplied with the clock pulses no longer. Afterward, the count of the counter 42 remains unchanged and the tuning voltage derived from the digital-to-analog converter 43 is held at a fixed value. The searching operation comes to a stop.
Then, when the search start instruction of the search re-start pulse is issued again, the latch 33 and 39 are reset to enable AND gates 35 and 40. The clock pulses from the high speed clock pulse generator 36 are supplied to the counter 42, restarting the searching operation.
Another modification in the start/stop circuit 9 and the tuning voltage generator 10 is shown in FIG. 8. When the search sta
rt instruction or the search re-start pulse is supplied to the reset input terminal of the latch 33 via the OR gate 34, the Q output of the latch 33 in the reset state will assume a "H" level with the AND gates 35 and 49 enabled. The other latches 39 and 50 are also reset in response to the search start instruction or the search re-start pulse with the Q outputs thereof at a "L" level and the Q outputs thereof a "H" level. The AND gate 40 is enabled while the AND gate 46 and 51 remain disabled. The 320 Hz clock pulses from the high speed clock pulse generator 36 are derived via the AND gate 40, the OR gate 41 and the AND gate 35 and supplied to a count up input terminal of an up/down counter 42' in the tuning voltage generator 10. The counter 42' is sequentially incremented at a high speed, the count of which is supplied to the digital-to-analog converter 43. As a result, the converter 43 develops a gradually rising DC voltage which is supplied as the tuning voltage to the tuner 2 via the memory circuit 11. In this case variations in the tuning voltage are comparatively quicker and the searching operation is carried out by the increase of the local oscillation frequency.
Under these circumstances, when the television signal is received, The AFT circuit 4 develops the AFT detector output and the synchronizing separator 6 develops the vertical synchronizing signal. If there is the negative output sensed by the AFT negative output detector 44, the output of the detector 44 will assume a "H" level to enable the AND gate 45. The vertical synchronizing signal is supplied to the set input terminal of the R-S type latch 39 via the AND gate 45, setting the same. Since the Q and Q outputs of the latch 39 assume "H" and "L" levels respectively, the AND gate 46 is enabled and the AND gate 40 is disabled. The clock pulses with 160 Hz from the low frequency clock pulse generator 47 are supplied via the AND gate 46, the OR gate 41 and the AND gate 35 to the count up input terminal of the counter 42' to execute the counting operation at a relatively low speed. The DC voltage or the tuning voltage derived from the digital-to-analog converter 43 shows variations at a rate which is reduced to one half its initial rate. The searching operation is carried out with low speed in order to eventually increase the local oscillation frequency.
Thereafter, when the polarity of the AFT detector output changes from negative to positive during the slow searching operation, the output of the AFT positive output detector 37 increases to a "H" level, enabling the AND gate 38 such that the vertical synchronizing signal is supplied to a set input terminal of an R-S type latch 50 therethrough. The result is that the latch 50 is placed into the set state with the Q output thereof at a "H" level and the Q output thereof at a "L" level. An AND gate 57 is enabled and the AND gates 40 and 46 are disabled. Therefore, clock pulses with, for example, 20 Hz are derived from an extremely low speed clock pulse generator 52 and supplied to a count down input terminal of the counter 42' via AND gates 51 and 49. The count of the counter 42' is gradually decremented at an extremely low speed. A gradually dropping tuning voltage is suddenly obtainable from the converter 43 and a rate of variations in the tuning voltage is reduced to a large extent. The searching operation is carried out with extremely low speed in a sense to decrease the local oscillation frequency.
If the output of the AFT positive output detector 37 changes to a "L" level while executing the extremely slow searching operation in the opposite direction, an output of an inverter 53 will change to a "L" level with the output of the AND gate 48 at a "H" level. The latch 33 is set with the Q output changing to a "L" level. The AND gates 35 and 49 are disabled to stop supplying the counter 42' with the clock pulses any more. Thereafter, the content of the counter 42' is fixed and the tuning voltage from the digital-to-analog converter 43 remains unchanged. In this way, the searching operation comes to a halt at the normal point of local oscillation.
If the search start instruction or the search re-start pulse is then given, then all of the latches 33, 39 and 50 are reset to enable the AND gates 35 and 40 again. The clock pulses from the high speed clock pulse generator 36 are supplied to the counter 42', executing the high speed searching operation.
Although in the given example the three clock pulse generators 36, 47 and 52 are employed for the high speed phase, low speed phase and extremely low speed phase of the searching operation, a single clock pulse generator with the frequency division ability can be a substitute theref
or.
An embodiment of the present invention shown in FIGS. 9 through 11 includes an out-of-tuning detector 65 in addition to the start/stop circuit 9, the tuning voltage generator 10, the memory circuit 11 and the signal decision circuit 12.
When the search start instruction is given to the start/stop circuit 9 during the presettable tuning operation, an AFT ON/OFF switch 64 will be turned off automatically, shifting from one terminal a to another b . A reference voltage from a reference voltage generator 63 is supplied to an AFT terminal of the tuner 2. The preset tuning operation keeps on under these circumstances.
The re-preset tuning operation is carried out in the following manner. If the memory circuit 11 associated with a desired channel is given the tuning instruction, then the tuning voltage stored in that memory circuit 11 is supplied to the tuner 2 via the tuning voltage generator 10 in order to select the desired channel.
The out-of-tuning detector 65 is enabled at a moment upon receipt of the above mentioned tuning instruction, where the AFT detector output voltage obtained from the AFT circuit 4 is compared with the given reference voltage from the reference voltage generator 63. If there is almost no deviation from the optimum tuning point, both the voltages are substantially equal with no development of the output pulse. On the other hand, if a difference therebetween exceeds a critical value, this is sensed to deliver the output pulse which in turn is supplied as the search re-start pulse to the start/stop circuit 9. The preset tuning operation restarts when the tuner 2 has becomes out of tuning.
The out-of-tuning detector 65 is illustrated in detail in FIG. 10, which comprises switches SW11 and SW12, transistor Q11 and Q12, resistors R11, R12 and R13, an OR gate OR11 and so on. Upon receipt of the tuning instruction the switches SW11 and SW12 are turned on instantly so that the reference voltage from the reference voltage generator 63 is applied to the base of the transistor Q11 and the emitter of the transistor Q12 via the switch SW11 and the resistor R11, whereas the AFT detector output voltage from the AFT circuit 4 is applied to the emitter of the transistor Q11 and the base of the transistor Q12 via the switch SW12. Provided that the local oscillation frequency stands at the normal point without any substantial deviation, the AFT detector output voltage will be nearly equal to the reference voltage (say, within one volt) and the transistors Q11 and Q12 will be in the cut off state. No output voltage is developed at the collectors of the transistors Q11 and Q12. When being in the out-of-tuning state, the AFT detector output voltage will tend to somewhat increase over the reference voltage (say, one volt higher), placing the transistor Q11 into the on state with a positive pulse voltage appearing at the collector thereof. This pulse is supplied to the tuning voltage generator 10 directly or via the start/stop circuit 9 and supplied as the start/stop pulse to the start/stop circuit 9 via the OR gate OR11. As a result, the re-search operation is initiated and the tuning voltage at the tuning voltage generator 10 is gradually increased. Therefore, the local oscillation frequency will be reverted back to the normal point of tuning. When the signal decision circuit 12 issues the memory instruction, the instantaneous tuning voltage is loaded into the memory circuit 11 thereby completing the re-preset tuning operation. If the local oscillation frequency will be increased above the normal point, the transistor Q12 is turned on to develop the output pulse at the collector thereof. This is supplied to the start/stop circuit 9 and the tuning voltage generator 10, gradually decreasing the tuning voltage at the tuning voltage generator 10.
An embodiment shown in FIG. 12 is effective with the abili
ty of temporarily inhibiting the supply of the memory instructions to the memory circuit and skipping the memorizing of undesired channels when the capacity of the memory circuit 11 is small. There is further provided a memory skip circuit 66 which controls the transferring of the memory instructions from the signal decision circuit 12 to the memory circuit 11. While the memory skip circuit 11 is normally connected to the contact a , the memory instruction is supplied from the signal decision circuit 12 to the memory circuit 13 via the skip circuit 13 each time a specific channel is selected. The respective tuning voltages are therefore stored in the memory circuit 11 at these moments.
If an undesired channel is selected and received, then a skip instruction is given to the memory skip circuit 66 by way of any means, putting it toward the contact b . At this moment the memory instruction is supplied as the search restart pulse to the start/stop circuit 9 which restarts the searching operation to seek the next succeeding channel. Since the memory skip circuit 66 has then been returned to the contact a , the next memory instruction is supplied to the memory circuit 11, loading the tuning voltage of that channel into the memory circuit 11.
In an embodiment shown in FIG. 13, the tuning instruction from the signal decision circuit 12 is supplied to a blinking enable circuit 70 which comprises an AND g
ate and an amplifying transistor. Pulses derived from a pulse oscillator 71 are gated as well as the tuning instruction, energizing a light emitting diode 72 to notify the operator of the tuning operation.
An embodiment shown in FIG. 14 is adapted to produce audiable sounds instead of release of light. An audio silence circuit 75 is enabled by the tuning instruction from the signal decision circuit 12, which provides the output thereof for an audio circuit 76 to shut out the television audio signals. No television audio signals are released from a loud speaker 77. Meanwhile, the tuning instruction is supplied to an intermittent sound generator 78 which creates intermittent sound signals through synthesis of pulse signals from a pulse oscillator 79 and a frequency divider 80. The synthesized sound signals are supplied to the audio circuit 76.
As a result, intermittent sounds are released from the loud speaker 7 during the automatic tuning operation. Once the tuning operation has been completed and the true television signal has been received, these intermittent sounds are prohibited and the true television sounds are released from the loud speaker 77.
The tuning instruction with a "H" level from the signal decision circuit 12 is amplified by the audio silence circuit 75 and supplied to the audio circuit 76, which shuts out the television sound signals. The tuning instruction with a "H" level is also supplied to an AND gate 81 in the intermittent sound circuit 78. The AND gate 81 always receives pulses from the pulse oscillator 79 consisting of a multivibrator. These pulses are also supplied to the frequency divider 80 such that the AND gate 81 develops intermittent pulse signals, which are supplied to the audio circuit 76 and then the loud speaker 77.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.
SONY TRINITRON E/W Pincushion distortion correction apparatus CIRCUIT:
A pincushion distortion correction saturable reactor is a saturable transformer comprising a core having four legs, controlled and control coils being coupled to the core legs in a perpendicular relation to each other. The core gap for the controlled coil is provided in an unbalanced form, and a parabolic current at the vertical scanning frequency (or at horizontal scanning frequency) containing a superimposed DC component is supplied through the control coil to modulate the inductance of the controlled coil. The inductance of the controlled coil is thus reduced in a region where the magnetomotive force produced by the control coil is greater than that produced by the control coil to preclude deflectional distortion in the neighborhood of the center of the reproduction on the screen and improve the horizontal linearity.
1. A pincushion distortion correction apparatus for television receivers comprising;
a saturable transformer including a ferromagnetic core forming a cubic magnetic loop path structure, said ferromagnetic core consisting of two ferromagnetic core pieces having four legs and two common portions, a controlled winding wound on the first and second ones of said four legs of the core, a control winding wound on the second and third ones of said four legs of the core, and a space gap means provided between said two ferromagnetic core pieces;
a deflection coil being connected in series with said controlled winding; and
a signal source for supplying a control parabolic signal to said control winding.
2. A pincushion distortion correction apparatus according to claim 1, wherein said two pieces constituting ferromagnetic core have respectively four legs and a common portion, and said space gap means is provided between the first and second legs of said two pieces of cores. 3. A pincushion distortion correction apparatus according to claim 1, wherein one piece of said ferromagnetic core has four legs and a common portion and the other core is a ferromagnetic core plate, and also wherein said space gap means is provided between the top of the first and second legs of said one core and said core plate. 4. A pincushion distortion correction apparatus for television receivers comprising;a saturable transformer including a ferromagnetic core forming a cubic magnetic loop structure, said ferromagnetic core consisting of two core pieces and, said cubic magnetic loop having four magnetic legs and two common portions, a horizontal winding wound on the first and second legs of the core, a vertical winding wound on the second and third legs of the core, and a space gap means provided between said first and second legs of one of the ferromagnetic core pieces and the other core piece;
a horizontal deflection coil connected in series with said horizontal winding; and
a signal source for supplying a vertical parabolic signal to said vertical winding.
5. A pincushion distortion correction apparatus according to claim 4, wherein said two pieces constituting the ferromagnetic core each have four legs and a common portion, and also wherein said space gap means is provided between the first and second one of the four legs of one of the core pieces on one hand and the corresponding legs of the other core piece on the other hand, and third and fourth legs of the two cores are in direct contact. 6. A pincushion distortion correction apparatus according to claim 4, wherein one of said core pieces of the ferromagnetic core has four legs and a common portion and the other core piece is a plate, and also wherein said space gap means is provided between the first and second ones of said four legs of said one of core pieces on one hand and said plate core piece on the other hand.BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to pincushion distortion correction apparatus and, more particularly, to an apparatus to this end having a control coil and a controlled coil, these coils being coupled to a saturable magnetic core in a perpendicular relation to each other.
2. Description of the Prior Art
A prior-art saturable reactor apparatus for correcting pincushion distortion in a television receiver has a construction as shown in FIG. 1.
In the pincushion distortion correction transformer 21 shown in FIG. 1, saturable E and I type cores 22 and 23 are held in face to face relationship to each other with a predetermined gap l g provided between them, a control coil 27 is wound on a central leg 24 A of the E type core 22, and first and second controlled coils 28 B and 28 C are wound on the respective opposite end legs 24 B and 24 C of the same core such that they operate differentially with respect to each other. For correcting horizontal pincushion distortions, a parabolic current changing at the vertical scanning frequency is caused through the control coil 27 to modulate the horizontal deflecting current flowing through the controlled coils 28 B and 28 C , thus obtaining a correction such that the horizontal deflection current becomes maximum at the center of the vertical scanning portion. The inductance L H of the transformer 21 is given as ##EQU1## where N H1 and N H2 are respectively turns numbers of the first and second controlled coils 28 B and 28 C (N H1 =N H2 ), l is the average length of the magnetic path, S is the sectional area of the core, and μ e is the effective magnetic permeability while μO is the magnetic permeability of a vacuum.
FIG. 2 shows a pincushion distortion correction transformer disclosed in a earlier patent application filed by the same applicant, and it is mentioned here for the purpose of faccilitating the understanding of the present invention. In this transformer 31, a control coil 37 and a controlled coil 38 are wound in a perpendicular relation to each other on legs 34 and 35 of a pair of four leg cores 32 and 33. The core 32 has a square or rectangular plate-like base portion 34 E and four legs 34 A to 34 D extending from the four corners of the base portion. The four legs have equal sectional area. Likewise, the core 33 has a base portion 35 E and four legs 35 A to 35 D . In FIG. 2, the legs 34 D and 35 D are concealed and not shown. The cores 32 and 33 having this construction are held such that the ends of the legs 34 A to 34 D of the former are respectively brought into contact with the corresponding legs 35 A to 35 D of the latter through predetermined gaps to define a constant space l g . The control coil 37 is wound on the legs 34 B and 34 D of the core 32 as a set, and the controlled coil 38 is wound on the legs 35 A and 35 B of the core 33 as a set. The inductance of this perpendicular transformer 31 is given as ##EQU2## N H in equation (2) is the turns number of the controlled coil 38 having almost half the turns of FIG. 1, and this means that for the example in FIG. 2 substantially the same variable inductance characteristic can be obtained with one half the turns number compared with the prior-art example of FIG. 1.
However, these pincushion distortion correction saturable reactor apparatus shown in FIGS. 1 and 2, have disadvantages; for example, raster shrinkage occurs in the neighborhood of the center of the screen, and the horizontal linearity is inferior.
FIG. 3 is a graph showing the variable inductance characteristic of the perpendicular transformer 31 shown in FIG. 2. In this graph, the abscissa represents the horizontal deflecting current I H (in A), and the ordinate represents the inductance L H (in μH). The vertical deflecting current I V (in mA) is taken as the parameter, and characteristic curves for 0,10,20,40 mA respectively are shown. When the inductance characteristic is as shown in FIG. 3, the reproduction on the screen has a character as shown in FIG. 4. The reproduction shown in FIG. 4 is obtained when a reference pattern consisting of a plurality of uniformly spaced vertical lines is reproduced on the television screen after the horizontal pincushion distortion correction using the transformer 31 mentioned above. The ratio of the interline space in the reproduction of FIG. 4 with respect to the interline average space in the reference pattern (in %) is as shown in FIG. 5. It will be seen that the raster shrinkage is produced in the neighborhood of the center of the screen, particularly in a horizontal deflecting current region between from -1 to +1 A. Due to this shrinkage, the horizontal linearity is inferior. Therefore the dynamic range of the variable inductance defined by the DC superimposition characteristics thereof becomes narrow.
SUMMARY OF THE INVENTION
The present invention seeks to overcome the aforementioned drawback inherent in the prior art, and its object is to provide a pincushion distortion correction saturable reactor apparatus, which is simple in construction and can improve the variable inductance characteristic and preclude the distortion of deflection in the neighborhood of the center of the reproduction, thus permitting wide improvement of the horizontal linearity and extension of the DC superimposition variable inductance dynamic range.
In accordance with an aspect of present invention, the apparatus for correcting pincushion distortion comprises a core having a gap, a control coil and a controlled coil, the control and controlled coils being wound on the core in a perpendicular relation to each other, the gap having an unbalanced configuration in the path of magnetic flux produced by the controlled coil, the control coil supplying a parabolic current for pincushion distortion correction, and the controlled coil supplying a deflecting current to be corrected.
The above and other objects, features and advantages of the illustrated embodiments of the invention will appear from the description given below, which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view showing a prior art example.
FIGS. 2 through 5 illustrate information concerning a transformer, given for the purpose of facilitating the understanding of the present invention, and of which FIG. 2 is a perspective view of the transformer;
FIG. 3 is a graph showing the variable inductance characteristic in FIG. 1 or 2;
FIG. 4 is a plan view showing the reproduction on a television screen in example FIG. 1 or 2;
FIG. 5 is a graph showing the horizontal linearity;
FIGS. 6 and 7 show a first embodiment of the present invention, and of which FIG. 6 is a perspective view showing the apparatus before the assembly, and FIG. 7 is a perspective view showing the apparatus after the assembly.
FIGS. 8 through 13 show a second embodiment of the present invention, and of which FIG. 8 is a perspective view showing the apparatus before the assembly thereof, FIG. 9 is a perspective view showing the apparatus after assembly, FIG. 10 is a fragmentary perspective view of the apparatus for illustrating the operation thereof, FIG. 11 is a graph showing the variable inductance characteristic, FIG. 12 is a plan view showing the reproduction on a television screen, and FIG. 13 is a graph showing the horizontal linearity.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Now, a preferred embodiment of the present invention will be described in conjunction with some preferred embodiments thereof with reference to the accompanying drawings.
FIGS. 6 and 7 show a first embodiment of the pincushion distortion correction saturable reactor apparatus 1 according to the present invention. FIG. 6 shows a perspective view of the apparatus before the assembly thereof, and FIG. 7 shows a perspective view of the apparatus after assembly. In these Figures, the apparatus comprises cores 2 and 3 having an identical shape and made of a ferrite material. The core 2 has a plate-like base portion 4 E , for instance having a square or rectangular shape, and four legs 4 A ,4 B ,4 C and 4 D perpendicularly projecting from the four corners of one side of the base portion and having an equal sectional area. Likewise, the other core 3 has a base portion 5 E and four leg portions 5 A ,5 B ,5 C and 5 D . These cores 2 and 3 are arranged such that the legs 4 A to 4 D of the former abut on the corresponding legs 5 A to 5 D of the latter. More particularly, an adjacent two of the four legs of the core 2, for instance legs 4 A and 4 B are coupled to the corresponding legs of the other core, for instance legs 5 A and 5 B via a spacer 6. Thus, the faces of the legs facing each other are inclined with respect to each other, and the gap is increased toward the reader. The thickness of the spacer 6 is set substantially to 2 l g , i.e., double the gap interval l g in the afore-mentioned prior-art construction. A control coil 7 is wound on a pair of legs, namely the leg 4 B of the core 2 in contact with the spacer 6 and the leg 4 D adjacent to the leg 4 B but not in contact with the spacer 6. A controlled coil 8 is wound on a pair of legs 5 A and 5 B of the other core 3 in contact with the spacer 6. Alternatively, the controlled coil 8 may be wound on pair legs 5 C and 5 D which are not in contact with the spacer 6. The magnetic flux produced by the current through the control coil 7 passes through a loop constituted by the legs 4 A and 5 A and legs 5 B and 4 B. The magnetic flux produced by the current through the controlled coil 8 passes through a loop constituted by the legs 4 A and 5 A and legs 5 C and 4 C . Since the facing faces of the individual pairs of legs constituting the path of magnetic flux set up by the controlled coil 8 are inclined due to the spacer 6 interposed between the legs 4 A and 5 A and also between the legs 4 B and 5 B , the gap between these facing surfaces is increased toward the reader in the FIG. 7, that is, the gap formed in the path of magnetic flux set up by the controlled coil 8 has an unbalanced form. In the afore-mentioned prior-art example (shown in FIG. 2), in which the facing surfaces of the individual pair legs are parallel, the gaps in the magnetic flux paths for both the control and controlled coils are balanced in form.
FIGS. 8 through 10 show a second embodiment of the present invention. In this embodiment of the pincushion distortion correction saturable reactor apparatus 11, a pair of cores 12 and 13 which have different shapes are used. The assembled form of the pincushion distortion saturable reactor apparatus 11 is practially the same as the apparatus of the first embodiment, but this embodiment is different from the first embodiment in the position, in which the core halves of the apparatus are coupled to each other, and the assembly can be more readily made.
More particularly, referring to FIGS. 8 and 10, the core 12 has a base portion 14 E , for instance having a square or rectangular shape, and four legs 14 A ,14 B ,14 C and 14 D perpendicularly projecting from the four corners of the base portion and somewhat a greater length (capable of accommodating two coils). The core 13, on the other hand, consists of a square or rectangular plate corresponding to the base portion of cores in the first embodiment.
These cores 12 and 13 are arranged such that they abut on each other with a spacer 6 provided in contact with two adjacent legs 14 A and 14 B of the core 12 to form a gap of an unbalanced form for the controlled coil 8. The coil 7 is wound on the set of legs 14 B and 14 D , and the controlled coil 8 is wound on a set of legs 14 A and 14 B in contact with the spacer 6. In this construction, the gap in the magnetic flux path for the controlled coil 8 varies for different portions of the facing surfaces and thus has an unbalanced form.
In the use of the first and second embodiments for the lateral pincushion distortion correction, parabolic current I V containing an appropriate DC bias is supplied to the control coil 7, and horizontal deflecting current I H is supplied to the controlled coil 8. In this case, the turns number N V of the control coil 7 is selected relatively large to reduce the exciting current I V so that a flux φ V within a saturating region is produced by the magnetizing force N V I V . For the control coil 8 a large diameter wire is used, and its turns number N H is set to a value necessary for obtaining the required variable inductance for the lateral pincushion distortion correction.
The first and second embodiments having the above constructions according to the present invention operate practically in the same way, so the operation of the second embodiment only will be described.
The flux φ V produced by the current I V through the control coil 7 passes through the leg 14 B , base portion 14 E and leg 14 A of the core 12 and the core 13 as shown by dashed arrows in FIG. 9. Also, although not shown, a flux is caused to pass through the leg 14 D , base portion 14 E and 14 C of the core 12 and core 13. On the other hand, the flux φ H produced by the current I H through the controlled coil 8 passes through a loop constituted by the leg 14 A , base portion 14 E and leg 14 C of the core 12 and the core 13 as shown by solid arrows in FIG. 9. These fluxes φ V and φ H do not link with each other, so that no induction voltage is produced. Thus, by causing a parabolic current at the vertical scanning frequency to flow through the control coil 7, the inductance of the controlled coil 8 can be varied to obtain the correction of the lateral pincushion distortion.
Now, the effects of the gap having the unbalanced form will be described. In a state when the magnetomotive force N V I V provided by the control coil 7 is less than the magnetomotive force N H I H provided by the controlled coil 8 (i.e., N V I V H I H ), the flux through the four legs 14 A to 14 D , and hence the magnetic permeability, is controlled by the magnetomotive force N H I H . Thus, in the neighborhood of the end faces of the legs 14 C and 14 D free from the spacer 6, the magnetic saturation in the core sets gradually in from the contact points of the legs 14 C and 14 D with the core 13, and substantially the similar variable inductance characteristic as that obtained with the balanced gap perpendicular transformer 31 shown in FIG. 2 can be obtained.
On the other hand, in a state when the magnetomotive force N V I V is greater than the magnetomotive force N H I H (i.e., N V I H >N H I H ), the saturation of the core in the neighborhood of the gaps defined by the end faces of the legs 14 C and 14 D is determined by the magnetomotive force N V I V . For the flux φ V , most flux flows in one loop through the legs 14 C and 14 D , because the other magnetic loop which includes the legs 14 A and 14 B has two wide gaps, therefore the magnetic reluctance of this loop is larger than that of the former. Therefore the large flux φ V concentrates at the contact points of the legs 14 C and 14 D . The concentration of flux makes the points saturate and, the saturated points act as the effective gaps. With the saturation in the neighborhood of the gaps defined by the legs 14 C and 14 D , the magnetic reluctance of the gaps is apparently increased. Also, the distance of the gap in the magnetic flux path for the controlled coil 8 is increased in the gaps defined by the legs 14 C and 14 D . The flux φ H and the apparent gap Δl g are shown in FIG. 10.
With the apparent increase of the magnetic reluctance (i.e., increase of the gap distance), the inductance is reduced to L H , which is expressed as ##EQU3## where l is the average length of magnetic path, S is the sectional area of the core, and μ e is the effective permeability, while μ O is the permeability of a vacuum.
FIG. 11 shows the variable inductance characteristics of the pincushion distortion correction saturable reactor apparatus having the above construction. In the graph of FIG. 11, the ordinate is taken as the variable inductance L H ' in μH, and the abscissa is taken as the horizontal deflecting current I H in A. Characteristic curves shown are obtained when the vertical parabolic current I V is respectively 0,10,20 and 40 mA. These characteristic curves have substantially M-shaped forms with the variable inductance L H , reduced in an I H range in the neighborhood of 0 corresponding to the central portion of the screen. Thus, in the reproduction, the deflectional distortion in the central portion of the television screen can be widely improved as shown in FIG. 12. FIG. 12 is similar to FIG. 4, showing the reproduction of a reference pattern consisting of uniformly spaced vertical lines. In this case, extremely improved horizontal linearity compared with that shown in FIG. 5 can be obtained as shown in FIG. 13. Also, the dynamic range for the control coil current I V and controlled coil current I H can be increased. Further, with the same outer case size and current I H , a larger CRT size correction is possible even with a reduced value of current I V . Furthermore, with the same amplitude of control current, a larger CRT where the horizontal deflecting current is higher is possible to correct.
The characteristics of the prior-art reactor apparatus of FIG. 1, as shown in FIGS. 3 through 5, and the characteristics of the reactor apparatus according to the present invention, as shown in FIGS. 11 through 13, are based upon data obtained from experiments using a 20-inch color television receiver with a deflection angle of 100 degrees for 10% pincushion distortion correction. The relevant conditions and performance are shown in table 1.
A signal source means S is indicated in FIG. 7 for supplying a control parabolic signal to the control winding 7, and a deflection coil means D is indicated in FIG. 7 as being connected in series with the controlled winding 8, for the sake of diagrammatic illustration.
| TABLE 1 |
| ______________________________________ |
| Present Item Invention Prior Art |
| ______________________________________ |
Core Data Gap 75μ (unbalanced) 38 (balanced) N V /N H (turns ratio) 1200 T /16 T 900 T /9 T + 9 T Outer dimensions 18 × 18 × 22 mm 19 × 21.5 × 30 mm of core Volume of core 4608 mm 3 9747 mm 3 Total weight 38.5 g 58.5 g Performance Horizontal linearity +1.4%.about.-2.7% +6.3%.about.-5.7% Controlled power 0.6 W 0.8 W Heat generation 20° C. 30° C. from core |
| ______________________________________ |
The data listed in Table 1 for the present invention are for the second embodiment. According to the present invention, the volume of the apparatus can be reduced to 0.58 times that of the prior-art apparatus. Also, the total weight can be reduced to 0.66 times that in the case of the prior art. Further, in the performance, the horizontal linearity can be improved, and the heat dissipation of the core can be reduced.
As has been described in the foregoing, with the pincushion distortion correction saturable reactor apparatus according to the present invention, which is a saturable transformer comprising a core having four legs and respective common portions (such as 4E, 5E, FIG. 7, and 13, 14E, FIG. 9), and controlled and control coils coupled to the core legs in a perpendicular relation to each other, the core gap for the controlled coil is provided in an unbalanced form, and a parabolic current at the vertical scanning frequency (or at horizontal scanning frequency) containing a superimposed DC component is caused, through the control coil, thus modulating the inductance of the controlled coil.
By the unbalance of the gap is meant that the gap distance varies with different portions of the facing surfaces defining the gap. This can be obtained by interposing a spacer between two of the four legs on which the controlled coil is wound as mentioned above or between the other two legs so that the surfaces forming the gap are inclined with respect to each other.
With this construction, the variable inductance is reduced in a region in which the magnetomotive force produced by the control coil is greater than that produced by the controlled coil and, as a whole, characteristic curves having M-shaped forms can be obtained. Thus, the deflectional distortion in the neighborhood of the center of the reproduction on the screen is reduced, so that horizontal linearity can be widely improved. In addition, the dynamic range of the variable inductance inclusive of the superimposed DC portion is extended, so that it is possible to obtain size reduction and wide cost reduction compared with the prior art. Further, it is possible to realize the reduction of heat dissipation of the core, reduction of the controlled power, reduction of the number of component parts connected to the transformer and also reduction of the area of the printed circuit board occupied by the transformer.
The above embodiments of the present invention are by no means limitative, and the invention may be applied to the top and bottom pincushion distortion correction as well. Also, various other changes and modifications are possible without departing from the scope and spirit of the present invention.
An automatic frequency control (AFC) circuit is disclosed which comprises an oscillating circuit for generating repetitive pulses, a generator for generating comparison signals having a slope portion in response to the repetitive pulses, and a phase comparison circuit which compares the comparison signals, and synchronous (sync) signals and based on the comparison supplies control signals to the oscillating circuit. The AF circuit further comprises a limiting circuit connected between the comparison signal generator and the phase comparison circuit which limits the maximum and minimum levels of the
comparison signals to predetermined levels, and thereby predeterminedly limits the control range of the AFC circuit. 1. An automatic frequency control signal generating circuit, comprising:
an oscillating circuit for generating repetitive pulses;
means for receiving said repetitive pulses and generating comparison signals having sloped portions and maximum and minimum levels in response to said repetitive pulses;
a source of reference signals;
phase comparison means having a first input terminal supplied with said comparison signals, a second input terminal supplied with said reference signals and an output terminal for supplying automatic frequency control signals to said oscillating circuit for controlling its frequency within a control range; and
limiting means connected between said comparison signal generating means and said phase comparison means for limiting said maximum level and said minimum level of said comparison signals to first and second predetermined levels respectively, thereby limiting said control range of said automatic frequency control signal generating circuit to a predetermined range.
2. An automatic frequency control signal generating circuit according to claim 1; wherein said comparison signal generating means comprises integrating means for generating saw-tooth wave signals as said comparison signals in response to said repetitive pulses. 3. An automatic frequency control signal generating circuit according to claim 1; wherein said limiting means comprises a series circuit including sources of first and second reference potentials, first and second diodes connected together and respectively connected to said first reference potential and said second reference potential, the connecting point of said first and second diodes being connected to an output terminal of said comparison signal generating means. 4. An automatic frequency control signal generating circuit for a television receiver, comprising;a source of reference signals;
an oscillator for generating control pulses;
an output circuit for producing repetitive pulses in response to said control pulses;
an integrating circuit for generating saw-tooth wave signals having maximum and miniumum levels in response to said repetitive pulses from said output circuit;
a phase comparator for comparing the phase of said saw-tooth waves and the phase of said reference signals, and supplying output signals to said oscillator as automatic frequency control signals; and
an amplitude limiting circuit connected between said integrating circuit and said phase comparator, for limiting said maximum and minimum levels of said saw-tooth wave signals to first and second predetermined levels.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an automatic frequency control (AFC) circuit and more particularly to an AFC circuit, preferably is used in a television receiver, which has a predeterminedly limited control range.
2. Description of the Prior Art
I
n a prior art horizontal AFC circuit of a television receiver, as shown in FIG. 1, the output from a horizontal oscillator 1 which can be, for example, a control pulse is supplied to a horizontal output circuit 2 and a flyback pulse therefrom is fed to a saw-tooth wave generator 3. Though not shown, the horizontal output circuit 2 comprises a deflection circuit and a high voltage generating circuit. The saw-tooth wave signal from saw-tooth wave generator 3 is supplied, as a comparison signal, to a phase comparator 4 which is also supplied with a horizontal synchronizing (sync) signal H through a terminal 5. In phase comparator 4 the saw-tooth wave signal is compared with the horizontal sync signal H to detect the phase difference between the saw-tooth wave signal and the horizontal sync signal. The detected phase difference is applied to horizontal oscillator 1 as an AFC voltage e c . As shown in FIG. 2, when the horizontal sync signal H is coincident with the center φ 0 of the downward sloping portions of the comparison signal, that is, when the phase difference between the comparison and sync signals is 0 (zero), the synchronization is maintained for phase differences of which corresponds to the ends of the downward sloping portion of the comparison signal. For phase differences of ±φ cm , the AFC output voltage e c has a maximum value of ±e cm .
If the AFC control sensitivity is taken as β, the maximum frequency range within which the f cm oscillating frequencies are controlled, hereinafter referred to as the control range, is: f cm =±2πβe cm
When the value of e cm in the above formula is need constant, regardless of frequency variation, then the value of f cm is constant.
Generally, the comparison signal, which is supplied by saw-tooth wave generator 3, is provided by integrating the flyback pulse. Both the width of the flyback pulse, which is determined by an LC resonance of horizontal output circuit, and the inclination of the rising portion of the comparison signal, which is determined by an RC time constant of the sawtooth generator, are constant. Therefore, the value of e cm varies with the frequency resulting in a variable value of f cm .
For example, as shown throughout FIGS. 3A, 3B, and 3C, both the width of the downward sloping portion and the inclination of the rising portion of the comparison signals are constant. As a result, when the frequency becomes high (FIG. 3A) as compared with its reference state (FIG. 3B), the value of e cm becomes small as represented by e' cm and when the frequency becomes low (FIG. 3C) as compared with the reference state (FIG. 3B), the value of e cm becomes large as represented by e" cm .
Therefore, when the frequency of the horizontal output signal is high, the differences between the minimum and maximum control signal amplitudes, hereinafter referred to as the amplitude range become smaller resulting in a reduced control range f cm . In contrast thereto, when the frequency of the horizontal oscillator signal is low, the amplitude range becomes larger resulting in an increase of control range f cm .
Typically for a variable control range as described heretofore, the AFC circuit is designed with the smaller control range, corresponding to high oscillating frequencies, as a reference. Such a reference, however, results in the control range at lower oscillating frequencies becoming either too large or at least larger than necessary.
When the control range at the lower oscillating frequencies is too large, the amplitudes of the control signals, that is, the values of ±e cm , are too high or low to be applied to horizontal oscillator 1 and thereby results in an unacceptable frequency correction. Such unacceptably high or low values of e cm can occur, for example, when the sync signal disappears during switching of television channels resulting in the oscillating frequency becoming too low and thereby creating a voltage in the horizontal output circuit that is abnormally high. Therefore, it is necessary that the control range of the AFC circuit be made as small as possible for lower frequencies.
Further, if the control range is too large, the AFC circuitry may unnecessarily adjust the oscillating frequency when noise is present on a weakly received signal.
Accordingly, an AFC circuit should necessarily have as small a control range as possible. Such a small control range is possible by providing maximum and minimum values of e cm irrespective of frequency variation.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an AFC circuit which avoids the drawbacks of the prior art.
More specifically, it is an object of the present invention to provide a new and improved AFC circuit whose control range is constant.
It is another object of the present invention to provide a new and improved AFC circuit which limits the maximum and minimum values of the amplitude range.
According to an aspect of the present invention, an AFC circuit comprises:
an oscillating circuit for generating repetitive pulses;
means for receiving said repetitive pulses and generating comparison signals having a slope portion and maximum and minimum levels in response to said repetitive pulses, said generating means having an output terminal;
a source of reference signals;
phase comparison means having a first input terminal supplied with said comparison signals, a second input terminal supplied with said reference signals and an output terminal for supplying said automatic frequency control signal to said oscillating circuit for controlling its frequency within a control range; and
limiting means connected between said comparison signal generating means and said phase comparison means for limiting said maximum level and said minimum level of said comparison signals to first and second predetermined levels respectively, thereby limiting said control range of said automatic frequency control signal generating circuit to a predetermined range.
The above, and other objects, features and advantages of the present invention will become apparent from the following description which is to be read in conjunction with the accompanying drawings, in which like reference numerals designate like elements and parts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a prior art AFC circuit;
FIG. 2 and FIGS. 3A to 3C are waveform diagrams used to explain the operation of the prior art circuit shown in FIG. 1;
FIG. 4 is an embodiment of saw-tooth wave generating and limiter circuitry in accordance with the present invention;
FIGS. 5A, 5B, and 5C illustrate respectively input and output waveforms of the saw-tooth wave generator and the output waveform of the limiter shown in FIG. 4;
FIG. 6 is an alternative embodiment of circuitry which replaces the circuitry of FIG. 4 and produces a comparison signal in accordance with the present invention; and
FIGS. 7A and 7B illustrate respectively an input waveform supplied to and an output waveform produced by the circuitry shown in FIG. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention will be hereinafter described with reference to the attached drawings.
FIG. 4 includes an in
put terminal 11 connected to horizontal output circuit 2 (not shown) and an input capacitor 12. Input capacitor 12 is connected to resistors 13 and 14. Capacitor 12 and resistors 13 and 14 form a bias circuit which biases a base of an NPN-type transistor 15. Transistor 15 has a grounded emitter and a collector connected through a resistor 16 to a power supply terminal 17 which is at a voltage V cc and through a series connection of a resistor 18 and a capacitor 19 to ground. The connection point between resistor 18 and capacitor 19 is connected to power supply terminal 17 through a series connection of a capacitor 20 and a resistor 21. The connection point of capacitor 20 and resistor 21 is connected to power supply terminal 17 through a resistor 22 and a diode 23 wherein the cathode and anode of diode 23 are respectively connected to terminal 17 and resistor 22. The connection point of capacitor 20 and resistor 21 is also connected to ground through resistor 22 and a series connection of a diode 24 and a capacitor 25 which is grounded wherein the cathode and anode of diode 24 are respectively connected to the connection point of resistor 22 and diode 23 and to capacitor 25. The connection point of diode 24 and capacitor 25 is connected to the connection point of voltage dividing resistors 26 and 27. Resistors 26 and 27 are connected between terminal 17 and ground. The connection point between diodes 23 and 24 is connected to a base of an NPN-type transistor 28 whose collector is connected to power supply terminal 17 and whose emitter is grounded through a resistor 29 and connected to an output terminal 30. Output terminal 30 is connected to an input terminal of phase comparator 4 (not shown).
Diodes 23 and 24 form a limiter circuit and capacitor 25 and resistors 26 and 27 form a direct current (d.c.) voltage source having a voltage level of E.
When a repetitive pulse, such 
as a flyback pulse, as shown in FIG. 5A, is applied to input terminal 11, a saw-tooth wave (FIG. 5B) is generated at the connection point of capacitor 20 and resistor 22 which in turn is fed to the limiter circuit which produces a waveform as shown in FIG. 5C. That is, the value e cm is limited to an upper level V cc +V D and a lower level E-V D (where V D is the forward voltage drop of diodes 23 and 24).
Since the value e cm is within a fixed range, the control range is constant resulting in a desired control range which is fixed regardless of frequency. That is, the present invention provides a control range which is constant irrespective of the frequency and thereby avoids the possibility of an unnecessary expansion of the control range at low frequencies and the resulting erroneous operation caused by the expanded control range.
An alternative embodiment of the present invention is shown in FIG. 6 which includes input terminal 11 connected through capacitor 12 to the base of a PNP-type transistor 31, which is biased by the resistors 13 and 14. Transistor 31 has an emitter connected to power supply terminal 17 and collector grounded through a parallel circuit of a resistor 32 and a capacitor 33. The collector of transistor 31 is also connected through a series connection of a capacitor 34 and a resistor 35 to an emitter of an NPN-type transistor 36. A base of transistor 36 is connected to a voltage dividing point of resistors 37 and 38 and a collector thereof is connected to power supply terminal 17 through a resistor 39. An emitter of transistor 36 is grounded through a resistor 40. Output terminal 30 is connected to the collector of transistor 36.
A repetitive pulse, such as a flyback pulse as shown in FIG. 7A, is supplied from the horizontal output circuit 2 and is applied to the input terminal 11. During those periods of each cycle when there is no flyback pulse, transistor 31 turns ON which charges capacitor 33 resulting in voltage at the emitter of transistor 36 rising and thereby causing transistor 36 to turn OFF. During periods when transistor 36 is turned off, output terminal 30 is at a voltage level of V cc as shown in FIG. 7B. During that portion of each cycle when a flyback pulse occurs, transistor 31 turns OFF, allowing capacitor 33 to discharge through resistor 32. As a result, the potential at the emitter of transistor 36 gradually lowers and transistor 36 turns ON resulting in the output voltage at output terminal 30 gradually lowering to ground potential. When the period of the flyback pulse terminates, once again transistors 31 turns ON, charging capacitor 33 immediately, turning transistor 36 OFF and charging the voltage at output terminal 30 to V cc . That is, a signal is produced having a magnitude of V cc when the flyback pulse is absent and gradually lowering to ground potential during the flyback pulse period.
Thus the comparison signal, e cm , magnitude is restricted to a range between V cc and ground potential and thereby provides a desired control range regardless of the frequency. More particularly, in either embodiment the present invention provides a predetermined control range.
The present invention, as described heretofore has used the downward sloping portion of the comparison signal during phase comparison with a reference signal. However, the present invention can be applied as well to circuitry which provides a comparison signal having a rising slope portion during flyback pulse periods wherein control signal e cm is selected from the rising slope portion.
Although illustrative embodiments of this invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.
SONY DST EHT FBT TRANSFORMER Bobbin structure for high voltage transformers EHT Output.
A coil bobbin for a fly-back transformer or the like having a bobbin proper. A plurality of partition members or flanges are formed on the bobbin proper with a slot between adjacent ones. At least first and second coil units are formed in the bobbin proper, each having several slots, formed between the flanges, and first and second high voltage coils are wound on the first and second coil units in opposite directions, respectively. A rectifying means is connected in series to the first and second coil units, and a cut-off portion or recess is provided on each of the partition members. In this case, a wire lead of the coil units passes from one slot to an adjacent slot through the cut-off portion which is formed as a delta groove, and one side of the delta groove is corresponded to the tangent direction to the winding direction.
1. A fly-back transformer comprising a coil bobbin comprising a plurality of parallel spaced discs with a first adjacent plurality of said disc formed with delta shaped slots having first edges which extend tangentially to a first winding direction and a first winding wound on said first adjacent plurality of said discs in said first winding direction, a second adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to a second winding direction opposite said first winding direction and a second winding wound on said second adjacent plurality of said discs in said second winding direction, a third adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to said first winding direction and a third winding wound on said third adjacent plurality of said discs in said first winding direction and said second plurality of adjacent discs mounted between said first and third plurality of adjacent discs. 2. A fly-back transformer according to claim 1 wherein adjacent ones of said first adjacent plurality of discs are mounted such that their delta shaped slots are orientated 180 degrees relative to each other. 3. A fly-back transformer according to claim 2 including a first winding turning partition mounted between said first and second adjacent plurality of discs and formed with grooves and notches for changing winding direction between said first and second windings and a second winding turning partition mounted between said second and third adjacent plurality of discs and formed with grooves and notches for changing the winding direction between said second and third windings. 4. A fly-back transformer according to claim 3 wherein said first and second winding turning partitions are formed with winding guiding slots for guiding the winding between the first, second and third adjacent plurality of discs. 5. A fly-back transformer according to claim 2 including a first rectifying means connected between one end of said first winding and one end of said second winding, and a second rectifying means connected between the second end of said second winding and one end of said third winding. 6. A fly-back transformer according to claim 5 wherein the second end of said first winding is grounded and a third rectifying means connected between the second end of said third winding and an output terminal.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a bobbin structure for high voltage transformers, and is directed more particularly to a bobbin structure for high voltage transformer suitable for automatically winding coils thereon.
2. Description of the Prior Art
In the art, when a wire lead is reversely wound on a bobbin separately at every winding block, a boss is provided at every winding block and the wire lead is wound on one block, then one end of the wire lead is tied to the boss where it will be cut off. The end of the wire lead is tied to another boss, and then the wire lead is wound in the opposite direction. Therefore, the prior art winding method requires complicated procedures and the winding of the wire lead cannot be rapidly done and also the winding can not be performed automatically. Further, the goods made by the prior art method are rather unsatisfactory and have a low yield.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly an object of the invention is to provide a coil bobbin for a fly-back transformer or the like by which a wire lead can be automatically wound on winding blocks of the coil bobbin even though the winding direction is different among the different winding blocks.
Another object of the invention is to provide a coil bobbin for a fly-back transformer or the like in which a bridge member and an inverse engaging device for transferring a wire lead from one wiring block to an adjacent wiring block of the coil bobbin and wiring the wire lead in opposite wiring directions between adjacent wiring blocks, and a guide member for positively guiding the wire lead are provided.
According to an aspect of the present invention, a coil bobbin for a fly-back transformer or the like is provided which comprises a plurality of partition members forming a plurality of slots, a first coil unit having several slots on which a first high voltage coil is wound in one winding direction, a second coil unit having several slots on which a second high voltage coil is wound in the other direction, a rectifying means connected in series to the first and second coil units, and a cut-off portion provided on each of the partition members, a wire lead passing from one slot to an adjacent slot through the cut-off portions, each of the cut-off portions being formed as a delta groove, and one side of the delta groove corresponding to a tangent to the winding direction.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like reference numerals and letters designate the same elements and parts, respectively.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the construction of a fly-back transformer;
FIG. 2 is a connection diagram showing an example of the electrical connection of the fly-back transformer shown in FIG. 1;
FIG. 3 is a schematic diagram showing an example of a device for automatically winding a wire lead of the fly-back transformer on its bobbin;
FIG. 4 is a perspective view showing an example of the coil bobbin according to the present invention;
FIG. 5 is a plan view of FIG. 4;
FIGS. 6 and 7 are views used for explaining recesses or cut-off portions shown in FIGS. 4 and 5; and FIGS. 8A and 8B cross-sectional views showing an example of the inverse engaging means according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
When the high voltage winding of a fly-back transformer used in a high voltage generating circuit of a television receiver is divided into plural ones and then wound on a bobbin, the divided windings (divided coils) are connected in serie
s through a plurality of rectifying diodes.
When the winding is divided into, for example, three portions, such as divided coils La, Lb and Lc, they are wound on a bobbin proper 1 from, for example, left to right sequentially in this order as shown in FIG. 1. In this case, if the divided coils La and Lc are selected to have the same sense of turn and the middle coil Lb is selected to have the opposite sense of turn from the coils La and Lc, the distance between the terminal end of coil La and the start of coil Lb and the distance between the terminal end of coil Lb and the start of coil Lc can be got relatively long. Therefore, diodes Da and Db can be mounted by utilizing the space above the block on which the middle coil Lb is wound as shown in FIG. 1, so that it becomes useless to provide spaces for diodes between the divided coils La and Lb and between the divided coils Lb and Lc and hence the bobbin proper 1 can be made compact.
FIG. 2 is a connection diagram showing the connection of the above fly-back transformer. In FIG. 2, reference numeral 2 designates a primary winding (Primary coil) of the fly-back transformer, reference letter L designates its high voltage winding (secondary coil), including divided coils La, Lb and Lc, 3 an output terminal, and 4 a lead wire connected to the anode terminal of a cathode ray tube (not shown), respectively.
An example of the bobbin structure according to the invention, which is suitable to automatically wind coils, which are different in sense of turn in each winding block as shown in FIG. 1, on the bobbin, will be hereinafter described with reference to the drawings.
FIG. 3 is a diagram showing an automatic winding apparatus of a wire lead on a coil bobbin. If it is assumed that the wire lead is wound in the order of w
inding blocks A, B and C in FIG. 1 and the wire lead is wound on the block A with the bobbin proper 1 being rotated in the counter-clockwise direction as shown in FIG. 3, the relation between the bobbin proper 1 and the wire lead becomes as shown in FIG. 3. In this figure, reference numeral 6 designates a bobbin for feeding the wire lead.
Turning to FIG. 4, an example 10 of the bobbin structure or coil bobbin according to the present invention will be described now. In this example, the winding blocks A, B and C for the divided coils La, Lb and Lc are respectively divided into plural slots or sections by plural partition members or flanges 11, and a cut-off portion or recess 12 is formed on each of the flanges 11 through which the wire lead in one section is transferred to the following winding section.
As shown in FIG. 6, each recess 12 is so formed that its one side extends in the direction substantially coincident with the tangent to the circle of the bobbin proper 1 and its direction is selected in response to the sense of turn of the winding or wire lead. In this case, the direction of recess 12 means the direction of the opening of recess 12, and the direction of recess 12 is selected opposite to the sense of turn of the wi
nding in the present invention.
Now, recesses 12A, which are formed in the winding block A, will be now described by way of example. The positions of recesses 12A formed on an even flange 11Ae and an odd flange 11A 0 are different, for example, about 180° as shown in FIGS. 6A and 6B. Since the bobbin proper 1 is rotated in the counter-clockwise direction in the winding block A and hence the sense of turn of the wire lead is in the clockwise direction, the recess 12A is formed on the even flange 11Ae at the position shown in FIG. 6A. That is, the direction of recess 12A is inclined with respect to the rotating direction of bobbin proper 1 as shown in FIG. 6A. In this case, one side 13a of recess 12A is coincident with the tangent to the circle of bobbin proper 1, while the other side 13b of recess 12A is selected to have an oblique angle with respect to the side 13a so that the recess 12A has a predetermined opening angle.
The opening angle of recess 12A is important but the angle between the side 13a of recess 12A and the tangent to the circle of bobbin proper 1 is also important in the invention. When the wire lead is bridged or transferred from one section to the following section through the recess 12A, the wire lead in one section advances to the following section in contact with the side 13a of recess 12A since the bobbin proper 1 is rotated. In the invention, if the side 13a of recess 12A is selected to be extended in the direction coincident with the tangent to the circle of bobbin proper 1, the wire lead can smoothly advance from one section to the next section without being bent.
In the invention, since the middle divided coil Lb is wound opposite to the divided coil La, a recess 12B provided on each of flanges 11B of the winding block B is formed to have an opening opposite to that of recess 12A formed in the winding block A as shown in FIGS. 6C and 6D.
As shown in FIG. 5, terminal attaching recesses 14 are provided between the winding blocks A and B to which diodes are attached respectively. In the illustrated example of FIG. 5, a flange 15AB is formed between the flanges 11A 0 and 11B 0 of winding blocks A and B, and the recesses 14 are formed between the flanges 11A 0 and 15AB and between 15AB and 11B 0 at predetermined positions. Then, terminal plates 16, shown in FIG. 4, are inserted into the recesses 14 and then fixed there to, respectively. The terminal plates 16 are not shown in FIG. 5. Between the winding blocks B and C and between the blocks A and B, similar terminal attaching recesses 14 are formed, and terminal plates 16 are also inserted thereinto and then fixed thereto.
As described above, since the divided coil Lb is wound opposite to the divided coils La and Lc, it is necessary that the winding direction of the wire lead be changed when the wire lead goes from the block A to block B and also from the block B to block C, respectively.
Turning to FIG. 7, an example of the winding or wire lead guide means according to the present invention will be now described. In FIG. 7, there are mainly shown a bridge member for the wire lead and an inve
rse member or means for the wire lead which are provided between the winding blocks A and B. At first, a bridge means 20 and its guide means 21, which form the bridge member, will be described. The bridge means 20 is provided by forming a cut-out portion or recess in the middle flange 15AB located between the winding blocks A and B. In close relation to the bridge means or recess 20, the guide means 21 is provided on a bridge section X A at the side of block A. This guide means 21 is formed as a guide piece which connects an edge portion 20a of recess 20 at the winding direction side to the flange 11A 0 of block A in the oblique direction along the winding direction through the section X A .
Next, an inverse engaging means 22 will be now described with reference to FIGS. 7 and 8. If the flange 11B 0 of FIG. 7 is viewed from the right side, the inverse engaging means 22 can be shown in FIG. 8A. In this case, the tip end of one side 13a of recess 12B 1 is formed as a projection which is extended outwards somewhat beyond the outer diameter of flange 11B 0 . The inverse engaging means 22 may take any configuration but it is necessary that when the rotating direction of the bobbin proper 1 is changed to the clockwise direction, the wire lead can be engaged with the recess 12B 1 or projection of one side 13a and then suitably transferred to the next station.
Another guide means 23 is provided on a bridge section X B at the side of winding block B in close relation to the inverse engaging means 22. The guide means 23 is formed as a guide surface which is a projected surface from the bottom surface of section X B and extended obliquely in the winding direction. This guide means or guide surface 23 is inclinded low into the means 22 and has an edge 23a which is continuously formed between the middle flange 15AB and the flange 11B 0 .
In this case, it is possible that the guide means 21 and guide surface 23 are formed to be the same in construction. That is, both the guide means 21 and 23 can be made of either the guide piece, which crosses the winding section or guide surface projected upwards from the bottom surface of the winding section. It is sufficient if the guide means 21 and 23 are formed to smoothly transfer the wire lead from one section to the next section under the bobbin proper 1 being rotated.
Although not shown, in connection with the middle flange 15BC between the winding blocks B and C, there are provided similar bridge means 20, guide means 21, inverse engaging means 22 and another guide means 23, respectively. In this case, since the winding direction of the wire lead is reversed, the forming directions of the means are reverse but their construction is substantially the same as that of the former means. Therefore, their detailed description will be omitted.
According to the bobbin structure of the invention with the construction set forth above, the wire lead, which is transferred from the block A to the section X A by the rotation of bobbin proper 1, is wound on the section X B from the section X A after being guided by the guide piece 21 to the recess 20 provided on the middle flange 15AB, and then transferred to the recess 22 provided on the flange 11B 0 guide surface 23, bridged once to the first section of winding block B through the recess 22 (refer to dotted lines b in FIG. 7). Then, if the rotating direction of the bobbin proper 1 is reversed, the wire lead is engaged with the bottom of recess 22 (refer to solid lines b in FIG. 7). Thus, if the above reverse rotation of bobbin proper 1 is maintained, the wire lead is wound on the block B in the direction reverse to that of block A. When the wire lead is transferred from the block B to block C, the same effect as that above is achieved. Therefore, according to the present invention, the wire lead can be automatically and continuously wound on the bobbin proper 1.
After the single wire lead is continuously wound on blocks A, B and C of bobbin proper 1 as set forth above, the wire lead is cut at the substantially center of each of its bridging portions. Then, the cut ends of the wire lead are connected through diodes Da, Db and Dc at the terminal plates 16, respectively by solder.
In the present invention, the projection piece, which has the diameter greater than that of the flange 11B, is provided in the bridge recess 12 to form the inverse engaging means 22 as described above, so that when the winding direction is changed, the wire lead engages with the inverse engaging means 22 without errors when reversing the winding direction of the wire lead.
If the diameter of the projection piece of means 22 is selected, for example, to be the same as that of the flange 11B, it will not be certain that the wire lead engages with the means 22 because it depends upon the extra length of the wire lead and hence errors in winding cannot be positively avoided.
Further, in this invention, the bridge means is provided on the flange positioned at the bridging portion of the bobbin which has a number of dividing blocks separated by flanges, and the inverse engaging means is provided and also the guide means is provided at the former winding section to cooperate with the inverse engaging means. Therefore, the wire lead can be positively fed to the bridge means, and the transfer of the wire lead to the following winding section can be carried out smoothly.
Further, in this invention since one side of the recess 12 is selected coincident with the tangent of the outer circle of the bobbin proper 1 and also with the winding direction, the wire lead can be smoothly bridged to the following section. Due to the fact that the direction of recess 12 is changed in response to the winding direction, even if there is a block on which the wire lead is wound in the opposite direction to that of the other block, the wire lead can be continuously and automatically wound through the respective blocks.
The above description is given for the case where the present invention is applied to the coil bobbin for the high voltage winding of a fly-back transformer, but it will be clear that the present invention can be applied to other coil bobbins which require divided windings thereon with the same effects.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention, so that the spirits or scope of the invention should be determined by the appended claims only.
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