BLAUPUNKT SCOUT COMMANDER IR16 COLOR P CHASSIS FM100-20GS INTERNAL VIEW

The CHASSIS FM100-20GS was fitted in many models type from BLAUPUNKT and SIEMENS brand types.

The CHASSIS FM100-20GS is developed by BLAUPUNKT-SIEMENS under joint venture with BOSCH.

This chassis is a complex type and it employs high quality components and it is highly engineered.

You will not find a dry joint on these chassis, soldering are Excellent even after 30 Years.


Was highly reliable but the Line output EHT Transformer was failing Very often causing from defocusing of picture to EHT discarge and even a no start of the tellye at all.

Basically the EHT Bleeder output was going "off limits" during aging landing to abnormal or no function at all.

Even the HR-DIEMEN replacement was failing since it was too much an exact replica !!!!!!


Tuning control Unit MEMOTRONIC 8668 302 620 B2620F2 ASIC AY-3-8203 TUNING Controller Miscellaneous Digital Circuit - ECONOMEGA II,A digital tuning system

+ U334M (TELEFUNKEN) REMOTE DECODER, Infrared Xmtr-Rcvr for Remote Control - Receiver,fcl 4MHz,Binary Code.


Even synchronization IC uses Hybrid IC Technology on Ceramic substrate.

And the Frame deflection driving / control circuitry IC uses Hybrid IC Technology on Ceramic substrate.



On a ceramic substrate, spiral-type inductors of a single layer wiring of a metal thin film are provided and respectively connected to a wiring pattern formed on another face of the substrate via through holes. A semiconductor chip is flip-chip mounted on the substrate in a face-down manner. On the face of the semiconductor chip, capacitors composed of a highly dielectric material, resistors formed by an ion implantation method or a thin-film forming method, and FETs are provided, respectively. Interconnection between the substrate and an external circuit board is achieved employing terminals formed at end faces of the substrate. The terminals have a concave shape with respect to the end face of the substrate. Thus, there is no need to use a package, and miniaturization and reduction in cost of a high-performance hybrid IC is achieved.

1. A hybrid IC comprising:
a substrate including a front face, a back face opposite the front face, and side faces interposed between the front face and the back face which define an outer perimeter of the substrate;
at least one inductor formed on at least one of the front face and the back face of the substrate;
a semiconductor chip mounted on the front face of the substrate by flip-chip bonding;
at least one terminal formed in a predetermined portion of the side faces of the substrate,
wherein the semiconductor chip comprises a plurality of circuit elements provided therein, at least one of the plurality of circuit elements being an MIM capacitor having a metal-insulation film-metal (MIM) structure, the insulation film being composed of a highly dielectric material.


2. A hybrid IC according to claim 1 further comprising at least one matching circuit for matching an input signal to the circuit elements provided inside the semiconductor chip, the matching circuit comprising at least one inductor.

3. A hybrid IC according to claim 2, wherein a wiring pattern is formed of a single metal layer on both the front and back faces of the substrate, the wiring patterns on the respective front and back faces of the substrate being interconnected with each other via through holes, and the at least one inductor comprised in the matching circuit is formed in the wiring pattern on one of the respective front and back faces of the substrate.

4. A hybrid IC according to claim 2, wherein the matching circuit is constituted only by inductors and comprises at least one serial inductor and at least one parallel inductor.

5. A hybrid IC according to claim 4, wherein the parallel inductor comprised in the matching circuit is a spiral-type inductor, outermost wiring of the spiral-type inductor being grounded.

6. A hybrid IC according to claim 2, wherein the inductors comprised in the matching circuit are a spiral-type inductor or a meander-type inductor.

7. A hybrid IC according to claim 2, wherein the matching circuit comprises an inductor and a capacitor, the capacitor being formed inside the semiconductor chip.

8. A hybrid IC according to claim 7, wherein the inductor comprised in the matching circuit is a spiral-type inductor or a meander-type inductor.

9. A hybrid IC according to claim 1, wherein the at least one terminal includes at least an RF terminal functioning as an input terminal for an RF signal, an LO terminal functioning as an input terminal for an LO signal, an IF terminal functioning as an output terminal for an IF signal, a ground terminal, and a supply terminal.


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- VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)


TDA3300 3301 TV COLOR PROCESSOR

This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).

Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.

The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.

It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.


90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.

ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.

4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.

Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.

Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.




BLAUPUNKT  SCOUT COMMANDER  IR16 COLOR P  CHASSIS FM100-20GS  Supply is based on TDA4600 (SIEMENS).

Power supply Description based on TDA4601d (SIEMENS)

TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.

Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.

Description:

The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.













The CHASSIS FM 100-20 CA delivers a totally uncommon Frame deflection system, derived from previous chassis types. (YEARS 1978)

Plus the E/W Correection circuit uses the same Technology.

It's a system called S.S.V.D. which stays for Synchronized Switched Vertical Deflection.

The system is highly reliable and does dissipate energy like linear amplifier types like A class or AB class Types and should not be confused with D Class amplifier.


Abstract:

In a switched vertical deflection circuit, two SCR switches couple horizontal retrace pulses to a capacitor. A modulator couples pulse width modulated gating pulses to the SCR's. The SCR's couple to the capacitor successively smaller portions of the horizontal retrace pulses during a first part of the vertical trace interval and successively larger portions during a second part for developing in a vertical deflection winding a sawtooth vertical deflection current. The modulator couples gating pulses to one of the SCR's during the vertical retrace interval for substantially loading the horizontal deflection circuit during the vertical retrace interval for preventing undesired oscillations within the horizontal deflection circuit.

What is claimed is:

1. A switched vertical deflection system comprising:
a horizontal deflection circuit including first means for generating horizontal rate energy signals;
a vertical deflection winding;
energy storage capacitance means coupled to said vertical deflection winding;
first and second switching means coupled to said first means and said energy storage capacitance means; and
second means coupled to said first and second switching means for switching conductive states of both of said switching means for coupling successively smaller portions of said horizontal rate energy signals to said energy storage capacitancemeans during a first part of a vertical trace interval and successively larger portions of said horizontal rate energy signals during a second part of said vertical trace interval for developing a vertical deflection current in said vertical deflectionwinding during said vertical trace interval,
said second means causing said first switching means to conduct during a vertical retrace interval for coupling substantial portions of said horizontal rate energy signals to said energy storage capacitance means during said vertical retraceinterval for preventing undesired oscillations within said horizontal deflection circuit.
2. A system according to claim 1 wherein said first and second switching means comprise controlled semiconductors, said second means coupling first and second signals to said first and second switching means for switching conductive states ofboth of said controlled semiconductors.
3. A system according to claim 2 wherein said second means includes transformer means for coupling said first signals to said first switching means.
4. A system according to claim 3 wherein said first switching means comprises a silicon controlled rectifier, a secondary winding of said transformer means coupled between the gate and cathode electrodes of said silicon controlled rectifier.
5. A system according to claim 2 including vertical signal means coupled to said second means for generating a vertical rate signal for modulating said first and second signals at a vertical rate.
6. A system according to claim 5 wherein said vertical signal means includes first circuitry for generating a component of said vertical rate signal that inhibits conduction of said second switching means during said vertical retrace interval.
7. A system according to claim 6 wherein said first circuitry comprises an RC differentiating circuit.
8. A system according to claim 7 wherein the time constant of said differentiating circuit is selected to provide a duration for said component of said vertical rate signal substantially equal to said vertical retrace interval.
9. In a television receiver including a horizontal deflection circuit comprising a horizontal deflection generator and a horizontal output transformer, a switched vertical deflection circuit comprising:
a vertical deflection winding;
energy storage capacitance means coupled to said vertical deflection winding;
first and second controllable switches coupled to said capacitance means and to respective secondary windings of said horizontal output transformer for coupling horizontal retrace signals to said capacitance means; and
a modulator coupled to said first and second controllable switches and responsive to a source of vertical rate signals for providing to said controllable switches during said vertical trace interval horizontal rate signals modulated at a verticalrate for varying the amount of each horizontal retrace signal coupled to said capacitance means for generating a vertical deflection current in said vertical deflection winding during said vertical trace interval, said switched vertical deflectioncircuit substantially loading said horizontal deflection circuit at the beginning and end of said vertical trace interval,
said modulator providing signals to said first controllable switch during said vertical retrace interval for coupling said horizontal retrace signals to said capacitance means during said vertical retrace interval for substantially loading saidhorizontal deflection circuit during said retrace interval for preventing undesired oscillations within said horizontal deflection circuit.
10. A circuit according to claim 9 wherein said vertical rate signals cause said modulator to provide for conduction of said first controllable switch during said vertical retrace interval and for inhibiting conduction of said second controllable swith during said vertical retrace interval.

Description:

BACKGROUND OF THE INVENTION

This invention relates to switched vertical deflection circuits for a television receiver.

In a switched vertical deflection circuit of the type disclosed in U.S. Patent Application Ser. No. 595,809, now U.S. Pat. No. 4,048,544, filed July 11, 1975, by Peter Eduard Haferl, entitled, SWITCHED VERTICAL DEFLECTION SYSTEM, horizontalrate energy, in the form of horizontal retrace pulses from a horizontal output transformer of a horizontal deflection circuit, charges a capacitor in parallel with a vertical deflection winding. A first switch, such as an SCR, couples successivelysmaller portions of the horizontal rate energy to the capacitor during a first part of the vertical trace interval and a second switch, such as another SCR, couples successively larger portions of the horizontal rate energy during a second part of thevertical trace interval. The voltage across the capacitor is integrated by the vertical deflection winding into a sawtooth vertical deflection current. The conduction of the two SCR switches is controlled by horizontal rate pulse width modulated pulsescoupled from a modulator to the SCR gate electrodes.

At the start of vertical retrace, the second SCR switch which had previously been conducting is maintained in cutoff. The vertical deflection winding and the capacitor form a resonant retrace circuit. A disconnect diode coupled to the gate ofthe first SCR switch is reversed biased, maintaining the SCR in cutoff independent of the gating pulses generated by the modulator. With both SCR's nonconducting, resonant retrace of the current in the vertical deflection winding is accomplished. Atthe start of the subsequent vertical trace interval, the disconnect diode is no longer reverse biased. Pulse width modulated gating pulses to the first SCR enable the SCR to couple the horizontal retrace pulses to the capacitor for generating thesawtooth deflection current in the vertical deflection winding.

Both SCR's conduct relatively large amounts of current at the beginning and end of the vertical trace interval, respectively. Neither SCR conducts during the vertical retrace interval. Accordingly, loading of the horizontal deflection circuitby the switched vertical deflection circuit will be greatest at the beginning and end of the vertical trace interval, with substantially no loading occurring during the vertical retrace interval. Such load interruption during the vertical retraceinterval may cause undesirable modulation of the horizontal deflection current and undesirable oscillations within the horizontal deflection circuit. These oscillations may appear, for example, in the "S" shaping capacitor or in the horizontal outputtransformer windings as the load impedance of the vertical deflection circuit abruptly changes. It is, therefore, desirable to provide a switched vertical deflection circuit in which undesirable oscillations within the horizontal deflection circuit areprevented.

SUMMARY OF THE INVENTION

A switched vertical deflection circuit comprises a horizontal deflection circuit including apparatus for generating horizontal rate energy signals, a vertical deflection winding, an energy storage capacitance, first and second switches and aswitching circuit coupled to the switches. The switching circuit switches the conductive states of the switches for coupling successively smaller portions of the horizontal rate energy signals to the energy storage capacitance during a first part of thevertical trace interval and successively larger portions during a second part for developing a vertical deflection current in the vertical deflection winding during the vertical trace interval. The switching circuit causes the first switch to conductduring the vertical retrace interval for coupling substantial portions of the horizontal rate energy signals to the energy storage capacitance during the vertical retrace interval for preventing undesired oscillations within the horizontal deflection circuit.

CHASSIS FM100-20GS BLAUPUNKT vertical deflection system and method:SSVD
To permit use of a circuit in which the energy derived during horizontal flyback is used to control vertical deflection, without damage to the vertical deflection system upon vertical flyback, the vertical deflection output stage is dimensioned to have a time constant which is less, preferably about half, of the time constant of the sawtooth wave generator controlling vertical deflection. The vertical deflection output stage forms, in essence, a parallel oscillatory circuit which, to provide the lesser time constant, is damped.

1. In a television receiver,
having means (1, 2) coupling out a portion of the energy delivered by the horizontal deflection circuit during line flyback or retrace;
a vertical deflection output stage (V) including deflection means (L_V1, L_V2) and a charge capacitor element (C);
and a sawtooth wave generator (S), which controls application of the coupled-out energy derived from the horizontal deflection circuit to the vertical deflection means (L_V1, L_V2), a method to control vertical deflection
comprising, in accordance with the invention, the step of
additionally controlling application of the energy to the vertical deflection means by the sawtooth wave generator during the vertical flyback or retrace interval by reversely re-charging said capacitor element during said interval.


2. Method according to claim 1, wherein the re-charging step is carried out continuously.

3. Method according to claim 1, wherein the re-charging step is carried out linearly.

4. Method according to claim 1, wherein the vertical deflection output stage includes, vertical deflection coil elements (L_V1, L_V2) and forming with said charge capacitor element (C) said deflection means, a feedback resistor element (R) and a vertical correction circuit element (4), said charge capacitor element and said other elements being connected to form a parallel oscillatory circuit;
said method including the step of controlling the damping of the parallel oscillatory circuit by controlling the relative parameters of said elements.


5. In a television receiver, a vertical deflection system including means (1, 2) coupling out a portion of the energy delivered by the horizontal deflection circuit during line flyback or retrace;
a vertical deflection output stage (V) including vertical deflection means (L_V1, L_V2);
and a sawtooth wave generator (S) controlling application of the coupled-out energy to the vertical deflection means during the flyback interval
and wherein, in accordance with the invention,
the time constant (τ_S) of the sawtooth wave generator (S) is longer than the time constant (τ_V) of the vertical deflection output stage (V).


6. Vertical deflection system according to claim 5, wherein the time constant of the vertical deflection output stage is about twice as long as that of the sawtooth wave generator (S).

7. Vertical deflection system according to claim 5, wherein the ratio of time constants (τ_S /τ_V) is between about 1.5 to 2.5.

8. Vertical deflection system according to claim 5, wherein the vertical deflection output stage (V) includes a charge capacitor element (C), vertical deflection coil elements (L_V1, L_V2) forming said vertical deflection means, a feedback resistor element (R) and a vertical correction circuit element (4), said elements being connected to form a parallel oscillatory circuit;
and wherein said oscillatory circuit is a damped oscillatory circuit.


9. Vertical deflection system according to claim 8, wherein the elements of said oscillatory circuit are dimensioned to provide a time constant which is about half of the time constant of the sawtooth wave generator (S) and is in the order of about 0.5 ms.

Description:

The present invention relates to a deflection circuitry for television receivers, and more particularly to a deflection circuit in which energy contained in the horizontal flyback is used in the vertical deflection system.
Video scanning in television receivers is effected, as well known, by a vertical deflection circuit. A pulse generator is synchronized by pulses included in the video signal. The pulses are then applied over a pulse generator, a driver and an output stage to deflection systems, usually deflection coils.
Various types of solid-state circuits have been proposed; for example, U.S. Pat. No. 4,048,544 describes a transistorized vertical deflection circuit with additional circuitry to stabilize the pulses. The time constant of the pulse generator and of the driver stage of such circuits is less than the time constant of the output or final power stage of the vertical deflection circuit. Such vertical deflection circuits have some disadvantages, particularly in that the transistors are operated at high voltages which may result in flash-over and thus damage or destruction of the transistor. The power required to control the final output transistors is already substantial and thus the overall operating efficiency of such a vertical deflection circuit is low.
In earlier developments, a vertical deflection circuitry was proposed which avoids some of the disadvantages of this transistorized circuit; in this earlier circuit, a portion of the energy contained in the horizontal flyback is coupled out and is directly utilized in order to supply current for the vertical deflection coils. To control application of current, a controlled sawtooth wave generator is connected to the final output stage of the vertical deflection circuit, the sawtooth wave generator having a short retrace or flyback time. These vertical deflection circuits also have some disadvantages. The energy derived for vertical deflection is obtained from the horizontal flyback; thus, changes in loading in the vertical deflection circuitry affect the horizontal output stage. The vertical deflection circuit is subject to substantial changes in loading during the vertical flyback or retrace since, in accordance with the previously known circuit, the vertical deflection circuit is not controlled during the vertical flyback or retrace. The lack of control of the vertical deflection circuit causes abrupt changes in loading which result in undesired spurious oscillations in the vertical output stage. These oscillations can so feed back or react on the horizontal output stage that the horizontal flyback pulses are overloaded, the vertical stage starts to oscillate, and high voltages may occur therein during the vertical flyback. This, necessarily, degrades the image quality of the reproduced video picture. High-voltage flash-over may occur and electronic components, particularly solid-state semiconductor elements can be destroyed thereby.
It is an object of the present invention to provide a vertical deflection circuit for television receivers, which has the advantages of utilizing a portion of the energy contained in the horizontal deflection circuit during horizontal flyback without causing abrupt changes in loading on the horizontal output stage and preventing undesired spurious and uncontrolled oscillation of the vertical output stage.
SUBJECT MATTER OF THE PRESENT INVENTION
Briefly, the sawtooth wave generator which controls charging of a charge capacitor of the vertical output stage is controlled to in turn control the charge on the capacitor also during vertical retrace; in accordance with a feature of the invention, this control is obtained by so arranging and relatively matching the time constants of the sawtooth wave generator and of the parallel oscillatory circuit formed by the vertical deflection coils of the T.V. receiver and the charge capacitor that the time constant of the vertical deflection output stage is less, preferably about half that of the time constant of the sawtooth wave generator. This matching can be obtained by so selecting the values of the components of the vertical deflection output stage that the resulting oscillatory circuit formed by the capacitor, resistance elements in the circuit, and the vertical deflection output stage form a damped oscillatory circuit.
The invention will be described by way of example with reference to the accompanying drawings, wherein the single FIGURE is a schematic diagram of a vertical deflection output stage in which the method of the present invention is carried out, and utilizing the system thereof.
A horizontal deflection output stage 1 is connected to a horizontal output transformer 2 which has coupling windings W ₁ and W ₂ to derive a portion of the energy contained in the line retrace. This energy is stored in the inductances L ₁ and L ₂ and then applied through thyristors Th ₁ and Th ₂ to a charge capacitor C. A control circuit 3 is provided triggering the thyristors Th ₁ and Th ₂ in such a manner that the charge capacitor C is positively charged during the first half of the video scan and negatively during the second half of the video scan. The charge capacitor C is discharged through the vertical deflection coils L _V1 and L _V2 , a vertical correction circuit 4 for vertical correction and a feedback resistor R. The voltage drop across feedback resistor R is fed back to the control circuit 3 in order to ensure exact triggering of the thyristors Th ₁ and Th ₂ and to control the desired deflection current.
Positive deflection current is obtained during the first half of the video scan by the triggered thyristor Th ₁ ; negative deflection current is derived during the second half of the video scan by the triggered thyristor Th ₂ . The thyristors Th ₁ and Th ₂ can be triggered during a portion of the video scan simultaneously to result in a linear deflection and provide overlapping, opposite deflection currents.
The control circuit 3, together with the thyristors Th ₁ and Th ₂ , and the inductances L ₁ and L ₂ , forms a sawtooth wave generator S. The vertical deflection output stage V is formed of the vertical deflection coils L _V1 , L _V2 , the vertical correction circuit 4, the charge capacitor C and the feedback resistor R. As can be seen from the FIGURE, the capacitor C on the one hand, and the deflection coils, the correction circuit 4 and the resistor R on the other hand form a parallel oscillatory circuit.
The circuit, as far as the diagram is concerned, is known. Uncontrolled, undesired and spurious oscillations in the horizontal output stage can be avoided, in accordance with the invention, by reverse re-charging the capacitor C also during the vertical retrace interval. This re-charging of the capacitor C preferably is carried out continuously and desirably linearly. The controlled re-charging of the capacitor C can be readily obtained by arranging the relative values of the components in the sawtooth wave generator S and in the vertical output stage V such that the time constant τ _S of the sawtooth wave generator is longer than the time constant τ _V of the vertical deflection output stage. Mathematically: τ _S >τ _V (1)
preferably, the quotient of the time constants should be between 1.5 and 2.5, most desirably about 2, mathematically: 1.5>τ _S /τ _V <2.5 (2)
if the time constants of the respective circuits are properly arranged, the thyristors Th ₁ and Th ₂ can be precisely triggered also during the short time interval of the vertical flyback or retrace. Due to the short time constant, the vertical deflection circuit can then follow the control from the control circuit 3 exactly; the voltage dropped across the feedback resistor R will permit precise triggering, with respect to time, of the thyristors Th ₁ and Th ₂ also during the vertical flyback. In the first half of the video scan, the thyristor Th ₂ is triggered; in the second half, thyristor Th ₁ is triggered. This ensures linear flyback.
The time constant τ _V is essentially determined by the vertical deflection coils L _V1 , L _V2 , the correction circuit 4, and the feedback resistor R which, together with the capacitor C, form a parallel oscillatory circuit. A short time constant corresponds to high damping of this parallel oscillatory circuit. Thus, in accordance with a feature of the present invention, by suitably arranging the ratio of the time constants, the parallel oscillatory circuit will not start undesired uncontrolled oscillations which could interfere with image reproduction quality, or proper operation of the components of the T.V. receiver. The ratio of the time constants can be selected by suitable adjustment of the damping of the oscillatory circuit.
The vertical deflection circuit has an essentially continuous, uniform and even power requirement. This avoids abrupt changes in loading during the vertical retrace. Excessive over-compensation of horizontal flyback pulses, and resulting high voltages which may lead to undesired distortion of the reproduced image and possibly to damage or destruction of components of the video system are avoided. The vertical deflection circuitry, as described, can be readily manufactured and has high operating reliability. The efficiency is high and the power requirement is low.
Various changes and modifications may be made within the scope of the inventive concept.
In a typical T.V. receiver using vertical deflection coils of 20 millihenry inductance, a suitable time constant τ _V is 0.5 ms. In such a circuit, the resistor R can have a value 1 Ω capacitor C a value of 1.5 μF. and the reflected impedance of correction circuit 4 a value of 1 Ω.
The sawtooth wave generator has a time constant of 1 ms, providing for a slow rise time for 20 milliseconds. The circuit 3 is well known and described in U.S. Pat. No. 4,048,544.

CHASSIS FM100-20GS BLAUPUNKT SSVD E/W CORRECTION Pincushion correction circuit
A side pincushion correction circuit having an impedance circuit in series with the deflection coil. A controlled switch coupled in a branch of the impedance circuit is operated at times during the second half of the horizontal retrace interval which are progressively advanced during the first half of vertical interval and retarded during second half of vertical interval. Enhanced inside pincushion distortion correction is provided when the impedance circuit includes a capacitor coupled in series with the switch.




1. A pincushion correction circuit for a kinescope deflection apparatus including horizontal and vertical deflection generator systems, comprising:
a horizontal deflection winding coupled to the horizontal deflection generator system for accepting scanning current therefrom;
an impedance circuit for presenting an impedance between first and second terminals and further including a third terminal, and first coupling means for coupling said first terminal to said third terminal;
second means for serially coupling said first and second terminals of said impedance circuit with said deflection winding;
controllable switch means including a control electrode and a controlled current path coupled between said second and third terminals;
control means coupled to the horizontal and vertical deflection generator systems and to said control electrode for operating said controllable switch means at a time during the second half of the horizontal retrace interval which time is progressively advanced during a first portion of the vertical scan interval and which is progressively retarded during a second portion of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.


2. A pincushion correction circuit in accordance with claim 1 wherein said first coupling means comprises a direct connection.

3. A pincushion correction circuit in accordance with claim 1 wherein said impedance circuit comprises first inductance means coupled between said first and second terminals.

4. A pincushion correction circuit in accordance with claim 3 wherein said first coupling means comprises capacitance means coupled between said first and third terminals.

5. A pincushion correction circuit according to claim 3 wherein said first coupling means comprises:
capacitance means;
second inductance means;
means for serially coupling said capacitance means with said second inductance means; and
means for coupling the serial combination of said capacitance means and said second inductance means between said first and third terminals.


6. A pincushion correction circuit according to claim 3 wherein said coupling means comprises second inductance means coupled between said first and third terminals.

7. A pincushion correction circuit according to claim 6 further comprising means for magnetically coupling said first inductance means with said second inductance means.

8. A pincushion correction circuit according to claim 7 further comprising capacitance means serially coupled with said second inductance means.

9. A pincushion correction circuit according to claim 8 wherein said first and second inductance means have substantially the same self-inductance.

10. A pincushion correction circuit according to claim 1 wherein said controllable switch means comprises a controllable rectifier including said control electrode and said controllable current path, a unidirectional current conducting device, and wherein said controllable current path is coupled in parallel with said unidirectional current conducting device.

11. A pincushion correction circuit according to claim 10 wherein the anode of said unidirectional current conductive device is coupled to the cathode of said controllable rectifier and the cathode of said unidirectional current conducting device is coupled to the anode of said controllable rectifier.

12. A pincushion correction circuit according to claim 1 wherein said control means comprises gating pulse generator means coupled to said controllable switch and to the horizontal and vertical deflection generator systems for producing repetitive switch gating pulses during the second half of each horizontal retrace pulse interval, said gating pulses terminating substantially at the termination of said horizontal retrace pulse and initiating at a time which is progressively advanced during a first portion of the vertical scan interval and progressively retarded during a second portion of the vertical scan interval.

13. A pincushion correction circuit according to claim 12 wherein said gating pulse generator means comprises:
parabola generating means coupled to the vertical deflection generator system for generating a parabolic signal at the vertical deflection rate;
means coupled to the horizontal deflection generator system for generating a horizontal rate signal during the horizontal retrace pulse period;
modulating means coupled to said horizontal rate signal generating means and to said parabolic signal generating means for generating a horizontal rate pulse width modulated by said parabolic signal; and
gating means coupled to said horizontal rate signal generating means and to said modulating means for generating switch gating pulses representative of the absence of said horizontal rate signal and of said horizontal rate pulse.


14. A pincushion correction circuit according to claim 12 wherein said gating pulse generator means comprises: parabola generating means for generating a parabolic signal at the vertical deflection rate; means for generating a horizontal rate signal during the horizontal retrace pulse interval; and
comparator means coupled to said parabola generator means and to said horizontal rate signal generating means for producing said repetitive gating pulses.


15. A pincushion correction circuit according to claim 14 wherein said comparator means comprises: differential amplifier amplitude comparison means having a first and a second input;
said first input being coupled to said parabola generating means; and
said second input being coupled to an output of said horizontal rate signal generating means and said horizontal rate signal comprises a ramp.


16. A pincushion correction circuit for a kinescope deflection apparatus including horizontal and vertical deflection generator systems, comprising:
a horizontal deflection winding coupled to the horizontal deflection generator system for accepting scanning current therefrom;
an impedance circuit including a capacitor coupled in parallel with an inductor;
means for serially coupling said impedance circuit with said deflection winding;
controllable switch means including a control electrode and a controlled current path serially coupled with a branch of said impedance circuit; and
control means coupled to the horizontal and vertical deflection generator and to said control electrode for operating said controllable switch means at a time during the second half of the horizontal retrace interval which time is progressively advanced during a first portion of the vertical scan interval and which is progressively retarded during a second portion of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.


17. A pincushion correction circuit according to claim 16 wherein said controllable switch is serially coupled in the capacitive branch of said impedance circuit.

18. A pincushion correction circuit according to claim 17 wherein the inductive branch of said impedance circuit comprises an autotransformer.

19. A pincushion correction circuit according to claim 18 wherein said controllable switch comprises a controllable rectifier, a unidirectional current conducting device and having said controllable current path coupled in parallel with said unidirectional current conducting device.

20. A pincushion correction circuit according to claim 19 wherein the anode of said unidirectional current conducting device is coupled to the cathode of said controllable rectifier and the cathode of said unidirectional current conducting device is coupled to the anode of said controllable rectifier.

21. A pincushion correction circuit according to claim 16 wherein said control means comprises gating pulse generator means coupled to said controllable switch and to the horizontal and vertical deflection generator systems for producing repetitive switch gating pulses during the second half of each horizontal retrace pulse interval, said gating pulses terminating substantially at the termination of said horizontal retrace pulse and initiating at a time which is progressively advanced during a first portion of the vertical scan interval and progressively retarded during a second portion of the vertical scan interval.

22. A pincushion correction circuit according to claim 21 wherein said gating pulse generator means comprises:
parabola generating means coupled to the vertical deflection generator system for generating a parabolic signal at the vertical deflection rate;
means coupled to the horizontal deflection generator system for generating a horizontal rate signal during the horizontal retrace pulse period;
modulating means coupled to said horizontal rate signal generating means and to said parabolic signal generating means for generating a horizontal rate pulse width modulated by said parabolic signal; and
gating means coupled to said horizontal rate signal generating means and to said modulating means for generating switch gating pulses representative of the absence of said horizontal rate signal and of said horizontal rate pulse.


23. A pincushion correction circuit according to claim 21 wherein said gating pulse generator means comprises: parabola generating means for generating a parabolic signal at the vertical deflection rate; means for generating a horizontal rate signal during the horizontal retrace pulse interval; and
comparator means coupled to said parabola generator means and to said horizontal rate signal generating means for producing said repetitive gating pulses.


24. A pincushion correction circuit according to claim 23 wherein said comparator means comprises: differential amplifier amplitude comparison means having a first and a second input;
said first input being coupled to said parabola generating means; and
said second input being coupled to an output of said horizontal rate signal generating means and said horizontal rate signal comprises a ramp.


25. A television kinescope deflection apparatus comprising:
a vertical deflection generator coupled to a vertical deflection coil for producing vertical scanning current therethrough;
a horizontal deflection generator system for generating horizontal rate current;
a horizontal deflection winding coupled to said horizontal deflection generator for accepting horizontal rate current therefrom for scanning;
impedance means;
controllable switch means; first coupling means for coupling said horizontal deflection winding with a first terminal of said impedance means so as to form a series circuit, said impedance means having a second terminal remote from said first terminal; second coupling means coupling a first end of the controlled current path of said controllable switch means with said first terminal, and third coupling means for coupling the other end of the controlled current path of said controllable switch means with said second terminal; and
control means coupled to said vertical and to said horizontal deflection generator systems and to said controllable switch means for operating said controllable switch means at a time during the horizontal retrace interval which is progressively advanced during a first portion of the vertical scan interval and which is progressively retarded during a second portion of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.


26. A television kinescope deflection apparatus according to Claim 25
wherein
said control means closes said controllable switch means at a time during the horizontal retrace interval which is progressively advanced during the first half of the vertical scan interval and progressively retarded during the second half of the vertical scan interval.


27. A television kinescope deflection apparatus according to claim 26 wherein said impedance means comprises first inductance means coupled between said first and second terminals.

28. A television kinescope deflection apparatus according to claim 27 wherein said second coupling means comprises capacitance means coupling said first terminal of said impedance means to said first end of said controllable switch means.

29. A television kinescope deflection apparatus according to claim 27 wherein said second coupling means comprises second inductance means coupling said first terminal of said impedance means to said first end of said controllable switch means.

30. A television kinescope deflection apparatus in accordance with claim 27 wherein said second coupling means comprises second inductance means coupling said first terminal of said impedance means to said first end of said controllable switch means and further comprising magnetic coupling means for magnetically coupling said first inductance means with said second inductance means.

31. A television kinescope deflection apparatus according to Claim 27 wherein said second coupling means comprises capacitance means and second inductance means.

32. A television kinescope deflection apparatus according to claim 31 wherein said first and second inductance means have substantially the same self-inductance.

33. A television kinescope deflection apparatus according to claim 31 wherein said capacitance means and said second inductance means are serially coupled.

34. A television kinescope deflection apparatus according to claim 31 further comprising magnetic coupling means for magnetically coupling said first and second inductance means.

35. A television kinescope deflection apparatus according to claim 31 wherein said first and second inductance means are windings of an autotransformer.

36. A television kinescope deflection apparatus in accordance with claim 25 wherein said controllable switch means comprises a controllable rectifier including a control electrode and a controllable current path, a unidirectional current conducting device, and wherein said controllable current path is coupled in parallel with said unidirectional current conducting device.

37. A television kinescope deflection apparatus according to Claim 36 wherein the anode of said unidirectional current conductive device is coupled to the cathode of said controllable rectifier and the cathode of said unidirectional current conducting device is coupled to the anode of said controllable rectifier.

38. A television kinescope deflection apparatus according to Claim 25 wherein said control means comprises gating pulse generator means coupled to said controllable switch and to said horizontal and vertical deflection generators for producing repetitive switch gating pulses, said gating pulses terminating substantially at the termination of said horizontal retrace pulse.

39. A television kinescope deflection apparatus according to Claim 38 wherein said gating pulse generator means comprises: parabola generating means coupled to the vertical deflection generator for generating a parabolic signal at the vertical deflection rate; means coupled to said horizontal deflection generator system for generating a horizontal rate signal during said horizontal ratrace pulse period; modulating means coupled to said horizontal rate signal generating means and to said parabolic signal generating means for generating a horizontal rate pulse width-modulated by said parabolic signal.

40. A television kinescope deflection apparatus according to Claim 39 wherein said modulating means comprises: comparator means coupled to said parabola generator means and to said horizontal rate signal generating means for producing said repetitive gating pulses.

41. A television kinescope deflection apparatus according to Claim 40 wherein said comparator means comprises: differential amplifier amplitude comparison means having a first and a second input; said first input being coupled to said parabola generating means; and said second input being coupled to an output of said horizontal rate signal generating means and wherein said horizontal rate signal comprises a ramp.

42. A television kinescope deflection apparatus comprising: a vertical deflection generator coupled to a vertical deflection coil for producing vertical scanning current therethrough; a horizontal deflection generator system for generating horizontal rate current; a horizontal deflection winding coupled to said horizontal deflection generator for accepting horizontal rate current therefrom for scanning; impedance means; controllable switch means; means coupling said impedance means and said controllable switch means in series with said deflection winding for defining a path for said horizontal rate current; control means coupled to said vertical and to said horizontal deflection generator systems and to said controllable switch means for operating said controllable switch means at a time during the horizontal retrace interval which is progressively advanced during the first half of the vertical scan interval and which is progressively retarded during the second half of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.

Description:

BACKGROUND OF THE INVENTION
This invention relates to a kinescope pincushion distortion correction circuit.
It is known in the art that side or East-West pincushion distortion of the raster on a kinescope such as utilized in a television receiver may be substantially eliminated by modulating the horizontal rate deflection current amplitude through the horizontal deflection coils by a substantially parabolic current component at a vertical scanning rate. Generally the desired modulation has been accomplished by passive currents in which a control or primary winding of a saturable reactor or transformer is energized by vertical rate energy and a secondary winding is placed in circuit with the horizontal deflection winding. The horizontal deflection current amplitude is modulated by the vertical deflection current such that the raster width is reduced at the top and bottom of the raster.
Another known arrangement for side pincushion distortion correction involves a capacitor coupled in parallel with the vertical deflection winding. As is disclosed in copending application Ser. No. 07161/75 for Peter E. Haferl and entitled "VERTICAL DEFLECTION SYSTEM", the capacitor is charged by energy from the horizontal retrace pulse under the control of switches. In both the passive saturable reactor circuits and in the switched vertical deflection circuit according to the aforementioned copending application, side pincushion correction is obtained by loading the high voltage transformer of the horizontal deflection system during the horizontal retrace time. In order to obtain correctly shaped side pincushion correction the loading of the high voltage transformer is modulated at the vertical deflection rate, as by the vertical deflection current. Thus, maximum loading occurs at the top and bottom of the picture and minimum loading occurs at the center of the picture.
The variable loading of the horizontal retrace pulse at the vertical rate results in the generation of a further pincushion distortion, known as inside pincushion distortion to distinguish from the outside or peripheral pincushion distortion ordinarily referred to. This further pincushion distortion occurs within the raster as a result of time modulation of the start of horizontal scan caused by the vertical rate loading. Increased trace duration resulting from time modulation of the horizontal retrace pulse at the top and bottom of vertical scan increases the portion of the resonant period of the deflection coil 26 with S correction capacitor 28 subtended during trace. Thus, the inside pincushion distortion appears in the region between the center line and the extreme left and right sides of the picture as an insufficient pincushion correction.
The amount of inside pincushion correction depends upon the geometry of the picture tube and on the amount of outside pincushion distortion requiring correction. With the advent of wide-angle large viewing screen picture tubes it has been found that the inside pincushion distortion may be objectionable to the point that correction is required.
A prior art arrangement for the solution of the inside pincushion correction problem, in addition to structure utilized for conventional pincushion correction, uses a separate saturable reactor or transductor in series with the horizontal deflection winding. The control winding of the saturable reactor is driven by a vertical deflection rate signal and modulates the inductance of the horizontal deflection circuit to correct for the change in "S" shaping and thereby correct the inside pincushion distortion. This prior art solution has disadvantages which include critical design of the saturable reactor, temperature dependence of the saturable reactor, cost of the saturable reactor, and a control range so limited as to often be insufficient to compensate for construction tolerances.
SUMMARY OF THE INVENTION
A pincushion correction circuit includes an impedance coupled in series with a horizontal deflection winding. The impedance circuit contains two branches, one of which is always in series with the deflection winding. The second branch of the impedance circuit is paralleled with the first branch by a controllable switch. The controllable switch is gated on at a time during the second half of the horizontal retrace interval. The time during the second half of the horizontal retrace interval at which the switch is gated on is progressively advanced during a first portion of the vertical scan interval and is progressively retarded during the second portion of the vertical scan interval.




CHASSIS FM100-20GS Description of the EHT FLYBACK Transformer used in Blaupunkt CHASSIS types. High-voltage-secondary transformer, particularly television line transformer:


To decrease the internal resistance of a transformer operable as a television line transformer of the "diode-split" type, the secondary winding sections are matched to each other and to the frequency of operation of the transformer in such a manner that the current in the respective sections will flow at respectively different instants of time; in a preferred form, the winding sections, on the average, are tuned to a harmonic of the frequency of the signal applied to the primary and are positioned on winding forms or holders such that the distance between the bottom wall of the primary and the bottom wall of the secondary is constant over the entire length of the windings. Preferably, the tuning of the respective winding sections is effected by matching of the primary winding to the secondary within the region of the secondary winding sections.




1. High-voltage secondary transformer, particularly television line transformer, having
a primary winding (5) and a secondary winding (7a, 7b, 7c) in which the secondary winding is subdivided into a plurality of windings sections (7a-7b-7c), and a plurality of rectifier diodes (10) connecting said secondary winding sections together,
wherein, in accordance with the invention,
the secondary winding sections (7a, 7b, 7c) are physically positioned with respect to the primary winding to form spatially separated winding sections, each having individual inductance and capacity values and with respect to the primary, and each other, said positioning on the primary winding being effected to result in current flow in the respective sections (7a, 7b, 7c) of the secondary at respectively different instants of time.


2. Transformer according to claim 1, wherein the secondary winding sections are tuned to a harmonic of the frequency of the signal applied to the primary winding (5).

3. Transformer according to claim 2, wherein the respective winding sections (7a, 7b, 7c) of the secondary are tuned to the primary (5) by matching the primary winding to the secondary in the region of the respective secondary winding section.

4. Transformer according to claim 3, wherein the distance between the inner dimension of the primary winding and the inner dimension of the secondary winding is constant throughout the length of a winding section.

5. Transformer according to claim 4, wherein said distance is constant throughout the length of all the winding sections.

6. Transformer according to claim 5, for use as a television high-voltage transformer further comprising a resistor (R) connected to one of the secondary winding sections to provide a bleeder voltage for focussing of an image tube of a television apparatus,
comprising a housing being formed with a first portion receiving said primary winding (5) and said secondary winding sections (7a, 7b, 7c) and a resistor chamber portion defining a chamber (16) in which said resistor (R) is located, said resistor chamber portion being separated from the portion retaining said windings by an air gap (15).


7. Transformer according to claim 3, for use as a television high-voltage transformer further comprising a resistor (R) connected to one of the secondary winding sections to provide a bleeder voltage for focussing of an image tube of a television apparatus,
comprising a housing being formed with a first portion receiving said primary winding (5) and said secondary winding sections (7a, 7b, 7c) and a resistor chamber portion defining a chamber (16) in which said resistor (R) is located, said resistor chamber portion being separated from the portion retaining said windings by an air gap (15).

Description:

The present invention relates to a transformer providing a high-voltage secondary output, and particularly to a television line transformer having a secondary winding which is subdivided into winding sections or portions interconnected by rectifiers.
BACKGROUND AND PRIOR ART
Television line transformers frequently have divided secondaries, that is, secondaries which are subdivided into sections, connected by rectifier diodes. These transformers, particularly when used as line transformers in TV apparatus, are supplied at the primary with signals of line frequency, and then provide the anode voltage for the TV electron gun, image tube at the secondary. Line transformers in which the secondaries are subdivided and connected by diodes are referred to as "diode-split" transformers. The voltages induced in the partial secondary windings or winding sections add in the form of a voltage doubler or voltage multiplier until the desired high voltage is reached. The stray or leakage capacitances within the transformer and particularly the stray capacitances of the partial windings with respect to a reference voltage act as intermediate storage capacities for the portions of the voltages which are being added.
Transformers of this type have a disadvantage in that they have poor regulation. As a voltage source, they have a comparatively high inherent or internal resistance. Changes in loading which may occur thus lead to changes in output voltage. Applied to a TV system, instability of the format of the resulting image may occur. Changes in loading often are the consequence of changes in beam current.
THE INVENTION
It is an object to provide a transformer, particularly suitable as a line transformer, which has a suitable low internal resistance so that the output power obtained therefrom will be at a voltage which is essentially constant and independent of variations in loading experienced in ordinary television sets, without the necessity of complex circuitry.
Briefly, a transformer of the diode-split type is so constructed that the secondary winding sections are matched to each other and to the frequency of operation of the transformer that the current in the respective section flows at respectively differently instants of time. In a preferred form, the winding sections, on the average, are tuned to a harmonic of the frequency of the signals applied to the primary. Tuning of the various winding sections can be effected by matching the configuration or winding arrangement or number of turns of the respective sections to the primary within the range of the inductive coupling between the primary and the particular section of the secondary. In accordance with a preferred feature, the primary is located within the secondary, and the distance between the inner winding portion of the coil of the primary and the inner winding portion of the coil forming the secondary is essentially constant over the entire width of the windings.
Transformers of this type often are associated with external circuitry, and particularly with a resistor which is connected to a specific secondary section and on which the focussing voltage for the TV image tube can be taken off. In accordance with a feature of the invention, the housing for the transformer is formed with a lateral chamber, remote from the transformer windings themselves and separated therefrom by an air gap. The transformer windings, as well as the chamber for a resistor from which the tapping voltage can be taken off, is filled with a potting compound. This resistor, also referred to as a bleeder resistor, can be applied by thin film or hybrid technology on a small ceramic plate and, by the specific location, is removed from the field generated by the transformer and thus provides a stable output voltage.
The transformer construction in accordance with the present invention, when used as a line transformer in a TV set provides for a more stable picture since it has substantially improved regulation with respect to prior art transformers by having an inherent or inner resistance which is less than that of previously used units. Tuning of the sections of the secondary winding is simple by matching the configuration of the primary winding to the configuration of the secondary sections, which is easier to accomplish in manufacture than if the secondary is matched to the primary.
Drawings, illustrating an example, wherein:
FIG. 1 is a side view, partially in section, of a line transformer for television use, having rectifier diodes located within the transformer and connected between individual winding sections; and









FIG. 2 is a top view, with part of the housing cut away and in section, of the transformer of FIG. 1.
The transformer is a "diode-split" transformer, the principle of which is known. The transformer 1 is located within a plastic, typically injection-molded plastic, housing 2 which receives a potting compound 3 after the transformer is assembled within the housing. In FIG. 1, the front wall of the housing has been removed. The housing 2 receives, or inherently forms, a coil form 4 for the primary winding 5 of the transformer. The coil form 4 may be part of the housing structure, that is, molded integrally therewith, the coil 5 being wound initially as a coreless or formless structure so that it can be slipped directly over the form 4 which, as best seen from FIG. 2, is essentially a cylinder open at one end. A different type of housing can be used, however, in which the coil form 4 does not form an intergral, molded part, but rather is inserted as a separate form or winding body for the primary.
A coil carrier 6 is located on the primary 5 to receive the secondary of the transformer 1. In accordance with a feature of the invention, the secondary winding is wound in three sections 7a, 7b, 7c, which subdivide the secondary. The secondary winding sections 7a, 7b, 7c are each located in three winding chambers 6a, 6b, 6c of the form 6. The winding chambers 6a, 6b, 6c each have five winding grooves 8 in which the winding sections 7a, 7b, 7c each are uniformly distributed. These winding grooves 8 may, however, be non-uniformly distributed if it is desired to effect matching of the tuning of the winding sections to the primary by this distribution; in a preferred form, however, the distribution of the grooves 8 is uniform. The result of this subdivision of the windings into sections 7a, 7b, 7c, physically separated, i.e. axially spaced from each other (see FIG. 1), is a consequent division of capacity and inductance of the secondary into respectively, individually positioned individual capacity and inductance values and mutual capacity and inductance values of the sections, resulting in different phasing of the current flow, i.e. current flow in the respective sections at respectively different instants of time.
Holders 9 are located above each one of the winding chambers 6a, 6b, 6c, as best seen in FIG. 2, preferably formed integrally with the winding holder or body 6. The holders 9 receive the diodes 10. The diodes 10 are located in the holders 9 with externally bent connecting wires 11. The connecting wires extend through openings or passages of caps 12 snapped over the holders 9, thus securing the diodes 10 on the holders 9. The low-voltage connection of the transformer 1 is effected by connecting pins 13; some of the pins 13, shown in FIG. 1, may be left unconnected and serve as positioning elements. The high-voltage load is connected by a high-voltage cable--not shown--to a connecting bushing 14 located at the side opposite the low-voltage terminals 13.
The housing is formed with a separately arranged chamber 16, separated from the remainder of the transformer by an air gap 15. A ceramic plate 17 on which a resistor R, applied by hybrid technology is located, is positioned in the chamber 16. Thus resistor, forming a bleeder resistor, can be used to generate the focussing voltage for the image tube of the TV set for which the transformer is particularly suitable by connection to a tap point on one of the winding sections 7a, 7b, 7c, by a suitable connection, not shown for simplicity.
The average tuning frequency of the winding sections 7a, 7b, 7c is tuned to a harmonic of the frequency of the signal applied to the primary. The respective winding sections 7a, 7b, 7c are tuned by matching the primary winding to the secondary in the region of inductive coupling of the primary to the respective section of the secondary. The inner diameter of the form 4 for the primary winding and the inner diameter of the secondary winding form or holder 6 are concentric and equidistant throughout at least the length of one of the winding sections, and preferably uniform throughout their entire length.
The transformer will form a voltage source of low internal resistance and thus can be used without additional circuitry or without increasing the size of the transformer. Miniaturization of the transformer is thus possible which is particularly important in modern television equipment.
Making the inner wall of the primary winding and the inner wall of the secondary winding in such a manner that the distances between these two walls are uniform reduces the overall size and substantially simplifies manufacture of the tuned winding sections. It was previously thought necessary to tune the winding sections with respect to each other by varying the thickness of the windings or the distances of the inner limits of the windings with respect to each other. In the transformer as described, this is not necessary and, rather, the inner wall of the transformer primary and the inner wall of the transformer secondary winding sections is uniform which results in a structure in which the comparatively complex secondary winding sections can be made identical to each other, since tuning or matching of the output is obtained by matching the secondary and primary by the shape of the primary winding. The primary winding is matched to the secondary by different magnetic coupling of the primary with respect to the sections of the secondary, that is, with a coupling which differs between the sections of the secondary; and by respectively different stray capacitances between the sections of the secondary and the primary winding, that is, by so arranging the coils that the stray capacitances of any one of the sections 7a, 7b, 7c of the secondary with respect to the primary are different.
The potting compound 3 can be filled into the transformer after assembly; the resistor secured to the ceramic plate 17 is connected before potting to a tap of the secondary winding. The resistor, by being located in chamber 16 separated from the housing of the transformer itself, eliminates undesired capacitative losses or stray currents which otherwise occur between the secondary winding of the transformer and the resistor. Such stray currents are a minimum by the separation of the resistor from the remainder of the transformer by the air gap, and its positioning in a separate chamber. This separation effectively eliminates electric stray fields which have a disturbing effect at line frequency, since the focussing voltage is undesirably modulated thereby.
In an operating example, a transformer designed for 625 lines, 50 frames (PAL standard) was wound with a diameter of the bottom 4 of 22.5 mm, having 110 turns of 0.31 mm wire to form the primary; over this form, a secondary with an inner winding diameter for the winding sections 7a, 7b, 7c, of 24.1 mm was placed; the secondary was composed of 2910 turns of 0.071 mm wire, having each three sections of 5 grooves, interconnected by diodes.