IRRADIO (SALORA) TIPO 4300. MOD. KADET 16.Can. CHASSIS SALORA STA046B UNITS VIEW.

CHASSIS SALORA STA046B UNITS VIEW.


- IF UNIT STD014F TB1440 STCC25 SN7666N

- SOUND DISCR UNIT STEJ04A TBA120

- SOUND AMPL OUT STEN02 TBA800

- THYRISTOR SWITCH HORIZONTAL OUT UNIT STP012B

- STAB SUPPLY VCC12V

- FRAME DEFLECTION OUTPUT UNIT STW011

- HORIZONTAL DEFLECTION PROTECTIVE UNIT STPR02B

- HORIZONTAL DEFLECTION STABILIZATION UNIT STL001B

- E/W CORRECTION UNIT STX011A

- TUNING SEARCH UNIT + CLOCK STCN24B AY-5-1203A AY-5-8320

- RGB AMPL UNIT STY032

- CHROM + LUM UNIT STE011J TBA396 TDA3950A



 

 DIGITAL CLOCK ON SCREEN DISPLAY MEYHOD:

The introduction of l.s.i. MOS integrated circuits has allowed semiconductor manufacturers to include many complex functions on one chip. General Instruments have produced several such chips for the TV industry, amongst the more interesting being the AY-5-8300 8320 series of channel and time display chips. These provide video outputs which superimpose a digital clock or the channel number on the television picture. It's interesting to see how fast semiconductor technology has advanced even in the 70's.

Circuit Description:
The display chip chosen for this post is the AY-5-8320. This provides a four digit clock display with decimal point and a channel number display from 1-16. Both displays appear on a background rectangle for easy viewing. The time and channel displays can be enabled independently. To the display chip we must add a digital clock. This is again an l.s.i. MOS chip, the G.I. AY-5-1203A. Like most digital clocks it uses the 50Hz mains as a clock input, with digital counters to produce the time display output. Pin connections for the two l.s.i. chips, and a typical TV display, are shown on Fig. 1. 

The circuit diagram of the digital clock and the character generator is shown on Fig. 2: ICI is the 1203 digital clock chip and IC2 the display chip. The digital clock produces a four -digit output. To transmit this in binary form would require sixteen lines. The clock chip economises on pin connections by sending each digit (four binary bits) in turn. This is called multiplexing. These four binary bits are available at pins 16 to 19 of the 1203. To identify the digits as they are sent, the 1203 provides four multiplex slot signals MX1-4 which appear at pins 3-6. When MX1 is at a 
binary 1 the minutes units binary bits are on pins 16 to 19, when MX2 is at a 1 the minutes tens binary bits are present and so on. A strobe output is provided at pin 20. This occurs in the centre of each multiplex slot, and is used by the display chip to gate the data from the clock. The display chip thus obtains and stores all four digits of the time display. The multiplexing frequency is determined by a capacitor (C2) from pin 23 to the positive supply. It is nominally set to 50kHz, although this is not critical. The AY5-8320 display chip IC2 requires (in addition to the time data) line and field sync pulses to position the display, and a 1.1MHz oscillator input. The 1.1MHz oscillator has to be inhibited by the line sync pulse and synchronised on each TV line to prevent ragged edges appearing on the characters. The oscillator consists of the quad CMOS nand IC3, with the frequency of oscillation determined by R3, RV1, C1. 
 
The sync pulses are produced by the sync extraction circuit shown in Fig. 3 (to be described later).
These pulses may be positive -going or negative -going depending on the TV set being used. The circuit requires positive -going line sync pulses at pins 8 and 9 of IC3, and negative -going field sync pulses at pin 7 of IC2. The inverters (IC4 a -d) and the wire links allow the correct polarity signal to be chosen. There is little data available as to what actually goes on inside the 8320 display chip, although it is probably along the lines of the score display article in the September 1975 Practical Wireless . The necessary delays will be generated by digital counters from the 1.1MHz clock. The display chip IC2 produces two outputs, a time output on pin 3 and a background output on pin 2. These are at a binary 1 in the asserted state. These outputs are buffered by IC5 and inverters IC4 e and f to produce the following signals for the video switching: (a) Gate Video. This is at a binary 1 when the normal TV picture is present on its own and at a 0 when the background and time display are added. (b) Gate Time. This is the video output for the time/channel digits and is at a 1 in the asserted state. (c) Background a (IC5 pin 11). This is the background output, inhibited during the time display. It's at a 1 during the background but at a 0 during the time/channel display. (d) Background b (IC4 pin 6). This is a 1 for the entire background and time display. Depending on the colours required for the number and background, the "gate hue" and "gate background" outputs can be taken from background a or b by selecting the corresponding wire links. The time display is produced by taking pin 22 of IC2 to a binary 1. Capacitor C5 keeps the display on for about six seconds after the 1 input is removed. Pin 22 can be triggered by a momentary contact on a push-button or, ultimate luxury, from an ultrasonic remote transmitter.

The time is set by connections A and B. Taking A to a 1 advances the minutes display at two per second; taking B to a 1 similarly advances the hours. The 50Hz clock arrives via C3 and is clipped and buffered by R7, R8, D2, D3. The clock chip IC1 produces at pin 7 a 50kHz burst for 0.5 seconds every second. This is smoothed by R4, D I, C4 and presented to the colon input (pin 20) on the display chip to give a flashing colon display. Some people find flashing colons annoying: if R4, D 1 and C4 are omitted and R6 is inserted the colon becomes steady. The colon output from the clock also drives Tr4 to give a front panel LED display. The colon stops flashing after a power failure, and starts again when either of the set time buttons is pressed. The front panel LED thus indicates that the clock is healthy. The channel data is presented in binary form at terminals W, X, Y, Z, W being the least significant bit. The display is offset by one bit, i.e. 0000 gives 1, 0100 gives 5 and so on. The channel display is enabled by taking terminal V to a binary 1.

Interfacing with the Television Receiver:
Fig. 3 shows the sync extraction circuits and a general purpose video mixing circuit. Before describing these it's probably best to outline the basic requirements of the television interface. The display system needs field and line sync signals from the television receiver. It's highly unlikely that these would be available at the correct levels, and depending on the set and the take off point chosen they can be of either polarity. If oscillograms are shown in the service manual, suitable signals should be easily found - in most if not all television sets. They will probably be found in either the sync separator, the flyback blanking circuits or around the scan output stages. If oscillograms are not available it will be necessary to do a bit of detective work around likely points in the circuit. It's preferable to use scan flyback pulses because of their amplitude and the low source impedance (this avoids loading the sync circuits). 
The sync extraction circuits shown in Fig. 3 will accept either positive- or negative -going signals. For negative - going inputs, Trl and Tr2 are forward biased by R14/R18: with positive -going inputs R13/R17 are used instead. The input resistors R12 and R16 form a potential divider with the selected resistor, and the transistors are turned on for positive inputs or off for negative inputs. The wire links shown in Fig. 2 allow the correct polarity signals to be chosen for the display circuit. The values for R12-14 and R16-18 depend on the amplitude of the incoming waveforms. Transistors Tr 1/Tr2 need about 0.1mA base current, so the values will be of the order of 100kS2. This should not load the TV circuit to which it's connected. With some waveforms which are close to or cross OV, capacitors C6 and C7 can be replaced with wire links. If C6 and C7 are used they should be of suitable voltage rating for the circuit to which they are connected. The connection to the video stages presents many options. The majority of colour TV sets today are cathode driven with RGB signals. The description of techniques for interfacing the time display with the set's video circuitry will be mainly directed at cathode drive therefore.

 A, typical simple RGB output stage is shown in Fig. 4. The RGB signal from the demodulator i.c. is fed first to a preamplifier or buffer (generally a one transistor stage) then to the high -voltage transistor which drives the appropriate c.r.t. cathode.





 A "brute force and ignorance" method of inserting the time and background display is to parallel three high - voltage transistors Tr 1 etc. with the RGB outputs along the lines shown in Fig. 5. The signals driving these could be
picked up from the "gate time", "gate background a and b" outputs (Fig. 2). The trimpots RV1 etc. set the current through the output transistors and hence the cathode potentials when the logic signals are at a binary 1. By selection of the right logic signals and suitable settings of the trimpots almost any colour combination for the time and its background could be chosen.

To prevent the display appearing superimposed on the video from unused cathodes, it will again be necessary to resort to brute force. Transistors Tr2 etc. pull down the bases of the buffer preamplifier transistor, turning the television RGB signals off. These transistors are driven from the "background b" signal which is present for the entire display on each line. A more subtle method is to use the 4016 CMOS analogue switch to intercept the video from the demodulator i.c. and substitute in its place the time display. The 4016 i.c. looks like a perfect switch in series with a 300E2 resistor. The switch is controlled by the logic gate input, the switch being closed for a binary 1 and open for a binary 0. The operating time is around 200nS, which is adequate for our application. Cathode drive RGB output stages fall into two categories: direct coupled from the demodulator to. the cathode with clamping earlier in the circuit, or a.c. coupled with clamping at the c.r.t. cathodes. Direct coupled amplifiers are the easiest ones to modify, so these will be dealt with first.

 All that's usually required here is to insert the 4016 switch in the base circuit of the output transistor. Fig. 6 shows a suitably modified red drive circuit. Switch SW1 controls the video and SW2 the voltage set by RV1. Switch SW1 is closed by the "gate video" signal from Fig. 2, and SW2 from the selected logic output (gate time, background or hue). The other two amplifiers are dealt with in a similar manner. One small modification is required to the output from the demodulator i.c. This doesn't like having no load, tending to wander off and do its own thing when the video switches are open. To prevent this, a 10k52 resistor should be added from pins 1, 2 and 4 to OV as shown. Next we must deal with a.c. coupled circuits.

A typical example is the tv chassis here described.

 The RGB output circuit (red one) used in this chassis is shown in Fig. 7. The simplest way to deal with this is to insert the 4016 switch at the point shown. Because the video is unclamped at this point, the time display levels will vary according to the picture content. For the best results it's necessary to clamp the video before substituting the time display. This is done by the transistor clamp shown in Fig. 7. The video is a.c. coupled and clamped by Tr 1. The clamp voltage of 4.7V is chosen to bias the 4016 switches in the centre of their range. The clamped video is then switched, along with the d.c. levels from the trimpot RV I, to insert the time display. The modified video is then a.c. coupled back to 3RV8 on the TV chassis. The 30052 resistance of the 4016 is effectively connected in series with 3RV8 etc. These may require slight adjustment therefore. Alternatively the dearer 4066 chip may be used. This is identical to the 4016, but has a resistance of 6052. With the general description over we can turn to the circuit in Fig. 3. IC6 and IC7 are two quad CMOS switches. IC6 gates the video from the three demodulator outputs. IC7 gates the levels on RV2 RV4 to give the three outputs on pins K, L, M. The fourth, Y, is used in older colour -difference sets and will be described later. The gating of the levels on RV2 - RV4 is done by the gate logic signals from Fig. 2. Also shown in Fig. 3 is the power supply. This is a fairly conventional i.c. regulator, made adjustable by the inclusion of Tr3 in the common return line. The operating voltage range for IC I is 12-18V, for IC2 it's 16-19V, and for the B picked up from the "gate time", "gate background a and b" outputs (Fig. 2). The trimpots RV1 etc. set the current through the output transistors and hence the cathode potentials when the logic signals are at a binary 1. By selection of the right logic signals and suitable settings of the trimpots almost any colour combination for the time series CMOS it's less than 18V. The supply chosen is 16- 17V therefore. A wire link is included so that the power supply can be adjusted before it's connected to the rest of the circuit.