PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) INTERNAL VIEW.

This version of the PHILIPS K12 is introducing the TRD TUNING SYSTEM (TUNING REMOTE DIGITAL) WHICH allows direct selection of channel frequency on front keyboard or even via remote through a help of a Ucontroller which sends command to the TRD Units system.
Furthermore it has a programmable realtime digital clock which allows to start the tellye at a prefixed time on a prefixed program.
This chassis is even showing the use of the TEXAS INSTRUMENTS TMS1000 used here as a Remote control decoder /receiver plus realtime programmable clock timer feature.


Texas Instruments TMS1000
General

General Information
Texas Instruments was locked in a race with Intel to create the first microprocessor. By most accounts Intel won with the 4004, but there are a few die hard TI fans who say the TMS1000 was first, because it was the first “computer on a chip” and that the 4004 was just a calculator chip.

Texas Instruments followed the Intel 8080 with the 4-bit TMS1000. So, while Intel was leading the industry in microprocessors, TI led with this industry unique design "a computer on a chip", specifically designed for control and automation purposes. The 1000 was the first MCU (MicroComputer Unit) , which is an MPU (MicroProcessor Unit) with other support chips (such as RAM, ROM, counters, timers, I/O interfaces) integrated on to the same silicon chip.

The original 1000 family consists of 6 chips the TMS1000 and TMS1200 are basic chips, the TMS1070 and TMS1270 are high voltage versions to interface to displays, the TMS1100 and TMS1300 provide twice the on-board ROM and RAM. The TMS1000, TMS1070, and TMS1100 are 28-lead packages, the TMS1200, TMS1270, and TMS1300 are 40-lead versions of the same chips (just 200 to the 28-lead chip numbers).

In the 80's TI added to the 1000 family. The 28-lead TMS1170 started with a TMS1100 base and added fluorescent display drive capability and expanded memory (2KB ROM). The TMS1370 was the same as the TMS1170 and added 27 I/O lines. An expanded memory group based on the original TMS1000 chips was also created. They were the TMS1400, TMS1470, and TMS1700 (64 Bytes RAM, 4KB ROM). There were 40-lead versions of the TMS1400 and TMS1470, which because the TMS1600 and TMS1670. CMOS versions were also added, denoted with a "C" suffix, such as TMS1200C.

The TMS1000 also had system evaluator chips. The original evaluator chips were the TMS1098 and TMS1099. These 64-lead evaluator chips were ROM-less versions of their corresponding standard chips. The TMS1099 supported the TMS1000/TMS1200 and the TMS1070/1270. The TMS1098 supported the TMS1100/1300. Later evaluators were introduced to support the entire TMS1000 family, they were the SE1000P (supports TMS1000,1070,1200,1700), SE2200P (supports TMS1100,1170,1300,1370), and the SE1400P (supports 1400, 1470, 1600, 1670).

The success of the the TMS1000 is demonstrated by its long lifecycle (over 20 years) and its expanded product line. The TMS1000 is found in many appliances, control systems, and games. Most of these chips were sourced by companies for direct use in their products and will have custom or house numbers on the chips (not the standard numbers listed above). Even TI used custom numbers in its products.




The PHILIPS CHASSIS K12 WAS the first PHILIPS monocarrier type. Previous K11 was a dual panel development type.

The PHILIPS chassis K12 doesn't share technology from previous CHASSIS K11 except for the 20AX SYSTEM CRT TUBE.

The chassis is a pretty unique type because it was introducing improvements and technology philosophy kindly singular and unique in it's fashion.



From signal processing to Video Matrixing to power supply technology and many further aspects this chassis was a reference to understand PHILIPS development flexibility.

This chassis has known many further versioning and enhancements even in more sophisticated and complex types with different CRT TUBE like the 30AX FAMILY.

Modularity is the main concept of construction but some Units like the E/W and FRAME UNIT gave problems in the insertion slot which often was burning the contacts producing several faults.

The solution was simple: A complete hardening with soldering and reworking of the enpoints of the Units contacts was a definitive solution for long time. But when the damage was more extended the only solution was to direct wire all contacts from Unit to chassis !



Line Deflection + EHT, Line synchronized Supply, EW Correction + Supply, Frame Deflection, Signal Section Parts.



PHILIPS   CHASSIS K12    HIGH-VOLTAGE GENERATING DEVICE / TRANSFORMER:

A high-voltage generating device which comprises a transformer having a secondary coil subdivided into sections which are series-connected via diodes. The beginning of the first section is connected to a point of fixed potential via a further diode. The beginning and the end of the first section are also connected to this fixed potential point via first and second capacitors, respectively. As a result, a tapping lead connected, for example, to the beginning of the second section provides a voltage of from one to two times the voltage difference across a section, as desired.


 Inventors: Tol, Franciscus (Eindhoven, NL) Baggermans, Albertus B. A. (Eindhoven, NL) U.S. Philips Corporation (New York, NY)


 1. A high-voltage generating device comprising, a transformer having a primary coil and a secondary coil which is divided into a plurality of sections, a plurality of diodes, means connecting the end of each section, except for the end of the last section, to the anode of a diode, the cathode of which is connected to the beginning of the next section, means connecting the end of the last section to the anode of a diode whose cathode is connected to a high-voltage lead, means connecting the cathode of at least one of the other diodes to a tapping lead, means connecting the beginning of the first section to the cathode of a diode whose anode is connected to a point of fixed potential, and means connecting the beginning and the end of the first section to the point of fixed potential via first and second capacitors, respectively.

2. A high-voltage generating device comprising, a transformer having a primary winding and a secondary winding with the secondary winding divided into a plurality of winding sections, a plurality of diodes, a high-voltage output terminal, means connecting said plurality of sections in series with said plurality of diodes between said output terminal and a point of fixed potential with each section coupled to the next section by a diode and with a first diode connecting the beginning of the first section to said point of fixed potential and a second diode connecting the end of the last section to said output terminal, first and second capacitors, means coupling the beginning and end of the first section to said point of fixed potential via said first and second capacitors respectively, and means for coupling the beginning of at least one other section to a further output terminal to supply a voltage of an amplitude determined in part by said capacitors.

3. A device as claimed in claim 2 wherein said first and second capacitors have equal capacitance values.

4. A device as claimed in claim 2 wherein said first and second capacitors have unequal capacitance values.

5. A device as claimed in claim 2 wherein said further output terminal is coupled to the beginning of the second section and wherein the voltage supplied by said further output terminal can be adjusted to a value between one and two times the voltage across a section by the choice of the relative capacitance values of said first and second capacitors.

6. A device as claimed in claims 2, 3 or 4 wherein the end of at least one winding section is directly connected to the beginning of the next winding section via said diode.

7. A device as claimed in claims 2 or 5 wherein said transformer comprises the horizontal deflection transformer of a television receiver, said output terminal supplying the high-voltage for the television receiver cathode ray tube and said further output terminal supplying the focus voltage for the cathode ray tube.

Description:

The invention relates to a high-voltage generating device, notably for a television picture tube, comprising a transformer with a secondary coil which is divided into a number of sections. The end of each section, except for the end of the last section, is connected to the anode of a diode, the cathode of each diode is connected to the beginning of the next section, but the end of the last section is connected to the anode of a diode whose cathode is connected to a high-voltage lead, the cathode of at least one of the other diodes also is connected to a tapping lead.

A device of this kind is known from the magazine "Funkschau" 1976, Heft 24, pages 1051-1054. For example, the focus voltage for a picture tube is derived from the tapping lead. The voltage at the area of this tapping depends on the number of sections and on the value of the high voltage. When a higher voltage is required, the tapping lead must be connected behind the next section on the secondary winding. In many cases, however, the voltage which is tapped off behind, for example, the first section is just too low, whereas that tapped off behind the second section is much too high.

An object of the invention is to enable a direct voltage to be tapped off behind the first section which amounts to from one to two times the voltage difference between the beginning and the end of this section.

To this end, the device in accordance with the invention is characterized in that the beginning of the first section is connected to the cathode of a diode whose anode is connected to a point carrying a fixed potential, the beginning and the end of the first section also being connected, via capacitors, to the point carrying the fixed potential.

By a suitable choice of the capacitance of the two capacitors, any voltage between one and two times the voltage across a section can be tapped off at the beginning of the second section.

It is to be noted that a transformer whose secondary winding is formed by a number of sections which are connected in series via diodes, the beginning of the first section also being connected to the cathode of a diode, is known per se from U.S. Pat. No. 4,091,349. However, in this transformer none of the intermediate diodes is connected to a tapping lead and the ends of the first section are not connected to capacitors either.

The invention will be described in detail hereinafter with reference to the accompanying diagrammatic drawing in which:

FIG. 1 shows a diagram of a known high-voltage generating device,

FIG. 2 is a diagram of the voltage present at a number of locations in the device shown in FIG. 1 at a given instant,

FIG. 3 shows a diagram of an embodiment of the device in accordance with the invention,

FIG. 4 is a diagram of the voltage present at a number of locations in the device shown in FIG. 3 at a given instant,

FIG. 5 is a diagram which represents the variation with time of the voltage in a number of locations in the device shown in FIG. 3, and

FIG. 6 shows a diagram to illustrate the voltage variation wih time at a location in various versions of the device shown in FIG. 3.


FIG.1 shows a known high-voltage generating device, comprising a transformer 1 with a primary coil 3 to which a pulse-shaped voltage is applied, for example, a line output transformer in a colour television receiver. The secondary coil is subdivided into four sections 5, 7, 9 and 11, the end of each of the first three sections 5, 7, 9 being connected to the anode of a diode 13,15, 17, respectively, the cathode thereof being connected to the beginning of the next section. The end of the last section 11 is connected to the anode of a diode 19, the cathode of which is connected to a high voltage lead 21 which is connected, for example, to the high voltage connection of a picture tube (not shown). The cathode of the first diode 13 is also connected to a tapping lead 23 wherefrom, for example, the focus voltage for said picture tube can be derived. The beginning of the first section 5 is connected, via a connection lead 25, to a point which carries a fixed potential.

FIG. 2 illustrates the voltage variation in each section, the number of turns n being plotted horizontally and the voltage V being plotted vertically. Each section consists of N turns in which voltage pulses 27 are induced. At the beginning of the first section 5, which is connected to a point carrying a fixed potential, the magnitude of the voltage pulses is zero and at the end of the turn N it is maximum and equal to U volts. The envelope 29 of the voltage pulses 27 is a straight line. Due to the strong capacitive coupling between the sections, no alternating voltages occur between corresponding turns of successive sections, so that the voltage pulses in the second section 7 vary across the section in the same manner as the pulses in the first section 5. The beginning of this second section thus carries a direct voltage U (due to the rectification of the voltage across the first section) and a pulse voltage zero, while the end of this section carries a pulse voltage of the magnitude U which is superposed on the direct voltage U. The same is applicable to the subsequent sections so that the voltage at the end of the fourth section 11 amounts to 4 U. It will be clear that the tapping lead 23 carries a voltage U.

FIG. 3 diagrammatically shows an embodiment of a device of the described kind which has been improved in accordance with the invention. Corresponding parts of the device are denoted by the same reference numerals as in FIG. 1. The difference with respect to FIG. 1 consists in that the beginning of the first section 5 is connected, by means of the connection lead 25, to the cathode of a diode 31 whose anode is connected to a point carrying a fixed potential, and in that at the beginning of the first section there is connected a first capacitor 43, a second capacitor 45 being connected to the end thereof, said capacitors also being connected to the point carrying a fixed potential.

If the capacitances of these capacitors are equal, their combined effect corresponds to that of a capacitor 33 which connects the centre of the section to a point carrying a fixed potential (denoted by a broken line).

The result of these steps is shown in FIG. 4 which shows, like FIG. 2, the voltage variation in the various sections. Thanks to the diode 31 and the effective capacitance 33, no longer the beginning but the centre of the first section 5 is maintained at a fixed potential for alternating voltages. As a result, the voltage pulses 35 induced in this section equal zero at the area of the central turn N/2 and are oppositely directed at the two ends of the section: thus

-U/2 at the beginning and +U/2 at the end. The capacitance 33 is charged so far that the diode 31 just becomes a conductive for each pulse, that is to say to a voltage +U/2 with respect to the point of fixed potential to which the anode of this diode is connected. The first section thus carries a mean voltage +U/2 on which there are superposed voltage pulses of the magnitude -U/2 at the beginning and +U/2 at the end of the section. This is shown in FIG. 5 in which the curve 37 represents the voltage variation as a function of the time at the beginning of the section. The curve 39 represents the voltage variation at the end of the section.

Due to the capacitive coupling between the first section 5 and the second section 7, corresponding turns of these two sections do not carry an alternating voltage with respect to each other, so that the voltage variation at the beginning of the second section corresponds to that of the first section, the mean voltage level, of course, being higher by the amount of te rectified voltage across the first section, so U volts. This is represented by the curve 41 in FIG. 5. It follows that the mean voltage on the tapping lead 23 equals 3 U/2 volts. This voltage is a direct voltage on which voltage pulses of -U/2 volts are superposed. If desired, these superposed voltage pulses can be eliminated by an RC network (not shown) connected to the tapping lead. Thus, a voltage is obtained on the tapping lead which is one and a half times that of the device shown in FIG. 1.

As has already been stated, it has been assumed that the capacitances of the capacitors 43, 45 are equal, so that the overall effect thereof can be represented by a capacitor 33 connected to the central turn. However, the voltage carried by the tapping lead 23 can be influenced by choosing these capacitances to be different.

When the values of the capacitors 43 and 45 are not the same, their combined effect corresponds to that of a capacitor 33 which is connected to a turn other than the central turn. The point in the section where the induced voltage pulses have the value zero is shifted accordingly across the section. When the capacitance of the first capacitor 43 is larger than that of the second capacitor 45, this point is situated nearer to the beginning of the section and vice versa. In extreme cases, this point may be situated at the beginning or at the end of the section. This means that the mean voltage level of the first section can vary from 0 to U volts. The direct voltage level of the curve 41 in FIG. 5 can vary accordingly from U to 2 U volts, the peaks of the negative pulses, of course, always reaching the level of the rectified voltage across the first section (U volts).

This is shown in FIG. 6 for a number of cases. The curve 41 in this Figure is identical to the curve 41 in FIG. 5

and relates to the symmetrical condition in which the capacitances of the capacitors 43 and 45 are equal. The curve 47 is obtained when the capacitance of the capacitor 43 (referred to hereinafter as C43) exceeds that of the capacitor 45 (referred to hereinafter as C45), so C43>C45. Curve 49 is obtained when C43<C45. Curve 51 represents an extreme situation where C43 is so large that the diode 31 is actually short-circuited for alternating voltages. This corresponds to the situation shown in FIG. 1. Finally, curve 53 represents the other extreme situation where C45 is so large that C43 can be neglected.

The foregoing demonstrates that the voltage at the tapping lead 23 can be adjusted between U and 2 U Volts by the choice of C43 and C45. The capacitors 43, 45 may consist of discrete components, but they may alternatively be formed during the winding of the section by using an adapted winding technique.

 

 

 

 

 

 

 

PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) CHASSIS K12 CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:

Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.

1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.

Description:

The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.

Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply

voltage device.

In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.

It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.

The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.


As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.

Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.

In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:



FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.

FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.

FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.

FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.

In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.

The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V _i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V _o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V _o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V ₀ . In fact, it is readily evident that output voltage V _o is proportional to the ratio δ :

V _o = V _i ^. δ

Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V ₀ . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V _o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V _o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).

However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V _o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.

In addition this facilitates smoothing of voltage V _o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V _o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.

It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.

In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.

A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.

In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V _o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.

It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i _C which flows in the collector of transistor 16 and of the drive voltage v ₁₄ across the terminals of secondary winding 14. During the flyback period (0, t ₁ ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v ₁₄ must then be absolutely negative. During the scan period (t ₁ , t ₄ ) a sawtooth current i _C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t ₃ when current i _C becomes zero lies, as is known, before the middle of the scan period. At the end t ₄ of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t _s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v ₁₄ is positive must end at the latest at the instant (t ₄ - t _s ) located after the commencement (t = 0) of the previous flyback.

The time δ T may be initiated at any instant t ₂ which is located between the end t ₁ of the flyback period and the instant t ₃ when collector current i _C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t ₂ , but collector current i _C is not influenced thereby, at least not when the supply voltage (= V _o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i _C of FIG. 2a represents the current flowing through the said efficiency diode.

After the instant t ₃ voltage v ₁₄ must be positive. In other words, the minimum duration of the period T when voltage v ₁₄ must be positive is (t ₄ - t _s ) - t ₃ whilst the maximum duration thereof is (t ₄ - t _s ) - t ₁ . In a television system employing 625 lines per raster the line period t ₄ is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t ₃ would be located approximately 26 μus after the instant t ₁ , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t _s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V _i has a peak-to-peak value of 40 V and V _i is nominally 270 V, then the lowest occurring V _i is:

0.85 × 270 V - 20 V = 210 V and the highest occurring V _i is

1.1 × 270 V + 20 V = 320 V. For an output voltage V _o of 135 V the ratio must thus vary between

δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.

A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V _i - V _o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V _o is maintained constant at nominal mains voltage V _o = δ V _inom . However, if as a result of an increase or a decrease of the mains voltage V _i increases or decreases proportionally therewith, i.e., V _i = V _i nom + Δ V, the positive portion of V ₁₄ becomes equal to n(V _i nom - V _o +Δ V) = n [(1 -δ)V _i nom +ΔV] = n(0.5 V _inom +ΔV) if δ = 0.5 for V _i = V _i nom. Relatively, this is a variation which is twice as great. For example, if V _i nom = 270 V and V _o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V _i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.

This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i _b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i _b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V _i = V _i nom +Δ V, then ##SPC1## because V _i nom = 2 V _o . Thus this variation is equal to that of the mains voltage and is not twice as great.

During switching off, t ₂ , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.

The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.

FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V _i - V _o = 0.5 V _i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V _i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.

Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.

In this connection it is to be noted that it is possible to obtain an output voltage V _o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V _i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.

The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.

If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V _o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V _o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.

The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V _o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V _i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.

Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V _o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.

Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.

As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.

A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V _o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.

Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.

The 50 Hz ripple voltage which is superimposed on the rectified input voltage V _i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V _i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.

PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) PHILIPS TRD (Tuning Remote Digital) Search type tuning system Chassis K12:Dics-Digital Tuning System For TV Receivers" by N.V. Philips' Gloeilampenfabrieken, Netherlands, 2/1977

A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past thosechannels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning systemfor a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control)detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.

Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuningsystems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.

Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptablereception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
The present invention relates to a television set which includes a picture display device, an alpha numerical character generating circuit connected to the said device, a control device and means for checking analogue data relating to the operation of the set, such as volume, brightness and color. The system commonly used on television receivers for tuning into the required channels is the so-called FREQUENCY SYNTHESIZER system. This system, made possible by the advent of integrated circuits, offers a number of advantages over other known systems, such as the conventional potentiometer type MECHANICAL MEMORY systems and the more recent so-called VOLTAGE SYNTHESIZER systems. The frequency synthesizer system is fully electronic enabling any channel to be called up directly by the user who formulates the channel number on a keyboard or other control device. The system usually consists of a quartz-controlled reference oscillator, a phase lock loop, a programmable divider and a computer which supplies the number to be sent to the programmable divider in response to the number of the channel set by the user. Thanks to the phase lock loop, for each channel number set by the user, the frequency of the local oscillator on the set is kept so stable and accurate that the set is tuned with great precision to the corresponding channel signal. For further details concerning frequency synthesizer tuning systems, refer to the article entitled "A Frequency Synthesizer for Television Receivers" by E. G. Breeze, published in the November, 1974 issue of the "Transactions BTR" Magazine, or "Digital Television Tuner Uses MOS LSI and Non Volatile Memory" by L. Penner, published in the April 1, 1976 issue of "Electronics".

The PHILIPS TRD Channel selection is controlled by a frequency synthesizer a sweep of available channels is made by a channel selecting arrangement and this sweep is arranged to be stopped when a signal is received. When the sweeping is stopped a fine tuning arrangement takes control to respond to the frequency of the received signal and to compensate for any drift of that signal.
According to this invention there is provided a receiver comprising frequency synthesizer controlled channel selection means which includes a fine tuning arrangement; means for initiating a sweep of available channels by the channel selection means; means for stopping the sweep on reception of a signal and means, operable on cessation of sweeping and responsive to the frequency of the signal, and arranged to control the fine tuning arrangement to compensate for frequency drift of the signal.
The receiver may be in the form of a television receiver.
The means operable a cessation of sweeping may comprise level detector means arranged to receive a signal whose level is representative of the frequency of the received signal and to provide an output signal when a predetermined frequency drift is detected.
In a preferred form two level comparators are provided each arranged to receive the frequency representative signal and a respective reference level and to provide an output respectively representative of an upward and downward frequency drift exceeding predetermined limits.
The signal whose level is representative of the frequency of the received signal may be provided by automatic frequency control (A.F.C.) means conveniently in the form of an A.F.C. discriminator.
The means operable or cessation of sweeping may be arranged to control the fine tuning arrangement via a signal path which includes means for blocking said signal path until the said signal is received.
The means for blocking may be in the form of gate means connected to the said signal path and arranged to receive a second input a signal indicative of the receipt of the said signal.
The means for initiating a sweep may comprise an operator control coupled to control input means of the channel selection means, and the means for stopping sweeping is operative to isolate the operator control from the said control input means.
The operator may be coupled to the channel selection means via gating means operative to open an operation of the operator control and the means for stopping sweeping may provide a signal operative to block the gating means or receipt of the said signal.
The means for stopping sweeping may include means for detecting the reception of the said signal which in a preferred form of television receiver comprises a sync comparator operative to compare video signals with line flyback signals and to provide an output signal whose level is indicitive of the reception of the said signal.
The frequency synthesizer system lends itself well to a number of different modes of television chanel tuning;
direct selection by formulating the required channel number as described above television channels are numbered: for example, in the European C.C.I.R. standard, V.H.F. band channels are numbered from 2 to 12 and U.H.F. band channels from 21 to 69; in the American Standard, VHF channels are numbered from 2 to 13 and UHF from 14 to 83).
memory selection: each of a certain set of keys corresponds to a preselected and memorised channel;
automatic scanning of all the channels of a given standard, or of all the channels contained in the memory or continuous scanning of all the frequency bands involved.
The first application enables immediate, direct selection of any one of the channels in the relative standard (60 in Europe, 82 in America).
the second enables faster detection of one of a limited number of preferred channels.
The third is a fast, simple way of finding out which standard channels can be received, which channels have been memorised and whether other broadcasting stations exist on non-standard frequencies such as the private broadcasting stations in Italy (there are currently over a hundred operating).

Other References:

Olson et al., "The Practical Application of On-Screen Display to a Television Receiver", IEEE Transactions on Broadcast and TV Receivers, _Aug. 1973, pp. 169-175.
Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.


A)- A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A first programmable frequency divider controlled by a reversible counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator, after passing through another programmable frequency divider, also is applied. The phase comparator output is a tuning voltage used to control the tuning of the local oscillator. A logic circuit is coupled to sense predetermined relationships of signals from a picture carrier detector, a sound carrier detector, an AFT discriminator circuit, and the presence of vertical synchronization signal components for changing the count in the reversible binary counter to adjust the first programmable frequency divider to compensate for channel frequency offsets which may occur in excess of the pull-in range of the AFT discriminator circuit. To permit operation of the receiver as a signal seek receiver, a pair of signal seek pushbuttons for the "up" and for the "down" direction, respectively, are provided. Operation of either of these pushbuttons functions in conjunction with further logic circuitry and in conjunction with timing circuitry to automatically step tune the receiver channel-by-channel in the selected direction until a channel with a signal present is sensed by the first logic circuit, whereupon the signal seek circuit operation is disabled until one or the other of the signal seek pushbuttons is reactivated.
1. A frequency synthesizer signal seek tuning system for a tuner of a television receiver capable of receiving a composite television signal, said system including in combination:

reference oscillator means providing a reference signal at a predetermined frequency;

local oscillator means in the tuner providing a variable output frequency in response to the application of a control signal thereto;

a programmable frequency divider having an input coupled to said reference oscillator means for producing an output signal having a frequency which is a programmable fraction of the frequency of the signal applied to the input thereto from saidreference oscillator means;

means coupled to the output of said programmable frequency divider and the output of said local oscillator means for developing a control signal and applying such control signal to said local oscillator means for controlling the frequency ofoperation thereof;

channel selection means coupled to said programmable frequency divider for establishing a predetermined initial programmable fraction therein each time a new channel is selected by said channel selection means;

control means coupled to the output of the tuner of the television receiver and further coupled to said programmable frequency divider for controlling said frequency divider to change the programmable fraction thereof in response to predeterminedconditions of the signals from the tuner; and

signal seek tuning means coupled to said channel selection means and said control means for causing said channel selection means to select a new channel in response to said predetermined conditions of the tuner signals persisting for a predetermined time period.

2. The combination according to claim 1, wherein the composite television signal has at least carrier signal components and synchronizing signal components and further including carrier sensing means coupled to receive at least the carriersignal components of the composite signal from the tuner and providing an output voltage indicative of the tuning of said receiver to a carrier component of said composite signal; and synchronizing signal component sensing means coupled to receive atleast said synchronizing signal components of the composite signal for providing a first predetermined output with synchronizing signal components sensed thereby; wherein said control means is coupled to the outputs of said carrier sensing means andsaid synchronizing signal components sensing means and further coupled to said programmable frequency divider means for changing the programmable fraction thereof in response to first predetermined conditions of signals at the outputs of said carriersensing means and said synchronizing signal components sensing means and the operation of said signal seek tuning means being terminated in response to second predetermined conditions of signals at the outputs of said carrier sensing means and saidsynchronizing signal components sensing means.

3. The combination according to claim 1, further including first and second switches in said signal seek tuning means for initiating a signal seek operation in the "up" and "down" directions, respectively, operation of one of said first andsecond switches causing said channel selection means to select the next channel in the selected direction and establishing said predetermined initial programmable fraction in said programmable frequency divider in response thereto.

4. The combination according to claim 3, wherein said control means terminates operation of said signal seek means in response to detection of second predetermined conditions of the signals from the tuner.

5. The combination according to claim 1, wherein said predetermined conditions of the tuner signals comprise first and second predetermined conditions, respectively; said programmable frequency divider has its input coupled to the output ofsaid reference oscillator means; and wherein said control means includes reversible digital counter means coupled to said programmable frequency divider, and logic circuit means coupled to the output of the tuner for causing said counter means to countin one direction when said first predetermined conditions exist and to count in the opposite direction when said second predetermined conditions exist.

6. The combination according to claim 5, further including additional means coupled to said counter means and coupled to said logic circuit means for inhibiting operation of said signal seek tuning means and for preventing a change in the countof said counter means when third predetermined signal conditions exist in the tuner output.

7. The combination according to claim 6, further including a second programmable frequency divider coupled to the output of said local oscillator means and producing an output signal having a frequency which is a programmable fraction of thefrequency of the signal applied to the input thereto from said local oscillator means; and wherein said channel selection means is further coupled to said second programmable frequency divider for controlling said second programmable frequency dividerto establish the programmable fraction thereof each time a new channel is selected by said channel selection means.

B)- A tuning system for a television receiver includes a local oscillator which is controlled first by a phase lock loop arrangement and then by an AFT discriminator arrangement for tuning the receiver to non-standard as well as standard frequency carriers. The phase lock loop arrangement includes a programmable divider for dividing the local oscillator frequency by a programmable factor corresponding to the presently selected channel. When the local oscillator is being controlled by the AFT discriminator arrangement, the count accumulated by the programmable divider during a reference interval determines how far the local oscillator frequency has drifted from its nominal value. If a predetermined frequency offset has been exceeded, control is returned to phase lock loop control and the programmable factor is incrementally changed.

1. In a system for tuning a television receiver to the various channels a viewer may select, apparatus comprising:

local oscillator means for generating a local oscillator signal;

counter means for generating a frequency divided signal by counting a predetermined number of periods of said local oscillator signal, said predetermined number being proportional to the frequency of said local oscillator signal;

means for generating a reference frequency signal;

phase control means for generating a control signal representing the phase and frequency deviation between said frequency divided signal and said reference frequency signal;

mode switching means for selectively coupling said control signal to said local oscillator means; said mode switching means initially coupling said control signal to said local oscillator means;

said local oscillator means changing the frequency of said local oscillator signal in response to said control signal until said frequency divided signal and said reference frequency signal to be in a predetermined phase and frequency relation;

said counter means accumulating a nominal number of counts during a predetermined portion of said frequency divided signal when said frequency divided signal and said reference signal are in said predetermined phase and frequency relationship;

means for generating a lock signal when said frequency divided signal and said reference frequency signal are in said predetermined phase and frequency relationship;

said mode switching means decoupling said control signal from said local oscillator means in response to said lock signal;

means for generating a count signal when said control signal is decoupled from said local oscillator means, said count signal having a duration with a predetermined time relationship to said reference frequency signal;

means responsive to said count signal for disabling said counter means from counting when said control signal is decoupled from said local oscillator means except during the duration of said count signal; and

means for generating an offset signal representing the deviation between the count accumulated by said counter means during a time interval corresponding to said predetermined portion of said frequency divided signal when said control signal isdecoupled from said local oscillator means and said nominal number of counts, said offset signal being coupled to said mode switching means to control the coupling of said control signal to said local oscillator means.

2. The apparatus recited in claim 1 wherein said means for generating said offset signal includes:

memory means for generating an output signal having a first amplitude when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;

means for resetting said memory means prior to the occurrence of said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillator means;

means for setting said memory means if the count accumulated by said counter during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillatormeans is less than said nominal number of counts by a first predetermined deviation; and

means for resetting said memory means if the count accumulated by said counter means during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said localoscillator means is greater than said nominal number of counts by a second predetermined deviation.

3. The apparatus recited in claim 1 wherein said counter means derives said frequency divided signal by counting a first number of periods during a first portion of said frequency divided signal and by counting a second number of periods duringa second portion of said frequency divided signal.

4. The apparatus recited in claim 3 wherein the various channels a viewer may select are partitioned into frequency bands, said first number is related to the channel selected by a viewer and said second number is related to the frequency bandin which the selected channel resides.

5. The apparatus recited in claim 4 wherein said predetermined portion is at least a part of said second portion.

6. The apparatus recited in claim 5 wherein said counter includes:

variable modulus frequency divider means for selectively dividing the frequency of said local oscillator signal by a first factor or a second factor, said first factor being related to the frequency spacing between channels in at least one ofsaid bands;

decade counter means for counting periods of the output signal of said variable modulus frequency divider;

channel number comparator means for generating a channel match signal when the number of periods counted by said decade counter means equals said first number, said decade counter means being reset in response to said channel match signal;

first factor stop comparator means for generating a first factor stop signal when the number of periods counted by said decade counter means equals a third number, said third number being also related to the band in which the selected channelresides but less than said second number, said variable modulus divider means being caused to divide by said second factor in response to said first factor stop signal; and

added count comparator means for generating an added count match signal when the number of periods counted by said decade counter means equals said second number, said decade counter means being reset in response to said added count match signal,said variable modulus divider means being caused to divide by said first factor in response to said added count match signal.

7. The apparatus recited in claim 6 wherein said nominal number of counts equals said second number.

8. The apparatus recited in claim 7 wherein said means for generating said offset signal includes means for resetting at least said decade counter means and for causing said variable modulus divider to divide by said first factor in response tothe initiation of said count signal.

9. The apparatus recited in claim 7 wherein said means for generating said offset signal includes:

memory means for generating an output signal when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;

means for resetting said memory means prior to the occurrence of said first factor stop signal during the duration of said count signal when said control signal is decoupled from said local oscillator;

means for inhibiting the generation of said added count signal when said control signal is decoupled from said local oscillator;

means for setting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is less than said second number by a first predetermineddeviation; and

means for resetting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is greater than said second number by a secondpredetermined deviation.

10. The apparatus recited in claim 9 wherein said means for generating said offset signal includes means for repetitively generating said offset signal.

11. The apparatus recited in claim 1 wherein said means for disabling said counter means includes input switching means for selectively decoupling said local oscillator signal from said counter means when said control signal is decoupled fromsaid local oscillator means except in response to said count signal; and

said counter means includes means for generating an illegal signal when an illegal channel has been selected;

said input switching means also decoupling said local oscillator signal from said counter means in response to said illegal signal.

12. The apparatus recited in claim 11 wherein:

said means for generating said illegal signal includes band selection means for generating a band traversed signal whenever the count accumulated by said counter corresponds to the boundary of a band and means for generating a band signalrepresenting the band in which the selected channel resides in accordance with which of said band traversed signals have been generated during said first portion of said frequency divided signal, said means for generating a band signal generating saidillegal signal when a band signal is not generated.

13. The apparatus recited in claim 11 wherein said means for generating said reference frequency also includes means for deriving a signal having a predetermined frequency; and said input means includes means for coupling said signal having apredetermined frequency to said counter means in response to said illegal signal.
Description: The present invention pertains to television tuning systems including a phase locked loop frequency synthesizerand particularly pertains to frequency counters which may be utilized in such systems.

In concurrently filed U.S. patent application Ser. No. 70,849, and now U.S. Pat. No. 4,031,549 by Henderson et al., assigned to the same assignee as the present invention, there is described a tuning device system for a television receiverwhich includes a phase locked loop for tuning a local oscilator to the nominal local oscillator frequencies required to tune the receiver to RF carriers at standard broadcast frequencies allocated to the various channels a viewer may select. The tuningsystem also includes an automatic fine tuning (AFT) frequency discriminator for tuning the local oscillator to minimize any deviation between the frequency of an actual picture carrier and the nominal picture carrier frequency. If the receiver iscoupled to a television distribution system which provides RF carriers having nonstandard frequencies arbitrarily near respective ones of the standard broadcast frequencies, when the phase locked loop has achieved lock at a nominal frequency, a modecontrol unit selectively couples the discriminator and a frequency drift control circuit to the local oscillator. If the frequency of the local oscillator drifts more than a predetermined offset from the frequency synthesized under phase locked loopcontrol because no carrier has been detected by the discriminator, discriminator and drift control are terminated so that the receiver will not be tuned to an undesired carrier such as, for example, the lower adjacent channel sound carrier, and phaselocked loop control is reinitiated to synthesize a local oscillator signal having a frequency incremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. After the phase locked loop is locked at anincremented frequency, discriminator control is again initiated. If, during this cycle of discriminator control, the local oscillator again drifts more than the predetermined offset from the incremented local oscillator frequency because no carrier isdetected by the discriminator, phase locked loop control is again reinitiated to synthesize a local oscillator signal having a frequency decremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. Ifduring any discriminator control cycle the local oscillator has not drifted further than the predetermined offset because the discriminator has tuned the local oscillator to a carrier within the predetermined offset, phase locked loop control is notreinitiated and the tuning sequence is complete.

In order to reduce the complexity, and therefore the cost, of an implementation of such a tuning system, it is desirable that individual potions of the system be capable of performing more than one function. For example, in copending UnitedStates Patent Application Ser. No. 663,097 filed for R. M. Rast on Feb. 27, 1976, and now U.S. Pat. No. 4,009,439 and assigned to the same assignee as the present invention, which is hereby incorporated by reference, there is described a frequencydivider for a television tuning phase locked loop tuning system. For each channel a viewer selects, the divider divides the frequency of the local oscillator signal by a number proportional to the nominal local oscillator frequency by forming a signalincluding first and second portions having durations respectively equal to first and second numbers of periods of the local oscillator signal. The first number is related to the selected channel number. The second number is related to the frequencyband in which the selected channel resides. To generate signals including in which band the selected channel resides for use in the phase locked loop itself and in the local oscillator to control its frequency range, a band selection unit is included asan integral part of the divider.

In accordance with the present invention, a programmable counter which may be used, for example, in a phase locked loop portion of a tuning system of the type decribed in the concurrently filed Henderson et al. application referenced above todivide the frequency of the local oscillator by a number proportional to the nominal local oscillator frequency for a selected channel is arranged so that it may also serve to generate a signal indicating whether or not the frequency of the localoscillator has drifted beyond a predetermined frequency offset after phase locked loop control of the local oscillator has been terminated. When the local oscillator is under phase locked loop control, the programmable counter accumulates a nominalnumber of counts during a predetermined portion of its output signal. Means are provided for generating a count signal after phase locked loop control of the local oscillator has been terminated. The count signal has a duration with a predeterminedtime relationship to a reference signal to which the local oscillator signal is locked when the local oscillator is under phase locked loop control. The counter is disabled from counting when the local oscillator is not under phase locked loop controlexcept during the duration of the count signal. Offset detection means, in response to the count signal, generates an offset signal representing the deviation between the count accumulated during a time interval corresponding to the predeterminedportion after phase locked loop control of the local oscillator has been terminated to determine how far the frequency of the local oscillator has drifted from the frequency synthesized under phase locked loop control.


C)- A tuning system for a television receiver includes a phase locked loop (PLL) configuration and an automatic fine tuning (AFT) configuration which are selectively enabled to operate to tune the receiver to nonstandard as well as standard frequency RF carriers which may be provided by cable and master antenna systems. After the selection of a new channel, the operations of the PLL and AFT configurations are sequentially enabled by a mode control apparatus. During the operation of the AFT configuration, an offset detector determines when the frequency of the local oscillator signal is caused to be more than a predetermined offset from its value established during the previous operation of the PLL configuration. In response, the mode control unit reestablishes the operation of the PLL configuration. Channel selection apparatus causes a new channel to be selected after a predetermined number of alternate operating cycles of the two configurations.

1. Apparatus for selectively tuning a receiver to any one of a plurality of RF carriers associated with respective channels, comprising:
local oscillator means for generating a local oscillator signal;
mixer means for combining a selected one of said RF carriers with said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value;
phase locked loop (PLL) means for selectively controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal;
programmable factor control means for determining programmable factor in accordance with the channel selected and for generating a CHANGE signal when a new channel is selected;
lock means for generating a LOCK signal when said local oscillator signal has a frequency substantially equal to said programmed frequency;
automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value;
offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means;
mode control means for enabling the operation of said PLL means in response to said CHANGE signal, for enabling the operation of said AFT means in response to said LOCK signal and for again enabling the operation of said PLL means in response to said OFFSET signal; and
channel selection means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated a predetermined number of times.
2. The apparatus recited in claim 1 wherein:
said predetermined number of times is equal to one.
3. The apparatus recited in claim 1 wherein:
said programmable factor control means is coupled to counter means for counting the number of times said OFFSET signal is generated to change said programmable factor by an increment less than the difference between programmable factors associated with respective adjacent channels when said OFFSET signal is generated a second predetermined number of times less than said first mentioned predetermined number of times; and
said channel selection means is also coupled to said counter means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated said first mentioned predetermined number of times.
4. The apparatus recited in claim 3 wherein:
said programmable factor control means increases said programmable factor by said increment in response to a first generation of said OFFSET signal and decreases said programmable factor by said increment in response to a second generation of said OFFSET signal and changes said programmable factor to the value associated with the next channel in response to a third generation of said OFFSET signal.
5. The apparatus recited in claim 4 wherein:
said programmable factor control means includes inhibiting means for inhibiting said programmable factor control means from changing said programmable factor to the value in response to said OFFSET signal after a predetermined time longer than the time required to tune said receiver to a selected channel.

Description:

BACKGROUND OF THE PRESENT INVENTION
The present invention relates to search type tuning systems.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past those channels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning system for a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control) detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuning systems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.
Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptable reception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
SUMMARY OF THE PRESENT INVENTION
The present invention is an improvement to the type of electronic tuning system which includes first tuning means for tuning a tuner to standard frequencies associated with respective channels, second tuning means for tuning the tuner to reduce deviations between the frequency of an IF carrier generated by the tuner and its desired or nominal value that may arise due to, e.g., offsets in the frequencies of received RF carriers, and mode switching means for selectively applying the first and second tuning control signals to the tuner. In this type of electronic tuning system, the operation of the first tuning means is enabled after a new channel is selected and the operation of the second tuning means is enabled after the first tuning means has completed its operation. During the operation of the second tuning means, an offset detector determines when the frequency of a local oscillator signal generated by the tuner becomes offset from value established during the operation of the first tuning means and causes the operation of the first tuning means to again be enabled.
In accordance with the present invention, search means are provided in the above described type of electronic tuning system for causing a new channel to be selected if no RF carrier is tuned by the end of a predetermined number of operating cycles of the second tuning means.

PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) CONVERGENCE CORRECTION CIRCUIT 20AX PHILIPS CHASSIS K12
Colour television display apparatus incorporating a television display tube

Colour television display apparatus provided with a display tube in which the electron beams are generated in one plane. The deflection coils are designed in such known manner that the landing points of the beams on the display screen coincide. Owing to tolerance angular errors of the orientation of the plane relative to one direction of deflection convergence errors are produced in the other direction of deflection. They are corrected by means of a magnetic quadripolar field the polar axes of which substantially coincide with the directions of deflection and the field strength of which is a substantially quadratic function of either deflection current or the sum of both functions.

1. Colour television display apparatus incorporating a television display tube having a display screen and two deflection coils for the deflection in two directions of electron beams which are generated in the tube substantially in one plane, a first direction of deflection being substantially parallel to the said plane whilst the second direction of deflection is substantially at right angles to the first direction, the field generated by the deflection coil for deflection in the first direction having a distribution in which its meridional image plane substantially coincides with the screen whilst the field generated by the deflection coil for deflection in the second direction has a distribution in which its sagittal image plane substantially coincides with the screen, the deflection errors due to comma and anisotropic astigmatism being substantially equal to zero, whilst at least one deflection coil is divided into two substantially equal coil halves, characterized in that in order to correct for tolerance angular errors in the orientation of the plane in which the electron beams are generated relative to the first direction of deflection the split deflection coil generates a magnetic quadripolar field the polar axes of which substantially coincide with the directions of deflection and the field strength of which is a substantially quadratic function of the instantaneous strength of the deflection current flowing through at least one deflection coil, and means for clamping the peak of said quadratic field. 2. Apparatus as claimed in claim 1, characterized in that a substantially parabolic correction current which is adjustable in amplitude and in polarity flows in the same direction as the deflection current in one coil half and in the opposite direction in the other coil half and is zero at the middle of the trace interval of the deflection current. 3. Apparatus as claimed in claim 2, in which one direction of deflection is horizontal and the other is vertical, characterized in that a line-frequency correcting current flows through the coil halves of the deflection coil for horizontal deflection and a field-frequency correction current flows through the coil halves of the deflection coil for vertical deflection. 4. Apparatus as claimed in claim 2, characterized in that a sawtooth current supplied by the deflection current generator which produces the deflection current flows through a potentiometer the setting of the slider on which determines the adjustment of the polarity and of the amplitude of the correcting current. 5. Apparatus as claimed in claim 4, in which the deflection current is of field frequency, characterized in that the setting of the slider on the potentiometer also renders symmetrical the deflection fields generated by the coil halves. 6. A display apparatus as claimed in claim 1 wherein said split coil field strength is substantially the sum of quadratic functions of the current flowing through both coils. 7. A color television deflection system for a television display tube having a display screen, said system comprising two deflection coils for the deflection in two directions of electron beams which are generated in the tube substantially in one plane, said first direction of deflection being substantially parallel to the said plane, the second direction of deflection being substantially at right angles to the first direction, the field generated by the deflection coil for deflection in the first direction having a distribution in which its meridional image plane substantially coincides with the screen, the field generated by the deflection coil for deflection in the second direction having a distribution in which its sagittal image plane substantially coincides with the screen, the deflection errors due to comma and anisotropic astigmatism being substantially equal to zero, at least one deflection coil comprising two substantially equal coil halves, means for correcting for tolernace angular errors in the orientation of the plane in which the electron beams are generated relative to the first direction of deflection comprising means for providing that the split deflection coil generates a magnetic quadripolar field the polar axes of which substantially coincide with the directions of deflection and the field strength of which is a substantially quadratic function of the instantaneous strength of the deflection current flowing through at least one deflection coil, and means for clamping the peak of said quadratic field. 8. A deflection system as claimed in claim 7 wherein said split coil field strength is substantially the sum of quadratic functions of the current flowing through both coils.

Description:

The invention relates to a colour television display apparatus incorporating a television display tube having a display screen and two deflection coils for the deflection in two directions of electron beams which are generated in the tube substantially in one plane, a first direction of deflection being substantially parallel to the said plane whilst the second direction of deflection is substantially at right angles to the first direction, the field generated by the deflection coil for deflection in the first direction having a distribution in which its meridional image plane substantially coincides with the screen whilst the field generated by the deflection coil for deflection in the second direction has a distribution in which its sagittal image plane substantially coincides with the screen, the deflection errors due to comma and anisotropic astigmatism being substantially zero, whilst at least one deflection coil is split into two substantially equal coil halves.

Such an apparatus is described by J. Haantjes and G. J. Lubben in "Philips Research Reports", Volume 14, February 1959, pages 65-97 and in U.S. Pat. No. 2,886,125. In this apparatus the landing points of the electron beams on the display screen coincide everywhere, in other words the various beams, which generally are three in number, which intersect the deflection plane along a straight line are imaged as points on the screen. It is assumed that both the construction of the device or devices which generate the beams, for example three cathodes, and the distribution of the deflection fields exactly satisfy the requirements derived in the said paper. In practice, however errors are produced which are due to tolerances so that the images of the beams on the screen are not points but lines which are substantially parallel to the second direction, i.e. convergence errors, for when a point is referred to what is actually meant is that each electron beam strikes a phosphor dot or stripe on the screen to cause it to luminesce in a given colour, the landing points being associated so as to be perceived as a single point. This is no longer the case if the aforementioned straight line, which is the projection of the plane of the three cathodes in the deflection plane, does not exactly coincide with the first direction of deflection but is at an angle thereto. This error is a tolerance error, i.e. it is small, and may be due to a slight misplacement of the cathodes and/or to a slightly incorrect field distribution within the display tube and hence to tolerances in the construction of the deflection coils.

If the first direction of deflection is horizontal and the second one is vertical, the said error entails a convergence error in the vertical direction. The aforementioned straight line in the deflection plane can be made to coincide with the horizontal direction of deflection by rotation. Attempts have been made to cancel the convergence errors due to this rotation by means of a coil which is axially arranged on the neck of the display tube and through which an adjustable direct current flows. The effect of this coil is comparable to that of a focussing coil; it exerts a force on the travelling electrons which causes their paths to be helical, so that some compensation is obtained. It has been found, however, that this solution has the following disadvantages: the residual errors in the corners are increased; the effect on the horizontal and vertical directions are different, so that satisfactory adjustment in both directions is difficult to realise; depending upon the axial position an undesirable influence may occur at the centre of the screen which in turn can be eliminated by the means, for example permanent magnets, provided for static convergence, requiring iterative and hence time-consuming trimming. Furthermore the coil is an expensive component.

The present invention is based on the recognition that the aforementioned convergence errors due to tolerance errors in the construction of the display tube and/or of the deflection coils can be eliminated by means of simple circuits without the need for additional components to be mounted on the neck of the display tube whilst avoiding the aforementioned disadvantages. For this purpose the apparatus according to the invention is characterized in that to correct for tolerance angular errors in the orientation of the plane in which the electron beams are generated relative to the first direction of deflection the split deflection coil generates a magnetic quadripolar field the polar axes of which substantially coincide with the directions of deflection and the field strength of which is a substantially quadratic function of the instantaneous strength of the deflection current flowing through either deflection coil or the sum of both quadratic functions.

It should be mentioned that it is known to use a split deflection coil to generate a quadripolar field the polar axes of which substantially coincide with the directions of deflection. This is described in U. S. Pat. No. 3,440,483 in which, however, the field strength of the quadripolar field is a function of the product of the values of the two deflection currents so that deflection errors due to anisotropic astigmatism can be corrected. In contradistinction thereto the present application described an apparatus having substantially no anistropic astigmatism whilst the quadripolar field generated according to the invention has a field strength which depends upon the value of either deflection current or upon the sum of the squares of the two deflection currents. For the sake of clarity it should be mentioned that in the apparatus according to the said U.S. Patent, in the absence of the correction quadripolar field described, the image of a beam on the screen is a tilted ellipse, whereas in the present application the corresponding image when not corrected is a vertical line.

The known apparatus has some isotropic astigmatism so that the vertical focal lines, i.e. the Meridional focal lines of the horizontal deflection plane and the sagittal focal lines of the vertical deflection plane, coincide with the display screen. Since the imaginary ribbon-shaped beam produced by the three beams together has substantially no dimension in the vertical direction, its image on the screen is a point. In these circumstances the term "isotropic astigmatism" as used herein in actual fact is to be understood to mean that the coefficients which determine the isotropic astigmatism differ from the desired values. Consequently the cross-sectional area on the screen of the imaginary thick beam of circular cross-section in the deflection plane (see FIG. 2 of the said paper in which, however, the three beams are generated in a vertical plane) does not degenerate into a straight line but takes the form of an ellipse the axes of which are parallel to the directions of deflection. Means for correcting such undesirable isotropic astigmatism is described in U.S. patent application Ser. No. 447,564 filed March 4, 1974. In this means a correcting quadripolar field which varies with the square of the strength of either deflection current is generated in the deflection region. However, the axes of said quadripolar field lie substantially along the diagonal between the axes of the deflection directions and the field is generated by separate windings and not by the deflection coil or coils. It should be noted that the apparatus according to the invention also may be subject to this defect which in this case may be corrected in the manner described in the said U.S. patent application. For the sake of simplicity this will be disregarded hereinafter, that is to say the deflection coil will be assumed to have the correct degree of isotropic astigmatism, causing the landing points of the beams on the screen to coincide in one point everywhere but for the abovementioned tolerance error.

In order that the invention may be more readily understood, embodiments thereof will now be described by way of example with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 is a sectional view of a colour television display tube subject to the defect to be corrected,

FIG. 2 shows schematically the ensuring convergence error on the display screen of the tube,

FIGS. 3, 4, 5 and 7 are circuit diagrams of embodiments of correction circuits, and

FIG. 6 is a wave form obtained in the circuit of FIG. 5.

FIG. 1 is a simplified elevation of a cross-section of a colour television display tube 1 taken on the deflection plane at right angles to the axis of the tube in a direction opposite to the direction of propagation of the electron beams, the deflection coils being omitted for simplicity. Three electron beams L, C and R are generated in one plane, the beam C substantially coinciding with the axis of the tube 1 and the beams L and R being located to the left and to the right respectively of the beam C. If the construction of the devices, for example cathodes, which generate the beams and the field distribution within the tube 1 were exactly as desired, the points of intersection of the beams L, C and R with the deflection plane would be a straight line coinciding for example with the X axis, which coincides with the direction of horizontal deflection, the Y axis coinciding with the direction of vertical deflection. However, owing to tolerances the points of intersection lie on a straight line D which is at an angle α to the X axis which it intersects in C.

The paper mentioned in the second paragraph of this application shows that an imaginary thick beam may be considered the cross-section S of which with the plane of deflection is a circle. The line section LCR of FIG. 1 is a diameter of this circle. If the horizontal deflection field has a distribution in which the meridional image plane substantially coincides with the display screen of the tube 1 whilst the vertical deflection field has a distribution in which the sagittal image plane substantially coincides with the screen, and if moreover the deflection errors due to comma and both anisotropic and isotropic astigmatism are substantially equal to zero, all the points on and within the circle S are imaged on vertical line everwhere on the screen. It is supposed that the correct degree of isotropic astigmatism is actually obtained. Otherwise the image of the circle S would be an ellipse the axes of which are parallel to the X and Y axes, i.e. there would be a horizontal convergence error.

In these circumstances the beams L, C and R of FIG. 3 are imaged on the screen 2 of the tube 1 along vertical lines, some of which are shown (in exaggerated form) in FIG. 2, with the exception of the image at the midpoint of the screen, i.e. without deflection, where they coincide. In the ideal case in which the beams L and R of FIG. 1 would lie on the X axis, i.e. with α = 0, in each triplet L', C', R' in FIG. 2 the points L' and R' would coincide with the point C'. Consequently the error angle α results in a vertical convergence error on the screen. In FIG. 1 the beam L lies above the X axis and the beam R beneath the X axis. Because the beams cross within the tube, the points L' and R' in FIG. 2 always lie beneath and above the point C' respectively.

According to the invention a magnetic correction quadripolar field is generated the polar axes of which substantially coincide with the X and Y axes and four lines of force of which are shown in FIG. 1. The quadripolar field does not influence the beam C which is located at the centre of the deflection plane. The beams L and R are subject to forces F _L and F _R respectively which are superposed on the forces exerted by the deflection fields. FIG. 1 shows that as a result the angle α is effectively reduced to substantially zero so that the convergence error of FIG. 2 is cancelled.

Such a quadripolar field is obtainable by causing an additional current, the difference current, to flow through a deflection coil divided in two coil halves in a manner such that the said current is added to the deflection current in one coil half and subtracted from it in the other coil half. FIG. 2 shows that the convergence errors on the left-hand and right-hand halves of the screen 2 have the same sign and that they have the same sign in the upper and lower halves. Hence it is desirable for the value of the difference current to vary substantially as the square of each deflection. Because initially the value and polarity of the angle α are unknown, the current must be adjustable both in amplitude and in polarity. At the middle of the line and field trace intervals the angle must be zero. For this purpose either one or both deflection coils may be used.

Because the images L', C', R' in FIG. 2 are vertical, i.e. are not tilted, the convergence error to be corrected is to be considered as an isotropic astigmatic deflection error. Hence the line-frequency component of the difference current must be a function of horizontal deflection only and its field-frequency component must be a function of vertical deflection only. Thus it is simpler, but not necessary, to cause the line-frequency component of the difference current to flow through the split deflection coil for horizontal deflection and its field-frequency component to flow through the split deflection coil for vertical deflection.

FIG. 3 shows a simple circuit for generating a line-frequency difference current which satisfies the said requirements. A line deflection current generator 3 at one terminal supplies a line-frequency sawtooth current i _H to line deflection coil halves 4' and 4", which in this embodiment are connected in parallel for the current i _H . Adjustable coils 5' and 5" of low inductance are connected in series with the coil halves 4' and 4" respectively. The coils 5' and 5" may be adjusted jointly and oppositely so as to eliminate in knwon manner any asymmetry of the deflection fields generated by coil halves 4' and 4". The ends of the coils 5' and 5" not connected to the coil halves 4' and 4" respectively are connected to one another via a potentiometer 6 the slider on which is connected to the other terminal of the generator 3. The resistance of, for example, 4.7 ohms of the potentiometer 6 is low compared with the impedance of the coil halves 4' and 4" for the line repetition frequency. Thus a sawtooth voltage the polarity and amplitude of which depend upon the position of the slider is produced across the potentiometer 6. As a first approximation this voltage may be considered as being produced by a voltage source of low internal impedance. The coil halves 4' and 4" pass a current which is proportioned to the integral of the voltage across the potentiometer 6 and consequently is the required parabolic correction difference current i _KH . In one coil half it flows in the same direction as the current i _H /2 and in the other coil half it flows in the opposite direction. For this purpose it is required that the position of the slider on the potentiometer 6 should differ from the electric midpoint thereof.

The potentiometer 6 is shunted by the series combination of two resistors 7' and 7" the junction point of which is connected to the anode of a diode 8 the cathode of which is connected to the slider on the potentiometer 6. The diode 8 and the resistors 7' and 7" ensure that the peak of the parabola will be at zero. In actual fact the diode 8 produces a direct current which compensates for the sagging of the parabola, provided that the resistances of the resistors 7' and 7" are equal and have the correct value, for example 8.2 ohms. This direct current also is a difference current and since the diode 8 is connected to the slider on the potentiometer 6 the reversal of its polarity is automatically effected together with that of the parabolic component.

A disadvantage of the circuit of FIG. 3 may be that the obtainable amplitude of the current i _KH is limited because the permissible value of the potentiometer 6 is limited, for a comparatively large value of this potentiometer will increase dissipation and give rise to a linearity error of the deflection current whilst the current i _KH will no longer be parabolic but will also include higher-order components. The amplitude i _KH may be increased without increasing the resistance of the potentiometer 6 by coupling the latter to the remainder of the circuit by means of a transformer. This may be achieved by an autotransformer, as is shown in FIG. 4. Two windings 19' and 19" which are bifilarly wound on the same core and have the polarities shown are connected in series between the ends of the coils 5' and 5" not connected to the coil halves 4' and 4" respectively. The potentiometer 6 is connected between two tappings on the windings 19' and 19" which are symmetrical with respect to the junction point thereof and the potentiometer slider is connected to said junction point via the series combination of the diode 8 and a resistor 7.

In the circuit shown in FIG. 4 the operation of the balancing coils 5' and 5" is not disturbed, provided that the overall inductance value of the windings 19' and 19" between the junction point of the winding 19' and the coil 5' and the junction point between the winding 19" and the coil 5" is small compared with the inductance value of the coil halves 4' and 4" and the coils 5' and 5" measured between the same points. In a practical embodiment of the circuit of FIG. 4 the latter value is 3.55 mH and the former value is 1.25 mH. This means that the effect of the balancing coils 5' and 5" is reduced by only about one third. The tappings on the windings 19' and 19" are provided at the midpoints thereof, the value of the resistor 6 is about 3.3 ohms and that of the resistor 7 about 0.5 ohm. It should be noted that the resistance of the windings 19' and 19" should not be too small, for otherwise the direct component of the difference current would be short-circuited.

FIG. 5 shows a simple circuit for producing a field-frequency difference current in field-frequency deflection coil halves 9' and 9". Since these coil halves are predominantly resistive for the field repetition frequency, the circuits shown in FIGS. 3 and 4 cannot be used. A field deflection current generator 10 supplies a fieldfrequency sawtooth current i _V to coil halves 9' and 9" which are connected in series in this embodiment. The series combination of a diode 11', a potentiometer 12' and a second diode 13' and the series combination of a third diode 11", a potentiometer 12" and a fourth diode 13" are connected in parallel with the series combination of the said coil halves, the said four diodes having the polarities shown in FIG. 5. An isolating resistor 14' is connected between the slider on the potentiometer 12' and the junction point of the coil halves 9' and 9", and an isolating resistor 14" is connected between the slider of the potentiometer 12" and the said junction point, the values of the isolating resistors being high relative to the impedance of the coil halves, for example about 100 ohms.

During one half of the field trace interval the current i _V flows in the direction shown. Diodes 11' and 13' are conducting whereas diodes 11" and 13" are cutoff. Across the potentiometer 12' a sawtooth voltage is produced so that, if the position of the slider of the potentiometer 12' is different from the electric midpoint of the potentiometer, a sawtooth correction difference current i' _KV flows through the coil half 9', for example in a direction opposite to that of the current i _V , whilst the coil half 9" passes a sawtooth correction difference current i" _KV in the same direction as the current i _V , the currents i' _KV and i" _KV being substantially equal. It should be noted that a difference current, in this embodiment i" _KV , flows through a diode, in this embodiment 13', from the cathode to the anode. However, because the elements 9', 9", 11', 12', 13' and 14' form a Wheatstone bridge comprising resistors, the diodes cannot be cut off.

During the other half of the trace interval current i _V flows in the other direction. The diodes 11" and 13" are conducting and the diodes 11' and 13' are cut off. Sawtooth difference currents are produced which are derived from the slider on potentiometer 12". In FIG. 6 the variation of the extreme value i _KVmax of the difference currents is shown as a function of time, T denoting the field trace interval. At the middle of the interval T these currents are zero, because the current i _V and hence the voltage across the potentiometer 12' or 12" respectively are zero. Owing to the voltage drop across the diode the difference currents are zero for a certain time before and after the middle of the interval T. The resulting curves may be regarded as approximate parabolas, for practice has shown that the residual convergence error is negligibly small. Because the difference currents produced are sawtooth currents, the potentiometers 12' and 12" ensure also that the deflection fields generated by the coil halves 9' and 9" are symmetrical. An advantage of the circuit of FIG. 5 is that the adjustments of the upper half and of the lower half are independent of one another, which conduces to clarity. In the embodiment described both potentiometers have a resistance of about 330 ohms.

It will be appreciated that the quadripolar field generated will only be capable of correcting for the vertical convergence error if the angle α is very small. The error introduced by the incorrect position of the line D is compensated for by the quadripolar field according to the invention, it is true, however, at large values of the angle α this field in turn introduces new errors, especially in the corners of the screen. Practice has shown that an angle of from 2° to 3° still can be corrected.

Hereinbefore no statement has been made about the construction of the deflection coils. If they are in the form of saddle coils, no special steps are required. If, however, they are wound toroidally, a step as described in U.S. patent application Ser. No. 390,701 filed August 23, 1973 must be used which consists in the introduction of the difference currents into the deflection coil halves via tappings. In this case the simple circuits of FIGS. 3, 4 and 5 are to be replaced by circuits in which the parabolic difference currents are generated in a different manner, for example by separate generators.

In the embodiments described the coil halves 4' and 4" for horizontal deflection are connected in parallel for the line deflection current i _H , whereas the coil halves 9' and 9" for vertical deflection are connected in series for the field deflection current i _V . Obviously this is not of importance for the invention and the coil halves may be connected in a different manner. FIG. 7 shows an embodiment in which the coil halves 4' and 4" are connected in series for the current i _H . In this embodiment two diodes 8' and 8" are required. It will further be appreciated that the invention may also be applied if the electron beams are generated in a plane of substantially vertical orientation, in which case the convergence error to be corrected is horizontal.

PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) On-screen channel display:An on-screen television display including means internally of the receiver for generating characters to indicate the channel number, time of day or other data. The system includes circuit means responsive to the horizontal and vertical sync signals of a television receiver for positioning and timing of the display. BCD data is coupled to a character generator, and the output of the character generator is then multiplexed with positioning and timing signals. The multiplexed output is coupled to a video interface which supplies the video signal to the cathode ray tube.


1. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.

2. A display system in accordance with claim 1 wherein said decoding means comprises a seven segment decoder.

3. A display system in accordance with claim 2 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexer to control the same.

4. A display system in accordance with claim 1 wherein said decoder is a seven segment decoder and wherein means are provided to gate the data output of said decoder which represent the vertical segments of the character to be displayed during given horizontal scans of the beam of the cathode ray tube.

5. A system ,in accordance with claim 1 including timing circuit means, means for multiplexing coded data representing each of said characters in accordance with timing signals from said timing circuit means, a seven segment decoder for decoding said multiplexed data, and means for using said decoded data to apply a video signal to the cathode ray tube of the television receiver.

6. A display system in accordance with claim 5 wherein there is provided an oscillator, means for keying the operation of the oscillator to the horizontal sync of the television receiver, and a counter for counting an output of said oscillator and for producing said timing signals.

7. A channel number display system in accordance with claim 6 wherein said data multiplexer has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexed data to inputs of said seven segment decoder.

8. A channel number display system in accordance with claim 7 wherein means are provided to blank the display system output for a time interval between the switching of said data multiplexer from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on the raster of the cathode ray tube.

9. A channel number display system in accordance with claim 8 wherein select means are provided to select one of a greater number of variable character displays, said means including a BCD signal responsive select circuit.

10. A channel number display system in accordance with claim 9 wherein said select means includes a four-six character select circuit for selecting either four or six character display.

11. A system for displaying a character on the raster of a television receiver comprising: means for developing coded data indicative of the character to be displayed, a seven segment decoder, means for coupling the coded data to the input of the seven segment decoder, means for using the output of the seven segment decoder to illuminate a seven segment display on the raster of a cathode ray tube, and wherein three outputs of the seven segment decoder represent the horizontal segments of the character to be displayed and the remaining four outputs represent the vertical segments thereof, and wherein there is provided a multiplexer, a horizontal scan counter, means for coupling the counter outputs to the multiplexer, means for coupling the three horizontal segment outputs to the multiplexer, a timing counter, means for using the timing counter to gate the four vertical segment outputs during each scan associated with the character display, and means for coupling the four gated vertical segment outputs to the multiplexer.

12. A display system in accordance with claim 11 wherein there is provided an oscillator, means for keying the oscillator to the horizontal scan of the cathode ray beam, said oscillator having a frequency substantially higher than the horizontal line frequency of the cathode ray tube, means for coupling the output of the oscillator to the timing counter to control the same.

13. A display system in accordance with claim 12 wherein means are provided to use the horizontal sync signal of the television receiver to enable said timing counter.

14. Apparatus for use with a television receiver, said receiver comprising a horizontal scanning circuit, a vertical scanning circuit, a video signal circuit, and a display device coupled to said scanning and video signal circuits, and creating a character on said display device in the form of line segments oriented in generally horizontal and vertical directions and superimposed over other information displayed thereon and comprising:
data means for developing coded data indicative of the character to be displayed;
decoding means having a plurality of outputs and producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed;
an oscillator coupled to said horizontal scanning circuit and synchronized to the operation of said horizontal scanning circuit and producing a signal at a frequency greater than the horizontal scanning frequency;
counting means coupled to the output of said oscillator and developing signals representative of the position of the horizontal scan;
gating means coupled to said decoding means and said counting means and gating said signals representative of the presence of a corresponding generally vertical line segment in response to the position of the horizontal scan;
matrix means for matrixing said gated signals representative of the presence of corresponding generally vertical line segments and said signals representative of corresponding generally horizontal line segments to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a horizontal scan;
signal selection means for selecting one of said line signals in accord with the position of the vertical scan; and
combining means coupled to said video signal circuit for combining said selected line signal with a signal representative of said other information displayed on said display device.


15. The apparatus of claim 14 wherein said character is displayed in the form of the presence or absence of seven line segments and said decoding means comprises a seven segment decoder having seven outputs and producing at each of said outputs a signal representative of the presence of a corresponding one of said seven line segments in the character to be displayed.

16. The apparatus of claim 14 creating at least two characters on said display device wherein said data means develops coded data indicative of the characters to be displayed and said apparatus further comprises multiplex means coupled to said data means, said decoding means and said counting circuitry for applying to said decoding means coded data indicative of different characters to be displayed in response to the position of the horizontal scan.

17. The apparatus of claim 16 further comprising means for preventing the display of said characters for a time interval including the switching of said multiplex means to provide spacing between said characters.

18. The apparatus of claim 14 further comprising a time delay circuit coupled between said oscillator and said horizontal scanning circuit and preventing the operation of said oscillator until a predetermined time period has elapsed following the commencement of a horizontal scan.

19. Apparatus for use with a television receiver, said receiver comprising a first scanning circuit for scanning in a first direction, a second scanning circuit for scanning in a second direction generally perpendicular to said first direction, a video signal circuit, and a display device coupled to said scanning and video signal circuits, and creating a character on said display device in the form of line segments oriented in generally said first and second directions and superimposed over other information displayed thereon and comprising:
data means for developing coded data indicative of the character to be displayed;
decoding means having a plurality of outputs and producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed;
timing and gating means coupled to said decoding means and said first scanning circuit and gating said signals representative of the presence of a corresponding line segment in said second direction in response to the position of the scan in said first direction;
matrix means for matrixing said gated signals representative of the presence of corresponding line segments in said second direction and signals representative of corresponding line segments in said first direction to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a scan in said first direction;
signal selection means for selecting one of said line signals in accord with the position of the scan in said second direction; and
combining means coupled to said video signal circuit for combining said selected line signal with a signal representative of said other information displayed on said display device.


20. A system for displaying at least two characters on the raster of a television receiver comprising: an oscillator, means for keying the operation of the oscillator to the horizontal sync of the television receiver, a counter for counting an output of said oscillator and for producing timing signals, means for developing and multiplexing coded data representing each of said characters to be displayed in accordance with said timing signals, a seven segment decoder having a plurality of inputs and outputs for developing signals on a predetermined combination of said outputs in response to each selected coded input, means for coupling the coded data to given inputs of said decoder, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal, and means for adding the generated video signal in the television receiver video circuit to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.

21. A channel number display system in accordance with claim 20 wherein said data developing and multiplexing means has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexing data to inputs of said seven segment decoder.

22. A channel number display system in accordance with claim 21 wherein means are provided to blank the display system output for a time interval between the switching of said data developing and multiplexing means from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on the raster of the cathode ray tube.

23. A channel number display system in accordance with claim 22 wherein select means are provided to select one of a greater number of variable character displays, said means including a BCD signal responsive select circuit.

24. A channel number display system in accordance with claim 23 wherein said select means includes a four-six character select circuit for selecting either four or six character display.

25. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.

26. A display system in accordance with claim 25 wherein said circuit means further comprises counting means coupled to the output of said oscillator and developing signals indicative of the horizontal position of the beam of the cathode ray tube of said broadcast television receiver.

27. A display system in accordance with claim 26 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for resetting said counting means.

28. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver, means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.

29. A display system in accordance with claim 28 wherein said decoding means comprises a seven segment decoder.

30. A display system in accordance with claim 28 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexing means to control the same.

31. A display system in accordance with claim 30 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for resetting said counting means.

32. A system for displaying a character indicative of the channel being received on the picture display device of a broadcast television receiver comprising: means for developing data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling said data to inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each data input, circuit means for processing the signal on said outputs of said decoder into a video signal for generating a line segment character and including an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding said video signal to other video signals being processed by said broadcast television receiver to develop a character display on said picture display device.

33. A system for displaying a character indicative of the channel being received on the picture display device of a broadcast television receiver comprising: means for developing data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling said data to inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each data input, circuit means for processing the signal on said outputs of said decoder into a video signal for generating a line segment character and including an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization circuitry of said broadcast television receiver for keying said oscillator, and means for adding said video signal to other video signals being processed by said broadcast television receiver to develop a character display on said picture display device.

Description:

BACKGROUND OF THE INVENTION
The use of on-screen display of a channel number, for instance, has been proposed in an article entitled, "Broadcast and Television Receivers" IEEE, Vol. BTR-15, No. 2, July 1969, however, the character generators which are available commercially are generally "read only memories" designed to display either 16 or 64 alpha-numeric characters. These character generators require 350 memory bits for 10 characters. In such a device, all 35 possible positions in a 5 × 7 font are used for the numerals. The character generator is the most expensive element of such a system.
A Co-pending Patent Application of Ralph Joseph Ludlam entitled, "Electronic Channel Selection & Device", Ser. No. 265,231, now abandoned, describes a system for producing digital information representative of a selected channel. This data may be used by the display system of the present invention.
FIELD OF THE INVENTION
The field of art to which this invention pertains is on-screen display of characters in a television receiver with character generation locally in the receiver.
SUMMARY OF THE INVENTION
It is an important feature of the present invention to provide an improved system for the display of characters on the screen of a television receiver using character generating means locally in the receiver.
It is another feature of the present invention to provide a relatively inexpensive means for generating characters in a system as described above.
It is a principal object of the present invention to provide an on-screen character display system for a television receiver which utilizes a character generator having a segment decoder for transforming digital information into line segment information and having means for gating and multiplexing the line segment information into a usable video output signal.
It is a further feature of the present invention to provide a character generator described above including a seven segment decoder having direct coupling from the output of the decoder to a multiplexing stage for the horizontal segments of each character and having coupling to the multiplexer through a gating circuit for the vertical segments of the character.
It is a further feature of the present invention to provide a circuit as described above which includes a vertical and horizontal delay means as well as vertical and horizontal blanking means to properly position the characters at a predetermined location on the screen of the television receiver.
It is an additional feature of the present invention to provide a circuit as described above which includes means for blanking the character generating portion of the video signal between characters to provide adequate spacing.
It is also an object of this invention to provide circuit means for generating additional characters such as characters to indicate the time of day on the screen of a television receiver.

Other References:

Olson et al., "The Practical Application of On-Screen Display to a Television Receiver", IEEE Transactions on Broadcast and TV Receivers, _Aug. 1973, pp. 169-175.
Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.



PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) Channel selector having a plurality of tuning systems:A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.

1. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-state switching circuit.


2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.

3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.

4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.

5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.


6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.


7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.

8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.

9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.

Description:

BACKGROUND OF THE INVENTION
This invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.