PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 Control circuit for a switched-mode power supply, particularly for a television receiver: PHILIPS CHASSIS CTV KM4 SWITCH MODE POWER SUPPLY.
A switched-mode power supply provided with a control stage and a switching stage coupled by means of a transformer. The collector of an additional transistor is connected to the transformer. In this manner the ratio of the collector current to the base current of the switching transistor can assume a predetermined value, for example a constant value whatever the value of the mains voltage applied to the power supply.
What is claimed is:
1. A control circuit for a switched-mode power supply, said power supply comprising a non-regulated rectified DC voltage source, a driver transistor, a first transformer having primary and secondary windings, an end of said primary being coupled to the collector-emitter path of said driver transistor, a switching transistor having a base coupled to said secondary, a second transformer having a primary winding coupled in series with said switching transistor, and a plurality of secondary windings, said control circuit comprising a first additional transistor having a collector coupled to the remaining end of the primary winding of the first transformer not connected to the driver-transistor and an emitter coupled to the non-regulated direct voltage source.
2. A control circuit as claimed in claim 1, further comprising a constant voltage source coupled to the base of the additional transistor.
3. A control circuit as claimed in claim 1, further comprising a constant current source, and a resistor coupled between the emitter of the additional transistor and the constant current source.
4. A control circuit as claimed in claim 3, wherein the constant current source comprises a second additional transistor, the two additional transistors being of complementary conductivity and their emitters being connected with each other through said resistor, the collector of the second additional transistor being coupled to the non-regulated rectified direct voltage source and the collector of the first additional transistor being coupled to the end of the primary winding of the first transformer not connected to the driver transistor.
5. A control circuit as claimed in claim 4, further comprising a resistor coupled in series with the collector circuit of said second additional transistor and the non-regulated rectified direct voltage source.
6. A control circuit as claimed in claim 5, further comprising a zener diode coupled between the base of the second additional transistor and the non-regulated voltage source.
7. A control circuit as claimed in claim 6, further comprising a resistance bridge coupled to the base of the first additional transistor and arranged between the two electrodes of the zener diode.
8. A control circuit as claimed in claim 7, wherein the driver transistor and the switching transistor do not conduct simultaneously, and the voltage between the two electrodes of the zener diode as well as the values of the resistors arranged between the said electrodes and of the resistor arranged between the emitters of the two additional transistors are chosen so that the first additional transistor is in the saturated state at the lowest value of the non-regulated voltage while it operates in the linear state at a higher value of said non-regulated voltage.
Description:
The present invention relates to a control circuit for a switched-mode power supply, particularly in a television receiver, said power supply comprising a rectified, non-regulated rectified DC voltage source, a driver transistor whose collector-emitter path is arranged in series with a primary winding of a first transformer, a secondary winding of the latter being coupled to the base of a switching transistor which is arranged in series with a primary winding of a second transformer having a plurality of secondary windings.
This type of switched-mode power supply is used more and more because of the numerous advantages it presents as regards energy efficiency, reliability, compactness, etc. However, as for the majority of the other types of power supplies, its operation on mains supplies of different voltages imposes the use of either a transformer with taps or switch-over from full wave rectification at the highest mains voltage to a voltage doubler rectification for the lowest mains voltage.
It is known that the specific qualities of a switched-mode power supply depend for a large part on the switching speed of the switching transistor at the moment at which the latter passes periodically from the conductive state to the blocking state; this speed is at its maximum when the switching transistor presents, at the turn-off moment, a certain ratio between the collector current and the base current IC/IB: if this ratio is too low, the delay in the recombination of the charges stored in the base increases the switching time; if it is too high there is the risk that the transistor is brought out of saturation before it is blocked, which results in its substantially immediate destruction. For the known switched-mode power supplies it is not possible to maintain a suitable IC/IB ratio in the presence of large variations of the non-regulated rectified DC voltage which result from the connection to the nominal mains voltages of, for example, 110 or 220 V; actually, if the variations in IB are substantially proportional to the variations in the non-regulated voltage, the same does not happen for those of the IC whose amplitude is less.
However, the importance of having a power supply which can operate without any switching on mains supplies of 110 or 220 V is evident: for the manufacturer it is cheaper to produce and the reliability is increased; while the user does not run the risk of incorrect manipulations, particularly when the power supply is destined for use in portable television sets.
One of the objects of the invention is to realize a control circuit which permits the switched-mode power supply to operate without switching in conditions which are substantially optimum and in the presence of mains voltage variations in the range of 90 to 250 Volts.
A further object of the invention is to ensure that said IC/IB ratio of the switching transistor has a predetermined and, more particularly a constant value at the turn-off moment whatever the value of the mains voltage applied to the power supply.
The control circuit according to the invention is characterized in that the end of the primary winding of the first transformer not connected to the driver transistor is connected to the collector of an additional transistor whose emitter is coupled with the non-regulated direct voltage source. Advantageously it is characterized in that the emitter of the additional transistor is connected to one end of a resistor, the other end of this resistor being connected to a constant current source, and that the constant current source is constituted by a second additional transistor, the two additional transistors being of complementary conductivity and their emitters being connected with each other through a resistor, whilst the collector of the second additional transistor is connected to one of the poles of the non-regulated rectified direct voltage source and the collector of the first additional transistor is connected to the end of the primary winding of the first transformer not connected to the driver transistor.
Whilst combining the action of a ballast transistor with that of a variable current generator, the circuit according to the invention thus maintains automatically a desired IC/IB ratio of the switching transistor whatever the value of the mains voltage applied to the power supply.
PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 PHILIPS CHASSIS CTV KM4:Two-state switched-mode power supply:
A switched-mode power supply having at least two output terminals for supplying at least two different voltages and capable of operating in an alternate state in which some of the voltages are reduced. The power supply includes at least two controllable voltage sources coupled, respectively, to the output terminals and at least one voltage regulating circuit coupled to control inputs of the voltage sources for reducing the output voltages of both voltage sources proportionately when the voltage on the output of a first one of the voltage sources exceeds a preset reference level. The power supply further includes a circuit for selectively coupling a second one of the voltages sources to the regulating circuit. If the output of the second voltage source exceeds that of the first voltage source, when the second voltage source is coupled to the regulating circuit, the output voltages of all the voltage sources are reduced proportionately, while the voltages on the power supply output terminals are also reduced except for the output terminal coupled to the regulating circuit.
1. A switched-mode power supply capable of operating optionally in two states, comprising at least two controllable voltage sources having respective control inputs, at least two power supply output terminals and first regulating means coupled to the control input on each of said voltage sources for supplying a signal which acts, on the switching operation, to reduce the values of the voltages supplied by all of the voltage sources when one voltage exceeds a first reference value, characterized in that said switched-mode power supply further comprises second regulating means also coupled to said control inputs for supplying a signal which acts, on the switching operation, to reduce the values of the voltages supplied by all the voltage sources when a voltage exceeds a second reference voltage,
first change-over elements for selectively connecting an output of one of the voltage sources to the first regulating means in a first state or to the second regulating means in a second state,
second change-over elements for selectively connecting one of said output terminals to one voltage source in the first state or to the other voltage source in the second state,
and a device which simultaneously controls the first and second change-over elements for selecting the desired state.
2
. A switched-mode power supply capable of operating optionally in two states, said power supply comprising a first voltage source having an output for supplying a first voltage and a control input, a second voltage source having an output for supplying a second voltage and a control input, said second voltage being higher than said first voltage, first and second output terminals coupled, respectively, to the outputs of said first and second voltage sources, and regulating means coupled to the control input of each of said voltage sources for supplying thereto a control signal when a voltage applied to said regulating means exceeds a reference level, characterized in that said regulating means is coupled to said first output terminal and said power supply further comprises a change-over element for selectively coupling said first output terminal to the output of said second voltage source, whereby, in a first of said two states, the outputs of said first and second voltage sources are connected, respectively, to said first and second output terminals, said regulating means generating said control signal based on the output of said first voltage source, and, in a second of said two states, the output of said second voltage source is connected to both said first and second output terminals, said regulating means generating said control signal based on the output of said second voltage source, said control signal thereby causing said first and second voltage sources to reduce said first and second voltages proportionately. 3. A switched-mode power supply as claimed in claim 2, characterized in that said power supply further comprises additional voltage sources connected to additional output terminals, said additional voltage sources having control inputs coupled to receive said control signal, whereby in said second state, voltages at the outputs of said additional voltage sources are reduced proportionately with said first and second voltages. 4. A switched-mode power supply as claimed in claim 3, characterized in that said power supply further comprises further regulating means coupled to at least the control input of one of said additional voltage sources for supplying a control signal when the voltage at the output of said additional voltage source applied thereto exceeds a further reference level, said further reference level being higher than said reference level. 5. A switched-mode power supply as claimed in claim 2, characterized in that said power supply further comprises further regulating means coupled to the control input of said second voltage source for supplying a control signal when said second voltage applied thereto exceed a further reference level, said further reference level being higher than said reference level. 6. A switched-mode power supply as claimed in claim 2 or 5, characterized in that said power supply further comprises a current limiter arranged in series with said change-over element. 7. A switched-mode power supply as claimed in claim 2 or 5, characterized in that said power supply further comprises a voltage-limiting circuit coupled between said change-over element and said first terminal.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a switched-mode power supply capable of operating optionally in two states, comprising at least two voltage sources and having at least two supply output terminals and comprising first means for supplying a signal which acts, on the switching operation, to reduce all the voltages supplied by the sources when one voltage exceeds a first reference value.
The invention also relates more specifically to a circuit capable of operating optionally in the following states:
either in a first state in which a first voltage source connected to a first output terminal applies thereto a first voltage, and at least a second voltage source connected to at least a second output terminal applies thereto a second voltage which is higher than the first voltage,
or in a second state in which a voltage which is higher than or equal to the voltage applied to the first terminal in the first state is applied to it, while a voltage is applied to the second terminal which is less than the voltage applied to it in the first state.
The circuits of the type according to the invention are used particularly in television receivers having a remote control. They may be in two states corresponding to either normal operation of the television receiver or to the stand-by state, in which the receiving circuits of the remote control are normally fed, while the other circuits are supplied with a reduced voltage or are not fed at all.
In widely circuits, two separate supply sections are used, one for the remote control receiving circuit, the other one for the remaining portion of the television receiver. This system is expensive as it requires two separate power supplies.
In another widely used circuit, one single switched-mode power supply is used, and the voltages, other than those feeding the remote-controlled receiver, are cut-off, by means of change-over switches, during the stand-by state. It is then necessary to provide the possibility to cut-off, during operation, several high voltages and currents, which necessitates the use of a plurality of highly reliable and therefore expensive interruptors.
German Patent Specification No. DE 2,620,191 discloses a more satisfactory circuit, in which one of the windings of a switched-mode supply transformer is wound in a sense opposite to the winding sense of the other windings. Consequently, the voltages from this winding do not depend on the duty cycle. By varying the duty cycle, it is possible to reduce the other voltages without modifying the voltage from the said winding, which is used to feed the remote control receiving circuit. This system has, however, the disadvantage that the voltage from the inverse winding is not stabilized by the overall stabilizing system and that it is then necessary to provide an additional series-arranged stabilizing circuit for the usual case in which the line voltage may vary considerably, and especially with the now prevailing tendency according to which the television sets may be connected without change-over to all the 90 v. to 250 v. lines voltages. This stabilizing circuit, apart from its price, has the disadvantage that it increases the power consumption in the stand-by state.
SUMMARY OF THE INVENTION
The circuit according to the invention has for its object to provide a power supply which does not have any of the above-mentioned disadvantages.
The circuit according to the invention is therefore characterized in that all the voltages from the sources are modified simultaneously in the same proportion, and, at the same time, at least one connection between an output terminal and a source is replaced by a connection between this output terminal and another source.
In an advantageous variation, two of these voltage sources are interconnected, while all the voltages from these sources are modified simultaneously in the same proportion.
A circuit according to the invention is characterized in that second means are furthermore provided for supplying a signal which acts on the switching operation to reduce together the values of the voltage supplied when a voltage exceeds a second reference value, and in that it also comprises:
first change-over elements for connecting one of the voltage sources optionally either to the first or to the second means,
second change-over elements for connecting an output terminal either to the one or the other voltage source,
and a device which simultaneously controls the first and second change-over elements for selecting the desired state.
In an advantageous variation, a circuit according to the invention is characterized in that the first means are connected to the first terminal and the circuit comprises change-over elements for adjusting the circuit to the second state by optionally connecting the first terminal to the second voltage source.
An advantageous embodiment of the invention is characterized in that a current limiter is arranged in series with the change-over elements, or the change-over elements comprise a controllable current limiter.
The advantage of the invention resides in the fact that it makes it possible to reduce all the voltages, except one, by means of one single interrupter through which no high currents flow, all the voltages remaining permanently stabilized by the single stabilizing circuit.
PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 VARACTOR TUNER BAND SWITCHING AND SIGNAL INDICATING CIRCUITRY:
A signal receiver having VHF and UHF varactor tuners and a channel indicating group for the upp
er and lower VHF channels and for the UHF channel includes band switching circuitry for selectively coupling a plurality of power sources to the tuners in accordance with activation of a particular channel indicating group. Also, the band switching circuitry is utilized in conjunction with a channel indicating meter circuit for providing a visual indication of the channel selected in each one of the channel indicating groups.
1. In a signal receiver having first, second, and third potential sources; VHF and UHF varactor tuners; first, second, and third channel indicating groups formed for selective coupling to the first potential source; and band switching circuitry having first, second, and third switching means for coupling the potential sources to the VHF and UHF tuners, channel indicating meter circuitry comprising: 2. The channel indicating meter circuitry of claim 1 wherein said means for coupling one of said pair of terminals of said channel indicating meter to a potential reference level and to the junction of said second switching means and third potential source includes a first unidirectional conduction device coupled intermediate said terminal and said potential reference level and a second unidirectional conduction device coupling the junction of said first unidirectional conduction device and potential reference level to said junction of said second switching means and third 3. The channel indicating meter circuitry of claim 1 wherein said means for coupling the other one of said pair of terminals of said channel indicating meter includes a first impedance coupling said terminal to a potential reference level and a second impedance coupling said terminal to 4. The channel indicating meter circuitry of claim 1 wherein said channel indicating meter provides a visual indication of a selected signal channel in accordance with the potential applied thereto from said channel 5. The channel indicating meter circuitry of claim 1 wherein said channel indicating meter includes a plurality of meter scales for visually indicating channels in the upper and lower bands of the VHF varactor tuner 6. In a signal receiver having first, second, and third potential sources; VHF and UHF varactor tuners; first, second, and third channel indicating groups each formed for selective coupling to a first potential source, band switching and channel indicating meter circuitry comprising in combination: 7. The band switching and channel indicating meter circuitry combination of claim 6 including a first impedance coupling said first terminal to said potential reference level and a second impedance coupling said first 8. The band switching and channel indicating meter circuitry combination of claim 6 including a first unidirectional conduction device coupling said 9. The band switching and channel indicating meter circuitry combination of claim 6 including a first unidirectional conduction device coupling said second terminal to said potential reference level and a second unidirectional conduction device coupled to said first unidirectional conduction device and potential reference level and to said second switching means and third potential source.
Description:
CROSS-REFERENCE TO OTHER APPLICATIONS
An application entitled "Pushbutton Tuning System" filed concurrently herewith in the names of William Lee Arrington and Lee Irving Merz (Ser. No. 326,759) and assigned to the assignee of the present application relates to a pushbutton tuner for selecting a signal channel wherein each one of the channels provide an output potential suitable for use with the band switching and channel indicating meter circuitry set forth in the present application.
BACKGROUND OF THE INVENTION
Generally, present-day television receivers utilize both VHF and UHF tuners with the VHF tuner having the usual upper band portion covering channels 7-13 and a lower band portion covering channels 2-6. Also, present-day tuners are commonly of the varactor type wherein channel or frequency selection is determined by the potentials applied to the tuners.
In the prior art it has been a common practice to provide ordinary mechanical switches for band switching the high and low bands of the VHF tuner and the UHF tuner. Moreover, printed circuit type switches have been utilized in an effort to overcome the usual problems associated with mechanical switches. However, printed circuits have not provided the answers for such mechanical problems as wear, contact failure, and lack of reliability even though the cost is undesirably increased.
Additionally, total electronic tuning systems using logic and digital techniques have been proposed for use with varactor tuners. In one known example, channel numbers are coded into binary numbers and the selection of a preset voltage on varactor diodes is made by a corresponding binary coded signal.
However, electronic tuning systems using logic and digital systems appear to be relatively expensive, require a large number of components, and have a reliability and repeatability factor which is relatively unknown in the industry. Moreover, repair and service problems associated with such a departure from known and more frequently employed techniques remains an unknown factor.
Additionally, it is highly desirable to provide some form of visual indicating apparatus whereby an operator is aware of the approximate tuning of the receiver. Obviously, the provision of such visual indicating apparatus at a minimum cost of materials and labor is of utmost importance.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention is to provide enhanced band switching circuitry for a multi-band signal receiver. Another object of the invention is to provide improved electronic band switching circuitry for varactor tuners in a signal receiver. Still another object of the invention is to provide improved visual indicating apparatus utilized with band switching circuitry in a multi-band signal receiver.
These and other and further objects, advantages and capabilities are achieved in one aspect of the invention by a multi-band signal receiver having VHF and UHF varactor tuners with channel indicating groups for the upper and lower VHF bands and the UHF band and band switching circuitry for selectively coupling a plurality of potential sources to the tuners in accordance with the particular channel indicating group selected. Also, channel indicating meter circuitry acts in conjunction with the band switching circuitry to provide a visual indication of the signal channel selected.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a diagrammatic illustration, in block and schematic form, of electronic band switching and channel indicating meter circuitry suitable for use in a multi-band signal receiver; and
FIG. 2 is an alternative embodiment of a channel indicating meter circuit.
PREFERRED EMBODIMENT OF THE INVENTION
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in conjunction with the accompanying drawings.
Referring to the drawings, band switching and channel indicating meter circuitry suitable for use in a television receiver includes first, second, and third channel indicating groups 3, 5, and 7 respectively. Each one of the channel indicating groups, 3, 5, and 7 includes a plurality of parallel coupled signal channels and each signal channel has a series connected neon bulb 9 and selector switch 11 coupled to a first potential source 13. Also, each channel includes a signal selector switch 14, ganged to the selector switch 11, and connected to an adjustable resistor 12 intermediate the first potential source 13 and a potential reference level such as circuit ground. Thus, the first channel indicating group 3, preferably includes signal channels 7-13, the second channel indicating group 5, includes signal channels 2-6, and the third channel indicating group 7 includes a selection of channels 14-83.
In operation, selection of a signal channel in any one of the first, second, or third channel indicating groups 3, 5, and 7 is effected upon closure of a selector switch 11 whereupon a potential from the first potential source 13 is applied to the series connected neon bulb 9 by the selector switch 11. Also, a potential representative of a signal channel within the channel indicating group 3, 5, and 7 is available at the ganged signal selector switch 14. Thus, there is provided a potential representative of the channel indicating group and another potential representative of a specific channel within the channel indicating group.
Coupled to the channel indicating groups 3, 5, and 7 respectively, is band switching circuitry including first, second, and third switching means 15, 17, and 19 respectively. The first switching means 15, in the form
of a transistor 16 in this instance, has a base electrode coupled to the first channel indicating group 3, representative of the upper band of signal channels 7-13. A collector electrode is coupled to a second potential source B+ while an emitter electrode is coupled to a varactor or varicap VHF type tuner 21. Obviously, the transistor may be replaced by other forms of electronic switching apparatus.
The second switching means 17 includes a pair of DC coupled PNP and NPN transistors, 23 and 25 respectively. The PNP transistor 23 has an emitter coupled to the second potential source B+, a collector DC coupled to the base of the NPN transistor 25, and a base electrode coupled via a biasing resistor 27 to circuit ground and by way of a first unidirectional conduction device 29 to the second channel indicating group 5 (channels 2-6). Also, a second unidirectional conduction device 31 couples the junction of the first unidirectional conduction device 29 and second channel indicating group 5 to the junction of the first channel indicating group 3 and first switching means 15. The NPN transistor 25 has a collector electrode coupled to the second potential source B+ and an emitter electrode coupled via a resistor 33 to a third potential source B- and to the VHF varactor or varicap tuner 21.
The third switching means 19 includes a transistor 35 having a base electrode connected to the third channel indicating group 7 and a collector electrode coupled to the second potential source B+. The emitter electrode of the transistor 35 is coupled to a UHF varicap or varactor tuner 37.
Additionally, channel indicating meter circuitry includes a meter 39 having a first terminal 41 coupled via resistors 42 and 44 to the signal selector switches 14 of the series connected first, second, and third channel indicating groups 3, 5, and 7 respectively and to the junction of the VHF and UHF tuners 21 and 37. This first terminal 41 of the meter 39 is also connected via a series connected first unidirectional conduction device 43 and resistor 45 to circuit ground. The junction of this first unidirectional conduction device 43 and resistor 45 is coupled via a second unidirectional conduction device 47 to the junction of the second switching means 17, the resistor 33 connected to the third potential source B-, and to the VHF tuner 21. Moreover, a second terminal 49 of the indicating meter 39 is coupled by a first resistor 51 to a potential reference level and by a second resistor 53 to the second potential source B+.
FIG. 2 illustrates an alternative form of channel indicating circuitry wherein an indicating meter 39 has a first terminal 55 coupled to the signal indicating or tuning means 57 of the first, second, and third channel indicating groups 3, 5, and 7 and via a series connected diode 59, first alterable resistor 61, and second alterable resistor 63 to a potential reference level. The terminal 55 is also coupled to the second alterable resistor 63.
A second terminal 65 of the meter 39 is coupled to the second potential source B+ and to the potential reference level. Also, the second terminal 65 is coupled via a resistor 67 and diode 69 to the junction of the second switching means 17, to the resistor 33 coupled to the third potential source B-, and to the VHF tuner 21. Moreover, a third diode 71 couples the second diode 69 and junction of the second switching means 17 to the alterable resistor 61.
As to operation, selection of any one of the parallel connected signal channels (channels 7-13) of the first channel indicating group 3 causes application of a potential from the first potential source 13 to the first switching means 15. The first switching means 15 including the transistor 16 is normally nonconductive or open-circuited. However, application of a potential from the potential source 13 renders the transistor 16 conductive whereupon a potential from the second potential source B+ is applied to the VHF tuner 21.
Also, it is to be noted
that the second switching means 17 is normally conductive whereupon the potential from the third potential source B- coupled to the VHF tuner 21 is "swamped-out" by the potential from the second potential source B+. Thus, activation of a signal channel (channels 7-13) of the first channel indicating group 3 causes application of a potential from the second potential source B+ to the VHF tuner 21 and "swamping-out" of a potential from the third potential source B- which is, in turn, coupled to the band switching terminal of the VHF tuner 21.
Activation of a parallel connected signal channel of the second channel indicating group 5 which includes the low portion (channels 2-6) of the VHF signal band, causes application of a potential from the first potential source 13 to the first switching means 15 via the diode 31 and to the second switching means 17 via diode 29. Thereupon, the first switching means 15 is rendered conductive and a potential from the second potential source B+ is applied to the VHF tuner 21. The second switching means 17 is rendered non-conductive, due to the bias potential developed across the resistor 27 via diode 29, whereupon the third potential source B- is no longer "swamped-out" but rather, is applied to the band switching terminal of the VHF tuner 21.
Selection of one of the parallel connected signal channels (channels 14-83) in the UHF band of signals causes activation of the third channel indicating group 7. Thereupon, a potential from the first potential source 13 is applied to the third switching means 19. This applied potential renders the transistor 35 conductive whereupon a potential from the second potential source B+ is applied to the UHF tuner 3. Thus, activation of the UHF tuner 3 is provided upon selection of a high frequency signal channel (channels 14-83).
It may be noted that each one of the switches 11 in each channel of the first, second, and third channel indicating groups 3, 5, and 7 is mechanically connected to the others in a manner such that only one of the switches 11 is operable at a time. In other words, activation of a second one of the switches 11 causes de-activation of a first one of the switches 11. Such a switching system is clearly set forth in the cross-referenced application entitled "Pushbutton Tuning System" filed concurrently herewith.
Additionally, the channel indicating meter circuitry is responsive to selection of a channel in any one of the first, second, and third channel indicating groups 3, 5, and 7. Upon selection of a channel (channels 7-13) in the upper portion of the VHF signal range, a positive potential provided by second potential source B+ will appear at the junction of the second switching means 17, resistor 33 coupled to the third potential source B-, and the band switching terminal of the VHF tuner 21. This positive potential appears at the junction of the first and second unidirectional conduction devices 43 and 47 back biasing the first unidirectional conduction device 43 whereupon conduction therethrough ceases and the potential of the first terminal 41 of the indicating meter 39 is raised to provide an approximate half-scale reading of the channel indicating meter 39. The indicating meter 39 is further advanced in accordance with a potential applied to the first terminal 41 via the series connected resistors 42 and 44 coupled to the particular channel (channels 7-13) selected. Thus, this further advance of the indicating meter 39 is effected by current flow via the series connected resistors 44 and 42, the indicating meter 39 and the resistor 51 coupled to circuit ground.
Upon selection of a channel (channels 2-6) in the lower portion of the VHF signal band, the third potential source B- is no longer "swamped-out" because of the non-conductivity of the second band switching circuitry 17 but rather, is applied to the second unidirectional conduction device 47 to effect a back-bias thereon. Thus, current supplied by the tuning voltage, derived via the first potential source 13 and second channel indicating group 5, flows through the indicating meter 39 via the resistors 44 and 42 and to circuit ground by way of the resistor 51. Also, a predetermined portion of this current flows to circuit ground by way of the first unidirectional conduction device 43 and resistor 45 coupled thereto. Thus, compression to the lower portion of the scale of the indicating meter 39 provides a maximum utilization of scale length.
In the UHF signal band (channels 14-83), a positive potential appears at the first terminal 41 as previously explained with respect to the upper portion (channels 7-13) of the VHF signal band. Also, a substantially equal positive potential is applied to the second terminal 49 of the indicating meter 39 as derived from the second potential source B+ via the resistor 53 coupled to the second terminal 49. Thus, by application of substantially equal potentials to the first and second terminals 41 and 49 of the indicating meter 39, the total length of the indicating scale may be employed. Moreover, the tuning voltage, as derived from the first potential source 13 and third channel indicating group 7, is applied via the resistors 44 and 42 to the first terminal 41 of the indicating meter 39 to provide a visual indication of the channel selected.
Thus, there has been provided a unique band switching circuit as well as a unique channel indicating meter circuit for a multi-channel signal receiver employing both VHF and UHF varicap or varactor tuners. This improved circuitry is inexpensive of components, circuitry, and assembly time while reliability and repeatability of results are enhanced. Not only is the undesired wear associated with mechanical systems eliminated but, more importantly, the electronic switching technique increases the time switching capabilities without appreciable increase in cost.
While there has been shown and described what is at present considered the preferred embodiment of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.
The PHILIPS CHASSIS KM4 is an awesome and amazing example of PHILIPS ENGINEERING.
THE PHILIPS CHASSIS KM4 It's the first PHILIPS CHASSIS FOR MULTISTANDARD FEATURING PAL 625 LINE AND SECAM 819 LINES with the PHILIPS 20AX SYSTEM CRT TUBE completely based on semiconductors and further advanced with ASIC'S around almost all signal processing boards even if the chassis is mainly based around discretes semiconductors both silicium and germanium diodes and transistor.
And is first Featuring the SONG IC TUNING SEARCH SYSTEM in such kind of apparatus.
It's developed in 2 main sections boards panels:
- DEFLECTIONS LEFT SIDE (POWER SIGNALS PANEL)
- SIGNAL RIGHT SIDE (SMALL SIGNALS PANEL)
- MIDDLE BOTTOM POWER SUPPLY UNIT.
- ABOVE ADDITIONAL FRAME DEFLECTION UNIT.
The chassis CTV KM4 is higly sophisticated and complex but it has an unique fashinating structure and design which expands his technology in a
way of simplicity which is today, long time, lost and forgotten (forever).
CIRCUIT ARRANGEMENT FOR GENERATING IN A PICTURE DISPLAY DEVICE A SAWTOOTH CURRENT OF LINE FREQUENCY HAVING AN AMPLITUDE VARYING AT FIELD FREQUENCY IN PHILIPS CHASSIS CTV KM4.
A circuit arrangement for generating by means of a modulator in a colour picture display device a sawtooth correction current of line frequency flowing through the line deflection coils and having an amplitude varying at field frequency for the purpose of obtaining a better colour superposition in the corners of the screen of the display tube, comprising means to add an additional correction current which flows in the same direction as the first mentioned current and which is proportional to the third power of both the line and the field deflection currents. Said means may be a saturable coil or a resonant circuit which is tuned to a frequency which lies between the like frequency and twice the value thereof. In the latter case the voltage present across the circuit may be used for correcting the North-South pincushion distortion. Also, the modulator is controlled by an amplifier comprising a linear and a voltage-dependent resistor which ensure that a
third-power component is added also to said field deflection current.
1. A distortion correction circuit for line and field deflection coils of a display tube, said circuit comprising line and field deflection generator means coupled to said coils respestively for producing line and field deflection signals respectively; a modulator means for providing a line frequency first correction current having a field frequency varying amplitude to at least one of said coils; and means for supplying an additional correction current distinct from said deflection signals that is a thrid power function of at least one of said deflection signals and for applying it to said one deflection coil in the same direction as said first correction current.
2. A circuit as claimed in claim 1 wherein said supplying means comprises a non-linear inductor series coupled to said modulator and having an inductance that decreases with increasing current.
3. A circuit as claimed in claim 1 wherein said supplying means comprises a tuned circuit including an inductor and a capacitor parallel coupled thereto, said circuit being tuned to a frequency between the line frequency and twice the line frequency and being series coupled to said modulator.
4. A circuit as claimed in claim 3 wherein said inductor comprises a transformer primary, said transformer including a secondary; and further comprising means coupled to said secondary for correcting North-South pincushion distortion in said display tube.
5. A circuit as claimed in claim 1 wherein said modulator comprises diode switch means operating at the line frequency for coupling during the line scan time the field generator to a resonant circuit having a period twice the line flyback period, said resonant circuit including a capacitor and said line deflection coil; and further comprising a coil coupled in series between said line generator and said line coil.
6. A circuit as claimed in claim 5 further comprising a resistor series coupled to said capacitor.
7. A circuit as claimed in claim 5 further comprising a series circuit including in order a first capacitor, a pair of diodes that are non-conducting during the line flyback time, and a second capacitor, said series circuit being parallel coupled to said coil; and an inductance capacitance parallel resonant circuit coupled to the junction of the diodes, said circuit being resonant at a frequency between the line frequency and twice the line frequency.
8. A circuit as claimed in claim 1 further comprising amplifier means for applying said field signal to said modulator, said amplifier including a complementary pair of transistors adapted to receive a negative feedback network having an input coupled to the output electrodes of said transistors for receiving a zero average signal, said network comprising fixed and voltage dependent resistors coupled thereto.
9. A circuit as claimed in claim 1 further comprising a circuit coupled between said modulator and said field generator, said circuit comprising a fixed and a voltage dependent resistor parallel coupled thereto.
10. A circuit as claimed in claim 1 further comprising North-South pincushion correction means for adding a sinusoidal current of line frequency to said correction current.
11. A circuit as claimed 1 wherein said additional correction current is a third power function of both of said deflection signals.
Description:
The invention relates to a circuit arrangement for generating in a picture display device a sawtooth correction current of line frequency having an amplitude varying at field frequency, the picture display device being provided with a line and a field deflection current generator for applying a sawtooth current of line and field frequency to a line and a field deflection coil at a substantially constant peak-to-peak amplitude, and a modulator controlled by the field deflection generator for obtaining the amplitude variation of field frequency of the sawtooth correction current of line frequency, said sawtooth correction current of line frequency being proportional to the instantaneous value of the line deflection current and of the field deflection current.
U.S. Pat. No. 3,440,483 described a display device for colour television wherein for the purpose of correction on the screen of a display tube in the device use is made of a sawtooth correction current of line frequency having an amplitude varying at field frequency. From the beginning up to the end of the scan of a field period this correction current of line frequency is to decrease down to zero from a given value in a substantially linear manner, whereafter a substantially equal increase in the reverse current direction follows. This correction current is superimposed on the deflection current flowing in the line and/or field deflection coil, the peak-to-peak a
mplitude of the deflection current being substantially constant. Since the deflection coil is divided into two coil halves provided substantially symmetrically on either side of the neck of the display tube, it is possible to add the correction current in one coil half to the deflection current and to subtract it from the deflection current in the other coil half. The magnetic deflection field of one coil half will therefore be enlarged and that of the other coil half will be reduced to a substantially equal extent.
As has been described in the said U.S. patent the so-called anisotropic astigmatism of a deflection coil causes a distortion which gives an electron beam having a circular or ellipse cross-section a tilted ellipse shape, which distortion is dependent on the extent of the deflection. In other words, this distortion occurs most seriously in the corners of the displayed picture and it results in colour superposition errors. The said patent application shows that it is possible to eliminate this distortion with the aid of an oppositely directed distortion caused by the above-mentioned correction current.
The said amplitude variation of field frequency of the sawtooth current of line frequency is established by means of a modulator controlled by the field deflection current generator. The said patent application describes inter alia an arrangement wherein this modulator is formed as a multiplier to which information regarding the line and field deflection currents is supplied. If the centre horizontal line on the screen of the display tube is referred to as x'Ox and the central vertical line is referred to as y'Oy, wherein O is the centre of the screen while, as is common practice in mathematics, x'Ox extends from left to right y'Oy extends from bottom to top, it can be assumed that the compensating deviation Δ x which is established by means of the modulator is in the first instance proportional to x and to y. In this case x and y are the coordinates of one point on the screen relative to the previously defined system of coordinates. In this manner the compensating deviation Δ x is indeed increased in the corners of the screen and is zero on the axes x'Ox and y'Oy.
However, the invention is based on the recognition of the fact that the previously described correction is not sufficient to completely eliminate the colour superposition errors in the corners of the screen of the display tube. In order to be able to eliminate this the circuit arrangement according to the invention is characterized in that it includes means to add an additional correction current to the sawtooth current in the vicinity of the beginning and the end of each scan period, which additional current flows in the same direction as the said correction current and which is proportional to the third power of the line deflection current and to the third power of the field deflection current.
The correction currents may be produced in different manners. To this end the circuit arrangement according to the invention is further characterized in that the means for producing the additional correction current during the line scan period are obtained by means of a coil which is series-arranged with the modulator and whose inductance decreases when the current flowing therethrough increases and that the means for producing the additional correction current during the line scan period are obtained by means of a parallel circuit which is series-arranged with the modulator and whose resonant frequency lies between the line frequency and twice the value thereof.
Furthermore the invention is based on the recognition of the fact that the voltage which is present under these circumstances across the said parallel circuit may alternatively be used for other purposes. To this end, the circuit arrangement according to the invention is characterized in that the coil in the parallel circuit constitutes the primary winding of a transformer and that the voltage produced across the secondary winding of the transformer controls a circuit for the correction of the North-South pincushion distortion on the screen of a picture display tube present in the picture display device.
FRAME DEFLECTION CIRCUIT CHASSIS KM2
A field deflection circuit in which the deflection coil is connected to a direct voltage source during the flyback period so as to reverse the polarity of the deflection current. For this purpose the deflection coil is connected through a switch controllable connected to the direct voltage source, which switch is controlled by the difference between a voltage proportional to the steep-edged sawtooth input signal and a voltage proportional to the deflection current. This difference is considerable during the flyback period and is utilized for switching on the controllable switch; it becomes zero as soon as the deflection current has reached its required value at which the switch is switched off again. It is thus achieved that the polarity reversal is always terminated when the required value is reached, even when the direct voltage fluctuates and also when the inductive load is changed.
1. A circuit for generating an output deflection current for a deflection coil from an input sawtooth deflection voltage signal having a polarity changes at the start of the flyback period which are short with respect to said flyback period; said circuit comprising an amplifier having an input adapted to receive said input signal, and an output means adapted to be coupled to said coil for providing said output current; means coupled to said amplifier for generating a control voltage that is the difference between a voltage that is proportional to said input signal and a voltage that is proportional to said output current; a direct voltage source; and means for rendering said output current independent of voltage and load variations comprising means for reversing the polarity of said deflection current at the start of said flyback period including a switch means coupled to said amplifier and said source and having a control input coupled to said means for generating for coupling said coil to said source at the start of said flyback period and separating said coil from said source upon said deflection current reaching a selected value required for the start of the scan period.
2. A circuit as claimed in claim 1, wherein said amplifier comprises a junction having a potential that differs from a threshold value during said flyback period, said switch being coupled to said junction and switching at about said threshold value; and further comprising feedback means for applying said voltage proportional to said deflection current to said amplifier input.
3. A circuit as claimed in claim 2 wherein said junction potential goes below said threshold value during said flyback period, said switch switching above said threshold value.
4. A circuit as claimed in claim 2 wherein said junction potential exceeds said threshold value during said flyback period, said switch switching below said threshold value.
5. A circuit as claimed in claim 2 wherein said amplifier comprises first and second final stage class B push pull transistors, each of said transistors having emitter and collector conduction electrodes, a conduction electrode of one of said transistors being coupled to a like conduction electrode of said other transistor, said first transistor being conductive during said start of said scan period; a pass direction coupled diode having a first end coupled to first transistor conduction electrode, and a second end adapted to receive a first terminal of a power supply; a capacitor having a first end coupled to said diode first end, and a second end coupled to said switch; and a resistor having a first end coupled to said capacitor second end, and a second end adapted to receive a second terminal of said power supply.
6. A circuit as claimed in claim 5 wherein said like conduction electrodes comprise said collector electrodes and said diode first end is coupled to said first transistor emitter.
7. A circuit as claimed in claim 5 wherein said like conduction electrodes comprise said emitter electrodes and said diode first end is coupled to said first transistor collector.
8. A circuit as claimed in claim 5 further comprising a second cut off direction coupled diode having a first end coupled to a conduction electrode of said first transistor, and a second end coupled to the remaining conduction electrode of said first transistor.
Description:
The invention relates to a field deflection circuit including an amplifier whose input conveys a saw-tooth signal whose polarity changes at the commencement of the flyback period within a period of time which is very short as compared with the flyback period, the field deflection coil being connected to the output of said amplifier, and a controllable switch by means of which the deflection coil is connected to a direct voltage source at the commencement of the flyback pulse for the purpose of reversing the polarity of the deflection current.
As compared with a vertical deflection circuit in which the deflection coil with an additionally arranged capacitor is constituted as a part of a resonance circuit, which circuit performs an unattenuated half oscillation during the flyback period whereby considerable voltage amplitudes at the output of the amplifier circuit occur, the advantage of such a deflection circuit is that the direct voltage to which the deflection coil must be connected is not so high, so that transistors having a slight collector breakdown voltage can be used. In a circuit arrangement of the kind described in the preamble and in U.S. Pat. No. 3,070,727 the flyback voltage depends on the height of the direct voltage, the inductance of the deflection coil and the maximum deflection current in accordance with the relation T = LI/U, in which T denotes the duration of the polarity reversal, I denotes the height of the deflection current (measured from peak to peak), L denotes the inductance of the deflection coil and U denotes the height of the direct voltage.
In a known circuit arrangement of this kind the input of the controllable (transistor) switch is connected to the output of the amplifier through the series arrangement of a capacitor and a resistor. At the commencement of the flyback period the sawtooth voltage changes from its positive to its negative maximum value while a negative pulse becomes available through the RC member at the input of the transistor switch, which pulse causes this transistor to conduct and which connects the deflection coil to a negative direct voltage so that the current flowing through the coil is reversed in polarity. The duration of this polarity reversal depends on the time constant of the RC member before the input of the transistor switch. In case of fluctuations of the direct voltage to which the deflection coil is connected during the flyback period, the amplitude of the current reached by the deflection current during this polarity reversal of course also changes so that the scan period commences either at a too low or at a too high value of the vertical deflection current. Since in addition, as stated, the period of time during which the deflection coil must be connected to the direct voltage depends on the inductance of the deflection coil, the time constant of the RC member must be adapted to the inductance of the deflection coils.
An object of the present invention is to obviate these drawbacks and to provide a circuit arrangement in which the deflection coil is connected to the direct voltage as long as is necessary for reaching the amplitude of the deflection current required for the commencement of the scan period and in which an adaptation is not necessary when the inductance of the deflection circuit changes, for example, by including a transformer for the North-South raster correction.
Starting from a vertical deflection circuit of the kind described in the preamble this object is achieved according to the invention in that the controllable switch is controlled by the difference between a voltage which is proportional to the sawtooth signal and a voltage which is proportional to the deflection current, said two voltages and/or the switch being dimensioned in such a manner that the deflection coil is separated from the direct voltage by means of the switch as soon as the current flowing through the deflection coil has reached the value required for the commencement of the scan period.
The invention is based on the regulation of the fact that the sawtooth signal at the input of the amplifier and the current flowing through the vertical deflection coil have substantially the same variation throughout the scan period; during the flyback period the sawtooth signal is, however, reversed in polarity within a few microseconds, while the polarity reversal for the deflection current is considerably slower due to the limited direct voltage present at the deflection coil. These differences in the variation with time between the input signal and the deflection current may be utilized for the purpose of rendering the switch operative, which switch becomes inoperative again as soon as the deflection current has reached its value required for the commencement of the scan period, because then no difference exists any longer between the sawtooth input signal and the deflection current.
According to a further embodiment of the invention the voltage proportional to the deflection current is applied as a feedback voltage to the input of the amplifier and the controllable switch is connected to a point of the amplifier whose potential exceeds a threshold value only during the flyback period, which threshold value renders the controllable switch operative.
In order th
at the invention may be readily carried into effect, an embodiment thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawing. In this embodiment a class B push-pull amplifier is used which, as is known, has a lower dissipation then a class A amplifier for a determined deflection output. The amplifier is substantially symmetrical so that two corresponding parts are denoted by two corresponding reference numerals (for example, 12, 12').
The input signal 1 is applied through a capacitor 2 of 10 μF to the interconnected bases of the input transistors 3 and 3'. The collector of npn-transistor 3 is connected through a resistor 4 of 1.5 kOhms to the positive supply voltage terminal, while its emitter is connected through a resistor 5 of 6.8 kOhms to the negative supply voltage. Transistor 3' is of the pnp type and accordingly it has a polarity which is opposite to that of transistor 3; however, the resistors 4' in the collector lead and 5' in the emitter lead have the same values as resistors 4 and 5. The collector of the transistor 3(3') is connected to the base of a pnp- (npn-) transistor 6 (6') whose emitter is connected through a resistor 7 (7') of 470 Ohms to the positive (negative) supply voltage. The collectors of transistors 6 and 6' are connected together through a diode arranged in the pass direction. The collector voltages of transistors 6 and 6' are applied to the bases of transistors 8 and 8' which are of a conductivity type opposite to that of the transistors driving them. The collectors of transistors 8 and 8' are connected through resistors 9 and 9' to the bases of final transistors 10 and 10' which are again of a conductivity type which is opposite to that of the transistors driving them. The collectors of transistors 10 and 10' are connected together and the junction is connected to ground through the deflection coil 11 and a low-value resistor 12 of 2.2 Ohms. The final transistors are protected by diodes 15 and 15' from the voltage peaks occurring at the deflection coil when the current is reversed in polarity and when flashovers occur in the picture display tube, said diodes being connected in the blocking direction in parallel with the collector-emitter path of the final transistors. In case of a short circuit at the end of the final stage the driver current is limited by the resistors 9, 9'.
In case of a class B push-pull stage the output potential is normally highly dependent on the adjusted quiescent current which in turn is determined by the ambient temperature. In the present circuit arrangement this would give rise to the fact that the vertical position of the picture highly depends on the temperature. To avoid this, the bases of the final transistors 10 and 10' are connected through the series arrangement of diodes 13 and 13' arranged in the pass direction and resistors 14 and 14' to supply voltage terminal for their emitters. A resistor 16 of 47 kOhms arranged between the cathode of the diode 13 connected to the positive potential and the anode of the diode 13' connected to the negative potential ensures that the diodes 13 and 13' are always slightly biassed. As a result the base potential and the quiescent current of the final transistors 10 and 10' is determined by the bias voltage of these diodes when the input signal fails, hence when transistors 8 and 8' are cut off. Since this bias voltage is already very low and is even more reduced by the voltage drops at resistors 14 and 14', quiescent currents of a few μA can be adjusted. The distortions of the output signal to be expected at such a low quiescent current adjustment are eliminated in known manner (Austrian Pat. specification 245038) in that the bases of the final transistors are not connected to the emitters of the driver stages 8 and 8' but to their collectors so that the output resistance of the driver stages 8, 8' driving the final transistors 10, 10' is considerably larger than the input resistance of the final stages. The non-linearity of the input resistance therefore does not exert any influence on the course of the signal.
A voltage is derived from resistor 12 which is applied through resistors 17 and 17' to the emitters of input transistors 3 and 3'. The voltage 18 proportional to the deflection current derived from resistor 12 has the same phase and substantially also the same shape as the input signal 1 and therefore acts as a direct current feedback. The mean value of the deflection current and hence the position of the picture is determined in this circuit arrangement by the potential at the bases of transistors 3 and 3'. To adjust this potential a potentiometer connected to the supply voltage would be sufficient, while its wiper would be connected to the bases of the input transistors, but in this case the position of the picture would be greatly dependent on fluctuations in the supply voltage. Adjustment of the picture position substantially independent of supply voltage fluctuations is obtained when, as shown in the drawing, the base is connected to the wiper on a potentiometer 18' of 5 kOhms whose ends are connected to ground through resistors 19 and 19' of 22 kOhms and further resistors 20 and 20' of 330 Ohms, the junction of resistors 19, 20 and 19', 20' being connected through resistors 21 and 21', respectively, to the positive and negative potential, respectively. The amplifier and particularly the driver stages 8, 8' and the final stages 10, 10' are substantially insensitive to hum voltages so that the positive voltage of 24 volts and the negative voltage of -20 Volts need not be especially smooth. For the preliminary stages this smoothing may be effected in known manner by resistors 22 and 22' of 680 Ohms arranged in the supply lead which resistors together with capacitors 23 and 23' of 500 μF constitute a smoothing member.
It is achieved by the direct current feedback that the deflection current is adjusted such that the voltage fed back on the emitters of the input transistors 3 and 3' corresponds but for a small difference to the voltage at the bases of transistor 3 and 3' (for this reason the deflection current can be varied by varying the value of resistor 12 in case of a given amplitude of the input signal). As a result the deflection current has the same variation with time as the input signal 1 at least during the scan period. At the beginning of the flyback period the input voltage changes within a few microseconds from its positive to its negative maximum value; the deflection current can, however, not be reversed in polarity at the same rate. As a result the base-emitter voltage of the input transistors 3 varies substantially stepwise after the beginning of the flyback period when the input signal has already reached its negative peak value while the deflection current has only very slightly varied. The bases of the input transistors 3, 3' become thus considerably more negative so that the lower transistor 3' and at the same time the transistors 6', 8', 10' conduct heavily while transistors, 3, 6, 8 and 10 are cut off. This voltage variation produces a negative voltage step, for example, at the interconnected emitters of driver transistor 8, 8' which emitters are connected to ground through a resistor 24 of 100 Ohms, said voltage step being applied to the input of a controllable switch 27 through a potential divider consisting of resistors 25 of 1 kOhm and 26 of 22 kOhms and having one end connected to the said emitters and the other end connected to the positive supply voltage, so that said switch then onducts. In the conducting state the switch 27 must conduct current in both directions; when using a transistors switch the collector-emitter path of the switching transistor may be connected for this purpose in parallel with a diode having an opposite pass direction and having such a polarity that it does not conduct during the scan period.
The current flowing through the deflection coil might alternatively be reversed in polarity when the deflection coil would be directly connected via the switch to the negative supply voltage. In case of a negative supply voltage of - 20 Volts, a deflection inductance of 30 mH and a deflection current of 1,2 A (peak-to-peak) a time of 1.8 ms would, however, be required for reversing the polarity of the deflection current; a flyback period of less than one ms is, however, desirable. This shorter flyback period could be obtained by increasing the negative and the positive supply voltage. Then, however, the dissipation of the final stage transistors 10, 10' would also be increased.
In the circuit arrangement shown in the drawing the duration of the flyback period is reduced by means of a clamping circuit without increase of dissipation of the final stage transistors. For this purpose the emitter of transistor 10', unlike the emitter of transistor 10 is not directly connected to the associated voltage supply terminal but through a diode 28 conducting in the pass direction. In addition the emitter of transistor 10' is connected through a large capacitor 29 of 250 μF to the end of the transistor switch not connected to the negative supply voltage, which end is simultaneously connected through a resistor 30 of 220 Ohms to the positive supply voltage terminal. The clamping circuit operates as follows:
During the scan period capacitor 29 is charged through resistor 30 and the diode 28, a voltage of + 24 Volts occurring at the end of capacitor 29 connected to the switch and a voltage of approximately - 20 Volts occurring at the other end, so that a voltage of approximately 44 Volts is present at the capacitor. As soon as the transistor switch 27 conducts as a result of the steep-edged voltage step of the input voltage 1 the electrode of capacitor 29 which was positive (+ 24 Volts) up till that instant is connected to the negative supply voltage; this potential step is transferred to the other electrode of the capacitor which was previously at - 20 Volts and subsequently at approximately - 60 Volts. Diode 28 is blocked at this voltage.
At the beginning of the flyback period a negative voltage peak is produced at the end of the deflection coil 11 connected to the amplifier output, and this as a result of the sudden cut-off of the final stage transistor 10 which was still conducting relatively strongly at the end of the scan period. The negative voltage peak is limited by diode 15' to a voltage which is slightly more negative than - 60 Volts, for example, -60.6 Volts. The deflection current flows via diode 15' in the same direction as it did previously through transistor 10, but due to the negative voltage at the end of the deflection coil connected to the amplifier output it decreases to the value of zero. Subsequently, the current is reversed in polarity and flows through the collector-emitter path of the npn transistor 10' whose base also carries a positive voltage during the first part of the flyback period. The voltage at the deflection coil is then only slightly less negative than the voltage on the left-hand electrode of capacitor 29 due to the small voltage drop on the collector-emitter path of transistor 10', so that the deflection current furthermore decreases at approximately the same rate as during the first half of the flyback period, because substantially the same voltage is present at the deflection coil. Simultaneously also the voltage at resistor 12 decreases and hence the difference between the base-emitter voltages of the input transistors 3 and 3'. Consequently the lower half of the class B push-pull amplifier becomes less conducting so that the emitter potential of transistors 8 and 8' becomes again less negative. In case of suitable dimensioning of the potential divider 25, 26 and of the threshold at which the transistor switch 27 is opened again it can be achieved that opening is effected just at the instant when the deflection current has reached its required value. The capacitor 29 is still further charged during the first part of the flyback period and the more the lower its capacitance is, and during the second part of the flyback period it is discharged to the voltage present at the commencement of the flyback period. The mean value of the potential on the left-hand electrode of this capacitor is thus still more negative than - 60 Volts during the flyback period and the more as the capacitance of the capacitor is lower so that the deflection current is reversed in polarity at an even faster rate. However, restrictions are imposed in this case due to the dielectric strength of the final stage transistors; consequently, when the dielectric strength of transistors 10, 10' is only slightly more than 60 Volts, a capacitor having a high capacitance (250 μF) is to be used, as in the embodiment.
This circuit arrangement is insensitive to fluctuations during operation. When, for example, the negative and/or the positive supply voltage increases, the flyback duration decreases; accordingly the emitter potential of the driver transistors 8 and 8' reaches the positive threshold value more quickly so that the switch is opened again and the polarity reversal is interrupted as soon as the deflection current has reached its required value.
PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 NORD SOUTH (NORD/SUD) CORRECTION CIRCUIT ARRANGEMENT FOR CORRECTING THE DEFLECTION OF AT LEAST ONE ELECTRON BEAM IN A TELEVISION PICTURE TUBE BY MEANS OF A TRANSDUCTOR :
A circuit arrangement for raster correction in a television picture tube by means of a transductor whose power winding is connected in parallel with at least a portion of the line deflection coils, the line deflection genera
tor having a low internal impedance. In order to increase this impedance a mainly inductive impedance is connected in series with the generator. In a picture tube employing at least two electron beams the series impedance may include the convergence circuit. As a result the convergence in the corners of the picture screen is also improved. The linearity control circuit may likewise form part of the series impedance.
1. A deflection circuit for a cathode ray tube comprising a transistor horizontal deflection generator; a horizontal deflection coil parallel coupled to said generator; means for pincushion correction of said tube comprising a saturable reactor having a control winding adapted to receive a vertical deflection signal and a power winding parallel coupled to at least a portion of said deflection coil; and means for increasing the effectiveness of said correction means comprising an impedance element external to said generator having a substantially inductive reactance series coupled between said generator and said coil. 2. A circuit as claimed in claim 1 wherein said generator comprises a transformer having a tap and said power winding has a first end coupled to said coil and a second end coupled to said tap. 3. A circuit as claimed in claim 1 wherein said impedance element comprises means for controlling the linearity of the beam deflection. 4. A deflection circuit for a cathode ray tube having at least two electron beams comprising a transistor horizontal deflection generator; a horizontal deflection coil parallel coupled to said generator; means for pincushion correction of said tube comprising a saturable reactor having a control winding adapted to receive a vertical deflection signal and a power winding parallel coupled to at least a portion of said deflection coil; means for increasing the effectiveness of said correction means comprising an Impedance element external to said generator having a substantially inductive reactance series coupled between said generator and said coil; and means for dynamically converging said beams comprising a convergence circuit coupled to said horizontal generator and to said transductor. 5. A circuit as claimed in claim 4 wherein said generator comprises a transformer having a tap and said power winding has a first end coupled to said coil and a second end coupled to said tap. 6. A circuit as claimed in claim 4 wherein said impedance element comprises means for controlling the linearity of the beam deflection.
Description:
The invention relates to a circuit arrangement for correcting the deflection of at least one electron beam (raster correction) in a television picture tube by means of a saturable reactor a power winding of which is connected in parallel with at least a portion of the coils for the horizontal deflection, the current flowing through these coils being supplied by a deflection generator having a low internal impedance.
A circuit arrangement for raster correction with the aid of a transductor is described, for example, in U.S. Pat. No. 3,444,422. In this patent the power winding of a transductor is connected in parallel with the horizontal deflection coils while the control winding receives a signal of field frequency so that the current of line frequency which flows through the deflection coils is modulated at the field
-frequency (East-West correction), whereas the vertical deflection current is modulated at the line frequency (North-South correction). However, in this known arrangement there is the difficulty that the transductor can exert little influence on the horizontal deflection current if the internal impedance of the deflection generator is low because the transductor then only constitutes an additional load on the generator. This is the case when the deflection generator includes a valve with feedback -- or a switch formed with one or more transistors. In order to be able to use a transductor arrangement also in such a case the circuit arrangement according to the invention is characterized in that a mainly inductive impedance is connected in series between the said parallel arrangement and the deflection generator.
Due to the step according to the invention the internal impedance of the deflection generator is increased and the different components of the circuit remain mainly inductive so that the deflection current is more or less linear when the voltage provided by the deflection generator during the line scan period is substantially constant. The series impedance may be, for example, a fixed coil. However, the invention is furthermore based on the recognition of the fact that the increase in the internal resistance of the horizontal deflection generator may not only be obtained by a constant impedance, but other arrangements envisaging other improvements of the deflection may be used for this purpose. In that case even special improvements may be obtained as will be apparent hereinafter and possible small non-linearities of the additionally used arrangements have no detrimental results.
It is true that in known convergence circuits in picture tubes employing a plurality of electron beams a satisfactory improvement is obtained for the central horizontal and vertical lines of a picture tube of the shadow mask type. However, it is found that convergence errors may subsist in the corners of the picture. Known circuit arrangements which correct these second-order errors are often complicated and expensive. In the circuit arrangement according to the invention a satisfactory compensation of such convergence errors is possible in a simple manner if the series impedance which is arranged between the horizontal deflection generator and the deflection coils includes the convergence circuit. In this manner the sum of the deflection current and of the current derived for the field correction and modulated by the transductor flows through the convergence circuit so that the desired additional convergence correction in the corners of the written raster is obtained.
In order that the invention may be readily carried into effect a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a circuit arrangement in which the transductor is connected in parallel with the deflection coils, while in
FIG. 2 the transductor is only fed by part of the voltage applied to the deflection coils.
FIG. 1 shows two line-output transistors 1 and 2 which are arranged in series. The emitter of transistor 2 is connected to ground through a winding 3 while the collector of transistor 1 is connected through a winding 4 and a small series impedance 5, preferably a resistor, to the positive terminal of a supply source V
b whose negative terminal is connected to ground.
Windings 3 and 4 are wound together with
an EHT-winding 6 on the same transformer core 7. The ends of windings 3 and 4 remote from each other are connected through the capacitor 10 for the S-correction to the deflection-unit consisting of two windings 8 and 9 arranged, for example, in parallel. The base of transistors 1 and 2 receive pulses of line frequency in a manner not shown in FIG. 1 so that these transistors are cut off during the flyback period. During the scan period, a substantially constant voltage is applied to the deflection unit. Consequently a more or less sawtooth-shaped current flows through windings 8 and 9. The bipartite power winding 11 of a transductor ensuring the raster correction is connected in parallel with this deflection unit 8, 9. The control winding 12 of said transductor, and a converting capacitor 13 in parallel therewith form part of the circuit for the vertical deflection through terminals 14 and 15. An adjustable coil 16 with which the raster correction can be adjusted exactly is connected in series with winding 12.
Windings 3 and 4 have the same number of turns so that pulses of the same amplitude and reversed polarity are produced at the emitter of transistor 2 and at the collector of transistor 1. As a result a disturbing radiation of these pulses is reduced. Furthermore, transistor types are chosen in this Example for transistors 1 and 2 whose collector-base diodes may function as efficiency diodes. All this has been described in U.S. Pat. No. 3,504,224.
According to the invention the convergence circuit 17 is arranged through a separation transformer 20 between the end of winding 3 remote from winding 4 and the horizontal deflection coils 8, 9. Furthermore, this current branch includes the linearity control circuit 21 which comprises the parallel arrangement of a resistor and a coil whose inductance is adjustable, for example, by means of premagnetization of the core of the coil. A current, which is the sum of the current for the deflection coils 8, 9 and of the current for the power winding 11 of the transductor, flows through the primary winding of transformer 20. This primary current is transformed to the secondary circuit of transformer 20 so that a current flows through convergence circuit 17.
In known arrangements the convergence current is only influenced by the deflection current itself. It has been found that in this case the convergence correction is not sufficient in the corners of the picture. At these areas, where the deflection in both directions is at a maximum, a greater intensity of the convergence current is required. This is especially the case in picture tubes having a great deflection angle and according to the invention this is achieved in that the current which is derived from the power winding 11 of the transductor for the raster correction is also applied to the convergence circuit. This current flows from the horizontal deflection generator constituted by windings 3 and 4 through the primary winding of transformer 20 to power winding 11 of the transductor. The transductor current is in fact at a minimum in the center of the picture and increases towards the edges and particularly towards the corners. Thus the convergence current varies in the desired manner. According to the invention the desired improvements of the convergence correction and simultaneously the likewise desired increase in the internal resistance of the horizontal deflection generator is consequently obtained without a considerable increase in the number of required circuit elements and without disturbing the normal operation of the circuit arrangement. Due to transformer 20 a terminal of convergence circuit 17 may be connected to ground so that the convergence can be adjusted safely. If necessary, a suitable impedance transformation may also be obtained with the aid of transformer 20.
The linearity control circuit 21 may alternatively be connected in series with the said branch which includes transformer 20. As a result the internal resistance of the horizontal deflection generator for the line frequency is further increased without the field correction and the convergence correction being disturbingly influenced.
FIG. 2 shows a modification of the circuit arrangement according to the invention in which the deflection current is not changed relative to that of FIG. 1. The end of power winding 11 of the transductor shown on the upper side of FIG. 1 is connected to ground in FIG. 2. In addition convergence circuit 17 is included between winding 3 and ground so that separation transformer 20 may be omitted. If as a first approximation the impedances 5 and 17 are assumed to be negligibly small relative to the other impedance of the circuit arrangement, power winding 11 may be considered to be connected to a tap on the deflection generator 3, 4. Consequently, only approximately half the voltage of the deflection generator is applied to transductor winding 11 which winding must
therefore be proportioned in such a manner that it can convey a current which is approximately twice as large as that of FIG. 1. This larger current also flows through convergence circuit 17 which, with the omission of separation transformer 20, is favorable for the convergence in the corners of the picture screen.
In FIG. 2 the emitter of transistor 2 is connected to ground i.e., the said tap on the deflection generator. During the scan period the series arrangement of supply source V
b and windings 3 and 4 FIG. 1 is substantially short-circuited by transistors 1 and 2. In order that these transistors in the circuit arrangement according to FIG. 2 operate under the same circumstances as those in FIG. 1, an additional winding 24 must be wound on core 7 between windings 4 and 6, winding 24 having the same number of turns as winding 3, and the collector of transistor 1 must be connected to the junction of windings 6 and 24.
The end of power winding 11 connected to ground in FIG. 2 may alternatively be connected for the desired adjustment of the corner convergence to a different tap on the transformer, that is to say, on winding 3 or 4.
Resistor 5 serves in known manner mainly as a safety resistor so that in case of an inadmissible load of the EHT, for example, as a result of flash-over in the picture tube, the supply voltage for transistors 1 and 2 is reduced so that overload of these transistors is avoided.
PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 E/W CORRECTION Circuit arrangement in an image display apparatus for (horizontal) line deflection
Line deflection circuit in which the deflection coil is east-west modulated. In order to cancel an east-west dependent horizontal linearity defect the inductance value of the linearity correction coil is made independent of the field frequency, for example by means of a compensating current. In an embodiment this current is supplied by the shunt coil of the east-west modulator.
1. Circuit arrangement for use with a line deflection coil, said circuit comprising a generator means adapted to be coupled to said coil for producing a sawtooth line-deflection current through said line deflection coil, said deflection current having a field-frequency component current, a horizontal linearity correction coil adapted to be coupled in series with said deflection coil and including an inductor having a bias-magnetized core, and means for making the inductance value of the linearity correction coil substantially independent of the field frequency component current. 2. Circuit arrangement as claimed in claim 1, wherein said making means includes a current supply source means for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the compensating current having a field-frequency variation. 3. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is opposite to the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have the same direction. 4. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is the same as the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have opposite directions. 5. Circuit arrangement as claimed in claim 2, wherein said correction coil further comprises an additional winding disposed on the core, said additional winding being coupled to said supply source means to receive the compensating current. 6. Circuit arrangement as claimed in claim 5, further comprising modulator means for modulating the line deflection current with said field frequency component, said modulator including a compensation coil coupled in series with said additional winding. 7. Horizontal linearity correction coil comprising a core made of a magnetic material and bias-magnetized by at least one permanent magnet, and an additional winding disposed on the core. 8. Image display apparatus including a circuit arrangement as claimed in claim 1.
Description:
The invention relates to a circuit arrangement in an image display apparatus for (horizontal) line deflection, which apparatus also includes a circuit arrangement for (vertical) field deflection, provided with a generator for generating a sawtooth line-frequency deflecting current through a line deflection coil and with a modulator for field-frequency modulation of this current, the deflection coil being connected in series with a linearity correction coil in the form of an inductor having a bias-magnetized core.
By means of the linearity correction coil the linearity error due to the ohmic resistance of the deflection circuit is corrected. The sign of the bias magnetisation is chosen so that it is cancelled by the deflection current at the beginning of the deflection interval, so that the inductance of the correction coil is a maximum, whereas the voltage drop across the deflection coil then is a minimum. This voltage drop is adjustable by adjustment of the starting inductance of the correction coil. During the deflection interval the core gradually becomes saturated so that the inductance of, and the voltage drop across, the correction coil decrease. Thus the linearity error can be cancelled exactly at the beginning of the interval, that is to say on the left on the screen of the image display tube, and with a certain approximation at other locations.
In image display tubes using a large deflection angle, raster distortion, which generally is pincushion-shaped, of the image displayed occurs. This distortion can be removed in the horizontal direction, the so-called east-west direction, by means of field-frequency modulation of the line deflection current, the envelope in the case of pincushion-shaped distortion being substantially parabolic so that the amplitude of the line deflection current is a maximum at the middle of the field deflection interval.
It was found in practice that the said two corrections are not independent of one another, that is to say the adjustment of the east-west modulation affects horizontal linearity. As long as the modulation depth is not excessive, a satisfactory compromise can be found. However, in display tubes having a deflection angle of 110° and particularly in colour display tubes in which the deflection coils have a converging effect also, it is difficult to find such a compromise. A tube of this type is described in "Philips Research Reports," volume Feb. 14, 1959, pages 65 to 97; the distribution of the deflection field is such that throughout the display screen the landing points of the electron beams coincide without the need for a converging device. Owing to this field distribution, however, the pin-cushion-shaped distortion in the image displayed in the east-west direction is greater than in comparable display tubes of another type. Hence there must be east-west modulation of the line deflection current to a greater depth. It is true that under these conditions horizontal linearity can correctly be adjusted over a given horizontal strip after the east-west modulation has been adjusted correctly, i.e., for a rectangular image, but it is found that in other parts of the display screen a serious linearity error remains. When vertical straight lines are displayed as straight lines in the right-hand part of the screen, they are displayed as curved lines in the left-hand part.
It is an object of the present invention to remove the said defect so that horizontal linearity can satisfactorily be adjusted throughout the screen, and for this purpose the circuit arrangement according to the invention is characterized in that it includes means by which the inductance of the linearity correction coil is made substantially independent of the field frequency.
The invention is based on the recognition that the defect to be removed is due to a field-frequency variation of the said inductance because the latter is current-dependent. According to a further recognition of the invention the circuit arrangement is characterized in that it includes a current supply source for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the current being field-frequency modulated. The circuit arrangement according to the invention may further be characterized in that an additional winding is provided on the core of the linearity correction coil and is traversed by the compensating current. A circuit arrangement in which the modulator for modulating the line deflection current includes a compensation or bridge coil may according to the invention be characterized in that the additional winding is connected in series with the said coil.
The invention also relates to a linearity correction coil for use in a line deflection circuit having a core which is made of a magnetic material and is bias magnetized by at least one permanent magnet, which coil is characterized in that an additional winding is provided on the core.
Embodiments of the invention will now be described by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is the circuit diagram of a known circuit arrangement for line deflection in which the line deflection current is east-west modulated,
FIG. 2 shows the distorted image which is displayed on the screen when the circuit arrangement of FIG. 1,
FIG. 3 is a graph explaining the observed defect, and
FIGS. 4 and 7 show embodiments of the circuit arrangement according to the invention by which this defect can be cancelled.
FIG. 1 is a greatl
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG.
To the base of transistor Tr line-frequency switching pulses are supplied. In known manner the said series combination is connected to the supply voltage source during the deflection interval (the trace time), diode D and transistor Tr conducting alternately. During the retrace time these elements are both cut off. Under these conditions the current i y is a sawtooth current. The coil L, which has a saturable ferrite core which is bias-magnetized by means of at least one permanent magnet, serves to correct the linearity of the current i y during the trace time, whilst the capacitance of the capacitor C t is chosen so that the currenct i y is subjected to what is generally referred to as S correction. During the retrace time, at point A pulses are produced the amplitude of which is much higher than that of the voltage V b and would be constant in the absence of modulation source M. Information from the field deflection circuit, not shown, of the image display apparatus and line retrace pulses, the latter for example by means of a transformer, are supplied in known manner to modulation source M. Amplitude-modulated line retrace pulses having a field-frequency parabolic envelope, as indicated in the FIG., are produced at point B. During the line trace time the voltage at point B is zero. Thus the current i y is given the desired field-frequency modulated form which is also shown in FIG. 1.
The amplitude of the envelope in point B at the beginning and at the end of the field trace time and the amplitude of this envelope at the middle of the said time can both be adjusted so that the image displayed on the display screen of the display tube (not shown) has the correct substantially rectangular form. If, however, the required modulation depth is comparatively large, a linearity error of the line deflection is produced which cannot be removed by means of the correction coil L.
FIG. 2 shows the image of a pattern of vertical straight lines as it is displayed on the screen with the correction coil L adjusted so that horizontal linearity is satisfactory along and near the central horizontal line. In FIG. 2 the defect is exaggerated. It is found that horizontal linearity is defective in other areas of the screen so that the vertical lines are displayed correctly in the right-hand half of the screen but as curves in the left-hand path, the defect increasing as the line is farther to the left.
This phenomenon can be explained with reference to FIG. 3. In this FIG. the inductance L of the linearity correction coil is plotted as a function of the magnetic field strength H. In the absence of current, H has a value H 0 owing to the bias magnetization. If an approximately linear sawtooth current i (t) as shown in the b
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t .
Because owing to the east-west modulation the amplitude of current i(t) varies, the amplitude of L(t) also varies. This implies a field-frequency variation of L which is non-linear. This variation is undesirable. In the case of a small variation of the amplitude of current i(t) the variation of L(t) can be more or less neglected, but this is no longer possible when the amplitude of current i(t) varies greatly owing to the east-west modulation. L(t) varies according to different curves. FIG. 3 shows two of such curves and also illustrates the fact that the undesirable variation of L(t) is greatest at the beginning of the trace time and smallest at the end thereof.
FIG. 4 shows a circuit arrangement in which the defect described can be corrected. On the core of the correction coil L of the circuit of FIG. 1 an additional winding L 2 is provided. Winding L 2 is connected to a current source which produces a compensating current i 2 which has a line-frequency sawtooth variation and a field-frequency amplitude modulation. The envelope here also is parabolic, however, with a shape opposite to that of deflection current i y , that is to say having a minimum at the middle of the field trace time. The direction of current i 2 and the winding sense of winding L 2 relative to that of coil L are chosen so that the magnetic field produced in the core by winding L 2 has the same direction as the field produced by coil L. Hence the two field strengths are added
. The amplitude of current i 2 and the turns number of winding L 2 can be chosen so that current i y flows through inductances the total value of which is not dependent upon the field frequency. The curve L(t) of FIG. 3 remains substantially unchanged. Consequently the undesirable field-frequency modulation is removed without variation of the bias magnetization, which would have been varied if current i 2 were a field-frequency current. Obviously the same result can be achieved by a choice such of the direction of current i 2 and of the winding sense of winding L 2 that the two field strengths are subtracted one from the other, whilst the curvature of the envelope of current i 2 has the same direction as that of the envelope of current i y .
The current source of FIG. 4 may be formed in known manner by means of a modulator in which a line-frequency sawtooth signal is field-frequency modulated, the envelope being parabolic. FIG. 5 shows a circuit arrangement in which current i 2 is produced by the modulation source which provides the east-west correction. In FIG. 5, the source M of FIG. 1 comprises a diode D', a coil L' and two capacitors C' r and C' t , which elements constitute a network of the same structure as the network formed by elements D, L y , C r and C t . The capacitor C' t is shunted by a modulation source V m which supplies a field-frequency parabolic voltage having a minimum at the middle of the field trace time.
With the exception of the linearity correction means to be described hereinafter, the circuit arrangement of FIG. 5 was described in more detail in U.S. Pat. No. 3,906,305. Hence it will be sufficient to mention that the capacitances of capacitors C r and C' r and of a capacitor C 1 connected between junction point A and earth and the inductance of coil L' are chosen so that the three sawtooth currents flowing through L y , L' and L 1 have the same retrace time. The capacitances of capacitors C t and C' t , which are large, are ignored. When voltage V b is constant, current i y is subjected to the desired east-west modulation having the form shown in FIG. 1.
Coil L y is connected in series with correction coil L, and winding L 2 is connected in series with coil L'. FIG. 5 shows that the current flowing through winding L 2 has the same waveform as the current i 2 of FIG. 4, for its envelope has the same shape as the voltage supplied by source V m . By a suitable choice of the number of turns of winding L 2 it can be ensured that the linearity correction remains the same for every line during the field trace time.
Modified embodiments of the circuit arrangement of FIG. 5 can also be used. FIG. 6 shows such a modified embodiment in which the capacitive voltage divider C r , C' r of FIG. 5 is replaced by an inductive voltage divider by means of a tapping on coil L 1 . A capacitor C 2 is included between the tapping and the junction point of diodes D and D', whilst capacitor C' t here forms part of two networks C t , L y and C' t , L' traversed by a sawtooth current. In FIG. 6 modulation source V m is connected via a choke coil L 3 to the junction point of D, D', C 2 and
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 .
Other east-west modulators are known in which the step of FIGS. 5 and 6 can be used. An example is the modulator described in the publication by Philips, Electronic Components and Materials: "110° Colour television receiver with A66-140X standard-neck picture tube and DT 1062 multisection saddle yoke," May 1971, pages 19 and 20, which modulator also comprises two diodes and a compensation coil L', which are arranged in a slightly different manner. In another example the east-west modulator and the line deflection generator are included in a bridge circuit whilst they are decoupled from one another by means of a bridge coil which has the same function as coil L' in FIGS. 5 and 6. In these circuit arrangements coil L and winding L 2 may be arranged in the same manner as in FIG. 6. The same applies to an east-west modulator using a transductor the operating winding of which is in series with the deflection coil.
In the abovedescribed embodiments of the circuit arrangement according to the invention the compensating current i 1 is provided by transformer action. In the embodiment of FIG. 7 the current source which supplies the current i 2 is connected in parallel with correction coil L, i.e., without an auxiliary winding. In this embodiment the east-west modulation is achieved not by means of a modulator, but by means of the fact that the supply voltage V b is the super-position of a field-frequency parabolic voltage on the direct voltage. In this known manner the supply source also is the modulator.
It will be seen that in the embodiments of FIGS. 4, 5 and 6 current i 2 counteracts the east-west modulation of deflection current i y . It was found in practice, however, that this counteraction is slight.
PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 DUAL SYNCH FREQUENCY. 625 LINES / 819 LINE PAL/SECAM:
A video display system operates at a plurality of horizontal scanning rates. A voltage source produces different voltage levels, one of which is selected in response to the horizontal rate selected. A horizontal deflection circuit produces retrace pulses having amplitudes dependent on the scanning rate. A high voltage transformer has a primary winding with a number of taps. The voltage source is connected to one of the taps in response to the horizontal deflection rate selected so that the high voltage level developed across the transformer secondary winding remains substantially constant independent of changes in retrace pulse amplitude.
1. A power supply and deflection circuit for use in a video display system comprising:
means for selecting one of a plurality of horizontal deflection rates;
horizontal deflection means coupled to said selecting means for operating at said selected horizontal deflection rate, incorporating means for producing horizontal retrace pulses having amplitudes dependent upon said selected horizontal deflection rate;
a voltage source providing a plurality of predetermined different voltage levels;
means for selecting one of said voltage levels in response to said selected horizontal deflection rate;
transformer means comprising:
a transformer winding comprising a plurality of winding turns having a first terminal coupled to said means for producing horizontal retrace pulses, and having a plurality of taps, each of said taps forming, with said first terminal, a transformer primary winding having a different number of winding turns dependent on the tap selected; and
a transformer secondary winding magnetically coupled to said primary winding for producing a secondary winding voltage in response to said retrace pulses on said primary winding; and
means for applying said selected voltage level to one of said taps in response to said selected horizontal deflection rate, said tap selected such that said secondary winding voltage remains substantially constant during retrace in response to retrace pulses of different amplitudes.
2. The arrangement defined in claim 1, wherein the number of winding turns of said primary winding is increased as said horizontal deflection rate is decreased. 3. The arrangement defined in claim 1, wherein said secondary winding produces a high voltage level in response to said retrace pulses on said primary winding.
Description:
This invention relates to power supply and deflection circuits for multiple scan rate video display systems and in particular to an arrangement for providing raster size compensation for different scanning or deflection rates.
One problem which arises as a result of an attempt to use common circuit components is associated with the horizontal deflection circuit. If the same flyback transformer, yoke inductance, and horizontal retrace capacitor are utilized, the horizontal retrace or flyback pulse will be substantially the same in width for each scanning rate. A constant width retrace pulse will, however, cause the trace/retrace ratio to change for different horizontal scanning frequencies or rates, with the ratio increasing for decreasing scan rates. The trace/retrace ratio will increase, however, by a factor greater than the ratio of the scanning rates, so that the retrace pulse amplitude tends to be greater at the lower scanning frequency. Since the retrace pulse amplitude determines the high voltage level via the high voltage transformer, the high voltage level will increase as the horizontal scanning frequency or rate decreases.
In accordance with an aspect of the present invention, a power supply and deflection circuit for use in a video display system comprises horizontal deflection means adapted for operating at a plurality of selectable horizontal deflection or scanning rates. The deflection means incorporates circuitry which produces horizontal retrace pulses that have amplitudes that depend on the selected horizontal scanning rate. A voltage source produces different voltage levels and means select one of those voltage levels in response to the selected scanning rate. A transformer has a primary winding with a number of winding turns and a first terminal that is connected to the retrace pulse producing circuit. The transformer winding also has a number of taps which each form a primary winding with the first terminal and have different numbers of winding turns. A transformer secondary winding is magnetically coupled to the primary winding and produces a high voltage level in response to the amplitude of the horizontal retrace pulses on the primary winding. Means couple the voltage source to one of the taps in response to the selected scanning rate so that the high voltage level remains substantially constant independent of changes in retrace pulse amplitude.
PHILIPS 22C942 MULTISTANDARD (KM4) CHASSIS KM4 SONG IC TUNING CHANNEL SELECTION SYSTEM:
A television tuning device having a circuit for continuously scanning at least one frequency band. Scanning can take place at two speeds and controls are provided for starting and stopping the scanning procedure. The scanning speed is automatically changed from high speed to low speed when a television channel is detected to allow ample time for scanning to be stopped manually. Alternatively, the scanning may be stopped automatically.
A station finder which switches to automatic frequency control during automatic finding in case of reception of
a transmitter and, if desired, continues to find a transmitter some time later with the frequency control switched off.
1. A receiver tuning circuit for a tuner comprising means for detecting the presence of a received signal having an input means for coupling to said tuner; a search tuning circuit having a capacitor means for a tuning voltage for said tuner, and an automatic frequency control circuit coupled to said capacitor, said tuning circuit and said automatic frequency control circuit charging said capacitor when activated; an operating device means coupled to said detecting means and said search tuning circuit for activation of said search tuning circuit and for subsequent deactivation of said search tuning circuit and activation of said automatic frequency control circuit upon detection of a received signal; and time constant circuit means coupled between said detecting means and said operating device means for repeatedly activating said search tuning circuit and deactivating said automatic frequency control circuit a selected time after said search tuning circuit has been deactivated. 2. A receiver tuning circuit as claimed in claim 1, wherein said operating device has a supply lead and the time constant circuit is coupled to the supply lead of the operating device. 3. A receiver tuning circuit as claimed in claim 1, wherein the detection circuit is coupled to an output of a frequency detector and includes a means for preventing pulling in on the same transmitter upon activation of said search tuning circuit.
Description:
The invention relates to a receiver tuning circuit including a search tuning circuit which can be activated by a control device in which the search tuning circuit is automatically switched off when a received station is detected by a detection circuit and an automatic frequency control circuit is switched on, and in which a time constant circuit changes the state of the receiver tuning circuit after a certain time.
A receiver tuning circuit of the kind described above is known from German Offenlegungsschrift 2,023,352 which after activation of the search tuning stops the search action when a transmitter transmitting a pilot signal is received and switches on an automatic frequency control circuit. The search tuning circuit must again be activated when the received transmitter is not desired. When a transmitter without a pilot signal is received, the search tuning circuit switches over to a slowed down searching action and the automatic frequency control remains switched off. The tuning circuit includes a time constant circuit which renders the detection circuit for the pilot signal inactive some time after the finder has been activated so that the circuit can then pull in on transmitters without a pilot signal.
This known tuning circuit is only suitable for special receivers. An object of the invention is to provide a tuning circuit which is more suitable for other receiver types.
To this end a receiver tuning circuit of the kind described in the preamble according to the invention is characterized in that the time constant circuit is incorporated in the tuning circuit in such a manner that again and again it switches on the search tuning circuit a certain time after having automatically switched it off and switches off the automatic frequency control as long as the search tuning circuit is maintained operative with the aid of the operating device.
By using the step according to the invention a receiver is obtained which upon activation of the search tuning circuit receives without distortion transmitter after transmitter each during a time determined by the time constant circuit. The search tuning can be rendered inactive with the aid of the operating device after the desired station has been found. The tuning circuit is very suitable for radio or television receivers for domestic use.
1. A television tuning device comprising a circuit scanning means for continuously scanning at least one band of receivable frequencies, manual control means for starting and stopping said scanning, a terminal means for applying a switch signal to said scanning means for switching from a first band-scanning speed to a second band-scanning speed lower than the first, and detection means for detecting the presence of a television channel by comparing received synchronization signals with local signals generated in the television receiver and for applying a switch signal to said terminal means for switching from said first band-scanning speed to said second band-scanning speed in the presence of said switch signal so that the band scanning continues at said second band-scanning speed until the manual control means stops the scanning.
2. A television tuning device according to claim 1, further comprising scanning stopping means for stopping the scanning automatically when a television channel has been correctly tuned in, speed reducing means for reducing band-scanning speed, and said detection means comprising first and second detecting means for detecting the presence of a television channel which act in sequence one after another for supplying to said speed reducing means control signals at successive instants so as to increase the effective time interval during which said scanning stopping means may operate.
3. A device according to claim 2, further comprising controlling means for controlling the tuning frequency of the receiver automatically for optimum tuning, said controlling means being activated or de-activated by said switch signal provided by the said detection means for detecting the presence of a television channel.
4. A device according to claim 1, in which said band-scanning circuit means includes means for generating scanning signals at increasing speed starting from the instant scanning commences, and means for stopping and restarting scanning when the presence of a television channel is detected so that scanning continues at the same speed as when it commenced.
nned in a reasonable length of time (let us say, the UHF band in one minute) band-scanning speed needs to be fairly high. Consequently, if the user is not quick enough in sending out the search-stop control signal, it is more than likely that the control will be sent when the required television channel has been overshot. If, by chance, there are two channels close to one another, the searching device may even stop on the second of the two, thus confusing the user who will not know which of the two channels he has tuned into.
The aim of the present invention is to provide a tuning device to overcome these problems.
With this aim in view, the present invention provides a television tuning device comprising a circuit for continuously scanning at least one band of receivable frequencies, manual control means for starting and stopping the said scanning procedure, a terminal for applying a switch signal for switching from a first band-scanning speed to a second band-scanning speed lower than the first, and detection means for detecting the presence of a television channel by comparing the received sync signals with local signals generated in the television receiver, and applying a switch signal to the said terminal for switching from the said first scanning speed to the said second scanning speed in the presence of the said switch signal, so that the band scanning continues at said lower speed until the manual control means produce the stopping scanning procedure.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 shows a block and circuit diagram of an exemplary television tuning device according to the invention; and
FIG. 2 shows the internal structure of exemplary integrated circuits used in the diagram of FIG. 1.
In the diagram, an input terminal receives an input signal from a frequency discriminating circuit, which forms part of a known automatic frequency control (AFC) circuit, the input signal being applied to a known Schmitt trigger circuit, generally designated 2. The output of circuit 2 is connected to a first input of a circuit 3 which has two outputs, one connected to set input S and one to reset input R of Flip Flop circuit 4. Input S of the said Flip Flop is also connected to a first input of an exclusive OR logic circuit 5 and a first output of a control circuit 6 which has a second output connected to input R of circuit 4 and an input connected to a terminal of a first push-button 7 the other terminal of which is grounded.
Number 8 represents an input for receiving line sync signals obtained in the known way from sync separating circuits, the signals being applied to a first input of a coincidence detecting circuit 10 the second input of which is connected to receive a line flyback pulse 9, obtained from the horizontal deflection circuits. The output of circuit 10 is connected to a signal translation circuit 11, the second input of circuit 3 and an output 12 which can be sent to activate the AFC circuits on the set. ON reset circuit 13 has a first output connected to the second input of circuit 5, which is also connected to the output of circuit 4 through disconnecting resistor 22, and a second output connected to the control input of circuit 3, which is also connected to the output of circuit 5 through resistor 14. The output of EX-OR circuit 5 is also connected to the input of matching stage 15 the output of which is connected to a second push-button 16 and a first control input (UP) of a tuning detection and memorising circuit 17. This has a second control (down) input connected to a third push-button 18. A detection speed switch input is connected to the output of circuit 11. Input 21 can be connected, in the known way, to a station keyboard, outputs 19 and 20 representing respectively the tuning voltage to be sent to the tuning circuit and the channel indication to be sent to an appropriate display, using known methods. Push-buttons 16 and 18 are the same as push-button 7 and therefore have their second terminals grounded.
The known station memory circuit 17 consists mainly of TEXAS INSTRUMENTS Ser. No. 76,720 and Ser. No. 76,727 integrated circuits, an amplifying transistor, a filter and passive components for piloting the said integrated circuits as recommended by the makers. Push-buttons 16 and 18 are connected to terminals 10 and 11 of integrated circuit Ser. No. 76,720 respectively. Input 21 is represented by terminals, 1, 15, 16, 17 and 18 of the same integrated circuit while terminal 13 is connected directly to the output of circuit 11. The components used for performing the required function are represented inside a number of the circuits already mentioned. The ratings of the resistors and condensers are shown directly in the diagram. The ratings of the remaining components are as shown in the Table below:
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NPN transistors BC 148B PNP transistors BC 158B Diodes 1N4148 NOR gates 1/4 F4001 (+ A supply) NAND gates 1/4 F4011 (+ A supply) + A 5V + B 12.5V + C 33V
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The circuit operates as follows:
rnal crystal coupled to pins 2 and 3. A pair of cascaded divide-by-two flip-flops provide the proper clock signal at pin 4. A D-type flip-flop, which provides waveform shaping, is coupled to pin 4, and has both Q and Q output signals applied to pins 13 and 14 respectively. Two additional cascaded divide-by-two flip-flops are coupled to the Q output of the D-type flipflop and provide buffered output signals on pins 6 and 9 for driving a LED display (not shown). Two keyboard scanning output signals are provided at pins 5 and 10 which are in synchronization with the LED output signals at pins 6 and 9 but are narrowed and delayed to avoid edge coincidence glitches.
The station memory is Texas Instrument integrated circuit of the type Ser. No. 76,720 which receives the clock signal at its pin 9 and applies it to 12 bit synchronous counter. Pins 15 to 18 and 1 correspond to the input terminal 21 of the present invention and are intended to carry a five bit code identifying the manually selected channel. The signals are applied to 5 to 20 line decoder which in turn applies signals to a 12 bit tuning voltage RAM. The pins 10 and 11 are the up and down frequency scanning controls shown in FIG. 1 and the VHF/UHF pin 13 is also scanning speed controlled. The scanning is effected by transferring the data of the prevailing channel into the transparent counter and modifying this data under the control of the tuning program generator, the counter being clocked up or down at rate determined by the tuning timer and the countdown frequency select circuit. When one or the other buttons connected to the pins 10 and 11 is depressed, the count is incremented initially at a slower rate, the rate increasing gradually until it reaches a miximum level determined by the signal applied to pin 13.
CRT TV EHT VOLTAGE MULTIPLIER - KASKADE COCKCROFT-WALTON CASCADE CIRCUIT FOR VOLTAGE MULTIPLICATION:
A Cockcroft-Walton cascade circuit comprises an input voltage source and a pumping and storage circuit with a series array of capacitors with pumping and storage portions of the circuit being interconnected by silicon rectifiers, constructed and arranged so that at least the capacitor nearest the voltage source, and preferably one or more of the next adjacent capacitors in the series array, have lower tendency to internally discharge than the capacitors in the array more remote from the voltage source.
1. An improved voltage multiplying circuit comprising,
2. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor is a self-healing impregnated capacitor which is impregnated with a high voltage impregnant.
3. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The invention relates in general to Cockcroft-Walton cascade circuits for voltage multiplication and more particularly to such circuits with a pumping circuit and a storage circuit composed of capacitors connected in series, said pumping circuits and storage circuit being linked with one another by a rectifier circuit whose rectifiers are preferably silicon rectifiers, especially for a switching arrangement sensitive to internal discharges of capacitors, and more especially a switching arrangement containing transistors, and especially an image tube switching arrangement.
Voltage multiplication cascades composed of capacitors and rectifiers are used to produce high D.C. voltages from sinusoidal or pulsed alternating voltages. All known voltage multiplication cascades and voltage multipliers are designed to be capacitance-symmetrical, i.e., all capacitors used have the same capacitance. If U for example is the maximum value of an applied alternating voltage, the input capacitor connected directly to the alternating voltage source is charged to a D.C. voltage with a value U, while all other capacitors are charged to the value of 2U. Therefore, a total voltage can be obtained from the series-connected capacitors of a capacitor array.
In voltage multipliers, internal resistance is highly significant. In order to obtain high load currents on the D.C. side, the emphasis in the prior art has been on constructing voltage multipliers with internal resistances that are as low as possible.
Internal resistance of voltage multipliers can be reduced by increasing the capacitances of the individual capacitors by equal amounts. However, the critical significance of size of the assembly in the practical application of a voltage multiplier, limits the extent to which capacitance of the individual capacitors can be increased as a practical matter.
In television sets, especially color television sets, voltage multiplication cascades are required whose internal resistance is generally 400 to 500 kOhms. Thus far, it has been possible to achieve this low internal resistance with small dimensions only by using silicon diodes as rectifiers and metallized film capacitors as the capacitors.
When silicon rectifiers are used to achieve low internal resistance, their low forward resistance produces high peak currents and therefore leads to problems involving the pulse resistance of the capacitors. Metallized film capacitors are used because of space requirements, i.e., in order to ensure that the assembly will have the smallest possible dimensions, and also for cost reasons. These film capacitors have a self-healing effect, in which the damage caused to the capacitor by partial evaporation of the metal coating around the point of puncture (pinhole), which develops as a result of internal spark-overs, is cured again. This selfhealing effect is highly desirable as far as the capacitors themselves are concerned, but is not without its disadvantages as far as the other cirucit components are concerned, especially the silicon rectifiers, the image tubes, and the components which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It is a further object of the invention to achieve multiples of the foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In accordance with the invention, the foregoing objects are met by making at least one of the capacitors in the pumping circuit, preferably including the one which is adjacent to the input voltage source, one which is less prone to internal discharges than any of the individual capacitors in the storage circuit.
The Cockcroft-Walton cascade circuit is not provided with identical capacitors. Instead, the individual capacitors are arranged according to their loads and designed in such a way that a higher pulse resistance is attained only in certain capacitors. It can be shown that the load produced by the voltage in all the capacitors in the multiplication circuit is approximately the same. But the pulse currents of the capacitors as well as their forward flow angles are different. In particular, the capacitors of the pumping circuit are subjected to very high loads in a pulsed mode. In the voltage multiplication cascade according to the invention, these capacitors are arranged so that they exhibit fewer internal discharges than the capacitors in the storage circuit.
The external dimensions of the entire assembly would be unacceptably large if one constructed the entire switching arrangement using such capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement which has no tendency toward spark-overs, consistent with satisfactory internal resistance of the voltage multiplication cascade and small dimensions of the entire assembly. This avoids the above cited disadvantages with respect to the particularly sensitive components in the rest of the circuit and makes it possible to design voltage multiplication cascades with silicon rectifiers, which are characterized by long lifetimes. Hence, a voltage multiplication cascade has been developed particularly for image tube circuits in television sets, especially color television sets, and this cascade satisfies the highest requirements in addition to having an average lifetime which in every case is greater than that of the television set.
A further aspect of the invention is that at least one of the capacitors that are less prone to internal discharges is a capacitor which is impregnated with a high-voltage impregnating substance, especially a high-voltage oil such as polybutene or silicone oil, or mixtures thereof. In contrast to capacitors made of metallized film which have not been impregnated, this allows the discharge frequency due to internal discharges or spark-overs to be reduced by a factor of 10 to 100.
According to a further important aspect of the invention, at least one of the capacitors that are less prone to internal discharges is either a foil capacitor or a self-healing capacitor. In addition, the capacitor in the pumping circuit which is adjacent to the voltage source input can be a foil capacitor which has been impregnated in the manner described above, while the next capacitor in the pumping circuit is a self-healing capacitor impregnated in the same fashion.
Other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, taken in connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to D5 connected in a cascade. An alternating voltage source UE is connected to terminals 1 and 2, said voltage source supplying for example a pulsed alternating voltage. Capacitors C1 and C2 form the pumping circuit while capacitors C3, C4 and C5 form the storage circuit.
In the steady state, capacitor C1 is charged to the maximum value of the alternating voltage UE as are the other capacitors C2 to C5. The desired high D.C. voltage UA is picked off at terminals 3 and 4, said D.C. voltage being composed of the D.C. voltages from capacitors C3 to C5. Terminal 3 and terminal 2 are connected to one pole of the alternating voltage source UE feeding the circuit, which can be at ground potential. In the circuit described here, a D.C. voltage UA can be picked off whose voltage value is approximately 3 times the maximum value of the pulsed alternating voltage UE. By using more than five capacitors, a correspondingly higher D.C. voltage can be obtained.
The individual capacitors are discharged by disconnecting D.C. voltage UA. However, they are constantly being recharged by the electrical energy supplied by the alternating voltage source UE, so that the voltage multiplier can be continuously charged on the output side.
According to the invention, in this preferred embodiment, capacitor C1 and/or C2 in the pumping circuit are designed so that they have a lower tendency toward internal discharges than any of the individual capacitors C3, C4 and C5 in the storage circuit.
It is evident that those skilled in the art, once given the benefit of the foregoing disclosure, may now make numerous other uses and modifications of, and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in, or possessed by, the apparatus and techniques herein disclosed and limited solely by the scope and spirit of the appended claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
er and lower VHF channels and for the UHF channel includes band switching circuitry for selectively coupling a plurality of power sources to the tuners in accordance with activation of a particular channel indicating group. Also, the band switching circuitry is utilized in conjunction with a channel indicating meter circuit for providing a visual indication of the channel selected in each one of the channel indicating groups.
The PHILIPS CHASSIS KM4 is an awesome and amazing example of PHILIPS ENGINEERING.
THE PHILIPS CHASSIS KM4 It's the first PHILIPS CHASSIS FOR MULTISTANDARD FEATURING PAL 625 LINE AND SECAM 819 LINES with the PHILIPS 20AX SYSTEM CRT TUBE completely based on semiconductors and further advanced with ASIC'S around almost all signal processing boards even if the chassis is mainly based around discretes semiconductors both silicium and germanium diodes and transistor.
And is first Featuring the SONG IC TUNING SEARCH SYSTEM in such kind of apparatus.
It's developed in 2 main sections boards panels:
- DEFLECTIONS LEFT SIDE (POWER SIGNALS PANEL)
- SIGNAL RIGHT SIDE (SMALL SIGNALS PANEL)
- MIDDLE BOTTOM POWER SUPPLY UNIT.
- ABOVE ADDITIONAL FRAME DEFLECTION UNIT.
The chassis CTV KM4 is higly sophisticated and complex but it has an unique fashinating structure and design which expands his technology in a way of simplicity which is today, long time, lost and forgotten (forever).
tor having a low internal impedance. In order to increase this impedance a mainly inductive impedance is connected in series with the generator. In a picture tube employing at least two electron beams the series impedance may include the convergence circuit. As a result the convergence in the corners of the picture screen is also improved. The linearity control circuit may likewise form part of the series impedance.
1. A deflection circuit for a cathode ray tube comprising a transistor horizontal deflection generator; a horizontal deflection coil parallel coupled to said generator; means for pincushion correction of said tube comprising a saturable reactor having a control winding adapted to receive a vertical deflection signal and a power winding parallel coupled to at least a portion of said deflection coil; and means for increasing the effectiveness of said correction means comprising an impedance element external to said generator having a substantially inductive reactance series coupled between said generator and said coil. 2. A circuit as claimed in claim 1 wherein said generator comprises a transformer having a tap and said power winding has a first end coupled to said coil and a second end coupled to said tap. 3. A circuit as claimed in claim 1 wherein said impedance element comprises means for controlling the linearity of the beam deflection. 4. A deflection circuit for a cathode ray tube having at least two electron beams comprising a transistor horizontal deflection generator; a horizontal deflection coil parallel coupled to said generator; means for pincushion correction of said tube comprising a saturable reactor having a control winding adapted to receive a vertical deflection signal and a power winding parallel coupled to at least a portion of said deflection coil; means for increasing the effectiveness of said correction means comprising an Impedance element external to said generator having a substantially inductive reactance series coupled between said generator and said coil; and means for dynamically converging said beams comprising a convergence circuit coupled to said horizontal generator and to said transductor. 5. A circuit as claimed in claim 4 wherein said generator comprises a transformer having a tap and said power winding has a first end coupled to said coil and a second end coupled to said tap. 6. A circuit as claimed in claim 4 wherein said impedance element comprises means for controlling the linearity of the beam deflection. 
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG. 
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t . 
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 . 
nned in a reasonable length of time (let us say, the UHF band in one minute) band-scanning speed needs to be fairly high. Consequently, if the user is not quick enough in sending out the search-stop control signal, it is more than likely that the control will be sent when the required television channel has been overshot. If, by chance, there are two channels close to one another, the searching device may even stop on the second of the two, thus confusing the user who will not know which of the two channels he has tuned into.
The aim of the present invention is to provide a tuning device to overcome these problems.
With this aim in view, the present invention provides a television tuning device comprising a circuit for continuously scanning at least one band of receivable frequencies, manual control means for starting and stopping the said scanning procedure, a terminal for applying a switch signal for switching from a first band-scanning speed to a second band-scanning speed lower than the first, and detection means for detecting the presence of a television channel by comparing the received sync signals with local signals generated in the television receiver, and applying a switch signal to the said terminal for switching from the said first scanning speed to the said second scanning speed in the presence of the said switch signal, so that the band scanning continues at said lower speed until the manual control means produce the stopping scanning procedure.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 shows a block and circuit diagram of an exemplary television tuning device according to the invention; and
FIG. 2 shows the internal structure of exemplary integrated circuits used in the diagram of FIG. 1.
In the diagram, an input terminal receives an input signal from a freque
rnal crystal coupled to pins 2 and 3. A pair of cascaded divide-by-two flip-flops provide the proper clock signal at pin 4. A D-type flip-flop, which provides waveform shaping, is coupled to pin 4, and has both Q and Q output signals applied to pins 13 and 14 respectively. Two additional cascaded divide-by-two flip-flops are coupled to the Q output of the D-type flipflop and provide buffered output signals on pins 6 and 9 for driving a LED display (not shown). Two keyboard scanning output signals are provided at pins 5 and 10 which are in synchronization with the LED output signals at pins 6 and 9 but are narrowed and delayed to avoid edge coincidence glitches.
The station memory is Texas Instrument integrated circuit of the type Ser. No. 76,720 which receives the clock signal at its pin 9 and applies it to 12 bit synchronous counter. Pins 15 to 18 and 1 correspond to the input terminal 21 of the present invention and are intended to carry a five bit code identifying the manually selected channel. The signals are applied to 5 to 20 line decoder which in turn applies signals to a 12 bit tuning voltage RAM. The pins 10 and 11 are the up and down frequency scanning controls shown in FIG. 1 and the VHF/UHF pin 13 is also scanning speed controlled. The scanning is effected by transferring the data of the prevailing channel into the transparent counter and modifying this data under the control of the tuning program generator, the counter being clocked up or down at rate determined by the tuning timer and the countdown frequency select circuit. When one or the other buttons connected to the pins 10 and 11 is depressed, the count is incremented initially at a slower rate, the rate increasing gradually until it reaches a miximum level determined by the signal applied to pin 13.
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