The tuning circuits has a large knob potentiometers tuning system which use voltage controlled capacitances such as varactor diodes as the frequency determining elements.
Therefore a stable AFC circuit is developed:
A superheterodyne receiver having an automatic intermediate frequency control circuit with means to prevent the faulty regulation thereof. The receiver has means for receiving a radio frequency signal and mixing the same with the output of a superheterodyne oscillator. This produces an intermediate frequency signal which is coupled to a frequency or phase discriminator to produce an error signal for controlling the frequency of the superheterodyne oscillator. A regulation circuit is provided having an electronic switch to interrupt the feedback circuit when only unwanted frequencies tend to produce faulty regulation of the superheterodyne oscillator.
TDA3190 TV SOUND CHANNEL (sgs)
The TDA3190 is a monolithic integrated circuit in a
16-lead dual in-line plastic package. It performs all
the functions needed for the TV sound channel :
.IF LIMITER AMPLIFIER .ACTIVE LOW-PASS FILTER
.AF PREAMPLIFIER .AF OUTPUT STAGE
The TDA3190 can give an output power of 4.2 W
(d = 10 %) into a 16 W load at VS = 24 V, or 1.5 W
(d = 10 %) into an 8 W load at VS = 12 V. This
performance, togetherwith the FM-IF section characteristics
of high sensitivity, highAM rejection and
low distortion, enables the device to be used in
almost every type of television receivers.
The device has no irradiation problems, hence no
external screening is needed.
The TDA3190 is a pin to pin replacement of
The electrical characteristics of the TDA3190 remain
almost constant over the frequencyrange 4.5
to 6 MHz, therefore it can be used in all television
standards (FM mod.). The TDA3190 has a high
input impedance,so it can work with a ceramic filter
or with a tuned circuit that provide the necessary
The value of the resistors connected to pin 9,
determine the AC gain of the audio frequency amplifier.
This enables the desired gain to be selected
in relation to the frequency deviation at which the
output stage of the AF amplifier, must enter into
Capacitor C8, connected between pins 10 and 11,
determines the upper cutoff frequency of the audio
bandwidth.To increase the bandwidth
the values of C8 and C7 must be reduced, keeping the ratio
C7/C8 as shown in the table of fig. 16.
The capacitor connected between pin 16 and
ground, together with the internal resistor of 10 KW
forms the de-emphasis network. The Boucherot
cell eliminates the high frequency oscillations
caused by the inductiveload and thewires connecting
Power supply is realized with mains transformer and Linear transistorized power supply stabilizer, A DC power supply apparatus includes a rectifier circuit which rectifies an input commercial AC voltage. The rectifier output voltage is smoothed in a smoothing capacitor. Voltage stabilization is provided in the stabilizing circuits by the use of Zener diode circuits to provide biasing to control the collector-emitter paths of respective transistors.A linear regulator circuit according to an embodiment of the present invention has an input node receiving an unregulated voltage and an output node providing a regulated voltage. The linear regulator circuit includes a voltage regulator, a bias circuit, and a current control device.
The bias circuit may include a bias device and a current source. The bias device has a first terminal coupled to the output terminal of the voltage regulator and a second terminal coupled to the control electrode of the current control device. The current source has an input coupled to the first current electrode of the current control device and an output coupled to the second terminal of the bias device. A capacitor may be coupled between the first and second terminals of the bias device.
In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
A circuit is disclosed for improving operation of a linear regulator, having an input terminal, an output terminal, and a reference terminal. The circuit includes an input node, a transistor, a bias circuit, and first and second capacitors. The transistor has a first current electrode coupled to the input node, a second current electrode for coupling to the input terminal of the linear regulator, and a control electrode. The bias circuit has a first terminal for coupling to the output terminal of the linear regulator and a second terminal coupled to the control electrode of the transistor. The first capacitor is for coupling between the input and reference terminals of the linear regulator, and the second capacitor is for coupling between the output and reference terminals of the linear regulator. The bias circuit develops a voltage sufficient to drive the control terminal of the transistor and to operate the linear regulator. The bias circuit may be a battery, a bias device and a current source, a floating power supply, a charge pump, or any combination thereof. The transistor may be implemented as a BJT or FET or any other suitable current controlled device.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3.
nd the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means. 6. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means, comprising a control circuit connected between said vertical output circuit and said vertical oscillator circuit for varying the width of each pulse produced by the vertical oscillator circuit in response to a DC control signal having a value corresponding to the width of the pulse component applied to the vertical deflection coil of the vertical output circuit for controlling the pulse width of the output of said vertical oscillator circuit and thereby the pulse width of said pulse component.
TDA1180P TV HORIZONTAL PROCESSOR:
The TDA1180P is a horizontal processor circuit for
b.w. and colour monitors. It is a monolithic inte-
grated circuit encapsulated in 16-lead dual in-line
INOISE GATED HORIZONTAL SYNC SEPARA-
INOISE GATED VERTICAL SYNC SEPARATOR
QUENCY RANGE LIMITER
IPHASE COMPARATOR BETWEEN SYNC
PULSES AND OSCILLATOR PULSES (PLL)
IPHASE COMPARATOR BETWEEN FLYBACK
PULSES AND OSCILLATOR PULSES (PLL)
ILOOP GAIN AND TIME CONSTANT SWITCH-
ING ( VCR)
ICOMPOSITE BLANKING AND KEY PULSE
IOUTPUT STAGES WITH HIGH CURRENT CA-
Pin 1 - Positive supply
The operating supply voltage of the device ranges
from 10V to 13.2V
Pin 2 and 3 - Output
The outputs of TDA1180P are suitable for driving
transistor output stages, they deliver positive pulse
at Pin 3 and negative pulse at Pin 2.
The negative pulse is used for direct driving of the
output stage, while positive pulse is useful when a
driver stage is required.
The rise and fall times of the output pulses are
about 150 ns so that interference due to radiation
Furthermore the output stages are internally pro-
tected against short circuit.
Pin 4 - Protection circuit input
By connecting Pin 4 of the IC to earth the output
pulses at Pin 2 and 3 are shut off ; this function has
been introduced to produced to protect the final
stages from overloads.
The same pulses are also shut off when the supply
voltage falls below 4V.
Pin 5 - Phase shifter filter
To compensate for the delay introduced by the line
final stages, the flyback pulses to Pin 6 and the
oscillator waveform are compared in the oscillator-
flyback pulse phase comparator.
The result of the comparison is a control current
which, after it has been filtered by the external
capacitor connected to Pin 5, is sent to a phase
shifter which adequately regulates the phase of the
The maximum phase shift allowed is: td = tp - tf
where tf is the flyback pulse duration.
Pin 5 has high input and output resistance (current
Pin 6 - Flyback input
The flyback pulse drives the high impedance input
through a resistor in order to limit the input current
to suitable maximum values.
The flyback input pulses are processed by a double
threshold circuit; this generates the blanking pulses
by sensing low level flyback voltage and the pulses
to drive the phase comparator by sensing high level
flyback voltage, therefore phase jitter caused by
ringing normally associated with the flyback pulse,
Pin 7 - Key and blanking pulse output
The key pulse for taking out the burst from the
chrominance signal is generated from the oscillator
ramp and has therefore a fixed phase position with
respect to the sync.
The key pulse is then added internally to the blank-
ing pulse obtained by correctly forming the flyback
pulse present at Pin 6.
The sum of the two signals (sandcastle pulse) is
available on low impedance at output Pin 7.
Pin 8 and 9 - Sync separators inputs
The video signal is applied by means of two distinct
biasing networks to pins 8 and 9 of the IC and
therefore to the respective vertical and horizontal
The latter take the sync pulses out of the video
signal and make them available to the rest of the
circuit for further processing.
Pin 10 - Vertical sync output
The vertical sync pulse, obtained by internal inte-
gration of the synchronizing signal, is available at
The output impedance is typically 10kΩ and the
lowest amplitude without load is 11V.
Pin 11 - Coincidence detector
From the oscillator waveform a gate pulse 7 µs
wide is taken whose phase position is centered on
the horizontal synchronism.
The gate pulse not only controls a logic block which
permits the sync to reach the oscillator-sync phase
comparator only for as long as its duration, but also
allows the latching and de-latching conditions of
the oscillator to be established.This function is
obtained by a coincidence detector which com-
pares the phase of the gate pulses with that of the
When the two signals are not accurately aligned in
time it means that the oscillator is not synchronized.
In this case the detector acts on the logic block to
eliminate its filtering effect and on the time constant
switching block to establish a high impedance on
Pin 12 (small time constant of low-pass filter).
This latter block also acts on the oscillator-sync
phase detector to increase its sensitivity and with it
the loop gain of the synchronizing system.
In this conditions the phase lock has low noise
immunity (wide equivalent noise bandwidth) and
rapid pull-in time which allows fairly short synchro-
Once locking has taken place the coincidence de-
tector enables the logic block, causes a low imped-
ance on Pin 12 and reduces the sensitivity of the
In these conditions the phase lock has high noise
immunity ( narrow equivalent noise bandwidth) due
to the complete elimination of interference which
occurs during the scanning period and the greater
inertia with which the oscillator can change its
To optimize the behaviour of the IC if a video
recorder is used, the state of the detector can be
forced by connecting Pin 11 to earth or to + VS. The
characteristics of the phase lock thus correspond
to the lack of synchronization.
Pin 12 - Time constant switch, (see Pin 11)
Pin 13 - Control current output
The oscillator is synchronized by comparing the
phase of its waveform with that of the sync pulses
in the oscillator-sync phase comparator and send-
ing its output current I13 (proportional to the phase
difference between the two signals) to Pin 15 of the
oscillator after it has been filtered properly with an
external low-pass circuit.
The time constant of the filter can be switched
between two values according to the impedance
presented by Pin 12.
The voltage limiter at the output of the phase
comparator limits the voltage excursion on Pin 13
and therefore the frequency range in which the
oscillator remains held-in.
The output resistance of Pin 13 is:
G low when V13 > 4.3 or V13 < 1.6V
G high when 1.6V < V13 < 4.3V
To prevent the vertical sync from reaching the
oscillator-sync phase comparator along with the
horizontal sync,a signal which inhibits the phase
detector during the vertical interval is taken from
the vertical output stage; inhibition remain even if
the video signal is not present.
The free running frequenc of the oscillator is deter-
mined by the values of the capacitor and of the
resistor connected to Pins 14 and 15 respectively.
To generate the line frequency output pulses, two
theresholds are fixed along the fall ramp of the
triangular waveform of the oscillator.
Pin14 - Oscillator (see Pin 13)
Pin 15 - Oscillator control current input (see
Pin 16 - Ground.