SALORA 17L61 CHASSIS L INTERNAL VIEW.

SALORA CHASSIS L  is A monocarrier chassis contains all functions of the receiver.

Most important and interesting part is the power supply and line deflection output + EHT part.

It combines power supply and line deflection in one special transformer.

This circuit is called IPSALO (Integrated Power Supply Salora) and is delveloped around a sophisticated hybrid IC SALORA LF0059.


The Salora K and L chassis employ the Ipsalo-3 power supply/line deflection circuit. Its features include the use of a single chopper transistor and yet another hybrid chopper control chip, this time type SALORA LF0059. The chassis themselves are very different in physical appearance, though the circuits are similar. The K is an upright, hinge -back type that's akin to the H and J chassis. It's used in sets fitted with 20, 21, 22, 24, 26 and 28in. tubes - from the sizes you'll note that some are "traditional" while others are FS tubes. The L is a horizontal, slide - out chassis which, in addition to the larger screen sizes, is also used in 14 and 15in. models. Both chassis are found under other guises, such as Hitachi, Granada, Finlandia and Luxor. Many of them are thus used as rental sets.

The Ipsalo-3 Circuit:

Fig. 1 shows the Ipsalo-3 circuit used in the K chassis. We'll provide a brief run-down on the circuit operation, starting with the action of the start-up circuit. The mains input is rectified by the bridge rectifier DB701-4 whose reservoir capacitor is CB707. Surge limiting is provided by RB702 and filtering by RB703/ CB708. A d.c. supply of some 300V is thus present across CB708. As with the previous chassis a diac, DTB705 in this circuit, is used to get things going. CB711 charges from the 300V line via RB704, and when the voltage across it reaches approximately 30V the BR100 diac fires. The pulse produced in this way at the base of the BU508 chopper transistor TB701 switches it on. DTB705's conduction rapidly discharges CB711: when the voltage across it drops to about 22V the diac switches off, removing TB701's base drive. At this point the current flowing through the primary winding (pins 1-2) of the Ipsalo transformer MB600 reverses. The voltage developed across the secondary winding 17-18 brings rectifier diode DB603 into conduction, charging CB604. Meanwhile CB711 charges again and the cycle repeats. Thus the voltages across CB604 and CB621/2 gradually build up. The PHILIPS TDA2579 timebase generator/sync chip ICB500 requires a switch -on supply at pin 16. During normal operation it's powered by a 12V supply at pin 10. As the voltage across CB621/2 builds up, a point is reached at which the voltage at pin 16 of ICB500 is sufficient for the line oscillator to start up. The set will now come into operation. The line -frequency pulses produced at pin 11 of the PHILIPS TDA2579 chip are fed to the line driver transistor TB502 and to pin 13 of the hybrid chopper control chip HB600, which now takes over the provision of drive for the chopper transistor. Once normal operation has been established, DB706 and RB705 ensure that the voltage across CB711 never reaches the level at which DTB705 will fire. During normal operation HB600 provides a pulse - width modulated drive to the chopper transistor to regulate the supplies derived from the Ipsalo transfor- mer. HB600 also incorporates overload protection cir- cuitry. The LF0059 has twenty pins and the usual green and white appearance. 'It's driven by 2V peak -to -peak line -frequency pulses at pin 13. For regulation, the voltage developed at pin 14 of the Ipsalo transformer by the action of the line output stage is sensed at either pin 5 (90° tubes) or pin 6 (110° tubes). If an overload results in the voltage at pins 8 and 16 rising to 9.5V the protection circuit in HB600 operates and the set trips. In the standby mode the control circuitry increases the voltage at pin 7 of HB600 from OV to 5V. As a result of the action of the internal circuitry the chopper is switched on when the negative -going edge of the line pulse at pin 13 occurs. Thus the chopper and the line output transistors are on at the same time. The latter continues to conduct until energy has been drained from the secondary windings of the Ipsalo transformer. The close -coupled windings 17-18 and 19-20 continue to develop sufficient voltage however to keep the chopper circuit, the line oscillator and the remote control circuitry in operation, so that the set can be brought back from the standby mode. In the K and large -screen L chassis the e.h.t. is derived from a diode -split winding on the Ipsalo transformer. With small -screen L chassis sets a tripler is used. K and L Chassis Compared The Ipsalo-3 circuit is the heart of these sets and is common to the K and L chassis. There are considerable variations in the rest of the circuitry however, and several different control systems are used. We will consider these latter arrangements in a subsequent instalment, when we give details of the enabling proce- dures, which again vary with the different versions of these chassis. The timebase and signal circuits used in the K chassis are fairly conventional. There's a definite resemblance to the J chassis in fact. The colour decoder for example is based on the use of a TDA3562A chip (ICB200), and the notes on this device on pages 103-4 of the December issue apply here as well. The line and field timebase generators and sync circuitry are in a PHILIPS TDA2579 chip (ICB500) as previously mentioned. A PHILIPS TDA3654 (ICB501) is used as the field output device. A parallel system is used for the vision and sound i.f. signals. The i.f. bandpass setting SAWF has two outputs, the sound i.f. going to a PHILIPS TDA2545A chip while the vision i.f. output goes to a PHILIPS TDA2549. There are several options available as plug-in PCBs with this chassis. Thus there appear to be several unused connectors and you may find yourself going in all directions if you try tracing the print connections. The options include teletext, a stereo sound decoder, a satellite TV decoder, SECAM and NTSC decoders and an f.m. tuner for radio reception. A pair of TDA2030 chips (ICE1/2) is used in sets with stereo sound facilities, with processing (tone and balance control etc.) carried out within a PHILIPS TDA1524A chip (ICE3). Non -stereo versions have a single TDA2030. The 6MHz f.m. output from the previously mentioned PHILIPS TDA2545A sound i.f. chip is fed to a TBA120T intercarrier sound chip on the audio module. The arrangements used in the L chassis are somewhat simpler. This is mainly due to the use of a TDA4505 chip that includes the i.f. signal processing and also incorpo- rates the sync circuits and timebase generators. The  colour decoder is a MOTOROLA TDA3301. Once again a PHILIPS TDA3654 is used for field deflection.


 Basic K Chassis Faults List:

 To round off this initial instalment on these chassis, here's a brief faults list covering common problems with the basic K chassis. Faults relevant to the Ipsalo-3 circuit also apply to the L chassis (but note that the circuit reference numbers differ with the small -screen version). (1) No go. On several occasions we've found the chopper transistor TB701 to be short-circuit and the filter resistor RB703 open -circuit. DB707, which is in parallel with TB701, is usually also short-circuit. (2) Set does not start initially but if left switched on will start after a time ranging from half a minute to several minutes. You will usually find that the 1,000µF 8.5V supply reservoir capacitor CB604 is open -circuit or leaky. We try to fit a replacement rated at 25V if the physical size permits in a particular set. CB601 which is in parallel with CB604 can also cause this problem. Several different values have been used in this position. We find that the higher value 1/LF improves starting and cures any problems here. It's not unusual to have to replace both these capacitors for a no start condition. (3) No sound, no picture but two bars present on the display. Monitor pin 11 of the PHILIPS TDA2579 timebase chip ICB500. You will find that line -frequency pulses begin to appear then, shortly after switch -on, stop. The cause is that the BC557 transistor TB541 in the switch -on line is short-circuit. (4) Noise and "splashes" on the picture. Suspect CB101 (22nF) which decouples pin 4 (tuning voltage) of the tuner unit. (5) Height and/or width twitch up/down or in/out. First check whether the height control RTB543 and/or the line phase control RTB542 is noisy. Usually however the SALORA LF0059 chopper control chip HB600 is faulty. You may, if you don't hold this device in stock, be able to monitor its output with a scope: usually however the fault is not regular enough for this. (6) No sound or vision. On several occasions the PHILIPS TDA2579 chip ICB500 has been faulty. This chip can also sometimes load down the 12V rail with the result that the set trips. (7) Intermittent no picture or sound with the channel display pulsing. This can occur with sets that incorporate teletext. Remove the teletext panel to confirm that the fault has cleared. If so the fault is due to misoperation of the crystal oscillator on this panel. Replace all associated components - the crystal, transistor, capacitors, etc. Then recheck. If the fault is still present suspect the ITT DPU2540 chip.

The video section is developed with Motorola TDA3301 TV COLOR PROCESSOR

I.F. and synchronization with TDA4505E Small Signal combination IC for colour TV

Control and tuning search functions are developed around the ITT SAA1293 Tuning Voltage Processor for Analog TV-Set.


SALORA 17L61 CHASSIS L - VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)


TDA3300 3301 TV COLOR PROCESSOR
The Decoder IC The centre -piece of the decoder is the Motorola TDA3300B i.c. which carries out all the luminance and U V Inputs from PAL delay line 9V Frequency nlyv Z 2RV2 100k chroma signal processing required. Features of this 40 -pin chip include: (1) Automatic black -current control via feedback from the RGB output circuits. (2) Peak beam current limiting to prevent blooming on highlights - in addition to the normal beam current limit- ing action. (3) Separate R, G and B input pins for the injection of teletext/data signals (or on -screen display of the channel number with frequency synthesis tuning). These signals can be varied by means of the user brightness and con- trast controls. (4) Low dissipation - about 600mW. (5) By adding a small adaptor panel with a TDA3030A SECAM-to-PAL converter i.c. during production the receiver is given multistandard (PAL, SECAM and NTSC-4.43) capability.

A block diagram of the TDA3300B i.c. is shown in Fig. 3. As with the better known TDA3560 single -chip decoder, both the chroma and the burst pass through the chroma delay line. The U output from this enters the TDA3300B at pin 8, passing to the U detector and to the burst detector. The latter is part of a phase -locked loop, the detector's output being applied via an H/2 (half-line frequency) switch to the 4.43MHz voltage -controlled crystal oscillator. The 4.43MHz reference oscillator's output is applied for PAL switching, and to the U detector via a voltage -controlled 90° phase shifter. This shifter is under the control of the 90° detec- tor which compares its output with the oscillator's output coming via the PAL switch: when the phase shift is cor- rect, the output from the 90° phase detector is zero. The combined effect of the two H/2 switches in the reference oscillator control loop - the two shown on the right-hand side - cancels phase detector offsets. The outputs from the U and V detectors include burst "flag" pulses which are used for a.c.c., ident and colour -killing - there are two colour -killing actions. RGB Output Stages The RGB output stages are of the class AB type and incorporate extra circuitry for c.r.t. black -current sampl- ing and beam limiting. Fig. 4 shows the red output stage. Under most conditions transistor 2TR1 acts as a class A amplifier, driving the tube's cathode via 2D5 and 2TR7. A high -value collector load resistor (2R33) is used to reduce the dissipation in 2TR1. The stage gain is set by the ratio of 2R40 and 2R36 to 2R25 and 2RV3, the latter setting the drive level. For good transient response it's necessary for the tube/base capacitance to be rapidly charged/discharged in accordance with the signal swings. There is no problem when 2TR1 is being driven from off to on, since the capacitance is discharged rapidly via 2D5 and 2TR1. When 2TR1 is driven from on to off however 2D5 will become reverse biased. Under these conditions 2TR4 acts as an emitter -follower so that the capacitance charges rapidly. Black -level stability is critical for good results. As we've 2R46 5k6 2R51 120k 2TR7 BF493S 2C43l Sampling circuit L -J 1k5 Field blanking J Red cathode _Tube input T"and base 810capacitance nlrr Reference Line pedestal blanking Sample -and - hold amplifier-ws switched on rt- Video Urn seen, the TDA3300B chip incorporates circuitry for automatic black -current correction. Making use of this reduces service calls and ensures constant performance despite tube ageing or circuit misadjustment. Feedback is required, and this is provided by the sampling circuit shown in the box with the broken outline. Transistor 2TR7 acts as an emitter -follower between the video output stage and the c.r.t.'s cathode. It's a low leakage type, the components 2C40, 2D10 and 2C43 ensuring that the circuit has negligible effect on the video signal. Since the beam current flows via 2R51, a voltage proportional to the beam current is produced across this resistor. It's fed into the TDA3300B at pin 22. Black -current Control For automatic black -current control the important thing is the small beam current that flows when the tube is biased just above cut off. To enable this current to be sampled, the TDA3300B replaces the video signal with a fixed reference pedestal voltage for a couple of lines at the end of each field blanking period (this pedestal can be seen as a grey line at the top of the picture if the height control's setting is reduced). The sample voltage at pin 22 of the i.c. is fed to one input of a sample -and -hold amp- lifier which is switched on to sample the input for one line only of the reference pedestal period. 2C33 acts as the black -current control reservoir capacitor, holding the charge acquired during the sampling time for the whole field period. This charge is added to the video signal within the i.c., thus maintaining the correct red gun black current. It's interesting to notice that when a set is switched on from cold there's a momentary screen bright -up with flyback lines as the beam current begins to flow. This is because it takes several fields for 2C33 (and the corre- sponding capacitors in the green and blue channels) to charge fully. Since the voltage continuously available across 2R51 is proportional to beam current, it's used within the i.c. for peak beam current limiting during the active line periods. This is in addition to beam current limiting via the con- trast control - and a crowbar trip that operates should the beam current exceed 3mA.

This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).

Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.

The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.

It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.


90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.

ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.

The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.

4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.

Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.

Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.

SALORA 17L61 CHASSIS L Regulated power supply device for a line sweep circuit in a television receiver:
1. A regulated power supply device, in particular for a line sweep circuit in a television receiver, whose output stage (30) contains a first electronic switch of the bidirectional type (36, 35), controlled periodically so as to be closed during the forward sweep and open during the fly-back, connected in parallel with a first series assembly containing line deviation coils (31) and a first capacitor (32), called the forward capacitor, which feeds these coils (31) during the closing of the first switch (36, 35), with a second capacitor (34), called the return capacitor, which forms a parallel resonant circuit with the inductance in particular of the coils (31) during the opening of the first switch (36, 35) and with a second series assembly containing a first winding (22) of a transformer (20), called the line transformer, and a third capacitor (33), called the power supply capacitor, which feeds the first winding (22) with D.C. voltage while the first switch (36, 35) is closed, the power supply device containing a chopper circuit (10) connected between the terminals (6, 7) of a D.C. power supply voltage source (5) and containing an inductor, called the chopper inductor, (16) and a second electronic switch (15), which is controlled, mounted in series, this second switch (15) containing a chopper transistor (11) controlled on its base by means of a recurring control signal, which is produced by means of the line return pulses picked up on a secondary winding (25) of the line transformer (20), in order to be alternately conducting and cut off during each line period, this chopper inductor (16) containing a second winding (21), called the power supply winding, of this transformer (20), which is intended for the transfer of energy between the chopper circuit (10) and the line sweep output stage (30), and being characterized by the fact that, the second switch (15) being also of the bidirectional type and containing, apart from the chopper transistor (11), which is operating in the saturated and cut off mode, a diode (12) mounted in parallel and in opposition with this transistor, the chopper circuit (10) contains also a fourth capacitor (13), called the turning capacitor, which forms a resonant circuit with the chopper inductor (16) during the opening periods of the second switch (15) which works with a constant cyclic ratio, the periods being obtained by means of a control signal which causes the cutting off of the chopper transistor (11) and their lengths being constant and greater than a half period of resonance of this resonant circuit (13, 16) whose length may reach about a half of a line period, and by the fact that the regulation of the energy exchanged between the chopper circuit (10) and the output stage (30) is obtained by the variation of the delay between the respective opening instants of the first (36, 35) and second (15) switches.

2. A power supply device as in claim 1, characterized by the fact that the transistor (11) in the second switch (15) is controlled by means of a regulation circuit (40) fed by an auxiliary winding (25) of the transformer (20) which supplies it with a signal one of whose peak amplitudes is proportional to the voltage at the terminals of the power supply capacitor (33) in the output stage (30), which is recharged by means of the chopper circuit (10), and whose peak to peak amplitude is proportional to a very high voltage supplied by another winding (23) of transformer (20), the regulation circuit (40) causing the delay in the instant of cut off of transistor (11) to vary with respect to the leading edge of the line return pulse produced by the opening of the first switch (36, 35).

3. A power supply device as in claim 2, characterized by the fact that the regulation by the phase shift between the respective cut off instants is obtained as a function either of the peak to peak amplitude or of the peak amplitude during the fly back or forward sweep of the signal at the terminals of one of the windings (21 or 25) of line transformer (20) by comparing this amplitude to a reference voltage and by controlling the delay as a function of the difference between the voltage corresponding to one of these amplitudes and the reference voltage, in order to stabilize either the sweep amplitude or the power supply voltage obtained by rectifying the line return pulse.
4. A power supply device as in claim 2, characterized by the fact that the regulation circuit (40) contains an unstable multivibrator (48) whose output is coupled to the base of chopper transistor (11) by means of a control stage (50) and which operates independantly on starting up, a circuit generating a variable delay which contains a phase shift stage (46) triggered by the line return pulses and supplying to the multivibrator (48) triggering pulses which are delayed with respect to the leading edges of the line return pulses, which cause the cutting off of chopper transistor (11), and a regulator stage (47), which supplies the phase shift stage (46) with a regulation signal that makes it possible to vary the delay between the respective leading edges of the line return pulses and the triggering pulses as a function of one of the peak amplitudes or of the peak to peak amplitude of the signal supplied by the auxiliary winding (25) of the transformer (20).

5. A power supply device as in claim 4, of the type in which the power supply capacitor (33) feeds a D.C. voltage to the whole line sweep circuit, characterized by the fact that the regulation circuit (40) is fed by means of an independant power supply circuit (51) which enables the chopper circuit (10) to be started up by the independant operation of the unstable multivibrator (48) in order to start up the power supply of the line sweep circuit with the chopper voltage induced in the first winding (22) of the transformer (20) and rectified by the diode (35) which is part of the first bidirectional switch (36, 35) which charges the power supply capacitor (33).

6. A power supply device as in one of claims 4 and 5, characterized by the fact that the phase shift stage (46) contains a delay generator which supplies a voltage, in the shape of recurrent saw teeth (460, 463) which are triggered by the leading edges of the line return pulses, to an analog voltage comparator stage (469, 4600, 4601), which supplies at its output negative pulses to the base of the transistor (483) in multivibrator (48) whose cutting off controls the cut off of chopper transistor (11) at instants at which the instantaneous saw tooth amplitude exceeds a fixed threshold voltage (VZ 4601), and by the fact that the regulator stage (47) contains an assembly (470, 471) rectifying the signal supplied by the auxiliary winding (25) which feeds a signal generator (476, 475) supplying a signal which modifies, from a predetermined threshold, the saw tooth slope as a function of one of the peak amplitudes or peak to peak amplitudes of this signal (v25).

7. A power supply device as in claim 6, of the type in which the free running operating frequency of the unstable multivibrator (48) is less than the line frequency, characterized by the fact that the unstable multivibrator (48) is controlled solely by the negative pulses coming from the comparator stage (469), which are applied to one (483) of the transistors in the multivibrator (48), whose cut off controls that of chopper transistor (11).

8. A power supply device as in one of claims 4 to 6, of the type in which the free running operating frequency of the unstable multivibrator (48) is greater than the line frequency in order to limit the peak voltage (V19max) on the collector of the chopper transistor (11), characterized by the fact that the transistor (480) in the multivibrator (48), whose state is complementary to that of the chopper transistor (11), is fed on its base through a diode (4803) by a synchronizing stage (49), which supplies negative pulses whose amplitude is equal to a predetermined fraction of that of the line return pulses, in order to lengthen the cut off state of this transistor (480) until the sum of these lengths is equal to the line period.

Description:

The present invention concerns a regulated power supply device, in particular for a line sweep circuit in a television receiver, which can also provide D.C. supplies to other circuits in this receiver by splitting up a D.C. supply voltage which is usually obtained by the rectification and filtering of the A.C. mains voltage by means of a chopper.

Known chopper converters of this type contain, generally connected in series between the output terminals of a D.C. power supply source (filtered rectifier), an electronic switch such as a switching transistor operating in the saturated and cut off mode and an inductor which includes the primary winding of a transformer in which at least one secondary winding supplies the A.C. energy obtained by the chopping, which is then rectified to provide the D.C. supply voltages with a ground insulated from the mains. In most of the known chopper power supplies, one can vary the output voltages by action on the cyclic ratio, i.e. the length of the saturated (closed) state of the switch, for example, by controlling periodically the transistor-chopper by means of a monostable flip-flop of variable length as a function of a voltage which may be picked up at the output of a rectifier fed by a secondary winding of the transformer so as to form a regulation loop.

Chopper power supplies have frequently been used in television receivers to eliminate the bulky and heavy mains supply transformer and make possible a regulation of the D.C. power supply voltage for this receiver. They have often been combined in particular at the output stage of the horizontal sweep circuit which supplies them with a pulse signal at the line frequency that can be used to control the chopping. Various combinations of sweep circuits and chopper power supplies have described, for example, in the French patents or patent applications with publication Nos. 2.040.217, 2.060.495, 2.167.549, 2.232.147 or 2.269.257, in which the regulation is also done by means of the variation in the cyclic ratio of the saturated and cut off states of the chopper transistor which, in some cases, is also used as the active element of the (final) output stage of the line sweep circuit or of the feeder stage which controls this circuit.
Chopper power supplies of the so called "pump" type in which the chopper transistor feeds one of the windings of the line transformer during the line return periods and in which the regulation is done by means of the variation of the internal resistance of this transistor or of a "ballast" transistor in series with this transistor are known, for example, from the French patents with publication Nos. 2.014.820, 2.025.365 or 2.116.335. A circuit of the "pump" type whose chopper transistor has a winding of the line transformer in its collector circuit and in which the sweep circuit is electrically insulated from the mains has been described in the article by Peruth and Schrenk in the German periodical, SIEMENS BAUTEILE REPORT Vol. 12 (1974), No. 4, pages 96-98. Its structure corresponds to the contents of the introduction to claim 1. In circuits of the "pump" type, the chopper transistor or the "ballast" transistor in series with it dissipates an amount of energy which is not negligable.

In the chopper device supplying power to the output stage of the line sweep circuit with which it is combined in accordance with the invention, one no longer uses regulation by variation of the internal resistance or of the length of the saturated state of the chopper transistor (or by variation of the cyclic ratio of the chopping with a constant periodicity) but one does the regulating by variation of the relative phase between the signals of the same frequency which are supplied respectively by the chopper circuit with a constant cyclic ratio and by the output stage of the line sweep, each of which is connected to one of the windings of a transformer called the line transformer through which the transfer of energy between the chopper circuit and the sweep output stage takes place as well as in the direction of the other secondary windings of the line tranformer such as the very high tension (V.H.T.) winding.

In accordance with the invention, a regulated power supply device, in particular for a line sweep circuit of a television receiver which contains an output stage fitted with a line transformer in which a first winding is connected in series with a supply capacitor, is connected in parallel with a first bidirectional switch controlled at the line frequency, the power supply device containing a chopper circuit with, connected in series between the terminals of a source of a D.C. power supply voltage, an inductor and a second electronic switch, which can also be controlled at the line frequency. The inductor in this circuit contains a second winding of the transformer which is intended for the transfer of energy between the chopper circuit and the output stage. This power supply device is in particular characterized by the fact that the second switch, which is also bidirectional and mounted in parallel with a tuning capacitor, is so controlled as to be alternately open and closed during each line period with a constant cyclic ratio and by the fact that the regulation of the power supplied and hence of the voltage at the terminals of the supply capacitor is done by variation of the phase delay between the respective opening instants of the first and second switch as a function of the peak amplitude of the line return pulse for example.

In accordance with a preferred way of making the invention, a power supply device in accordance with the preceding paragraph, in which the second bidirectional switch, which contains a switching transistor, is controlled on its base by a regulation circuit in which one input is fed by an auxiliary secondary winding of the line transformer supplying line return pulses, is remarkable in particular for the fact that the regulation circuit contains an unstable multivibrator controlling the base of the chopper transistor and operating independantly on starting up, a circuit generating a variable delay containing a phase shift stage, which is triggered by the line return pulses and supplies the multivibrator with triggering pulses that are delayed with respect to the leading edges of the line return pulses, which cause the cut off of the chopper transistor, and a regulator stage fed with the line return pulses and supplying to the phase shift stage a regulation signal which enables the delay in the triggering pulses to be varied with respect to the line return pulses as a function of one of the peak amplitudes or of the peak to peak amplitude of the line return pulses.

The invention will be better understood and others of its characteristics and advantages will appear from the description which follows, which is given as an example, and the drawings attached, which refer to it. Among them:

FIG. 1 represents part of a theoretical schematic diagram of a chopper power supply device combined with the output stage of the line sweep circuit in accordance with the invention;FIGS. 2a-2f and 3a-3f are diagrams of the voltage wave forms and/or current wave forms at various points in the circuit of FIG. 1 to explain the operation of this circuit;

FIG. 4 represents part of a synoptic schematic diagram of a simple production model (without a starter device) of regulation circuit 40 in FIG. 1;

FIG. 5 represents a block diagram of a preferred production model of regulation circuit 40 in FIG. 1 in accordance with the invention;





FIG. 6 represents a theoretical schematic diagram of the whole of the preferred production model of the regulation circuit in FIG. 5;

FIGS. 7a and 7b represent voltage wave forms illustrating the slaving of the frequency of the unstable multivibrator 48 to that of the line oscillator; and

FIGS. 8a-8c represent voltage wave forms illustrating the operation of the regulation by the variation in phase shift.

In FIG. 1 is shown schematically a chopper power supply device of line sweep output stage 30 in accordance with the invention which is electrically insulated from the A.C. mains which feed rectifier 5 whose output voltage is chopped. This power supply device has two terminals 1, 2 which are connected respectively to the two poles of the A.C. distribution mains (220 V, 50 Hz) and feed rectifier diode 3 and filter capacitor 4, whose capacity is high, which are connected in series and form together a rectifier assembly or a source of D.C. voltage 5. The output of rectifier assembly 5 formed by the two terminals 6 and 7 (plates) of the (electro-chemical) capacitor 4 is intended to supply a D.C. power supply voltage V A of the order of 300 V to chopper circuit 10. This chopper circuit 10 contains a controlled, bidirectional electronic switch 15, which consists of a switching transistor 11 of the NPN type connected with its emitter common and a junction semiconductor diode 12, which are connected in parallel in such a way as to conduct respectively in opposite directions (anti-parallel), and an inductor 16 consisting of a choke 14 and a winding 21 of a transformer 20, called a line transformer, connected in series. This winding 21 of line transformer 20 whose primary winding is normally connected in parallel with the coils of the horiziontal deviation circuit in the circuit of line sweep output stage 30 to the supply, through secondary windings, supply voltages in particular to the cathode ray tube will be called in what follows the supply voltage winding, because the transfer of energy between chopper circuit 10 and output stage 30 will be done through it. Switch 15 is mounted in parallel with a capacitor 13 and it is connected in series with inductor 16 (choke 14 and power supply winding 21 in series) between the output terminals 6 and 7 of D.C. voltage source 5. This capacitor 13 forms, because of its low capacity with respect to that of filter capacitor 4, with inductor 16 a parallel, resonant (oscillatory) circuit when electronic switch 15 is opened by the cutting off of switching transistor 11 by means of a control signal applied to its base.

Switching transistor 11 is here connected by its collector to one of the terminals of inductor 16, whose other terminal is connected to positive terminal 6 of source 5 which supplies D.C. power supply voltage V A , by its emitter to negative terminal 7 of source 5, which forms a ground, called the primary or hot ground, 8, which is connected to the A.C. mains but is insulated from that 39 of the television set. The base of transistor 11 is controlled by means of rectangular signals supplied by a regulation circuit 40, which is described further on, in such a way as to be alternately saturated and cut off. Regulation circuit 40 is, for example, fed by a secondary winding 25 of transformer 20, that supplies signals whose peak to peak amplitude is proportional to the peak amplitude of the line return pulse. This peak amplitude is a function of the energy transfer from chopper circuit 10 to the line sweep output stage 30 which is connected to another winding 22 of transformer 20.

One may note here that chopper circuit 10 resembles a classical, transistorized, line sweep output stage and that switching transistor 11 has been chosen to withstand high collector-emitter voltages (of the order of 1500 V), and that diode 12 has to withstand the same inverse voltage while switch 15 is open. One may also note that the inductance of choke 14 may be formed partly or wholly by the leakage inductance of power supply winding 21 in transformer 20.

The line sweep output stage 30, which is arranged in classical fashion, contains horizontal deviation coils 31 mounted in parallel and connected by one of their terminals to a first capacitor 32, called the "forward" or "S effect" capacitor, which feeds them during the forward sweep. The series mounting of coils 31 and forward capacitor 32 is connected in parallel, on the one hand, to a second controlled bidirectional switch containing a second switching transistor 36 and a second diode 35, called a "shunt" or "parallel" recuperation diode, which are connected in parallel to conduct in opposite directions, closed (conductor) during the forward sweep and open (cut off) during the return sweep, and, on the other hand, to a second capacitor 34, called the "return" capacitor, which forms, while the second switch is open, a parallel resonant circuit with the inductance of deviation coils 31. The common point of the collector of second transistor 36, of the NPN type, of the cathode of second diode 35 and return 34 and forward 32 capacitors is connected to one of the terminals 220 of winding 22 of transformer 20, which normally forms the primary winding of this transformer. The other terminal 221 of winding 22 is connected to one of the terminals of a third capacitor 33 of high capacity, whose other terminal is connected to the common point of deviation coils 31, return capacitor 34, the anode of second diode 35 and the emitter of second transistor 36, which is also connected to the ground 39 of the chassis of the television receiver, called the "cold" ground, because it is insulated from the A.C. power supply mains. It is at the terminals of this third capacitor 33 that one obtains the D.C. voltage feeding this stage, whose value determines, on the one hand, the peak to peak amplitude of the line sweep current of sawtooth form and, on the other hand, the amplitude of the line return voltage pulse which, when rectified after being transformed, supplies the very high voltage that polarizes the anode of the cathode ray tube (not shown here). The second transistor 36, also a switching transistor, is controlled by rectangular shaped signals supplied to input terminals 37 and 38 of stage 30, which are respectively connected to its base and its emitter, by a feed stage (not shown and called a "driver" in anglo-american literature) so that it is alternately cut off, during the sweep return, and saturated, during the second part of the forward sweep.

In classical transistor line sweep circuits, a D.C. voltage source generally feeds either terminal 221 of winding 22 directly or an intermediate connection to this winding through a diode (see French Pat. Nos. 1.298.087 dated Aug. 11, 1961, 1.316.732 dated Feb. 15, 1962 or 1.361.201 dated June 27, 1963) which isolates the primary winding of the line transformer from the D.C. voltage source during the line return interval.In the circuit of FIG. 1, it is the A.C. electrical energy transmitted by chopper circuit 10 through windings 21 and 22 of transformer 20 which charges capacitor 33 so that it supplies a regulated supply voltage to output stage 30. During the line sweep forward periods, when the second bidirectional switch 35, 36 of sweep output stage 30 is closed (conductor), the terminals of winding 22 of transformer 20 are directly connected to those of capacitor 33 which will then receive the energy supplied of by chopper circuit 10.

In FIG. 1, line transformer 20 also has a very high voltage winding 23, one terminal 230 of which may be connected to the ground 39 (or to terminal 220 of winding 22) and whose other terminal 231 is connected to the input of the very high voltage rectifier assembly or voltage multiplier (not shown) in classical fashion, and an auxiliary winding 24 which may be used to feed either a low voltage rectifier assembly or a load regulator assembly or the filament of the cathode ray tube (not shown). These secondary windings 23, 24 will receive their energy mainly from output stage 30 of the line sweep circuit through winding 22 of transformer 20, i.e. the line return pulses, the coupling between the windings will hence be as close as possible.

The operation of the power supply device in FIG. 1 will be explained below with that of output stage 30 of the line sweep circuit, with reference to FIGS. 2 and 3 of the drawing attached, representing diagrams of the voltage wave forms and/or current wave forms at various points in the schematic diagram of FIG. 1.In FIGS. 2 and 3, diagram (A) represents the saw tooth wave form of the sweep current i 31 (t) in the coils 31 of the horizontal deviation circuit. Diagram (B) represents the wave form of the voltage v 220 (t) on terminal 220 of winding 22, which is also that at the terminals of the second switch 35, 36. Diagram (C) is the wave form of the voltage v 21 (t) at the terminals of power supply winding 21 when its leakage inductance is negligable. It is obtained by the transforming of the A.C. component of voltage v 220 (t). Diagram (D) represents the wave form of the voltage v 19 (t) at the terminals of first switch 15 in chopper circuit 10, i.e. between the junction 19 of this chopper circuit with inductor 16 and primary ground 8, and diagram (E) represents as a dotted line the current i 16 (t) in inductor 16 when output stage 30 is not controlled and as a full line the current i 21 (t) resulting from the superimposition in winding 21 to current i 16 (t) on that induced by winding 22 when output stage 30 is working. Conversely, the current in winding 22 of transformer 20 results from the superimposition of the current induced by winding 21 on the current produced by the closing of the second switch 35, 36, which is analogous to i 31 (t) in diagram (A).

The wave forms of diagrams (D) and (E) in FIGS. 2 and 3 are out of phase respectively, one with respect to another, by a quarter of a line period T H /4 to allow the illustration of the regulation by the variation in the relative phase of the voltage v 21 and current i 21 waves in power supply winding 21.

The diagrams (F) represent the instantaneous energy E i transmitted by chopper circuit 10 to the output stage 30, which is equal to the product of the wave forms of current i 21 (t) and voltage v 21 (t) in winding 21, i.e. E i =-v 21 i 21 , for two different phase deviations between the voltage v 21 (t) and current i 21 (t) waves in power supply winding 21, which correspond respectively to a zero energy transfer in FIG. 2 and a maximum energy transfer in FIG. 3.

The operation of the line sweep output stage 30 is classical once the power supply capacitor 33 and forward capacitor 32 are charged to a D.C. voltage V 221 by means of a certain number of chopping cycles, which are independant on starting up, during which the negative half-cycles of the chopped voltage wave are rectified by recuperation diode 35.

During the forward sweep intervals t A , when the switch 35, 36 is closed from instant t 1 to instant t 3 , the current i 31 (see A) in the deviator varies roughly linearly between its negative peak values (at t 1 ) and positive ones (at t 3 ) with a passage through zero at instant t 2 , when current i 31 passes from diode 35 to transistor 36, which has previously been polarized to conduct. This corresponds to a roughly zero voltage v 220 (see B) at the terminals of switch 35, 36.

The line return interval t R is started by the cutting off of transistor 36 at instant t 3 , and the inductance of deviator 31 then acts as a parallel resonant circuit with the return capacitor 34 by causing the voltage v 220 (t) to pass through a positive half-sinusoid and reach its peak value at the instant t 4 (or t=0), called the line return pulse, and the current i 31 (t) to pass through a half-cosinusoid between the positive and negative peak values cited, with a passage through zero at the instant t 4 (or t=0). The mean value of the voltage wave form v 220 (t) at terminal 220 is equal to the D.C. power supply voltage V 221 at the terminals of power supply capacitor 33 and forward or S effect capacitor 32.

The respective peak to peak amplitudes of current i 31 (t) (hence the width of the screen sweep beam excursion) and of voltage v 220 (t) (hence the very high voltage) depend on the value of the D.C. voltage V 221 which feeds the horizontal sweep output stage and which, in most of the chopper power supplies of preceding techniques, is regulated and stabilized by modulating the length of the saturated state (the cyclic ratio) of chopper transistor 11 as a function of the amplitude of the line return pulse picked up on an auxiliary winding of line transformer 20 (hence of the voltage at the terminals of capacitor 33) and later of the rectified and filtered voltage in the network.

In accordance with the invention, the length t s of the saturated state of chopper transistor 11 and of the conducting state of diode 12 and, as a result, the ratio of this length to that of the complete cycle (line period T H ) or to that t B of the cut off state is constant and so chosen as to make the peak amplitude of voltage pulse v 19 , which is applied to the collector of transistor 11 during the cut off interval t B , considerably less than its collector-emitter D.C. breakdown voltage in the cut off state (V CEX ) which may exceed 1500 Volts. Thus, for a rectified voltage of 300 V, it is possible to limit the collector voltage V 19 to about 900 Volts by choosing a ratio t b /T H of about 0.5.

As a result, chopper circuit 10 must operate at the line frequency with conduction lengths t S (closed) and cut off lengths t B (open) of switch 15 preferably roughly equal (to a line half-period T H /2) and the regulation of the energy supplied to output stage 30 is done by causing the respective phases of the line return pulse v 220 (t) and the current i 21 (t) flowing through the power supply winding 21 of transformer 20 to vary as will be shown further on.

The operation of chopper circuit 10 (fed with D.C. voltage V A ) is in fact analogous to that of output stage 30, except as far as the form factor is concerned. This is determined mainly by the respective values of the inductance 16 (of choke 14 and the leakage inductance of winding 21 of transformer 20 connected in series) and of the capacity of tuning capacitor 13. The values L 16 and C 13 are chosen to obtain a half-period of oscillation slightly less than a line half-period, i.e.: ##EQU1## because the oscillation of the resonant circuit L 16 , C 13 occurs on one side and on the other of the D.C. voltage V A so that the cut off period of chopper switch 15 is greater than this half-period T D /2.

This operation of circuit 10 will first be explained with reference to diagrams D and E in FIG. 2. When, at the instant t=0, transistor 11 becomes saturated by a preliminary positive polarization of its base-emitter junction, it connects terminal 19 to ground 8 so that a current i 16 (t) (dotted on diagram E), which is increasing linearly, ##EQU2## passes through inductor 16 coming from positive terminal 6 of power supply 5.

When transistor 11 receives from regulation circuit 40 a cut off voltage at an instant preceding instant t 6 of the storage time of minority charge carries, switch 15 opens and the current stored in inductor 16, i 16 (t 6 )=V A t 6 /L=V A T H /4L, will flow through tuning capacitor 13 in oscillatory fashion, i.e. cosinusoidally, decreasing to a zero value, while voltage V 19 at junction 19 of inductor 16 and capacitor 13 will increase sinusoidally to a maximum value, these two values coinciding in time. Then, capacitor 13 discharges through inductor 16 also in oscillatory fashion until, at instant t 7 , voltage v 19 reaches a zero value, which corresponds to a minimum value, i.e. maximum negative, of current i 16 (t) whose absolute value is slightly less than the maximum positive value i 16 (t 6 ). The difference between the absolute peak values i 16 (t 6 ) and i 16 (t 7 ) is explained, on the one hand, by the ohmic losses in circuit 10 and, on the other, by the transfer of energy between this circuit and, in particular, output stage 30.

When oscillatory voltage v 19 (t) has exceeded the zero value slightly in the negative direction, diode 12 starts to conduct so as to connect terminal 19 to ground and produce in inductor 16 a current i 16 (t), which increases linearly from its maximum negative value i 16 (t 7 ) towards a zero value where transistor 11, which has already been polarized so as to be saturated, picks it up so that it reaches, at instant t 8 , its maximum positive value of instant t 6 again.

It is to be noted here that the mean value of the wave form of voltage v 19 at terminal 19 is equal to the D.C. power supply voltage V A between terminals 6 and 7 of filter capacitor 4 in rectifier assembly 5.

If one wishes to obtain an adequate energy transfer between chopper circuit 10 and line sweep output stage 30, it is advantageous to choose the value of inductor 16 in series with power supply winding 21, i.e. the sum of the leakage inductance of this winding and that of series choke 14, so that it is, for example, greater than or equal to three times the inductance L 31 of the horizontal deviation coils 31, multipled by the square of the transformation ratio between windings 22 and 21, i.e. L 16 ≥3l 31 (n 11 /n 21 ) 2 , and the value of this transformation ratio n 22 /n 21 so as to obtain at the terminals of winding 21, during the forward sweep and the closing of switch 15, an induced voltage v 21 (t) whose amplitude is between 100 and 150 Volts, i.e. between a third and a half the power supply voltage V A at terminals 6, 7 of filter capacitor 4.

As the D.C. voltage V 221 at the terminals of capacitor 33 is a function of the inductance L 31 of the horizontal deviation coils 31 and, because of this, is between 50 and about 140 Volts, the transformation ratio n 22 /n 21 , i.e. between the numbers of turns n 22 and n 21 of windings 22 and 21 respectively, is between 1 and about 4 (preferably between 2 and 3).

The choice of these parameters is only given here as an example, because the criterion of this choice is a relative separation between chopper circuit 10 and, in particular, circuit 30 which it feeds, i.e. so that current i 21 (t) in winding 21 is only induced in winding 22 with peak amplitudes which do not exceed about one third those of sweep current i 31 (t) in order not to upset the operation of sweep circuit 30 during the conduction of recuperation diode 35. Also, the voltage pulses v 19 (t) of the diagrams (D) in FIGS. 2 and 3 should not appear at the terminals of winding 21 and should not be transmitted to winding 22 at least during the opening of sweep switch 36, 35 (line return interval) to winding 22 other than with amplitudes sufficiently small not to upset the operation of output stage 30 and the very high voltage rectifier fed by winding 23, while ensuring an energy transfer sufficient to obtain a regulated power supply voltage at the value required.

Transformer 20 may therefore be made in such a way as to have looser coupling between windings 21 and 22, the self-inductance then consists of that (L 14 ) of choke coil 14 and the leakage inductance (L 21 ) of winding 21. Hence it is advantageous, when one uses a ferrite core (magnetic circuit) of rectangular shape (in the form of a frame), to place windings 22, 23 and 24 on one of the arms of this core and winding 21 and, later, winding 25 on the other. This will also help provide good insulation between the primary and secondary grounds 8 and 39. The dimension of the air gap in the magnetic circuit of transformer 20 or a magnetic shunt, which fixes the leakage inductance L 21 , and the inductance L 14 of the choke 14 are chosen with this result in view.

One may consider then that, from the point of view of the energy transfer from chopper circuit 10 to output stage 30, winding 21 is passed through by current i 21 , which consists of triangular shaped current i 16 and the current in winding 22, which is induced in saw tooth form, superimposed one on the other and that voltage v 21 , which appears at its terminals and is shown in diagrams (C) of FIGS. 2 and 3, is roughly analgous to that, v 220 , at the terminals of sweep switch 35, 36 but with a mean value of zero.

The energy transmitted by transformer 20 will then be approximately equal to the product of voltage v 21 (t) and current i 21 (t) multiplied by the cosine of the phase angle if one considers the fundamental waves at the line frequency (15.625 Hz). This is also true for each of the harmonics of the current i 21 (t) and voltage v 21 (t) waves if one develops them in a Fourier series.

The energy ceded duuring each line period T H by chopper circuit 10 output stage 30 through transformer 20 may then be written: ##EQU3## In inductor 16, as a first approximation, current i 21 (t) in a sum of an A.C. component i A (t) and a D.C. component I c and, considering that the losses of chopper circuit 10 itself are negligable, that the mean value of voltage v 21 is zero and that the D.C. component I c of i 21 does not take part in the energy transfer, one may write that the energy supplied by the D.C. source during this period E s =V A I C T H and the A.C. energy supplied by chopper circuit 10, ##EQU4## are roughly equal, i.e. ##EQU5## from which it appears that there is a mean D.C. current ##EQU6## supplied by source 5 which is a consequence of the exchange of energy between winding 21 and winding 22 in particular. The A.C. energy ceded, E H , and, as a result, the D.C. current I c of source 5, varies as a function of the cosine of the phase angle α between each of the respective harmonics of the current i 21 (t) and voltage v 21 (t). Hence one can obtain regulation by causing the phase of the wave of current i 21 (t) to vary in power supply winding 21 with respect to that of voltage v 21 (t) at its terminals to stabilize the sweep (the peak to peak amplitude of current i 31 ) and/or the very high voltage by acting on the charge supplied to capacitor 33 during each cycle.This is illustrated respectively on the diagrams (F) in FIGS. 2 and 3 showing the instantaneous power E i =-v 21 (t)i 21 (t) corresponding to two different phase angles between waves v 21 and i 21 , which indicate respectively minimum (zero) energy transfers when the zeros of current i 21 coincide with the maxima of voltage v 21 or when the respective maxima of voltages v 21 and v 19 are out of phase by a half period T H /2 and maximum energy transfers when the maxima of voltage v 21 and current i 21 coincide between circuit 10 and output stage 30.

On the diagram (F) in FIG. 2, one can see that, when there is a phase difference between the corresponding (positive) maxima of v 21 (t) and i 21 (t) of a quarter of a line period (T H /4) roughly, the energy transfer is zero, because there is equality between the surfaces bounded by the curve and the abscissa, which are respectively above and below it and give a mean value of zero as far as the energy supplied is concerned.

On the other hand, on the diagram (F) in FIG. 3 in which the product-v 21 (t)i 21 (t) corresponds to a coincidence of phase between the respective maxima of voltage v 21 and i 21 , one can see that, when one subtracts from the surfaces above the abscissa the surfaces corresponding to the shaded triangles below it, three zones remain on the positive side whose surfaces correspond to the energy which is effectively transferred whose mean value ##EQU7## is positive and shows an effective transfer of energy to output stage 30. This translates into a D.C. voltage V 33 at the terminals of capacitor 33 which forms, during the forward sweep (closing of switch 35, 36), the sole load on winding 22 (terminal 220 being connected to the ground 39).

Hence, one has shown above that, by causing the phase difference between the corresponding maxima of waves v 21 (t) and i 21 (t) to vary between 0 and T H /4, one can cause the energy transmitted to vary and, as a result, the voltage V 221 at the terminals of capacitor 33 which feeds output stage 30.

When the relative phase difference between v 21 (t) and i 21 (t) exceeds a quarter of a line period, as, for example, when the negative peak amplitude of v 21 (t) coincides with the negative peak amplitude of i 21 (t), i.e. a phase difference equal to a line half period (T H /2), the term of the energy E H becomes negative which indicates that it is output stage 30 which feeds chopper circuit 10, or, more precisely, voltage source 5 (capacitor 4). This is not permanently possible unless it is output stage 30, and hence capacitor 33, which is fed by a rectifier assembly, thus showing the reversibility of the power supply device in accordance with the invention, which is contrary to classical chopper power supplies.

Hence, the regulation is done by causing the phase of the opening of switch 15 in chopper circuit 10 to be varied by the cutting off of transistor 11 with respect to the phase of the opening of sweep switch 36, 35, which is controlled by the line oscillator (not shown) and is generally slaved in frequency and phase to the line synchronizing pulses of the video complex signal.

Such a variable phase delay is obtained from line return pulses picked up on one of the windings of transformer 20, such as winding 21 itself or, as shown in FIG. 1, auxiliary winding 25. These pulses may trigger a monostable flip-flop whose length is variable as a function of the error voltage supplied by a comparator in the form of a differential amplifier, one of whose inputs receives a voltage corresponding either to the positive amplitude of v 21 (t), which is proportional to the voltage V 33 (V 221 ) at the terminals of power supply capacitor 33 in output stage 30, or to the peak to peak amplitude of the line return pulse, which is proportional to the very high voltage, or to a combination of these two criteria. The other input of the differential amplifier receives a D.C. reference voltage, which may be adjusted, to allow the adjustment of the very high voltage and/or the horizontal sweep current amplitude.

It is to be noted here that power supply winding 21 may be connected between terminal 6 of capacitor 4 and choke 14 in two opposite directions so that the line return pulses can appear at its junction with choke 14 with opposite polarities. Two possibilities of the relative phase of voltage v 21 (t) respect to the current i 21 (t) in winding 21 result from this.

In FIG. 4, one has shown a partial block diagram (without a starting up device) of a simple way of making regulation circuit 40 which controls the cut off of transistor 11 in chopper circuit 10 with a delay which is variable with respect to the line return pulse as a function of the negative peak amplitude of the signal v 25 (t) supplied by auxiliary winding 25 of transformer 20.

Regulation circuit 40 in FIG. 4 is fed at its first input 401 with signal v 25 (t) supplied by one of the terminals 250 of auxiliary winding 25. This signal is roughly the reverse of signal v 21 (t) illustrated by the diagrams (C) respectively in FIGS. 2 and 3 in which one distinguishes, during each line period, a line return pulse of positive polarity and a negative plateau whose amplitude is proportional to D.C. voltage V 33 at the terminals of capacitor 30. This first input 401 feeds, through a first diode 410, the triggering input 411 of a first monostable flip-flop 41 of variable length, which produces at its output 413, in response to the leading edge of the return pulse, a rectangular signal whose length varies as a function of the D.C. voltage applied to its length control input 412.

Monostable flip-flops with a pulse length variable as a function of a D.C. voltage are known and a way of making them is described, for example, in French patent application No. 73.16116 made on May 4, 1973 by the present applicant.

This D.C. voltage controlling pulse length is obtained by means of a rectifier assembly 42, which is also fed by this first input 401 and contains a second diode 420 so connected as to conduct only while signal v 25 (t) is negative, a capacitor 421 in series with diode 420 which stores the negative peak values of v 25 (t), a resistive potentiometric divider assembly 422, 423 mounted in parallel with capacitor 421 and a polarity reverser 424 fed by the centre point of divider 422, 423 and supplying a positive voltage of the same level in reply to a negative input voltage, the respective terminals of capacitor 421 and divider 422, 423, which are not connected to diode 420, being connected together to primary ground 8.

The positive voltage proportional to V 33 supplied by reverser 420 feeds a first input 431 receives a stabilized reference voltage, for example, by means of an assembly 44 fed with the mains voltage V 6 , rectified and filtered, through a second input 402 of circuit 40. This assembly 44 contains a resistor 440 and a Zener diode 441 connected in series between the input 402 and primary ground 8 and it supplies, by means of a resistive divider assembly 442, which may be adjustable and is connected in parallel with Zener diode 441, the reference voltage to input 432 of comparator 43. The output 433 of comparator 43, which is connected to the control input 412 of the first monostable flip-flop 41, supplies it with a voltage proportional to the difference between the voltages which are applied respectively to its inputs 431 and 432 so as to cause the delay in the cut off of chopper transistor 11 to vary with respect to that of sweep transistor 36 (FIG. 1) in order to stabilize the D.C. power supply voltage V 33 of output stage 30.

The leading edges of the pulses supplied by output 413 of flip-flop 41 coincide roughly with those of the line return pulses and their rear or falling edges, which occur with variable delays with respect to the leading edges, are used to trigger, eventually through an inverter stage 450, a second monostable flip-flop 45 whose output feeds the base of chopper transistor 11 to cut it off. This second monostable flip-flop 45 supplies this base with negative rectangular signals at the line frequency, of constant length, which is greater than the half period of oscillation of resonant circuit 13, 15 and hence the half period (>T H /2) and less than three quarters of this same period (<3T H /4) so as to allow transistor 11 to accept the current i 16 (t) flowing through inductor 16 when the current in diode 12 disappears.

FIG. 5 is a block diagram of a preferred production model of a regulation circuit 40 (in FIG. 1) controlling transistor 11 of chopper circuit 10 in accordance with the invention.

In FIG. 5 regulation circuit 40 has an input 401 connected to one of the terminals of auxiliary winding 25 of line transformer 20 which feeds in parallel a first control input 461 of a phase shift stage 46, the input of a regulator stage 47 and, finally, the input of a synchronizing circuit 49. The output of regulator stage 47 feeds a second regulation input 462 of phase shift stage 46, these two stages 46, 47 forming together a variable delay generator. The output of phase shift stage 46 feeds a first triggering input 481 of an unstable multivibrator 48 whose second synchronizing input 482 is fed by the output of synchronizing circuit 49. This synchronizing circuit 49, whose operation will be described further on, is only necessary if the free running oscillation frequency of multivibrator 48 is greater than the line frequency. If this is not so, multivibrator 48 is synchronized in classical fashion by the triggering pulses applied to its input 481. The output of unstable multivibrator 48 feeds the input of a driver or control stage 50 formed by an amplifier. The output of control stage 50 (called a "driver" in anglo-american litterature), which is connected to output 402 of regulation circuit 40, feeds the base of transistor 11 in chopper circuit 10.

Auxiliary winding 25 supplies to input 401 of the regulation circuit a voltage wave form containing the line return pulses with a negative polarity, for example, similar to that shown in the diagrams (C) of FIGS. 2 and 3. These line return pulses, when applied to input 461 of phase shift stage 46 or the delay generator, control the triggering of a signal generator which supplies a voltage in the form of a positive saw tooth that is applied to one of the inputs of a voltage comparator stage whose other input is fed with a fixed reference voltage and which switches from its "high" state to its "low" state when the amplitude of the saw tooth voltage exceeds the value of the reference voltage. Regulation stage 47 also receives the line return pulses, rectifies them and transmits to regulation input 462 of phase shift stage 46 a signal in the form of a current which enables the slope of the saw tooth to be modified as a function of the amplitude of the line return pulse which is a function of the D.C. voltage at the terminals of power supply capacitor 33 (FIG. 1) in output stage 30. To obtain regulation of voltage V 33 , the phase shift must increase with the value of this voltage to regulate the transfer of energy between circuits 10 and 30. As a result, the slope of the saw tooth must decrease with the increase in amplitude of the return pulse. The comparator stage of phase shift circuit 46 feeds triggering input 481 of unstable multivibrator 48 to trigger it with a variable phase shift with respect to the leading edge of the return pulse, which corresponds to the energy transfer desired. Unstable multivibrator 48 is, preferably, synchronized in frequency with line sweep output stage 30 in a way which will be explained later by means of synchronizing circuit 49 which feeds its synchronizing input 482. The output of multivibrator 48 feeds the input of driver stage 50 for chopper transistor 11.

To enable the chopper circuit 10 to start up before the line sweep circuit is running and, in particular, its output stage 30, unstable multivibrator 48 must oscillate independantly and stage 50 must amplify the roughly square wave signal it supplies. For this purpose, an independant D.C. power supply voltage source 51 is connected to supply terminals 1, 2 of the A.C. mains and the voltage it supplies feed supply terminals 403, 404 and 405 of regulation circuit 40. When chopper circuit 10 starts operating independantly when the line sweep circuit containing in series a line oscillator, a driver stage and output stage 30 is not being fed, the chopper current i 16 (t) passing through power supply winding 21 is induced in winding 22 and it is rectified by the second diode 35 which charges positively power supply capacitor 33 which then also feeds the other stages of the sweep circuit with a D.C. voltage so that they start up. This starting up and the resulting regulation will be explained more in detail in what follows.

FIG. 6 is a theoretical schematic diagram of the preferred production model of regulation circuit 40 whose block diagram was shown in FIG. 5.
In FIG. 6, power supply voltage source 51 of regulation circuit 40 contains a rectifier assembly 52 of the voltage doubler type operating on a half wave with two diodes 521, 522 in series. The first diode 521 is connected by its anode to the second terminal 2 of the supply from the mains, which is connected to the primary ground 8 and by its cathode to the anode of the second diode 522 whose cathode is connected to the positive plate of a first chemical filter capacitor 523. The negative plate of the first filter capacitor 523 is connected to the anode of the first diode 521 and hence also to primary ground 8. The junction of the cathode of first diode 521 and the anode of second diode 522 is coupled to the first terminal 1 of the power supply from the mains through a coupling capacitor 520 which transmits to the rectifier assembly 52 the mains voltage and whose capacity is chosen as a function of the D.C. voltage desired (the voltage drop at the terminals of this capacity 520 of the order of a few microfarads makes it possible to obtain a rectified and filtered voltage of about 15 Volts). The junction of the positive plate of first filter capacitor 523 is connected to the positive plate of a second filter capacitor 524 through a resistor 525, the negative plate of this second capacitor 524 being connected to primary ground 8. The positive terminal of this second capacitor 524 supplies a first rectified and filtered voltage V F , on the one hand, through the first output terminal 510 of source 51 to the first positive power supply terminal 404 of regulation circuit 40 and, on the other hand, to a stabilizing assembly 53 containing in series a resistor 531 and a Zener diode 530 whose anode is connected to primary ground 8. The junction of resistor 530 with the cathode of Zener diode 530 is connected to the second output 511 of source 51, which supplies a second regulated voltage V R that feeds the second power supply input 403 of regulation circuit 40.

The first power supply input 404, which supplies a first voltage V F (15 V) that is higher than the second regulated voltage V R (5 V), only feeds control stage 50 of chopper transistor 11. Control stage 50 contains in series a phase shift stage 500 (called a "phase splitter" in anglo-american litterature) and an output stage 550 of the "series push-pull" type often used in integrated logic circuits of the TTL type. Phase splitter 500 contains a first NPN transistor 501 whose collector is connected through a collector resistor 502 to the first power supply input 404 and whose emitter is connected through an emitter resistor 503 to primary ground 8 through the third power supply terminal 405 of circuit 40. The base of transistor 501 is connected to the output of unstable multivibrator 48 through a diode 504 and to the second power supply input 403 through a polarizing resistor 505. Output stage 550 contains a second and third NPN transistors 551 and 552. The collector of the second transistor 551 is connected through a resistor 553 to the first power supply input 404, its base being connected to the collector of the first transistor 501. The emitter of the second transistor 551 is connected to the anode of a diode 554 whose cathode is connected to the collector of the third transistor 552. The base of the third transistor 552 is connected to the emitter of the first 501 and its emitter, through the third power supply terminal 405, to primary ground 8. The junction of the cathode of diode 554 with the collector of third transistor 552 is connected to the cathode of a Zener diode 555 and to the positive plate of a chemical capacitor 556, mounted in parallel to form a "battery" which facilitates the cutting off of switching transistor 11. The other terminal of the parallel assembly 555, 556 is connected, through an inductor 557 (choke) to the output 402 of regulation circuit 40, which feeds the base of switching transistor 11.

Control stage 50 is controlled by an unstable multivibrator 48 of the symmetrical type containing two NPN transistors 480, 483 mounted with their emitters common, i.e. with their emitters connected through the third power supply terminal 405 to primary ground 8. The collectors of the two transistors 480, 483 are connected respectively to the second power supply input 403, which receives the stabilized voltage V R , through two collector resistors 484, 485. The bases of the two transistors 480, 483 are connected respectively by means of two polarizing resistors 486, 487 also to the second power supply input 403. The base of first transistor 480 is also coupled to the collector of second transistor 483 through a first capacitor 488 and the base of second transistor 483 is coupled to the collector of the first 480 through a second capacitor 489. The respective values of the polarizing resistors 486, 487 and of the mutual coupling capacitors 488, 489 (crossed) of the two stages mounted with their emitters common determine, with the value of the stabilized power supply voltage V R , the lengths of the half periods of relaxation of multivibrator 48 whose sum (60 μsec) is chosen, preferably, less than that of a line period (64 μsec).

In the absence of line return pulses coming from the line sweep output stage 30 through auxiliary winding 25, multivibrator 48 is fed neither at its triggering input 481, which is connected to the cathode of a first diode 4802 whose anode is connected to the base of the second transistor 483, nor at its synchronizing input 482 which is connected to the cathode of a second diode 4803 whose anode is connected to the base of the first transistor 480. It will operate independantly then as soon as voltage is applied to the mains power supply terminals 1, 2 which feed, on the one hand, rectifier assembly 5 and, on the other, independant power supply 51. The power supply then provides multivibrator 48 with a stabilized power supply voltage V R and the driver stage 50 with a rectified filtered voltage V F . When multivibrator 48 starts to oscillate, it supplies at its output formed by the collector of its second transistor 483 rectangular signals of two levels (V R and V CEsat ), the lowest of which, through coupling diode 504, causes the cut off of the first transistor 501 in control stage 50. When the first transistor 501 is cut off, the base of the second transistor 551 in output stage 50 is connected, through the collector resistor 502, to the first power supply input 404 in circuit 40 so as to saturate it. The emitter current of second transistor 551 then passes, through the diode 554, the Zener diode 555 and inductor 557 (which limits the rate of rise of the current di/dt), in resistor 19 connecting the base of chopper transistor 11 to primary ground 8 and in this base in order to allow the saturation of chopper transistor 11, the third transistor 552 then being cut off by the cut off of the first 501. The voltage drop at the terminals of Zener diode 555 enables the positive polarizing voltage of the base to be reduced and the capacitor 556 to be charged to the Zener voltage V Z during its periods of conduction.

When the second transistor 483 of multivibrator 48 has switched from its saturated to its cut off state, its collector voltage is equal to the stabilized voltage V R and diode 504 cuts off. The base of first transistor 501 in control stage 50 is then connected to the second power supply input 403 (+V R ) through resistor 505, which causes it to saturate. Then the emitter current of this first transistor 501 feeds the base of the third transistor 552 which also becomes saturated while the second transistor 551, whose base is at a voltage (V CEsat 501 +V BE 552), which is roughly equal to that of its emitter (V F 554 +V CEsat 552), cuts off. The saturation of the third transistor 552 first brings the base of chopper transistor 11 to a negative voltage with respect to its emitter V BE 11 =-V Z +V CEsat 552 so as to cut it off rapidly by a rapid evacuation of the minority carriers in its base, this voltage V BE 11 then tending asymptotically to zero because the capacitor 556 discharges through resistor 19 and the third transistor 552 saturated. Chopper transistor 11 will remain cut off during the whole half period of oscillation of the resonant circuit L 16 , C 13 and will only accept the current of diode 12 afterwards if it is already positively polarized on its base by the switching of multivibrator 48 to the state in which its second transistor 483 again becomes saturated so as to cut off first transistor 501 and again saturate second transistor 551 in control circuit 50.

The alternate cut off and conduction of bidirectional switch 15 causes the appearance at terminal 19 of recurrent half sinusoids of voltage, shown by the diagrams (D) in FIGS. 2 and 3, a fraction of which is also present at the terminals of power supply winding 21 of line transformer 20, from where they are transmitted with a phase inversion (polarity) but without a D.C. component to winding 22 of line sweep output stage 30. The negative half cycles of its wave forms on terminal 220 of the winding are then rectified by the parallel ("shunt") recovery diode 35 whose current charges power supply capacitor 33 until the voltage V 33 on terminal 221, which feeds the whole of the line sweep circuit, is sufficient for the line oscillator (which is not shown) to start oscillating independantly, so as to control, through the driver stage (not shown), switching transistor 36 in output stage 30. Line sweep output stage 30 then starts to supply, at the terminals of winding 22 of line transformer 20, line return pulses v 220 (t), which are illustrated by the diagrams (B) in FIGS. 2 and 3. These pulses are transmitted to auxiliary winding 25 without a D.C. component and with (negative) phase inversion so as to have a wave shape analogous to that of the diagrams (C) in FIGS. 2 and 3, which makes possible first the synchronization of multivibrator 48 with the line oscillator frequency using an original slaving device which will be described further on and then the regulation of voltage V 33 by varying the delay between the leading edges of the line return pulses and the instant when chopper transistor 11 in switch 15 is cut off.

When multivibrator 48 and the line oscillator operate independantly and at different frequencies, this produces a beat because there are random phase variations between the line return pulses, v 220 (t) or v 21 (t), and the wave form of the chopper voltage v 19 (t), so that the energy supplied (or consumed) by chopper circuit 10 to (or from) output stage 30 varies from one cycle to another. This has as visible result a more or less big fluctuation in the amplitude of the line return pulses v 220 (t) which seem to be modulated in amplitude by a sinusoidal signal whose frequency is equal to the difference between that of multivibrator 48 and that of the line oscillator.

If one chooses to synchronize unstable multivibrator 48 in classical fashion soleby by means of periodic control pulses derived from the line return pulses through a variable delay circuit allowing regulation, it is sufficient for the independant oscillation frequency to be less than that of the line oscillator. One then obtains on starting up peak voltages V 19 , which are higher (overvoltages) on the collector of transistor 11 when it is cut off because, in the formula V 19max t B =V Amax T 48A , in which V 19max is the peak amplitude of the collector voltage (on terminal 19), t B the time during which switch 15 is cut off, V Amax the maximum supply voltage supplied by rectifier 5 and T 48A the free running period of multivibrator 48, T 48A being greater than T H . If one accepts this overvoltage V 19max and limits it by a choice of the saturation time t S slightly higher than the cut off time t B1 which is always equal to the half period of oscillation of L 16 and C 13 , it will not be necessary to slave multivibrator 48 before regulation and synchronizing circuit 49 can be omitted.

If, on the other hand, one wishes to avoid the excesses of the collector peak voltage V 19max on starting up, one chooses a free running period T 48A for multivibrator 48 less than the line period T H (64 μsec) and one synchronizes by acting only on the length of the cut off state of first transistor 480 in multivibrator 48 by lengthening it. During this same time interval, second transistor 483 of multivibrator 48 and second transistor 551 of driver stage 50 are saturated and the first 501 and third 552 transistors of this stage 50 are cut off so that the base of chopper transistor 11 is polarized to conduct.

This lengthening is done by means of a network 49 containing a diode 490 whose cathode is connected to the input 401 of regulation circuit 40 which receives the line return pulses from winding 25 with negative polarity and no D.C. component. The anode of diode 490 is connected to that of a Zener diode 491 whose cathode is connected to one of the terminals of a first resistor 492. The other terminal of this first resistor 492 is connected, on the one hand through a second resistor 493, to the synchronizing input 482 of unstable multivibrator 48 and, on the other hand through a third resistor 494, to the collector of the second transistor 483 in the multivibrator so that the line return pulse, negative and with its base cut off by Zener diode 491, cannot act on the base of the first transistor 480 during its periods of saturation so as to cut it off at the wrong time.

The process of slaving the frequency of multivibrator 48 by means of the line return pulses is shown by the diagrams of the wave forms in FIG. 7.

In FIG. 7, the diagram A represents the wave form at the terminals of auxiliary winding 25 of the line transformer 20 where line return pulses appear in the form of negative half sinusoids of amplitude V 25 at the line frequency (15.626 Hz). The diagram B shows the wave form of the voltage v BE 480 on the base of the first transistor 480. This wave form contains a first time interval t SA during which chopper switch 15 is conducting and transistor 480 is cut off. This time interval depends solely on the value of the components connected to this base, specifically the resistor 486 and the capacitor 488 and the supply voltage V R for this resistor 484. This wave form also contains a second time interval t B of fixed length during which chopper switch 15 is cut off and transistor 480 saturated. The sum of the intervals t SA and t B represents the period of independent operation T A of multivibrator 48 (of the order of 58 μsec for example).In FIG. 7 the first three periods of free running operation of multivibrator 48 are not changed because either the line return pulse occurs outside the cut off interval t SA of transistor 480 or its amplitude, with its base cut off by Zener diode 491 and reduced by the resistive voltage divider 492, 494, i.e. (V 25 -V Z 491)R 494 /(R 492 +R 494 ), is less in absolute value than the instantaneous base-emitter voltage v BE 480 (t). From the instant at which the cathode of the separator diode 4803 becomes more negative than its anode, which is connected to the base of transistor 480, it begins to conduct a current I 493 which discharges capacitor 488 through the resistor 493 in series with the resistors 492 and 494 in parallel. Current I 493 must be subtracted from the current I 486 , which is charging the capacitor, during the whole of the time the amplitude of the line return pulse exceeds the voltage v BE . The effect of this is to shift in time a part of the charging wave form of capacitor 496 and thus lengthen the cut off time t SA of transistor 480 by a time Δt S which will increase until the lengthened period of multivibrator 48 is equal to the line period T H . Because the conduction time of switch 15 is lengthened, the energy stored in inductor 16 increases. This increases the voltage V 33 and the amplitude of the line return pulse.

The process of slaving multivibrator 48 in frequency must of necessity lead to equality of these periods because an inequality gives rise to a variation in the peak amplitude of the line return pulse in a direction which affects the length of cut off time t SA +Δt S of transistor 480 in the opposite direction.

After the slaving of the frequency of unstable multivibrator 48 one can go on to the regulation by varying the phase shift between the respective cut off instants of the sweep transistor 36 and chopper transistor 11 by means of the phase shift 46 and regulator 47 stages in regulation circuit 40, which together form the variable delay generator.

Phase shift stage 46 contains a saw tooth generator which includes a first capacitor 460, one of whose terminals is connected to primary ground 8 while the other terminal is connected to one of the terminals of a first resistor 463 whose other terminal is connected to the second power supply input 403 which receives the stabilized voltage +V R , and a switch, which is intended to short-circuit the first capacitor 460 periodically. This switch contains a first NPN switching transistor 464 whose collector is connected to the junction of first capacitor 460 and first resistor 463, its emitter being connected to primary ground 8 and its base, through a second resistor 465, to the second power supply input 403 and, through a third resistor 466, to the anode of a diode 467, whose cathode is connected to the control input 461 of phase shift stage 46 which receives negative line return pulses from input 401 of circuit 40. The base of first transistor 464 is also coupled to primary ground 8 through a second capacitor 468.

When input 401 of circuit 40 receives a negative line return pulse, diode 467 starts to conduct and its current causes voltage drops at the terminals of resistors 465, 466 in series which brings transistor 464 to cut off by polarizing it negatively. Second capacitor 468 then charges to a negative voltage which will extend the length of the cut off of transistor 464 beyond the disappearance of the line return pulse for a part of the forward sweep period in order to have a sufficient regulation range available.

When the negative return pulse ceases, diode 467 cuts off and second capacitor 468 is charged gradually through resistor 465 to a positive voltage V BE of about 0.7 Volts, at which transistor 464 becomes saturated and discharges first capacitor 460.

During the cut off period of first transistor 464, first capacitor 460 is charged almost linearly through resistor 463 and supplies a voltage of positive saw tooth shape to the base of a second NPN transistor 469, whose collector is connected, through a fourth resistor 4600, to the second power supply terminal 403 (V R =+5 V). The emitter of second transistor 469 is connected, on the one hand, to the cathode of a Zener diode 4601 whose anode is connected to primary ground 8 and, on the other hand, to the second power supply terminal 403 through a fifth resistor 4602 which makes it possible to polarize the emitter of second transistor 469 at a fixed voltage V Z (between 2 and about 3 Volts).

Second transistor 469 forms, with resistors 4600, 4602 and Zener diode 4601, an analog voltage comparator stage which is cut off until the voltage applied at its base exceeds a threshold voltage resulting from the addition of Zener voltage V Z of diode 4601 to the voltage V BEm of about 0.7 Volts at which second transistor 469 saturated.

When second transistor 469 passes from its cut off state to its saturated state, its collector voltage v C 469 changes from V R to V Z +V CEsat . This negative change is transmitted through a coupling capacitor 4603 to the triggering input 481 of unstable multivibrator 48 which is connected, on the one hand, to the cathode of the first diode 4802 whose anode is connected to the base of the second transistor 483 and, on the other hand, to the first terminals of two resistors 4800 and 4801 which form a resistive voltage divider and whose second terminals are respectively connected to primary ground 8 and to the second power supply terminal 403 of circuit 40. This negative change, when transmitted to the base of second transistor 483 in multivibrator 48, causes it to cut off and, in the manner already described, the coppice of chopper transistor 11 also.

The regulation of the power transmitted by chopper circuit 10 to line sweep output stage 30 is obtained by the variation of the phase shift between the respective cut off instants of the sweep 36 and chopper 11 transistors by means of the regulator stage 47 which causes the charging voltage slope of the capacitor 460 to vary as a function of one of the parameters contained in the line return pulse.

The combined operation of the phase shift 46 and regulator 47 stages will be explained by means of FIG. 8, which illustrates the voltage wave forms at three points of these circuits 46, 47.
Regulator stage 47 contains a diode 470 whose cathode is connected to the input 401 of circuit 40, which receives the negative polarity line return pulses and whose anode is connected to the negative plate of a filter capacitor 471 and to one of the terminals of a resistive voltage divider containing a potentiometer 472 between two resistors 473, 474 in series and to the anode of a Zener diode 475. The cathode of Zener diode 475 is connected, on the one hand, to one of the terminals of a third resistor 477 whose other terminal is connected to primary ground 8 and, on the other hand, to the emitter of an NPN transistor 476 whose base is connected to the slider arm of potentiometer 472 and whose collector is connected to the regulation input 462 of the phase shift stage 46, which is connected to the junction of its first capacitor 460 with its first resistor 463 and the collector of its first transistor 464.

Diode 470 forms with capacitor 471 a rectifier of the negative peaks of the line return pulses, capacitor 471 supplying at its terminals a voltage which is a function of the negative peak amplitude of the line return.

This rectified peak voltage is applied, on the one hand, to the resistive divider assembly, 472-474, so that the slider arm of potentiometer 472 supplies a voltage which is a predetermined adjustable fraction of that voltage and, on the other hand, to the series assembly of Zener diode 475 and resistor 477 which polarizes this diode 475. As soon as the amplitude of the line return pulses exceeds the Zener voltage V Z of diode 475, it is opened up so as to supply at its cathode a voltage equal to the difference between the rectified peak voltage and the Zener voltage V Z . The cathode voltage of Zener diode 475 polarizes the emitter of transistor 476 whose base is polarized by divider assembly 472-474 and which starts to conduct as soon as the fraction of the rectified voltage supplied by the slider arm of the potentiometer is greater than the Zener voltage V Z in absolute value. Transistor 476 then forms a source of constant current proportional to its base-emitter voltage V BE , i.e. to V B -V Z when the latter is positive. The collector current of transistor 476 is therefore a current which discharges capacitor 460 during the intervals when transistor 464 is cut off so as to reduce the slope of the saw tooth voltage at the terminals of capacitor 460. The bigger the negative peak voltage of the line return pulses, the more the collector current of transistor 476 reduces the slope so as to increase the delay time between the leading edge of the line return pulse and the instant of change of the comparator transistor 469 from its cut off to its saturated state.This is indicated in FIG. 8, in which the diagram (A) shows the voltage wave form v 25 (t) at the terminals of auxiliary winding 25 whose line return pulses are of three different amplitudes V 25B , V 25F and V 25N , the diagram (B) represents the voltage wave form at the terminals of capacitor 460 corresponding to these three line return pulses and the diagram (C) represents the collector voltage v 469 (t) of comparator transistor 469.

In diagram (A) in FIG. 8, the first line return pulse is of a relatively small amplitude V 25B which does not cause the conduction of regulation transistor 476. To this corresponds in diagram (B) the steepest slope of the voltage wave v 460 (t) which starts at the instant t 1 of cut off of first transistor 464 in phase shift circuit 46 and the shortest length T B =t 2 -t 1 of this cut off because of the smaller negative charge of capacitor 468. At the instant t 2 , when voltage v 460 (t) becomes equal to V Z +V BEm , it no longer increases because the diode formed by the base-emitter junction of second transistor 469 limits the maximum level of this voltage and transistor 469 becomes saturated. This is illustrated by the diagram (C) in FIG. 8, in which one can see that the collector voltage v C 469 of second transistor 469 contains a negative square wave whose level is equal to V Z +V CEsat and which lasts until the instant t 3 of the opening up of the first transistor 464 which discharges capacitor 460 and, as a result, cuts off second transistor 469.

Because of the small phase delay t RB =t 2 -t 1 produced by the fast rise of the voltage v 460 (t), chopper circuit 10 supplies maximum energy to output stage 30 in the form of a high voltage V 33 at the terminals of the power supply capacitor 33. As a result, the next line return pulse will be of large amplitude V 25F . The comparator transistor 476 starts to conduct as soon as V BE becomes positive and the greater the amplitude V 25F to which the capacitor 471 charges, the greater the collector current. This collector current is to be subtracted from the charging current of capacitor 460 through the resistor 463. Hence, it causes a noticeable reduction in the slope of the rise in the voltage v 460 (t) which occurs between the instants t 4 and t 5 . The length of this rise, which corresponds to the phase delay t RF =t 5 -t 4 , will then be noticeably longer than before as well as the length of the cut off state T F of the first transistor 464. One can see then in the three diagrams that, when V 25F is large, the delay t RF is longer and the length of the negative pulse T F -t RF is slightly shorter.

This longer delay causes a reduction in the voltage V 33 compared with the preceding cycle in which it was too big and the next line return pulse (the third) will be of an amplitude V 25N greater than V 25B and less than V 25F . It will make it possible to obtain, by means of the corresponding collector current of the regulation transistor 476, a slope in which the rise from a voltage V CEsat near zero to a voltage V Z +V BEm is of a length equal to t RN =t 7 -t 6 . If the slider arm of potentiometer 472 has been so placed that the power supply voltage V 33 makes it possible to obtain a very high voltage for the cathode ray tube (which is not shown) and/or an amplitude of the horizontal sweep current saw tooth corresponding to their respective nominal values, the nominal amplitude V 25N of the line return pulse will be reproduced afterwards in recurrent fashion.

It is to be noted here that one can also use as a regulation criterion the positive amplitude of the signal v 25 (t), i.e. the positive plane whose level is proportional to the power supply voltage V 33 by using an analog phase inverter or another winding of line transformer 20 for example.

One will note also here that the main advantage of the regulation by the phase shift of a chopper circuit operating with a constant cyclic ratio and frequency, compared with that by the variation of one of them, is formed by the fact that the peak voltage applied to the collector of the chopper transistor, when it is cut off, is a function only of the mains voltage.


SALORA-L CHASSIS Regulated power supply incorporating a power transformer having a tightly coupled supplemental power transfer winding :



A regulated power supply for a television receiver includes a transformer having a primary winding coupled to a source of unregulated voltage. A transistor switch controls the interval during which the unregulated voltage causes current to flow in the primary winding. By transformer action, power is transferred to secondary windings which are coupled to receiver load circuits. The secondary winding voltages are regulated by control of the primary winding conduction interval. A supplemental winding is layer wound over the primary winding to transfer additional power to the load circuits. The primary winding may be electrically isolated from the secondary windings and from the supplemental winding.



1. A regulated power supply for a television receiver incorporating a plurality of load circuits comprising:
an unregulated voltage source electrically isolated from said load circuits;
a transformer core having first and second transformer core legs;
a first transformer winding, wound on said first transformer core leg and having first and second terminals, said first terminal coupled to and electrically nonisolated from said unregulated voltage source;
means, coupled to said first transformer winding second terminal for selectively energizing said first winding from said unregulated voltage source;
a second transformer winding, wound on said second transformer core leg, electrically isolated from said first transformer winding, for powering a given one of said load circuits in response to the energization of said first transformer winding; 
means for controlling the operation of said energizing means to maintain a constant voltage supply for said load circuits; and
a third transformer winding electrically isolated from said first transformer winding and wound on said first transformer core leg to overlay said first transformer winding for powering at least one of said load circuits in response to the energization of said first transformer winding.
2. The arrangement defined in claim 1, wherein said means for selectively energizing said first winding comprises a transistor switch. 3. The arrangement defined in claim 1, wherein said means for controlling the operation of said energizing means comprises a pulse width modulator. 4. The arrangement defined in claim 1, further comprising a plurality of transformer load windings wound on said second transformer core leg. 5. The arrangement defined in claim 1, wherein said first transformer winding is more closely coupled magnetically to said third transformer winding than to said second transformer winding. 6. The arrangement defined in claim 1, wherein said given one of said load circuits comprises a line deflection circuit, said line deflection circuit developing a retrace pulse across said second transformer winding. 7. The arrangement defined in claim 6, wherein said energizing means causes said energization of said first transformer winding to be terminated during the interval of said retrace pulse. 8. The arrangement defined in claim 1, wherein energy stored in said transformer core, during the time said first transformer winding is energized, is maintained in said transformer core by energization of said third transformer winding, when said first transformer winding is not energized, for supplemental transfer to at least one of said load circuits by said third transformer winding. 9. The arrange
ment defined in claim 8, wherein substantially all of said energy stored in said transformer core during energization of said first transformer winding is removed before energization of said first transformer winding reoccurs.

Description:

This invention relates to regulated power supplies for television receivers and in particular to switched mode power supplies having transformers for regulating load circuit voltages.
Many of the circuits in television receivers require carefully regulated power supplies in order to operate properly. For example, if the horizontal and vertical deflection circuit supply voltages are permitted to vary in an uncontrolled manner, the size of the scanned raster may change, producing an undesirable visual effect. Additional receiver circuits may be subject to excessive electrical stresses or may be damaged if supply voltages are not held within acceptable limits.
One type of voltage regulating circuit utilizes a silicon controlled rectifier (SCR) coupled to an unregulated voltage source developed from the ac line. During conduction of the SCR, current flow from the unregulated supply charges a capacitor, establishing a regulated voltage level. The conduction time of the SCR is controlled to maintain a fixed regulated voltage level. Decreases in the ac line voltage or increased circuit loading will cause an increase in the SCR conduction time and an increase in line voltage will result in a decrease in SCR conduction time.
The previously described SCR regulated power supply is not economically incorporated in a receiver which provides input and output terminals electrically isolated from the ac line. Such an arrangement is required when it is desired to provide the receiver with the capability to accept a direct video signal input, for example, from a video tape recorder or a video disc player, or from a home computer. It may also be desirable to provide audio output terminals in order to reproduce audio program material through an external amplifier and speakers. These input or output interface terminals must be accessible by the user of the television receiver, yet provide electrical isolation from the ac line to eliminate any shock hazard. Providing this isolation may be difficult in a receiver having an SCR regulated power supply, since the SCR is normally connected directly to the unregulated supply. Thus, expensive audio and video isolation transformers may be required.
An arrangement for electrically isolating the receiver load circuits from the ac line via the high voltage power transformer is disclosed in a copending application entitled "Regulated Power Supply Circuit", Ser. No. 426,360, filed on Sept. 29, 1982, in the name of D. H. Willis. The circuit described in that application includes a transistor switch which permits current from an unregulated voltage supply to energize a primary winding of the high voltage transformer. This in turn energizes the electrically isolated load circuit windings in order to power the associated load circuits. A supplemental transformer winding aids in transferring power to the load circuits. The conduction time of the transistor switch is controlled in order to regulate the magnitude of the voltages induced across the load circuit windings. The primary winding comprises one half of a bifilar-wound coil pair with the other half of the coil pair operable as a catch winding to return stored energy in the coil back at the unregulated supply when the transistor switch is turned off. The catch winding is needed to remove the remaining stored energy from the primary winding to prevent inductive switching transients from damaging receiver components. This arrangement requires the previously described bifilar primary coil, which increases transformer cost and complexity, and effectively limits the transistor switch conduction duty cycle to a maximum of approximately 50%. This insures that all of the stored energy in the primary winding can be transferred to the catch winding. Limiting the switch duty cycle also limits the amount of energy that may be transferred to the load windings which may limit the ability of the power supply to accurately regulate the load circuit voltages under extreme line voltage and circuit loading conditions.
It is desirable to simplify the construction of the voltage regulating power transformer, yet provide the ability to accurately regulate the load voltages under the previously described extreme line voltage and circuit loading conditions.
In accordance with the present invention, a regulated power supply for a television receiver which includes a number of load circuits comprises an unregulated voltage source coupled to a first terminal of a primary transformer winding. The unregulated voltage source is coupled to the primary winding second terminal and selectively energizes the winding. Means are provided which power the load circuits in response to the energization of the unitary winding. A control circuit is coupled between the load circuits and the energizing means for controlling the operation of the energizing means to maintain a substantially constant voltage supply for the load circuits. A supplemental transformer winding overlays the primary winding and powers at least one of the load circuits in response to energization of the primary winding.
In the accompanying drawing,
FIG. 1 is a schematic diagram of a television receiver regulated power supply constructed in accordance with the invention;
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1; and
FIG. 3 is a diagramatic representation of a high voltage transformer constructed according to the invention.
Referring to FIG. 1, an ac mains supply 10 is applied to a full-wave bridge rectifier 11 and a filter capacitor 12 to develop a source of unregulated voltage at a terminal 13. This unregulated voltage is applied to one terminal of a primary winding 14 of a high voltage power transformer 15. The other terminal of winding 14 is coupled to the collector of a transistor 16 and through a protection network 17, comprising a resistor 18, a diode 20 and a capacitor 21, to ground. Transistor 16 is switched by signals from a regulator control circuit 22 via an isolation transformer 28 to control the conduction of current from the unregulated voltage source through winding 14 in a manner that will be explained later.
Transformer 15 also includes a number of secondary windings and a tertiary winding 23, which generates a high voltage of the order of 25 KV at an ultor terminal 24 to be applied to the anode of a kinescope (not shown).
Among the secondary windings shown as comprising transformer 15 are winding 25, which provides a voltage which is rectified and filtered to develop a direct voltage of the order of 185 volts at a terminal 26 that may be used, for example, to power the kinescope drive circuits (not shown). Another secondary winding 27 is coupled to a horizontal deflection circuit 30, which comprises a horizontal output transistor 31, a retrace capacitor 32, a damper diode 33, a deflection yoke winding 34, and a deflection waveform S-shaping capacitor 35. Horizontal output transistor 31 is switched at a horizontal rate by signals from a horizontal driver circuit 36, which is controlled by a horizontal oscillator 37 in order to develop horizontal deflection current in deflection yoke winding 34. Winding 27 also generates a voltage which forms a regulated B+ supply at a terminal 40 of the order of 127 volts.
The voltage generated via the secondary and tertiary associated load circuits are carefully regulated in the following manner, which will be explained with reference to FIG. 2. Transistor 16 is rendered conductive by a switching signal at a time t ₁ from regulator control circuit 22, for example Matsushita AN5900, being applied to the base of transistor 16, thereby raising the base-emitter voltage (V _BE16 ), as shown in FIG. 2g. Current (I ₁₄ ) flows in primary winding 14 of transformer 15, as shown in FIG. 2a, from the unregulated voltage supply at terminal 13. Inductive energy is stored in winding 14 and in the magnetically permeable core of transformer 15. When transistor 16 is turned off, at time t ₃ , the voltage across winding 14 (V ₁₄ ) increases, as shown in FIG. 2b, and induces voltages across load windings 23, 25 and 27 by transformer action in order to power the previously described load circuits, such as horizontal deflection circuit 30.
The amount of energy that may be transferred in this way is dependent on factors which include the conduction time of transistor 16 and the degree of magnetic coupling between the primary winding 14 and the load windings. As previously described, it may be desirable to provide the receiver with direct video and audio input and output capability in order to interface external components, such as video sources, home computers or separate audio equipment, with the receiver. This requires that the user accessible interface connectors or terminals on the receiver be electrically isolated from the ac line in order to prevent the possibility of a user receiving a shock. This isolation may be accomplished by electrically insulating the "hot" primary winding 14 from the load windings. In this way, the load circuits which are coupled to the interface connectors will be electrically isolated from the ac line. This is shown in FIG. 1 by the use of different ground symbols to illustrate the ac line "hot" ground as compared to the isolated "cold" ground.
In the interest of safety, guidelines and requirements may exist which define the amount of insulating material that is needed or the physical separation between windings, particularly between the high voltage ultor winding and the low voltage windings, that is required. These insulation and physical separation requirements may produce a transformer having a reduced primary to load winding magnetic coupling compared to a transformer that does not provide as great a degree of electrical isolation. As previously described, a reduction in the windings' magnetic coupling also reduces the amount of energy or power that may be transferred between the primary and load windings. Under certain severe receiver operating conditions, such as low ac line voltage, receiver start-up, or high load circuit power requirements, there may be insufficient power transferred between primary winding 14 and the load windings to maintain accurate regulation of the load circuit supply voltages.
To prevent a degradation of the voltage regulating capabilities of the receiver under these conditions, a supplemental winding 41 of transformer 14 is provided and operates in the following manner. Supplemental winding 41 is coupled to primary winding 14 more tightly than are the load windings 23, 25 and 27. When transistor 16 turns off, at time t ₃ , this coupling causes the voltage across winding 41 (V ₄₁ ) to increase, as shown in FIG. 2c. This voltage is rectified and filtered and provides the source of regulated B+ voltage at terminal 40 and also provides power to operate horizontal deflection circuit 30. An intermediate tap 42 on winding 41 provides a low voltage source of the order of 16 volts via a diode 43 and a capacitor 48 at a terminal 44. The 16 volt source is also applied to and provides operating power for horizontal oscillator 37 and for regulator control circuit 22. In FIG. 1, the level of the 127 volt source is shown as sampled by regulator control circuit 22 to control the switching of transistor 16, in order to maintain accurately regulated load circuit supply voltages. Sampling of the 127 volt supply is shown for example only. Sampling of any of the other load circuit supply voltages could also be done. Supplemental winding 41 is magnetically tightly coupled to primary winding 14 by constructing primary winding 14 and supplemental winding 41 as layer windings with supplemental winding 41 wound to overlay primary winding 14, as shown in FIG. 3. By winding the transformer 15 in this way, it is possible for supplemental winding 41 to transfer between 20% to 50% of the total power required by the load circuits. Close magnetic coupling between the primary winding 14 and supplemental winding 41 as a result of the layer winding arrangement produces accurate regulation of the supplemental winding voltage. This permits the supplemental winding 41 to be used as a source of one or more regulated voltages for the receiver, such as the +16 volt supply as shown in FIG. 1. The potential difference between primary winding 14 and supplemental winding 41 is relatively small, as contrasted to the potential difference between primary winding 14 and high voltage winding 23, for example. This permits windings 14 and 41 to be layer-wound as previously described in order to provide tight magnetic coupling yet allows windings 14 and 41 to be electrically isolated through the use, for example, of 20 mils of Mylar between windings 14 and 41.
FIGS. 2d and 2e illustrate the waveforms of the current flow through windings 27 and 41, respectively. Current flow in winding 27 (I ₂₇ ) will closely resemble the deflection current in deflection yoke winding 34. Current flow in supplemental winding 41 (I ₄₁ ) decreases as the stored energy in the winding decreases. When this energy is depleted, current flow ceases. Current flow in winding 41 may also be terminated by the switching of transistor 16 terminating conduction of winding 14. The collector-emitter voltage of horizontal output transistor 31 (V _BE31 ), illustrating the horizontal retrace pulse, is shown in FIG. 2f.
When transistor 16 is turned off, by action of the switching pulses from regulator control circuit 22, the stored inductive energy in winding 14 causes the collector-emitter voltage of transistor 16 to rise. If this energy is not rapidly removed from winding 14, the collector-emitter voltage of transistor 16 may increase to a point at which transistor 16 is damaged. The tight magnetic coupling between primary winding 14 and supplemental winding 41 causes winding 41 to act as a clamp winding which limits the extent to which the collector voltage of transistor 16 can increase. This occurs because winding 41 expeditiously removes much of the energy from winding 14, as previously described, so that a relatively small amount of energy remains. Protection network 17 is provided, however, to aid in removing this energy in order to protect transistor 16. During the time transistor 16 is conducting, capacitor 21 discharges through resistor 18 and the collector-emitter path of transistor 16 to ground to a level determined by the voltage drop across resistor 18. When transistor 16 turns off, its collector voltage rapidly rises, creating an inductive voltage spike as shown in FIG. 2b. When the collector voltage exceeds the combination of the voltage level on capacitor 21 and the conduction threshold voltage of diode 20, diode 20 is rendered conductive, permitting winding 14 energy to charge capacitor 21. The voltage represented by the spike in FIG. 2b is therefore dissipated by capacitor 21, rather than by transistor 16, thereby protecting transistor 16. As described, this excess charge on capacitor 21 is removed via resistor 18 during conduction of transistor 16. Although some is removed from primary winding 14 by protection network 17, most of the energy in winding 14 is transferred to the loads by either the load windings or by supplemental winding 41.
As the load circuit power requirements decrease or the ac line voltage increases, transistor 16 conducts for a shorter period of time each horizontal interval, as shown by the dashed lines in the waveforms of FIG. 2. Transistor 16 is switched on at a time t ₂ and off at time t ₄ , resulting in a decreased current flow in primary winding 14 and supplemental winding 41.
The regulator circuit of FIG. 1 therefore provides accurate load circuit supply voltage regulation even under severe receiver operating conditions with a relatively simple high voltage transformer, yet provides ac line isolation of the load circuits to permit interfacing with external video or audio components.



 PHILIPS TDA4505E /  TDA4504B  Small Signal combination IC for colour TV:

FEATURES
· Gain controlled vision IF amplifier
· Synchronous demodulator for negative and positive
demodulation
· AGC detector operating on peak sync amplitude for
negative demodulation and on peak white level for
positive demodulation
· Tuner AGC
· AFC circuit with two control polarities and on/off-switch
· Video preamplifier
· Video switch to select either the internal video signal or
an external video signal
· Horizontal oscillator and synchronization circuit with two
control loops
· Vertical synchronization (divider system), ramp
generator and driver with automatic amplitude
adjustment for 50 and 60 Hz
· Transmitter identification (mute)
· Sandcastle pulse generation
· VCR/auto VCR switch
· Start-up circuit
· Vertical guard.


GENERAL DESCRIPTION
Having the capability to demodulate IF signals with either
positive or negative-going video information, the
TDA4504B (Fig.1) is contained within a 32 pin
encapsulation. It includes a three-stage vision IF amplifier,
mute circuit, AFC and AGC circuitry, fully synchronised
horizontal and vertical timebases with drive circuits and
integral three-level sandcastle pulse generator.
A functional colour tv receiver can thus be realized with the
addition of a tuner, audio demodulator and amplifier,
chroma decoder and respective line and field deflection
circuitry.

 FUNCTIONAL DESCRIPTION
Vision IF amplifier, demodulator
and video amplifier
Each of the three AC-coupled IF
stages permit the omission of DC
feedback and possess a control
range in excess of 20 dB.
The IF amplifier, which is completely
symmetrical, is followed by a passive
synchronous demodulator providing a
regenerated carrier signal. This is
limited by a logarithmic limiter circuit
prior to its application to the
demodulator.
A noise clamp circuit is provided at
the video input (pin 16) to limit
interference pulses below the sync tip
level and is more efficient than a
noise inverter in providing improved
picture stability during the presence of
interference.
The video amplifier has good linearity
and bandwidth figures.
AFC-circuit
Obtaining the AFC reference signal
from the demodulator tuned circuit
presents the advantage of utilizing a
single tuned circuit and one
adjustment. However, since the
frequency spectrum of the signal
applied to the demodulator is
determined by the characteristic of
the SAW filter, the resultant
asymmetrical spectrum with respect
to the vision carrier causes the AFC
output voltage to be dependent upon
the video signal. The TDA4504B thus
contains a sample-and-hold circuit.
With negative-going vision signals the
AFC is active only during the sync
pulse period. When positive-going
signals are applied to the device,
however, the AFC is continuously
active but filtered to ensure only a
small by-pass current is present in the
sample-and-hold circuit.
With weak input signals the drive
signal will contain considerable noise
which also possesses an
asymmetrical frequency spectrum
and could create an offset in the AFC
output voltage. The inclusion of a
notch in the demodulator tuned circuit
minimises this effect.
The sample-and-hold circuit is
followed by a high impedance output
amplifier. Thus the AFC control
gradient depends upon the load
impedance.
The AFC polarity switch is combined
with the start circuit (pin 12). It has a
negative slope when pin 12 is open or
connected to the main supply and a
positive slope when pin 12 is
grounded. The AFC is disabled when
the sample connection (pin 22) is
grounded.

AGC circuit
For signals employing negative modulation the AGC detector operates on peak sync level but upon peak white content
with those having positive modulation. Selection is facilitated by the system switch (pin 32):
The AGC detector currents are:
With a 6.8 mF AGC capacitor, the video tilt will be < 10% for positively modulated signals and < 2% for negative
modulation.
To obtain a rapid AGC action when executing a search tuning operation with the circuit set for peak white AGC, the
charge current is held at 55 mA until the detection of a transmitted signal.
The transmitter identification
A mute signal is generated to disable the audio preamplifier of an audio demodulator during the absence of a
transmission signal. When the video switch is in the internal mode, the identification of a transmitted signal is derived
from the coincidence detector.
In the external mode the IF part of the circuit has its own identification system. The system relies upon the detection of
sync. pulses on the incoming IF signal. The separated horizontal sync pulse charges the capacitor on pin 25 which drives
the mute output (pin 14).
The connection of a 1 MW resistor between pin 25 and VCC results in the mute information being overruled by the 50/60 Hz information derived from the internal vertical divider section.

50/60 Hz Information
In the external video mode and with a resistor of 1 MW from pin 25 to VCC the mute is overruled by the 50/60 Hz information from the divider system.

Video-switch
Video output from the demodulator is filtered to remove the audio carrier and DC-coupled to pin 16. If AC-coupling is
employed the internal noise clamp will operate on sync. tips.
The TDA4504B provides the opportunity for a direct video connection (e.g. via a peritel connector) to be made to the
device at pin 13. Selection between internal and external video is made by applying a switching potential to pin 18.
Video switch:
Gain reduction
To prevent crosstalk between the IF stages and the horizontal oscillator when the device is operated in its external video
mode with no RF input, the TDA4504B incorporates an option to reduce IF gain by 20 dB. This is accomplished by
connecting a 39 kW resistor between pin 17 and ground. Omission of this component results in the IF amplifier remaining
at full gain.
In the internal video mode the resistor must be disconnected to achieve the auto-VCR mode.

PINNING
PIN DESCRIPTION
1 black level internal video
2 AGC take over (output)
3 vertical ramp generator (output)
4 vertical drive (output)
5 vertical feedback (input)
6 tuner AGC (input)
7 ground
8 supply voltage
9 vision IF (input)
10 vision IF (input)
11 IF AGC (output)
12 start horizontal oscillator (output)/AFC polarity switch (input)
13 external video (input)
14 mute/50 / 60 Hz (output)
15 video switch (output)
16 internal video (input)
17 VCR switch (input)
18 video switch (input)
19 ground for some critical parts
20 video amplifier (output)
21 AFC (output)
22 AFC S/H, AFC switch (input)
23 vision demodulator tuned circuit
24 vision demodulator tuned circuit
25 coincidence detector/transmitter identification
26 horizontal oscillator
27 phase 1 detector (output)
28 sync separator (input)
29 horizontal drive (output)
30 sandcastle output/horizontal flyback (input)
31 phase 2 detector (output)
32 AGC system switch (input).

 Horizontal synchronization
The horizontal synchronization circuit
of the TDA4504B has been designed
as follows:
· The retrace of the horizontal
oscillator occurs during the
horizontal retrace and not during
the scan period. This has the
advantage that no interference will

be visible on the screen when
receiving weak input signals. Video
crosstalk will not disturb the phase
of the horizontal locking.
· Reduced frequency shift of the
horizontal oscillator due to noise
since the horizontal phase detector
reference signal is more
symmetrical and independent of
the supply voltage and
temperature.
· The phase detector current ratio for
strong and weak signals is
increased to obtain a better
performance during both VCR
playback and weak signal
reception. The switching level is
also independent of temperature
and supply voltage.
Vertical synchronization
Generation of the vertical sawtooth
(pin 3) is accomplished by a divider
that permits the production of a
vertical frequency of either 50 Hz or
60 Hz with freedom from adjustment,
amplitude correction and maximum
interference/disturbance protection.
A discriminator window checks the
vertical trigger pulse. When the
trigger pulse occurs before count 576,
the divider system operates in the
60 Hz mode otherwise the 50 Hz
mode is selected. (2 clock pulses
equal one horizontal line).
The divider section operates with
different reset windows. These
windows are activated via an up/down
counter. This increases its count by 1
for each occasion the separated
vertical sync pulse is within the
selected window. On each occasion
the vertical sync. pulse is not within
the selected window, the count is
reduced by 1.
LARGE (SEARCH) WINDOW; DIVIDER
RATIO BETWEEN 488 - 722
This mode is valid for the following
conditions:
1 divider locking to another
transmitter
2 divider ratio found, not within
the narrow window limits
3 up/down counter value of the
divider system operating in
narrow window mode, count
falls below 10.
NARROW WINDOW; DIVIDER RATIO
BETWEEN 522 - 528 (60 HZ) OR 622 -
628 (50 HZ)
The divider switches to this mode
when the up/down counter has
reached its maximum value of 15
approved vertical sync pulses. When
the divider operates in this mode and
a vertical sync pulse is missing within
the window, the divider is reset at the
end of the window and the count
lowered by 1. At a counter value
below 10, the divider switches to the
large window mode.
An anti-top flutter pulse is also
generated by the divider system. This
inhibits the horizontal phase-1
detector during the vertical sync
pulse. The width of this pulse
depends upon the divider mode. For
the large window mode the start is
generated at the divider reset. In the
narrow window mode the anti-top
flutter pulse starts at the beginning of
the first equalizing pulse. The anti-top
flutter pulse ends at count 10 for 50
Hz and count 12 for 60 Hz.
When out-of-sync is detected by the
coincidence detector, the divider is
switched to count 625. This results in
a stable vertical amplitude when no
input signal is available.FEATURES
· Gain controlled vision IF amplifier
· Synchronous demodulator for negative and positive
demodulation
· AGC detector operating on peak sync amplitude for
negative demodulation and on peak white level for
positive demodulation
· Tuner AGC
· AFC circuit with two control polarities and on/off-switch
· Video preamplifier
· Video switch to select either the internal video signal or
an external video signal
· Horizontal oscillator and synchronization circuit with two
control loops
· Vertical synchronization (divider system), ramp
generator and driver with automatic amplitude
adjustment for 50 and 60 Hz
· Transmitter identification (mute)
· Sandcastle pulse generation
· VCR/auto VCR switch
· Start-up circuit
· Vertical guard