The XONYCS COLOUR TV RECEIVER RC4020PS CHASSIS RECOR RC4021A is a monocarrier type. Note that all fundamental core parts are PHILIPS semiconductors based.
The chassis has a relatively simple design but is not necessarily the simplest.
..................And even if cheap.............It has some Rubycon capacitors in it...........................
transistor means operable in a first conducting mode and a second nonconducting mode, said transistor means coupled to said initialization signal source for conducting current upon receipt of an initialization signal therefrom;
a first inductor coupling said DC voltage source and said transistor means wherein energy is stored in said first inductor when said transistor means is rendered conducting following receipt of an initialization signal and energy is released therefrom following turn-off of said transistor means;
a second, grounded inductor in circuit with said first inductor and coupled by ground thereto and further coupled to said transistor means for storing the energy released by said first inductor by means of current flowing via ground from said first to said second inductor following the turn-off of said transistor means and providing said energy to said transistor means whereby said transistor means is again rendered conductive and energy is again stored in said first inductor in continuing the oscillation of said circuit; and
capacitor means coupling the junction of said first inductor and said transistor means to neutral ground potential, with the value of said capacitor means establishing the frequency of oscillation of said circuit.
2. The circuit of claim 1 wherein said transistor means comprises an NPN transistor including a collector coupled to said first inductor, a base coupled to said initialization signal source and said second inductor, and a grounded emitter.
3. The circuit of claim 2 further including resistor means coupling said second inductor to the base of said NPN transistor for limiting the current provided thereto.
4. The circuit of claim 1 wherein said initialization signal source is coupled to the base of said transistor means for providing said initialization signal thereto.
5. The circuit of claim 1 wherein said initialization signal source includes the combination of a third inductor inductively coupled to said first inductor and second transistor means coupled to said first transistor means for providing said initialization signal thereto.
6. The circuit of claim 1 wherein said first inductor forms a primary coil of a high voltage transformer for generating a high voltage pulsed output therefrom.
7. A self-oscillating high voltage, pulsed power supply comprising: a grounded, first DC voltage source;
first transistor means operable in a first conducting mode and a second nonconducting mode;
transformer means having a primary winding coupling said DC voltage source and said first transistor means and including first and second secondary windings inductively coupled to said primary winding, wherein energy is stored in said primary winding when said first transistor means is in said first conducting mode and energy is released therefrom when said first transistor means is in said second nonconducting mode with a high voltage output pulse provided to said second secondary coil when said first transistor means is in said second nonconducting mode;
initialization signal source means coupling said first secondary winding to said first transistor means for providing an initialization pulse thereto in response to said DC voltage source causing current to flow in the primary winding of said transformer means;
grounded inductor means in circuit with said primary winding of said transformer means and coupled by ground thereto and further coupled to said first transistor means for storing the energy released by said primary winding when said first transistor means is in said second nonconducting mode and providing said energy to said first transistor means whereby said first transistor means is again rendered conducting with energy again stored in said primary winding for continuing the oscillation of said power supply; and
capacitor means coupling the junction of said primary winding and said first transistor means to neutral ground potential, with the value of said capacitor means establishing the length of said high voltage output pulse.
8. The power supply of claim 7 wherein said first transistor means comprises an NPN transistor having a collector coupled to said primary winding, a base coupled to said initialization signal source means and said grounded inductor means, and a grounded emitter.
9. The power supply of claim 7 wherein said initialization signal source means includes the combination of a second DC voltage source and second transistor means coupled to said first secondary winding wherein said second transistor means is rendered conductive by said output pulse and is nonconductive in the absence of an output pulse from said first secondary winding.
10. The power supply of claim 7 further including a filter/rectifier network coupling said first secondary coil and said initialization signal source means.
11. The power supply of claim 7 further including resistor means coupling said grounded inductor means to said first transistor means for limiting the current provided thereto.
This invention generally relates to self-oscillating circuits and more specifically is directed to a free-running circuit particularly adapted for providing a periodic, pulsed output voltage.
In general, video information is displayed by a television receiver or a raster which is scanned horizontally at a first rate and scanned vertically at a second, generally slower rate. The received video information is presented as amplitude-modulated synchronizing pulses by which the raster scanning of the television receiver is synchronized with the information to be viewed. For proper picture framing, it is required that the horizontal sweep system be synchronized in frequency and phase of oscillation with the horizontal synchronizing signal transmitted from the broadcast station. This synchronization requirement is applicable not only in television receivers where the standardization of television waves establishes a predetermined relationship between horizontal and vertical synchronizing signals, but also in a video display as used in a computer terminal or in a data display presentation system which may be required to interface with a great variety of input synchronization signals.
Deflection circuits utilized in television receivers, and in CRT video displays in general, synchronize the deflection signals used to control the sweep of the electron beam therein with synchronizing pulses recovered from the composite video signal received by the television receiver or generated in the video display. The synchronized signals are typically generated by the charge-discharge cycle of a capacitor in generating a sawtooth current waveform having a predetermined period and magnitude. The ramp of the sawtooth current waveform is generally developed from the discharge of a capacitor while the capacitor is recharged during the retrace period. This sawtooth current waveform is applied to the CRT's deflection coils in causing the electron beam to sequentially and repetitively scan and retrace over the face plate of the CRT at the appropriate times.
The prior art discloses various approaches to deflection circuit design and, in particular, synchronization oscillator design to achieve synchronization of electron beam sweep with input synchronization pulses. Early attempts in this area utilized switching diodes in combination with a voltage source to alternately charge and discharge a capacitor. Later efforts employed switching transistors in CRT sawtooth current waveform generation circuits which resulted in improvements in switching speeds and power consumption. Still later work in this area gave rise to the development of silicon controlled rectifier (SCR) circuits formed of a semi-conductor assembly controlled by signals of small magnitude applied to a control electrode, or gate, and capable of operating at higher currents than that of normal rectifiers. The transistor and SCR CRT drive circuits, which generally took the form of multivibrator circuit combinations, were not without limitations. Transistorized multivibrators tended to be overly complicated while SCR oscillators suffered from instabilities, or drift, in the signal voltage levels required to initiate the transition to a stable oscillating state as well as requiring an outside source of high power signals to terminate the SCR's oscillatory state.
One example of an oscillator employed in the horizontal drive circuit of a video display is disclosed in U.S. Pat. No. 4,263,615 to Beaumont and Steinmetz. In this approach a variable time delay monostable multivibrator is triggered by the leading edge of the horizontal drive pulse, the clocked output signal of which is coupled to a precision astable multivibrator. Potentiometer adjustment of the monostable multivibrator provides for adjusting video information position with respect to raster scan while the astable multivibrator acts as the oscillator in synchronizing horizontal sweep circuitry to the horizontal input drive signal. The astable multivibrator is a free-running oscillator which oscillates at whatever frequency it is designed for until it receives an input synchronization signal, at which time it locks onto the frequency of the input synchronization signal which may be different that its original frequency. U.S. Pat. No. 4,253,117 to Kadlec discloses a system for increasing synchronization signal injection to a free-running multivibrator in the horizontal drive circuit of a video display for enhancing synchronization signal frequency capture range. By increasing sync signal frequency capture range, this system permits a video display such as used in a computer terminal or a data display presentation system to interface with a great variety of input sync signals. Another example of an oscillating circuit utilized in a video display is provided in U.S. Pat. No. 4,234,828 to Matthews wherein is disclosed an SCR-analogue dual coupled transistor vertical oscillator for synching the vertical sweep in a video display with a vertical synchronization input signal. This approach makes use of a coupled transistor configuration in combination with a capacitor for generating a precisely defined sawtooth voltage waveform for controlling vertical sweep and flyback with stable, free-running oscillation availabe at two, variable DC levels. The aforementioned systems involve the use of a multi-transistor multivibrator arrangement or a multi-transistor SCR analogue circuit arrangement for providing an oscillating output in response to a synchronization signal input.
The aforementioned self-oscillating circuits are responsive to sync signal inputs for driving a high voltage supply in the video display for controlling electron beam intensity and position therein. The high voltage power supply typically includes an isolation transformer. An example of a power supply designed for use in a television receiver is disclosed in U.S. Pat. No. 3,845,352 to Newman et al wherein the vertical deflection windings of the television receiver are coupled directly to the output of a push-pull amplifier comprising a complementary pair of electronic devices. Bipolar voltages for driving the complementary pair are derived from horizontal scanning signals by a pair of oppositely-poled secondary windings on the horizontal output transformer, or high voltage power supply. The unregulated high voltage input is thus controlled by the horizontal drive system for providing appropriate timing signals to horizontal deflection circuitry for controlling electron beam position on the face plate of the CRT. U.S. Pat. No. 4,261,032 to Cavigelli discloses a self-oscillating, high voltage DC power supply for a CRT. A charging circuit for an oscillator coil within the high voltage power supply is provided by means of a DC supply and a switching transistor connected between the coil and ground. A feedback coil inductively coupled to the oscillator coil and wound in the opposite direction is incorporated in the base drive circuit of the transistor switch. The feedback coil operates to open the switch by means of a current induced in the base drive circuit when the current in the feedback circuit reaches a predetermined level related to the current in the oscillator coil primary in regulating transistor operation.
The self-oscillating circuits and sawtooth generating high voltage supplies described above all make use of a plurality of inductively coupled transformer coils and/or multi-transistor multivibrating circuits. The present invention is intended to eliminate the complexity and expense of these approaches by providing a self-oscillating circuit comprised of a single transistor and a pair of isolated coils, one of which may be utilized as the primary of a high voltage sweep transformer to drive the CRT of a video display.
OBJECTS OF THE INVENTION
It is another object of the present invention to provide an improved self-oscillating circuit particularly adapted for use in a power supply for producing precisely controlled, periodic, high voltage output pulses.
Still another object of the present invention is to provide a free-running oscillator particularly adapted for driving cathode ray tube sweep circuitry in a video display.
A further object of the present invention is to provide an improved self-oscillating, high voltage DC power supply for energizing electronic apparatus such as cathode ray tubes and the like.
PHILIPS TDA3505 Video control combination circuit with automatic cut-off control:
The TDA3505 and TDA3506 are monolithic integrated circuits which perform video control functions in a PAL/SECAM
decoder. The TDA3505 is for negative colour difference signals −(R-Y), −(B-Y) and the TDA3506 is for positive colour
difference signals +(R-Y), +(B-Y).
The required input signals are: luminance and colour difference (negative or positive) and a 3-level sandcastle pulse for
control purposes. Linear RGB signals can be inserted from an external source. RGB output signals are available for
driving the video output stages. The circuits provide automatic cut-off control of the picture tube.
• Capacitive coupling of the colour difference and
luminance input signals with black level clamping in the
• Linear saturation control acting on the colour difference
• (G-Y) and RGB matrix
• Linear transmission of inserted signals
• Equal black levels for inserted and matrixed signals
• 3 identical channels for the RGB signals
• Linear contrast and brightness controls, operating on
both the inserted and matrixed RGB signals
• Peak beam current limiting input
• Clamping, horizontal and vertical blanking of the three
input signals controlled by a 3-level sandcastle pulse
• 3 DC gain controls for the RGB output signals (white
• Emitter-follower outputs for driving the RGB output
• Input for automatic cut-off control with compensation for
leakage current of the picture tube.
green storage capacitor for cut-off control
blue storage capacitor for cut-off control
positive supply voltage (+ 12 V)
blue storage for brightness
green storage for brightness
red storage for brightness
sandcastle pulse input
fast switch for RGB inputs
blue input (external signal)
green input (external signal)
red input (external signal)
saturation control input
colour difference input − (R-Y) or + (R-Y) respectively
colour difference input − (B-Y) or + (B-Y) respectively
contrast control input
brightness control input
white point adjustment, blue
white point adjustment, green
white point adjustment, red
ground (0 V)
control input for peak beam current limiting
automatic cut-off control input
storage capacitor for leakage current
red storage capacitor for cut-off control.
< 110 mA after warm-up.
Values are proportional to the supply voltage.
When V11-24< 0,4 V during clamping time - the black levels of the inserted RGB signals are clamped on the black
levels of the internal RGB signals.
When V11-24> 0,9 V during clamping time - the black levels of the inserted RGB signals are clamped on an internal
DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the
When pins 21, 22 and 23 are not connected, an internal bias voltage of 5,5 V is supplied.
Automatic cut-off control measurement occurs in the following lines after start of the vertical blanking pulse:
line 20: measurement of leakage current (R + G + B)
line 21: measurement of red cut-off current
line 22: measurement of green cut-off current
line 23: measurement of blue cut-off current
Black level of the measured channel is nominal; the other two channels are blanked to ultra-black.
All three channels blanked to ultra-black.
The cut-off control cycle occurs when the vertical blanking part of the sandcastle pulse contains more than 3 line
The internal blanking continues until the end of the last measured line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses, otherwise another control cycle begins.
The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate
the various pulses.
Blanked to ultra-black (−25%).
10. Pulse duration ≥ 3,5 µs.
PHILIPS TDA3653B TDA3653C Vertical deflection and guard circuit (90˚)
The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to
1.5 A peak-to-peak.
• Output stage
• Thermal protection and output stage protection
• Flyback generator
• Voltage stabilizer
• Guard circuit.
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.
PHILIPS TDA4650 Multistandard colour decoder, with negative colour difference output signals,
The TDA4650 is a monolitic
integrated multistandard colour
decoder for PAL, SECAM and NTSC
(3.58 and 4.43 MHz) with negative
colour difference output signals. The
colour-difference output signals are
fed to the TDA4660/TDA4661,
Switched capacitor delay line.
Identifies and demodulates PAL,
SECAM, NTSC 3.58 and NTSC 4.43
chrominance signals with:
– automatic standard identification
by sequential inquiry
– secure SECAM identification at
50 Hz only, with PAL priority
– four switched outputs for
chrominance filter selection and
– external service switch for
• PAL / NTSC demodulation
– H (burst) and V blanking
– PAL switch (disabled for NTSC)
– NTSC phase shift (disabled for
– PLL-controlled reference
– two reference oscillator crystals
on separate pins with automatic
– quadrature demodulator with
• SECAM demodulation
– quadrature-demodulator with a
single external reference tuned
– alternate line blanking, H and V
• Gain controlled chrominance
• ACC demodulation controlled by
• Internal colour-difference signal
output filters to remove the residual
Notes to the characteristics
For the SECAM standard, amplitude and H/2 ripple content of the CD signals (R−Y) and (B−Y) depend on the
characteristics of the external tuned circuit at pins 7 to 10. The resonant frequency of the external tuned circuit must
be adjusted such that the demodulated fo voltage level is zero in the −(B−Y) output channel at pin 3.
Now it is possible to adjust the quality of the external circuit such that the demodulated fo voltage level is zero in the
−(R−Y) output channel at pin 1. If necessary, the fo voltage level in the −(B−Y) output channel must be readjusted to
zero by the coil of the tuned circuit.
The external capacitors at the pins 2 and 4 (220 pF each) are matched to the internal resistances of the de-emphasis
network such that every alternate scanned line is blanked.
The fo frequencies of the 8.8 MHz crystal at pin 21, and the 7.2 MHz crystal at pin 19, can be adjusted when the
voltage at pin 17 is less than 0.5 V (burst OFF), thus providing double subcarrier frequencies of the chrominance
The inquiry sequence for the standard is: PAL − SECAM − NTSC (3.58 MHz) − NTSC (4.43 MHz).
PAL has priority with respect to SECAM, etc.
The super sandcastle pulse is compared with three internal threshold levels which are proportional to VP.
The present invention relates to an automatic mode detection for a TV broadcasting system (a broadcast system automatic-discriminating apparatus) which is provided in a multiple-system television receiver, automatically discriminates the television signals (TV signals) of different broadcast systems, and performs reception. 2. Description of the Related Art
A multiple-system television receiver, so as to deal with the different TV broadcast systems, for example, the NTSC broadcast system used in Japan, the PAL broadcast system used in Germany, the South American area, etc., the SECAM broadcast system used in France, etc. must discriminate the broadcast system by a certain means and operate the video receiver differently in accordance with each broadcast system.
Particularly in an area where TV signals of a plurality of broadcast systems can be received, in order to enable the viewer to watch the TV program without having to be concerned with the broadcast system, it is necessary to provide a broadcast system automatic-discriminating apparatus in which the broadcast system can be automatically discriminated on the TV receiver side, automatically discriminate the TV signals of the respective broadcast systems, and perform signal processing with respect to the TV signals by the methods in accordance with them.
In general, this type of broadcast system automatic-discriminating apparatus performs the automatic discrimination of the broadcast system according to the difference of the frequencies of the color sub-carrier waves (SC) provided for transferring the information of color in the TV signals of the respective broadcast systems.
PHILIPS TDA4565 Colour transient improvement circuit,
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
• Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
• A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
• Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
• Two Y output signals; one of 180 ns less delay.
PHILIPS TDA4661 Baseband delay line
The TDA4661 is an integrated baseband delay line circuit
with one line delay. It is suitable for decoders with
colour-difference signal outputs ±(R−Y) and ±(B−Y).
• Two comb filters, using the switched-capacitor
technique, for one line delay time (64 µs)
• Adjustment-free application
• No crosstalk between SECAM colour carriers (diaphoty)
• Handles negative or positive colour-difference input
• Clamping of AC-coupled input signals (±(R−Y) and
• VCO without external components
• 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 µs line)
• Sample-and-hold circuits and low-pass filters to
suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference
signals to suppress cross-colour.
PHILIPS PCA84C440 /401 8-bit microcontrollers with OSD and VST.
The 84C44X; 84C64X; 84C84X denotes the types:
• PCA84C440; 84C441; 84C443; 84C444
• PCA84C640; 84C641; 84C643; 84C644
• PCA84C840; 84C841; 84C843; 84C844.
which are 8-bit microcontrollers with On Screen Display
(OSD) and Voltage Synthesized Tuning (VST) functions.
All are members of the 84CXXX microcontroller family.
There are two oscillator types for the OSD function in the
various types, i.e.,
• RC oscillator: PCA84C440; 84C443; 84C640; 84C643;
• LC oscillator: PCA84C441; 84C444; 84C641; 84C644;
• 8-bit CPU, ROM, RAM, I/O in a single 42 leads shrink
• Over 80 instructions all of 1 or 2 cycles
• 29 quasi-bidirectional standard I/O port lines
• Configuration of I/O lines individually selected by mask
• External interrupt INT/T0
• 2 direct testable inputs T0 and T1
• 8-bit programmable timer/event counter
• 3 single level vectored interrupts (external,
• Power-on-reset and low voltage detector
• Single power supply
• 2 power reduction modes: Idle and Stop
• Operating temperature range: −20 to +70 °C
• Silicon gate CMOS fabrication process (SAC2).
Derivative features PCA84C640
Although the PCA84C640 is specifically referred to
throughout this data sheet, the information applies to all
the devices. The small differences between the 84C640
and the other devices are specified in the text and also
highlighted in Chapter 6.
The PCA84C640 comprises:
• The PCF84CXXXA processor core
• 6 kbytes mask-programmable program ROM
• 128 bytes RAM
• Multi-master I2C-bus interface
• AFC input for Voltage Synthesized Tuning
(VST; with 3-bit DAC and comparator)
• On Screen Display (OSD) facility for two rows of
• On Screen Display character set of 64 types
• Four programmable display dot sizes
• Half dot character rounding
• Seven colours for each character
• One 14-bit PWM output for VST
• Five 6-bit PWM outputs for analog controls
• Eight port lines with 10 mA LED drive capability
• 18 general purpose bidirectional I/O lines
plus 11 function-combined I/O lines
• 2 direct testable lines
• Programmable VSYNCN and HSYNCN input polarity
• RC oscillator for OSD function.
The Power-on-reset circuit monitors the voltage level of
VDD. If VDD remains below the internal reference voltage
level Vref (typically 1.3 V), the oscillator is inhibited.
When VDD rises above Vref, the oscillator is released and
the internal reset is active for a period of td (typically
Considering the VDD rise time, the following measures for
a correct Power-on-reset can be taken:
• If the VDD rises above the minimum operation voltage
before time period td is exceeded, no external
components are necessary (see Fig.6).
• If VDDhas a slow rise time, such that after the time
period (tVref+ td) has elapsed the supply voltage is still
below the minimum operation voltage (Vmin),
external components are required (see Figs 4 and 7).
To guarantee a correct reset operation, ensure that the
time constant RC ≥ 8 × tVDD.
A definite Power-on-reset can be realized by applying an
(external) RESET signal during power-on.
6-bit PWM DACs
Five PWM outputs are available for analog control
purposes e.g. volume, balance, brightness, saturation, etc.
The block diagram of a typical 6-bit PWM DAC is shown in
Fig.8. Each PWM output can generate pulses of
programmable length that have a repetition frequency of
1⁄64× fPWM, where fPWM =1⁄3× fXTAL.
PIN SELECTION FOR PWM OUTPUTS
The PWM outputs PWM1 to PWM5, share the same pins
as the Derivative Port lines DP0.1 to DP0.5.
Setting the (relevant PWM enable) bit PWMnE to:
• Logic 1, selects the relevant PWMx output function
• Logic 0, selects the relevant DP0.x Port function.
POLARITY OF THE PWM OUTPUTS
The polarity of all five PWM outputs is selected by the state
of the polarity control bit P6LVL.
Setting the control bit P6LVL to:
• Logic 0, sets the PWMx outputs to the default polarity
• Logic 1, inverts all the PWMx outputs.
ANALOG OUTPUT VOLTAGE
A DC voltage proportional to the PWM control setting may
be obtained by connecting an integrating network to each
of the PWM outputs (see Fig.9).
The analog value is calculated as follows:
• PWMDL is the decimal value of the contents of the
PWM data latch.
Therefore, the analog output voltage is:
HIGH time of the PWM pulse
repetition time of the PWM pulse
14-bit PWM DAC
The PCA84C640 has one 14-bit PWM DAC output (TDAC)
with a resolution of 16384 levels for Voltage Synthesized
Tuning. The PWM DAC (see Fig.10) consists of:
• 14-bit counter
• Two 7-bit DAC interface data latches (VSTH and VSTL)
• One 14-bit DAC data latch (VSTREG)
• Pulse control.
The polarity of output TDAC is selected with bit P14LVL.
Setting the bit P14LVL to:
• Logic 1, sets the TDAC output to the default polarity
• Logic 0, inverts the TDAC output.
The counter is continuously running and is clocked by f0.
The period of the clock,
The repetition time for one complete cycle of the counter:
The repetition time for one cycle of the lower 7-bits of the
Therefore, the number of tsub periods in a complete
cycle tr is:
DATA AND INTERFACE LATCHES
In order to ensure correct operation, interface data latch
VSTH is loaded first and then interface data latch VSTL.
The contents of:
• VSTH are used for coarse adjustment
• VSTL are used for fine adjustment.
At the beginning of the first tsub period following the loading
of VSTL, both data latches are loaded into data latch
VSTREG. After the contents of VSTH and VSTL are
latched into VSTREG, one tsub period is needed to
generate the appropriate pulse pattern.
To ensure correct DAC conversion, two (2) tsub periods
should be allowed before beginning the next sequence.
The coarse adjustment output (OUT1) is reset to LOW
(inactive) at the start of each tsub period.
It will remain LOW until the time
elapsed and then will go HIGH and remain so until the next
tsub period starts.
Fine adjustment is achieved by generating additional
pulses at the start of particular sub-periods (tsubn).
These additional pulses have a width of t0.
The sub-period in which a pulse is added is determined by
the contents of VSTL interface latch.
Table 3 gives the numbers of the tsubn, at the start of which
an additional pulse is generated, depending on the bit in
VSTL being a logic 0. When more than one bit is a logic 0
a combination of additional pulses are generated.
For example, if VSTL = 1111010, which is a combination
• VSTL = 1111110: sub-period 64, and
• VSTL = 1111011: sub-periods 16, 48, 80 and 112,
then additional pulses will be given in sub-periods
16, 48, 64, 80 and 112; this is illustrated in Fig.12.
If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,
then the TDAC output.
The AFC input is used to measure the level of the
Automatic Frequency Control signal. This is achieved by
comparing the AFC input signal with the output of a 3-bit
DAC as shown in Fig.14. DAC analog switches select one
of 8 resistor taps connected between VDD and VSS.
Consequently, eight different voltages may be selected
(see Table 4). The compare signal AFCC, can be tested to
determine whether the AFC input is higher or lower than
the DAC level.
The AFC input shares the same pin as the Derivative Port
line DP1.7. Setting the enable bit AFCE to:
• Logic 1, selects the AFC function
• Logic 0, selects the Derivative Port DP1.7 function.
ON SCREEN DISPLAY
• Display format: 2 rows × 16 characters
• Software controlled vertical and horizontal display
• 64 different (mask programmable) characters in ROM
• Black box background
• Four programmable display character sizes
• Four programmable character dot matrix sizes:
– 6 × 9 and 6 × 13
– 8 × 9 and 8 × 13
• Half-dot rounding for the whole screen
• 4 from 7 colours possible on screen
• Clock generator for On Screen Display function with:
– RC oscillator
– LC oscillator,
for the various types of PCA84C44X; 84C64X; 84C84X.
Horizontal display position control
The horizontal position counter is incremented every OSD
cycle after the programmed level of HSYNCN occurs at the
HSYNCN pin. The counter is reset when the opposite
polarity of the HSYNCN pulse is reached.
Vertical display position control
The vertical position counter is incremented every
HSYNCN cycle and is reset by the VSYNCN signal.
There are two types of oscillators available for the various
types. The oscillator is triggered on the trailing edge of
HSYNCN when the OSD logic is enabled and stops on the
following leading edge of HSYNCN.
The OSD oscillator must be externally adjusted to the
desired frequency (decreasing the OSD frequency gives
broader characters). Before the oscillation frequency can
be adjusted HSYNCN must be HIGH (if HLVL = 1).
Oscillation stops by setting the HSYNCN pin LOW when
HLVL = 1.
The RC oscillator is available in the types:
PCA84C440; 84C443; 84C640; 84C643;
The external RC network is connected between
pin 28 and VSS (see Fig.19).
The LC oscillator is available in the types:
PCA84C441; 84C444; 84C641; 84C644;
The external LC network is connected between
pins 28 and 29.