Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.

Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....
Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !

©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of
Engineer Frank Sharp. NOTHING HERE IS FOR SALE !

Sunday, October 6, 2013



The CHASSIS BE-4 is a higly advanced chassis developed around the MOTOROLA MC44007.
And A VIF Asic from PHILIPS.

Read here the descriptions of the circuits.

The STR-S5703 is specifically designed to meet the requirement
for increased integration and reliability in off-line quasi-resonant flyback
converters with indirect feedback. The device incorporates the primary
control and proportional drive circuit with a third-generation high-voltage
bipolar switching transistor.
Crucial system parameters such as maximum ON time and OFF
time are fixed during manufacture. Local control circuit decoupling and
layout are optimized within each device.
Cycle-by-cycle current limiting, under-voltage lock-out with hyster-
esis, over-voltage protection, and thermal shutdown protect these
devices during all normal and overload conditions. Over-voltage
protection and thermal shutdown are latched after a short delay. A
primary-side error amplifier with reference is included to facilitate
regulation from an auxiliary or bias winding of the power transformer. A
versatile triple-level inhibit circuit includes the OFF time synchronization
required to establish quasi-resonant operation. The inhibit function has
also been expanded to initiate operation in stand-by mode in which the
power supply delivers a small fraction of the steady-state output power.
The dual requirements of dielectric isolation and low transient thermal
impedance and steady-state thermal resistance are satisfied in an over-
molded single-in-line power package.
Proven in substantial volumes, this device and its fixed-frequency
counterparts represents a significant advance in off-line SMPS reliability
growth and integration. Similar devices with increased ratings are the
STR-S5707 and STR-S5708.
I Quasi-Resonant Operation for Low EMI and High Efficiency
I Output Power to 140 W
I Low-Power Output Standby Mode
I Indirect Feedback from Auxiliary Winding
Reduces External Component Count
I Pulse-by-Pulse Over-Current Protection
I Latched Over-Voltage and Thermal Protection
I Third-Generation Switching Transistor with Proportional Drive
I Maximum ON Time and Off Time Set During Manufacture
I Internal Under-Voltage Lockout with Hysteresis
I Over-Molded SIP with Integral Isolated Heat Spreader
Always order by complete part number: STR-S5703 .


The TDA8139 is a monolithic dual positive voltage
regulator designed to provide precision output volt-
ages of 5.1V and adjustable at currents up to
An internal reset circuit generates a reset pulse
when the output 1 decrease below the regulated
voltage value.
Output 2 can be disabled by TTL input.
Short circuit and thermal protections are included.

5.1V ± 2%
FROM 2.8 TO 16V

The TDA8139 is a dual voltage regulator with Reset
and Disable.
The two regulation parts are supplied from one
voltage reference circuit trimmed by zener zap
during EWS test. Since the supply voltage of this
last is connected at Pin 1 (VIN1), the regulator 2 will
not work if the Pin 1 is not supplied.
The outputs stages have been realized in dar-
lington configuration with a drop typical of 1.2V.
The disable circuit, switch-off the output 2 if a
voltage lower than 0.8V is applied at pin 4.
The Reset circuit checks the voltage at the output
1. If this one goes below VOUT - 0.25V (4.85V Typ.),
the comparator "a" (see Figure 1) discharges rap-
idly the capacitor Ce and the reset output goes at
once low. When the voltage at the OUT 1 rises
above VOUT -0.2V (4.9V Typ.), the voltage VCe
increases linearly to 2.5V corresponding to a delay
td following the low : td = Ce ⋅ 2.5V
(see figure 2),
then the reset output goes high again. To avoid
glitches in the reset output, the second comparator
"b" has a large hysteresis (1.9V).


The MC44002/7 is a highly advanced circuit which performs most of the
basic functions required for a color TV. All of its advanced features are under
processor control via an I2C bus, enabling potentiometer controls to be
removed completely. In this way the component count may be reduced
dramatically, allowing significant cost savings together with the possibility of
implementing sophisticated automatic test routines. Using the MC44002/7,
TV manufacturers will be able to build a standard chassis for anywhere in the
world. Additional features include 4 selectable matrix modes (primarily for
NTSC), fast beam current limiting and 16:9 display.
• Operation from a Single 5.0 V Supply; Typical Current Consumption
Only 120 mA
• Full PAL/SECAM/NTSC Capability (4 Matrix Modes)
• Dual Composite Video or S-VHS Inputs
• All Chroma/Luma Channel Filtering, and Luma Delay Line Are
Integrated Using Sampled Data Filters Requiring No External
• Filters Automatically Commutate with Change of Standard
• Chroma Delay Line is Realized with a 16 Pin Companion Device, the
• RGB Drives Incorporate Contrast and Brightness Controls and Auto
Gray Scale
• Switched RGB Inputs with Separate Saturation Control
• Auxiliary Y, R-Y, B-Y Inputs
• Line Timebase Featuring H-Phase Control, Time Constant and
Switchable Phase Detector Gain
• Vertical Timebase Incorporating Vertical Geometry Corrections
• 16:9 Display Mode Capability
• E-W Parabola Drive Incorporating Horizontal Geometry Corrections
• Beam Current Monitor with Breathing Compensation
• Analog Contrast Control, Allowing Fast Beam Current Limitation
• MC44007 Decoders PAL/NTSC Only

The MC44002/7 has
been designed to carry out all the processing of video
signals, display controls and timebase functions. There are
two video inputs which can be used for normal composite
video or separate Y and C inputs. In either case, the inputs
are interchangeable and selection is made via the I2C bus.
The video is decoded within the MC44002/7 and involves
separation, filtering, delay of the luminance part of the signal
and demodulation of the chroma into color difference signals.
The luminance (called Y1) together with the demodulated
R-Y and B-Y are all then brought out from the IC. The color
difference signals then enter the MC44140 which performs
color correction in PAL and the delay line function in SECAM.
Corrected color difference signals then re-enter the

The next stage is called the color difference stage where a
number of control functions are carried out together with
matrixing of the components to derive RGB signals. At this
point a number of auxiliary signals may also be switched in,
again all under MCU control. External RGB (text) and Fast
Commutate enter here; also an external luminance (Y2) may
be used instead of Y1. External R-Y and B-Y are switched in
via the delay line circuit to save pins on the main device. The
Y2 and External R-Y, B-Y will obviously be of considerable
benefit from the system point of view for use with external
The final stage of video processing is the RGB outputs which
drive the high voltage amplifiers connected to the tube
cathodes. These outputs are controlled by a sophisticated
digital servo-loop which is maintained and stabilized by a
sequentially sampled beam current feedback system.
Automatic gray scale control is featured as a part of this system.
Both horizontal and vertical timebases are incorporated
into the MC44002/7 and control is via the I2C bus. The
horizontal timebase employs a dual loop system of a PLL and
variable phase shifter, and the vertical uses a countdown
system. For the vertical, a field rate sawtooth is available
which is used to drive an external power amplifier with
flyback generator (usually a single IC). The line output
consists of a pulse which drives a conventional line output
stage in the normal way. The line flyback pulse is sensed and
used by the second loop for horizontal phase shift.
Where E-W correction is required, a parabola waveform is
available for this which, with the addition of a power amplifier,
can be used with a diode modulator type line output stage for
dynamic width and E-W control. The bottom of the EHT
overwinding is returned to the MC44002/7 and is used for
anode current monitoring.
Fast beam current limitation is also made possible by the
use of an analog contrast control.
A much more detailed description of each stage of the
MC44002/7 will be found in the next section. Information on
the delay line is to be found in its own data sheet.

The following information describes the basic operation of
the MC44002/7 IC together with the MC44140 chroma delay
line. The MC44002/7 is a highly advanced circuit which
performs all the video processing, timebase and display
functions needed for a modern color TV. The device employs
analog circuitry but with the difference that all its advanced
features are under processor control, enabling external
filtering and potentiometer adjustments to be removed
completely. Sophisticated feedback control techniques have
been used throughout the design to ensure stable operating
conditions and the absence of drift with age.
The IC described herein is one of a new generation of TV
circuits, which make use of a serial data bus to carry out
control functions. Its revolutionary design concept permits a
level of integration and degree of flexibility never achieved
before. The MC44002/7 consists of a single bipolar VLSI chip
which uses a high density, high frequency, low voltage
process called MOSAIC 1.5. Contained within this single 40
pin package is all the circuitry needed for the video signal
processing, horizontal and vertical timebases and CRT
display control for today’s color TV. Furthermore, all the user
controls and manufacturer’s set-up adjustments are under
the control of the processor I2C bus, eliminating the need for
potentiometer controls. The MC44002/7 offers an enormous
variety of different options configurable in software, to cater
to virtually any video standard or circumstance commonly
met. The decoder section offers full multistandard capability,
able to handle PAL, SECAM (MC44002 only) and NTSC
standards with 4 matrix modes available. Practically all the
filtering is carried out onboard the IC by means of sampled
data filters, and requires no external components or
Digital Interface
One of the most important features of MC44002/7 is the
use of processor control to replace external potentiometer
and filter adjustments. Great flexibility is possible using
processor control, as each user can configure the software to
suit their individual application. The circuit operates on a
bidirectional serial data bus, based on the well known I2C
bus. This system is rapidly becoming a world standard for the
control of consumer equipment.
I2C Bus
It is not within the scope of this data sheet to describe in
detail the functioning of the I2C bus. Basically, the I2C bus is
a two-wire bidirectional system consisting of a clock and a
serial data stream. The write cycle consists of 3 bytes of data
and 3 acknowledge bits. The first byte is the Chip Address,
the second the Sub-address to identify the location in the
memory, and the third byte is the data. When the address’
Read/Write bit is high, the second and third bytes are used to
transmit status flags back to the MCU.
Figure 6 shows a block diagram of the MC44002/7 Bus
Interface/Decoder. To begin with, the start bit is recognized
by means of the data going low during CLK high. This causes
the Counter and all the latches to be reset. For a write
operation, the Write address ($88) is read into the Shift
Register. If the correct address is identified, the Chip Address
Latch is set and at CLK 9 an acknowledge is sent.
The second byte is now read into the Shift Register and is
used to select the Sub-address. At CLK 18 a Sub-address
Enable is sent to the memory to allow the Data in the register
to be changed. Also, at CLK 18 another acknowledge is sent.
The third byte is now read into the Shift Register and the
Data bussed into the memory. The Data in the Sub-address
location already selected is then altered. A third acknowledge
is sent at CLK 27 to complete the cycle.
A Read address ($89) indicates that the MCU wants to
read the MC44002/7 status flags. In this instance, the
Read/Write Latch is set, causing the Memory Enable and
Subaddress Enable to be inhibited, and the flags to be written
onto the data line. Two of the status flags are permanently
wired one-high and one-low (O.K. and Fault), to provide a
check on the communication medium between the
MC44002/7 and the MCU.
At start-up the Counter is automatically reset and the Data
for each Sub-address is read in from the MCU. Only after the
entire memory contents have been transmitted, is Data 00
sent to register 00 to start the Horizontal Drive.
The MC44002/7 needs the full 27 clock cycles, or a stop
condition, to properly release the I2C bus.

Figure 7 shows a diagram of the MC44002/7 Memory
Map. It has 18 bytes of memory which are located at hex
sub-addresses 77 to 88. Sub-address 77 is used to set up the
vertical timebase mode of the IC and for S-VHS switching,
and consists of 8 separate data bits. The remaining 17 bytes
use the least significant 6-bits as an analog control register.
The contents of each are D/A converted, providing an analog
control current which is distributed to the appropriate part of
the circuit. Bits 6 and 7 are used singularly for switching
control functions.
Chroma Decoder
The main function of this section is to decode the incoming
composite video, which may be in any of the PAL, NTSC or
SECAM (MC44002 only) Standards, and to retrieve the
luminance and color difference signals. In addition, the signal
filtering and luma delay line functions are carried out in this
section by means of sampled data filters.
The entire decoder section operates in sampled data
mode using clocks generated by external crystals. The
oscillator, which is phase-locked in the usual way for
PAL/NTSC modes, provides the clock function for the whole
circuit. The crystals are selected by the MCU by means of a
control bit (XS). Only crystals appropriate to the standards
which are going to be received need to be fitted. A 17.7 MHz
crystal (4x PAL subcarrier) is used for PAL and SECAM
systems (50 Hz, 625 lines); and 14.3 MHz (4x NTSC
subcarrier) for the NTSC system (60 Hz, 525 lines). Nearly all
the filters, together with the luma delay line and peaking,
have been integrated, requiring no external components or
any adjustment. The filter characteristics are entirely
determined by the clocks and by capacitor ratios, and are
thus completely independent of variations in the
manufacturing process. The PAL/NTSC subcarrier PLL and
ACC loop filters have not been integrated in order to facilitate
testing. These filters consist of fixed external components.
Figure 8 is a block diagram of the main features of the
chroma decoder. Selection is first made between the Video 1
and Video 2 inputs. These may be either normal composite
video or separate luma and chroma which may enter the IC at
either pin. Commands from the MCU are used to route the
signals through the appropriate delay and filter sections.
In PAL/NTSC, a variable low pass filter, which can be
software bypassed (control bit T3), is then used to
compensate for IF filtering and the Q of the external sound
traps. Filter response is controlled by means of control bits
T1 and T2. It is not recommended to use this filter in SECAM
or in S–VHS, as luma–chroma delays will not be optimized.
Next, the video enters the luma path. The PAL/NTSC or
SECAM chroma signals are separated out by transversal
high pass filters. In SECAM mode, the chroma trap frequency
is dynamically steered to follow the instantaneous frequency
of the chroma.
Then, another transversal filter provides luma peaking,
which is also active in S–VHS mode. The high frequency
luma may be peaked (at about 3.0 MHz with the 17.7 MHz
crystal, and 2.4 MHz with the 14.3 MHz crystal) in 7 steps up
to a maximum of 8.5 dB, by a control word from the MCU.
Another control word is used to trim the delay in the luma
channel. Five steps of 56 ns (70 ns with the 14.3 MHz crystal)
are possible, giving a total programmable delay of 280 ns.
Steps 6 and 7 are used in S–VHS mode. The resulting
processed luma signal then proceeds to the color difference
section after being low–pass filtered by an active filter to
remove components of the crystal frequency, and twice that
frequency. The luma component (Y1) is made available at
Pin 29 for use with auxiliary external functions, as well as
When in the S–VHS mode, the S–VHS control bit controls
the signal paths. The luma signal bypasses the first section of
the luma channel, which contains the chroma trap. The
S–VHS chroma is passed directly to the PAL/NTSC decoder
without further filtering.
As all the delay and filter responses are determined by the
crystal, they automatically commute to the new standard
when the crystal is changed over. Thus, when the 14.3 MHz
clock is being used, the chroma trap moves to 3.58 MHz.
The filtered PAL/NTSC and SECAM chroma signals are
decoded by their respective circuits. The PAL/NTSC decoder
employs a conventional design, using ACC action for gain
control and the common double balanced multipliers to
retrieve the color difference signals. The SECAM decoder is
discussed in a separate subsection.

The actual decision as to a signal’s identity is made by the
MCU based on data provided by 3 flags returned to it,
namely: ACC Active, PAL Identified, and SECAM Identified.
Control bits SSA–SSD must be sent to set the decoder to
the correct standard.
This allows a maximum of flexibility, since the software
may be written to accommodate many different sets of
circumstances. For example, channel information could be
taken into account if certain channels always carry signals in
the same standard. Alternatively, if one standard is never
going to be received, the software can be adapted to this
circumstance. If none of the flags are on, color killing can be
implemented by the MCU. This occurs if the net Ident Signal
is too low, or if the ACC circuit is inactive due to too low a
signal level.
The demodulated color difference signals now enter the
Hue control section, where selection is made between
PAL/NTSC and SECAM outputs. The Hue control is simply
realized by altering the amplitudes of both color difference
signals together. Hue control is only a requirement in NTSC
mode and would not normally be used for other standards.
The function is usually carried out prior to demodulation of
the chroma by shifting the phase of the subcarrier reference,
causing decoding to take place along different axes. In the
MC44002/7, Hue control is performed on the already
demodulated color difference signals. A proportion of the R-Y
signal is added or subtracted to the B-Y signal and
vice-versa. This has the same effect as altering the reference
phase. If desired, the MC44002/7 can apply the Hue control
to simple PAL signals.
After manipulation by the Saturation and Hue controls, the
color difference signals are finally filtered to reduce any
remaining subcarrier and multiplier products. Before leaving
the chip at Pins 36 and 37, the signals are blanked during line
and frame intervals. The 64 ms chroma delay line is carried
out by a companion device, the MC44140.

Color Difference Stages
This stage accepts luminance and color difference
signals, together with external R,G,B and Fast Commutation
inputs and carries out various functions on them, including
clamping, blanking, switching and matrixing. The outputs,
consisting of processed R,G,B signals, are then passed to
the Auto Gray Scale section.
A block diagram of this stage is shown in Figure 10. The
Y2, R-Y, B-Y together with R, G and B are all external inputs
to the chip. The Y1 signal comes from the decoder section.
Each of the signals is back-porch clamped and then blanked.
The Y2 and R,G,B inputs have their own simple sync
separators, the output from which may be used as the
primary synchronization for the chip by means of commands
from the MCU.
The Fast Commutation is an active high input used to drive
a high speed switch; for switching between the Y and color
difference inputs and the R,G,B (text) inputs.
After blanking, the Y1 and Y2 channels go to the Luma
Selector which is controlled by means of 2 bits from the MCU.
From here the selected luma signal goes to the RGB matrix.
The two color difference signals pass through the saturation
control. From here they go to a matrix in which G-Y is
generated from the R-Y and B-Y, and lastly, to another matrix
where Y is added to the three color difference signals to
derive R,G,B.
Control bits (via the I2C bus) allow the matrix coefficients
to be adjusted in order to suit different requirements,
particularly in NTSC. Table 1 shows the theoretical
demodulation angles and amplitudes and the corresponding
matrix coefficient values for each of the 4 selectable modes.
(The A mode corresponds to the standard PAL/SECAM/NTSC
mode). Although primarily intended for NTSC, this feature can
also act on PAL/SECAM or external RGB signals.
The R,G,B inputs may take one of two different paths.
They may either go straight to the output without further
processing, or via a separate matrix and the saturation
control. The path taken is controlled in software. When the
latter route is selected, the R,G,B signals undergo a matrix
operation to derive Y. From this, R-Y and B-Y are easily
derived by subtraction from R and B; the derived color
difference signals are then subjected to saturation control.
This extra circuitry allows another feature to be added to the
TV set, namely the ability to adjust the color saturation of the
RGB inputs. After the saturation control the derived signals
are processed as before.

In order to implement automatic beam current limiting
(BCL), the possibility of fast contrast reduction has been
added. For normal operation, the Contrast control is
achieved by auto grey scale output loops and is I2C bus
controlled (see Section 4). In the case of excess beam
current, this control is not fast enough to protect the tube and
power supply stages. It is now possible, by acting on the
Pin 10 voltage, to reduce the contrast about 12 dB by
reducing the luma gain and saturation. In the case of direct
RGB mode, the RGB gains are also reduced.

Auto Gray Scale Control Loops
This section supplies current drives to the RGB cathode
amplifiers and receives a signal feedback from them,
proportional to the combined cathode currents. The current
feedback is used to establish a set of feedback loops to
control the dc level of the cathode voltage (cut–off), and gain
of the signal at the cathode (white balance). There are three
loops to control the dark currents dark loops and another
three to control the gains bright loops. The system uses 3
lines at the end of the vertical suppression period and just
before the beginning of the picture for sampling the cathode
current (i.e., one line for red, one for green and one for blue).
The first half of reach line is used for adjusting the gain of the
channel and is usually called the “bright” adjustment period.
The second half of the line is used for adjusting the dc level of
the channel and is called the “dark” adjustment.
The theoretical circuit diagram for one channel is shown in
Figure 13 along with the basic equations. The dc level (ldc)
and gain (G) are both controlled by 7 bit DACs which receive
data directly from latches in which the required values are
stored between sampling periods.

Horizontal Timebase
The horizontal timebase consists of a PLL which locks up
to the incoming horizontal sync, and a phase detector and
shifter whose purpose is to maintain the H-Drive in phase
with the line flyback pulse.
Because of on-chip component tolerances, the
free-running oscillator frequency cannot be set more
accurately than ± 40%; this range would be too much for the
line output stage to cope with. For this reason the
free-running frequency is calibrated periodically by other
means. During startup and whenever there is a channel
change, the phase detector is disconnected from the VCO for
2 lines during the blanking interval. A block diagram of the
line timebase is given in Figure 14. The calibration loop
consists of a frequency comparator driving an Up/Down
Counter. The count is D/A converted to give a dc bias which
is used to correct a 1.0 MHz VCO. The 1.0 MHz is divided by
64 to give line frequency and this is returned to the frequency
comparator. This compares Fh from the VCO with a
reference derived from dividing down the subcarrier
frequency. Any difference in frequency will result in an output
from the comparator, causing the counter to count up or
down; and thus closing the loop. Since the horizontal
oscillator is quite stable, this calibration does not need to be
carried out very often. After switch–on, the calibration loop
need only be enabled when the timebase goes out of lock.
A Coincidence Detector looks at the PLL Fh and compares
it with the incoming H-sync. If they are not in lock, a flag is
returned to the MCU. To allow for use with VCRs, the gain of
the phase detector may be switched by means of commands
from the MCU (bits HGAIN1 and HGAIN2). The gain of the
phase detector is switched to the maximum value at the end
of the vertical sync pulse and then reduced to the selected
value after about 11 lines. This allows the horizontal timebase
to rapidly compensate any horizontal phase jump (e.g. with a
VCR) during the vertical blanking period, thus avoiding
bending at the top of the picture.
Twice line frequency is output from the PLL which may be
divided by either 1 or 2 depending on the command of the
MCU. The x2 Fh will be used with Feature Boxes. The phase
of the Fh and flyback pulses are compared in a phase
detector, whose output drives a phase shifter. A 6-bit control
word and D/A converter are used to apply an offset to the
phase detector giving a horizontal phase shift control.
The presence of the horizontal flyback pulse is detected; if
it is missing a warning flag is sent back to the MCU which can
take appropriate action.
Vertical Timebase
The vertical timebase consists of two sections; a digital
section which includes a vertical sync separator and
standard recognition; and an analog section which generates
a vertical ramp which may be modified under MCU control to
allow for geometrical adjustments. A parabola is also
generated and may be used for pin-cushion (E-W) correction
and width control (see Figure 15).
In the digital section, the MC44002/7 uses a video sync
separator which works using feedback, such that the
threshold level of a comparator (slice level) is always
maintained at the center of the sync pulse. Sync from any of
the auxiliary inputs may also be used. The composite sync is
fed to a vertical sync separator, where vertical sync is
derived. This consists of a comparator, up/down counter and
decoder. The counter counts up when sync is high, and down
when sync is low. The output of the decoder is compared with
a threshold level, the threshold only being reached with a
high count during the broad pulses in the field interval.
When “Auto Countdown” is selected, the vertical timebase
in fact starts off in the “Injection Lock” mode. This means that
the timebase locks immediately to the first signal received, in
exactly the same way as an old type injection locked
timebase. A coincidence detector looks for counts of the right
number (525 e.g.), and causes a 4 bit counter to count up.
When there are 8 consecutive coincidences, the vertical
countdown is engaged, and the MSB of the counter is
brought out to set the flag. Similarly, non–coincidence, which
will occur if synchronizing pulses are missing or in the wrong
place, or if there is noise on the signals, causes the counter to
count down. When the count goes back to zero, after 8
noncoincidences, the timebase automatically reverts to
“Injection Lock” mode.
If it is known that lock will be lost (e.g., channel change), it
is possible to jump straight into Injection Lock mode and not
have to wait for the 8 consecutive non-coincidences. In this
way the new channel will be captured rapidly. Once locked on
to the new channel, “auto countdown” is then reselected by
the MCU.
Under some conditions such as some VCRs in Search
mode, it is possible to get signals having an incorrect number
of lines, meaning that the countdown flag will go off because
of successive non-coincidences. In these circumstances, if
“auto countdown” is selected, the timebase will automatically
lock to the signal in the Injection Lock mode.

PHILIPS TDA9806 Multistandard VIF-PLL and FM-PLL demodulator

· 5 V supply voltage
· Gain controlled wide band VIF-amplifier (AC-coupled)
· True synchronous demodulation with active carrier
regeneration (very linear demodulation,
good intermodulation figures, reduced harmonics,
excellent pulse response)
· Separate video amplifier for sound trap buffering with
high video bandwidth
· VIF AGC detector for gain control, operating as peak
sync detector for B/G
· Tuner AGC with adjustable takeover point (TOP)
· AFC detector without extra reference circuit
· AC-coupled limiter amplifier for sound intercarrier signal
· Alignment-free FM-PLL demodulator with high linearity,
switchable de-emphasis for FM
· Stabilizer circuit for ripple rejection and to achieve
constant output signals.
The TDA9806 is an integrated circuit for multistandard
vision IF signal processing and FM sound demodulation in
TV and VCR sets.

Vision IF amplifier
The vision IF amplifier consists of three AC-coupled
differential amplifier stages. Each differential stage
comprises a feedback network controlled by emitter
Tuner and VIF AGC
The AGC capacitor voltage is transferred to an internal IF
control signal, and is fed to the tuner AGC to generate the
tuner AGC output current (open-collector output). The
tuner AGC takeover point can be adjusted. This allows the
tuner and the SWIF filter to be matched to achieve the
optimum IF input level.
The AGC detector charges/discharges the AGC capacitor
to the required voltage for setting of VIF and tuner gain in
order to keep the video signal at a constant level.
Therefore for negative video modulation the sync level of
the video signal is detected.
Frequency Phase Locked Loop detector (FPLL)
The VIF-amplifier output signal is fed into a frequency
detector and into a phase detector via a limiting amplifier.
During acquisition the frequency detector produces a DC
current proportional to the frequency difference between
the input and the VCO signal. After frequency lock-in the
phase detector produces a DC current proportional to the
phase difference between the VCO and the input signal.
The DC current of either frequency detector or phase
detector is converted into a DC voltage via the loop filter,
which controls the VCO frequency.
VCO, travelling wave divider and AFC
The VCO operates with a resonance circuit (with L and C
in parallel) at double the PC frequency. The VCO is
controlled by two integrated variable capacitors. The
control voltage required to tune the VCO from its
free-running frequency to actually double the PC
frequency is generated by the Frequency-Phase detector
and fed via the loop filter to the first variable capacitor
(FPLL). This control voltage is amplified and additionally
converted into a current which represents the AFC output
signal. At centre frequency the AFC output current is equal
to zero.
The oscillator signal is divided-by-two with a Travelling
Wave Divider (TWD) which generates two differential
output signals with a 90 degree phase difference
independent of the frequency.
Video demodulator and amplifier
The video demodulator is realized by a multiplier which is
designed for low distortion and large bandwidth. The vision
IF input signal is multiplied with the ‘in-phase’ signal of the
travelling wave divider output.
The demodulator output signal is fed via an integrated
low-pass filter for attenuation of the carrier harmonics to
the video amplifier. The video amplifier is realized by an
operational amplifier with internal feedback and high
bandwidth. A low-pass filter is integrated to achieve an
attenuation of the carrier harmonics. The video output
signal is 1 V (p-p) for nominal vision IF modulation.
Video buffer
For an easy adaption of the sound traps an operational
amplifier with internal feedback is used. This amplifier is
featured with a high bandwidth and 7 dB gain. The input
impedance is adapted for operating in combination with
ceramic sound traps. The output stage delivers a nominal
2 V (p-p) positive video signal. Noise clipping is provided.
Intercarrier mixer
The intercarrier mixer is realized by a multiplier. The VIF
amplifier output signal is fed to the intercarrier mixer and
converted to intercarrier frequency by the regenerated
picture carrier (VCO). The mixer output signal is fed via a
high-pass for attenuation of the video signal components.

FM detector
The FM detector consists of a limiter, an FM-PLL and an
AF amplifier. The limiter provides the amplification and
limitation of the FM sound intercarrier signal before
demodulation. The result is high sensitivity and AM
suppression. The amplifier consists of 7 stages which are
internally AC-coupled in order to minimize the DC offset
and to save pins for DC decoupling.
The FM-PLL consists of an integrated relaxation oscillator,
an integrated loop filter and a phase detector. The
oscillator is locked to the FM intercarrier signal, output
from the limiter. As a result of locking, the oscillator
frequency tracks with the modulation of the input signal
and the oscillator control voltage is superimposed by the
AF voltage. The FM-PLL operates as an FM-demodulator.
The AF amplifier consists of two parts:
1. The AF preamplifier for FM sound is an operational
amplifier with internal feedback, high gain and high
common mode rejection. The AF voltage from the PLL
demodulator, by principle a small output signal, is
amplified by approximately 33 dB. The low-pass
characteristic of the amplifier reduces the harmonics of
the intercarrier signal at the sound output terminal, at
which the de-emphasis network for FM sound is
applied. An additional DC control circuit is
implemented to keep the DC level constant,
independent of process spread.
2. The AF output amplifier (10 dB) provides the required
output level by a rail-to-rail output stage. This amplifier
makes use of an input selector for switching to FM
de-emphasis or mute state, controlled by the mute
switching voltage.
Internal voltage stabilizer and 1¤2VP-reference
The bandgap circuit internally generates a voltage of
approximately 1.25 V, independent of supply voltage and
temperature. A voltage regulator circuit, connected to this
voltage, produces a constant voltage of 3.6 V which is
used as an internal reference voltage.
For all audio output signals the constant reference voltage
cannot be used because large output signals are required.
Therefore these signals refer to half the supply voltage to
achieve a symmetrical headroom, especially for the
rail-to-rail output stage. For ripple and noise attenuation
the 1¤2VP voltage has to be filtered via a low-pass filter by
using an external capacitor together with an integrated
resistor (fg = 5 Hz). For a fast setting to 1¤2VP an internal
start-up circuit is added.

PHILIPS SAA5288 TV microcontroller with full screen On Screen Display (OSD)

1.1 General
· On-chip TV control tuning
· Hardware and software compatible with SAA5290,
SAA5291 and SAA5296
· Single +5 V power supply
· RGB interface to standard decoder ICs, push-pull output
· SDIP52 package
· Single crystal oscillator for display and microcontroller.
1.2 Microcontroller
· 80C51 microcontroller core
· 16 kbyte mask programmed ROM
· 256 bytes of microcontroller RAM
· Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
· One 14-bit PWM for Voltage Synthesis tuner control
· Four 8-bit Analog-to-Digital Converters (ADCs)
· 2 high current open-drain outputs for directly driving
LED’s etc.
· Switchable bit or byte-oriented I2C-bus interface.
1.3 Display
· Single page (1024 ´ 8) on-board On Screen Display
(OSD) memory
· Double size width and height capability for OSD
· Enhanced display features including meshing,
shadowing and additional display attributes
· 260 characters in mask programmed ROM
· Display clock derived internally to reduce peripheral
components to a minimum
· Automatic FRAME output control with manual override
· Standby mode for display hardware
· 525-line and 625-line display
· 12 ´ 10 character matrix
· Stable Display via slave synchronization to Horizontal
Sync and Vertical Sync.
The SAA5288 is a microcontroller for use in televisions
with an OSD generator compatible with the Economy
Teletext/TV microcontroller family (SAA5290, SAA5291,
SAA5296 etc.). TV control facilities are provided by an
on-chip industry standard 80C51 microcontroller and a
1 kbyte DRAM is included for OSD memory.
Hardware and software compatibility with the Economy
Teletext/TV microcontroller family minimizes the changes
required to develop a TV control function for areas where
teletext is not broadcast.
The device cannot acquire Teletext but is based on a
Teletext device. Therefore, throughout this document
references are made to Teletext especially when
describing the Display/OSD section. The Display/OSD
section is fully compatible with a Teletext display and has
all the features associated with Teletext (i.e. double
height/width, flash, teletext boxes, graphics, etc.).
The Display section is described with reference to Teletext
to allow software compatibility with the Economy
Teletext/TV microcontroller family.

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