The CHASSIS GOLDSTAR PC04X is composed by 2 chassis sections. Bottom all Power, deflections, synch, video, VIF functions.
Left placed there is a board which carries TUNER, tuning functions, controls functions.
GENERAL BASIC TRANSISTOR LINE OUTPUT STAGE OPERATION:
The
basic essentials of a transistor line output stage are shown in Fig.
1(a). They comprise: a line output transformer which provides the d.c.
feed to the line output transistor and serves mainly to generate the
high -voltage pulse from which the e.h.t. is derived, and also in
practice other supplies for various sections of the receiver; the line
output transistor and its parallel efficiency diode which form a
bidirectional switch; a tuning capacitor which resonates with the line
output transformer primary winding and the scan coils to determine the
flyback time; and the scan coils, with a series capacitor which provides
a d.c. block and also serves to provide slight integration of the
deflection current to compensate for the scan distortion that would
otherwise be present due to the use of flat screen, wide deflection
angle c.r.t.s. This basic circuit is widely used in small -screen
portable receivers with little elaboration - some use a pnp output
transistor however, with its collector connected to chassis.
Circuit Variations:
Variations
to the basic circuit commonly found include: transposition of the scan
coils and the correction capacitor; connection of the line output
transformer primary winding and its e.h.t. ove
rwinding
in series; connection of the deflection components to a tap on the
transformer to obtain correct matching of the components and conditions
in the stage; use of a boost diode which operates in identical manner to
the arrangement used in valve line output stages, thereby increasing
the effective supply to the stage; omission of the efficiency diode
where the stage is operated from an h.t. line, the collector -base
junction of the line output transistor then providing the efficiency
diode action without, in doing so, producing scan distortion; addition
of inductors to provide linearity and width adjustment; use of a pair of
series -connected line output transistors in some large -screen colour
chassis; and in colour sets the addition of line convergence circuitry
which is normally connected in series between the line scan coils and
chassis. These variations on the basic circuit do not alter the basic
mode of operation however.
Resonance
The
most important fact to appreciate about the circuit is that when the
transistor and diode are cut off during the flyback period - when the
beam is being rapidly returned from the right-hand side of the screen to
the left-hand side the tuning capacitor together with the scan coils
and the primary winding of the line output transformer form a parallel
resonant circuit: the equivalent circuit is shown in Fig. 1(b). The line
output transformer primary winding and the tuning capacitor as drawn in
Fig. 1(a) may look like a series tuned circuit, but from the signal
point of view the end of the transformer primary winding connected to
the power supply is earthy, giving the equivalent arrangement shown in
Fig. 1(b).
The Flyback Period:
Since the operation of the
circuit depends mainly upon what happens during the line flyback period,
the simplest point at which to break into the scanning cycle is at the
end of the forward scan, i.e. with the
beam deflected to the right-hand side of the screen, see Fig. 2. At
this point the line output transistor is suddenly switched off by the
squarewave drive applied to its base. Prior to this action a linearly
increasing current has been flowing in the line output transformer
primary winding and the scan coils, and as a result magnetic fields have
been built up around these components. When the transistor is switched
off these fields collapse, maintaining a flow of current which rapidly
decays to zero and returns the beam to the centre of the screen. This
flow of current charges the tuning capacitor, and the voltage at A rises
to a high positive value - of the order of 1- 2k V in large -screen
sets, 200V in the case of mains/battery portable sets. The e
nergy
in the circuit is now stored in the tuning capacitor which next
discharges, reversing the flow of current in the circuit with the result
that the beam is rapidly deflected to the left-hand side of the screen -
see Fig. 3. When the tuning capacitor has discharged, the voltage at A
has fallen to zero and the circuit energy is once more stored in the
form of magnetic fields around the inductive components. One half -cycle
of oscillation has occurred, and the flyback is complete.
Energy Recovery:
First
Part of Forward Scan The circuit then tries to continue the cycle of
oscillation, i.e. the magnetic fields again collapse, maintaining a
current flow which this time would charge the tuning capacitor
negatively (upper plate). When the voltage at A reaches about -0.6V
however the efficiency diode becomes forward biased and switches on.
This damps the circuit, preventing further oscillation, but the magnetic
fields continue to collapse and in doing so produce a linearly decaying
current flow which provides the first part of the forward s
can,
the beam returning towards the centre of the screen - see Fig. 4. The
diode shorts out the tuning capacitor but the scan correction capacitor
charges during this period, its right-hand plate becoming positive with
respect to its left-hand plate, i.e. point A. Completion of Forward Scan
When the current falls to zero, the diode will switch off. Shortly
before this state of affairs is reached however the transistor is
switched on. In practice this is usually about a third of the way
through the scan. The squarewave applied to its base drives it rapidly
to saturation, clamping the vol
tage
at point A at a small positive value - the collector emitter saturation
voltage of the transistor. Current now flows via the transistor and the
primary winding of the line output transformer, the scan correction
capacitor discharges, and the resultant flow of current in the line scan
coils drives the beam to the right-hand side of the screen see Fig. 5.
Efficiency:
The
transistor is then cut off again, to give the flyback, and the cycle of
events recurs. The efficiency of the circuit is high since there is
negligible resistance present. Energy is fed into the circuit in the
form of the magnetic fields that build up when the output transistor is
switched on. This action connects the line output transformer
primary
winding across the supply, and as a result a linearly increasing current
flows through it. Since the width is
dependent on the supply voltage, this must be stabilised.
Harmonic Tuning:
There
is another oscillatory action in the circuit during the flyback period.
The considerable leakage inductance between the primary and the e.h.t.
windings of the line output transformer, and the appreciable self
-capacitance present, form a tuned circuit which is shocked into
oscillation by the flyback pulse. Unless this oscillation is controlled,
it will continue into and modulate the scan. The technique used to
overcome this effect is to tune the leakage inductance and the
associated capacitance to an odd harmonic of the line flyback
oscillation frequency. By doing this the oscillatory actions present at
the beginning of the scan cancel. Either third or fifth harmonic tuning
is used. Third harmonic tuning also has the effect of increasing the
amplitude of the e.h.t. pulse, and is generally used where a half -wave
e.h.t. rectifier is employed. Fifth harmonic tuning results in a
flat-topped e.h.t. pulse, giving improved e.h.t. regulation, and is
generally used where an e.h.t. tripler is employed to produce the e.h.t.
The tuning is mainly built into the line output transformer, though an
external variable inductance is commonly found in colour chassis so that
the tuning can be adjusted. With a following post I will go into the
subject of modern TV line timebases in greater detail with other models
and technology shown here at Obsolete Technology Tellye !
Supply is based on
TDA4601 (SIEMENS).
TDA4601 (SIEMENS)
Power supply Description based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN 
DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
THE TDA4600 is an IC Semiconductor circuit for sup
plying power to electrical equipment
includes a control circuit with a first terminal for reference voltage
connected, via a voltage divider formed of series connected resistances,
to the anode of a diode; a second terminal for zero-crossing
identification connected via a resistance to the cathode of the diode; a
third terminal serving as an actual value input directly connected to a
divider point of the voltage divider; a fourth terminal delivering a
sawtooth voltage connected via a resistance to a terminal of a
transformer primary winding; a fifth terminal serving as a protective
input connected via a resistance to the cathode of another diode and,
via two other resistances, to the cathode of a third diode having an
anode connected to an input of a rectifier circuit; a sixth terminal for
a reference potential connected via a capacitor to the fourth terminal
and via another capacitor to the anode of the first-mentioned diode; a
seventh terminal and an eighth terminal for respectively determining a
control pulse potential of and pulse-controlling a transistor both
connected via a resistance to a capacitor leading to the base of the
transistor; and a ninth terminal serving as a power-supply input
connected both to the cathode of the other diode and, via a capacitor,
to a respective terminal of two secondary windings of the transformer.
1.
Semiconductor circuit for supplying power to electrical equipment,
comprising a transformer having a primary winding connected, via a
parallel connection of a collector-emitter path of a transistor with a
first capacitor, to both outputs of a rectifier circuit supplied, in
turn, by a line a-c voltage; said transistor having a base controlled
via a second capacitor by an output of a control circuit acted upon, in
turn by the rectified a-c line voltage as actual value and by a
reference voltage; said transformer having a first secondary winding to
which the electrical equipment to be supplied is connected; said
transformer having a second secondary winding with one terminal thereof
connected to the emitter of said transistor and the other terminal
thereof connected to an anode of a first diode leading to said control
circuit; said transformer having a third secondary winding with one
terminal thereof connected, on the one hand, via a series connection of a
third capacitor with a first resistance, to the other terminal of said
third secondary winding and connected, on the other hand, to the emitter
of said transistor, the collector of which is connected to said primary
winding; a point between said third capacitor and said first resistance
being connected to the cathode of a second diode; said control circuit
having nine terminals including a first terminal delivering a reference
voltage and connected, via a voltage divider formed of a third and
fourth series-connected resistances, to the anode of said second diode; a
second terminal of said control circuit serving for zero-crossing
identification being connected via a fifth resistance to said cathode of
said second diode; a third terminal of said control-circuit serving as
actual value input being directly connected to a divider point of said
voltage divider forming said connection of said first terminal of said
control circuit to said anode of said second diode; a fourth terminal of
said control circuit delivering a sawtooth voltage being connected via a
sixth resistance to a terminal of said primary winding of said
transforme
r
facing away from said transistor; a fifth terminal of said control
circuit serving as a protective input being connected, via a seventh
resistance to the cathode of said first diode and, through the
intermediary of said seventh resistance and an eighth resistance, to the
cathode of a third diode having an anode connected to an input of said
rectifier circuit; a sixth terminal of said control circuit carrying
said reference potential and being connected via a fourth capacitor to
said fourth terminal of said control circuit and via a fifth capacitor
to the anode of said second diode; a seventh terminal of said control
circuit establishing a potential for pulses controlling said transistor
being connected directly and an eighth terminal of said control circuit
effecting pulse control of the base of said transistor being connected
through the intermediary of a ninth resistance to said first capacitor
leading to the base of said transistor; and a ninth terminal of said
control circuit serving as a power supply input of said control circuit
being connected both to the cathode of said first diode as well as via
the intermediary of a sixth capacitor to a terminal of said second
secondary winding as well as to a terminal of said third secondary
winding.
Description:
The invention relates to a blocking
oscillator type switching power supply for supplying power to electrical
equipment, wherein the primary winding of a transformer, in series
with
the emitter-collector path of a first bipolar transistor, is connected
to a d-c voltage obtained by rectification of a line a-c voltage fed-in
via two external supply terminals, and a secondary winding of the
transformer is provided for supplying power to the electrical equipment,
wherein, furthermore, the first bipolar transistor has a base
controlled by the output of a control circuit which is acted upon in
turn by the rectified a-c line voltage as actual value and by a
set-point transmitter, and wherein a starting circuit for further
control of the base of the first bipolar transistor is provided.
Such
a blocking oscillator switching power supply is described in the German
periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known
that the purpose of such a circuit is to supply electronic equip
ment,
for example, a television set, with stabilized and controlled supply
voltages. Essential for such switching power supply is a power switching
transistor i.e. a bipolar transistor with high switching speed and high
reverse voltage. This transistor therefore constitutes an important
component of the control element of the control circuit. Furthermore, a
high operating frequency and a transformer intended for a high operating
frequency are provided, because generally, a thorough separation of the
equipment to be supplied from the supply naturally is desired. Such
switching power supplies may be constructed either for synchronized or
externally controlled operation or for non-synchronized or free-running
operation. A blocking converter is understood to be a switching power
supply in which power is delivered to the equipment to be supplied only
if the switching transist
or
establishing the connection between the primary coil of the transformer
and the rectified a-c voltage is cut off. The power delivered by the
line rectifier to the primary coil of the transformer while the
switching transistor is open, is interim-stored in the transformer and
then delivered to the consumer on the secondary side of the transformer
with the switching transistor cut off.
In the blocking converter
described in the aforementioned reference in the literature, "Funkschau"
(1975), No. 5, Pages 40 to 44, the power switching transistor is
connected in the manner defined in the introduction to this application.
In addition, a so-called starting circuit is provided. Because several
diodes are generally provided in the overall circuit of a blocking
oscillator according to the definition provided in the introduction
hereto, it is necessary, in order not to damage these diodes, that due
to the collector peak current in the case of a short circuit, no
excessive stress of these diodes and possibly existing further sensitive
circuit parts can occur.
Considering the operation of a blocking
oscillator, this means that, in the event of a short circuit, the
number of collector current pulses per unit time must be reduced. For
this purpose, a control and regulating circuit is provided.
Simultaneously, a starting circuit must bring the blocking converter
back to normal operation when the equipment is switched on, and after
disturbances, for example, in the event of a short circuit. The starting
circuit shown in the literature reference "Funkschau" on Page 42
thereof, differs to some extent already from the conventional d-c
starting circuits. It is commonly known for all heretofore known
blocking oscillator circuits, however, that a thyristor or an equivalent
circuit replacing the thyristor is essential for the operation of the
control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of th
e
invention to provide a possible circuit for the control circuit which
is particularly well suited for this purpose. It is yet another object
of the invention to provide such a power supply which is assured of
operation over the entire range of line voltages from 90 to 270 V a-c,
while the secondary voltages and secondary load variations between
no-load and short circuit are largely constant.
With the
foregoing and other objects in view, there is provided, in accordance
with the invention, a blocking oscillator-type switching power supply
for supplying power to electrical equipment wherein a primary winding of
a transformer, in series with an emitter-collector path of a first
bipolar transistor, is connected to a d-c voltage obtained by
rectification of a line a-c voltage fed-in via two external supply
terminals, a secondary winding of the transformer being connectible to
the electrical equipment for supplying power thereto, the first bipolar
transistor having a base controlled by the output of a control circuit
acted upon, in turn, by the rectified a-c line voltage as actual value
and by a set-point transmitter, and including a starting circuit for
further control of the base of the first bipolar transistor, including a
first diode in the starting circuit having an anode directly connected
to one of the supply terminals supplied by the a-c line voltage and a
cathode connected via a resistor to an input serving to supply power to
the control circuit, the input being directly connected to a cathode of a
second diode, the second diode having an anode connected to one
terminal of another secondary winding of the transformer, the other
secondary winding having another terminal connected to the emitter of
the first bipolar transmitter.
In accordance with another feature of the inventio
n,
there is provided a second bipolar transistor having the same
conduction type as that of the first bipolar transistor and connected in
the starting circuit with the base thereof connected to a cathode of a
semiconductor diode, the semiconductor diode having an anode connected
to the emitter of the first bipolar transistor, the second bipolar
transistor having a collector connected via a resistor to a cathode of
the first diode in the starting circuit, and having an emitter connected
to the input serving to supply power to the control circuit and also
connected to the cathode of the second diode which is connected to the
other secondary winding of the transformer.
In accordance with a
further feature of the invention, the base of the second bipolar
transistor is connected to a resistor and via the latter to one pole of a
first capacitor, the anode of the first diode being connected to the
other pole of the first capacitor.
In accordance with an added
feature of the invention, the input serving to supply power to the
control circuit is connected via a second capacitor to an output of a
line rectifier, the output of the line rectifier being directly
connected to the emitter of the first bipolar transistor.
In
accordance with an additional feature of the invention, the other
secondary winding is connected at one end to the emitter of the first
bipolar transistor and to a pole of a third capacitor, the third
capacitor having a
nother
pole connected, on the one hand, via a resistor, to the other end of
the other secondary winding and, on the other hand, to a cathode of a
third diode, the third diode having an anode connected via a
potentiometer to an actual value input of the control circuit and, via a
fourth capacitor, to the emitter of the first bipolar transistor.
In
accordance with yet another feature of the invention, the control
circuit has a control output connected via a fifth capacitor to the base
of the first bipolar transistor for conducting to the latter control
pulses generated in the control circuit.
In accordance with a
concomitant feature of the invention, there is provided a sixth
capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although
the invention is illustrated and described herein as embodied in a
blocking oscillator type switching power supply, it is nevertheless not
intended to be limited to the details shown, since various modifications
and structural changes may be made therein without departing from the
spirit of the invention and within the scope and range of equivalents of
the claims.
The construction and method of operation of the
invention, however, together with additional objects and advantages
thereof will be best understood from the following description of
specific embodiments when read in connection with the accompanying
drawings, in which:
FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and
FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.
Referring
now to the drawing and, first, particularly to FIG. 1 thereof, there is
shown a rectifier circuit G in the form of a bridge current, which is
acted upon by a line input represented by two supply terminals 1' and
2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path
of an NPN power transistor T1 i.e. t
he
series connection of the so-called first bipolar transistor referred to
hereinbefore with a primary winding I of a transformer Tr. Together
with the inductance of the transformer Tr, the capacitance C1 determines
the frequency and limits the opening voltages of the switch embodied by
the first transistor T1. A capacitance C2, provided between the base of
the first transistor T1 and the control output 7,8 of a control circuit
RS, separates the d-c potentials of the control or regulating circuit
RS and the switching transistor T1 and serves for addressing this
switching transistor T1 with pulses. A resistor R1 provided at the
control output 7,8 of the control circuit RS is the negative-feedback
resistor of both output stages of the control circuit RS. It determines
the maximally possible output pulse current of the control circuit RS. A
secondary winding II of the transformer Tr takes over the power supply
of the control circuit, in steady state operation, via the diode D1. To
this end, the cathode of this diode D1 is directly connected to a power
supply input 9 of the control circuit RS, while the anode thereof is
connected to one terminal of the secondary winding II. The other
terminal of the secondary winding II is connected to the emitter of the
power switching transistor T1.
The cathode of the diode D1 and,
therewith, the power supply terminal 9 of the control circuits RS are
furthermore connected to one pole of a capacitor C3, the other pole of
which is connected to the output 3' of the rectifier G. The capacitance
of this capacitor C3 thereby smoothes the positive half-wave pulses and
serves simultaneously as an energy storage device during the starting
period. Another secondary windi
ng
III of the transformer Tr is connected by one of the leads thereof
likewise to the emitter of the first transistor T1, and by the other
lead thereof via a resistor R2, to one of the poles of a further
capacitor C4, the other pole of which is connected to the
first-mentioned lead of the other secondary winding III. This second
pole of the capacitor C4 is simultaneously connected to the output 3' of
the rectifier circuit G and, thereby, via the capacitor C3, to the
cathode of the diode D1 driven by the secondary winding II of the
transformer Tr as well as to the power supply input 9 of the control
circuit RS and, via a resistor R9, to the cathode of a second diode D4.
The second pole of the capacitor C4 is simultaneously connected directly
to the terminal 6 of the control circuit RS and, via a further
capacitor C 6, to the terminal 4 of the control circuit RS as well as,
additionally, via the resistor R6, to the other output 4' of the
rectifier circuit G. The other of the poles of the capacitor C4 acted
upon by the secondary winding II is connected via a further capacitor C5
to a node, which is connected on one side thereof, via a variable
resistor R4, to the terminals 1 and 3 of the control circuit RS, with
the intermediary of a fixed resistor R5 in the case of the terminal 1.
On the other side of the node, the latter and, therefore, the capacitor
C5 are connected to the anode of a third diode D2, the cathode of which
is connected on the one hand, to the resistor R2 mentioned hereinbefore
and leads to the secondary winding III of the transformer Tr and, on the
other hand, via a resistor R3 to the terminal 2 of the control circuit
RS.
The nine terminals of the control circuit RS have the following purposes or functions:
Terminal
1 supplies the internally generated reference voltage to ground i.e.
the nominal or reference value required for the control or regulating
process;
Terminal 2 serves as input for the oscillations provided
by the secondary winding III, at the zero point of which, the pulse
start of the driving pulse takes place;
Terminal 3 is the control
input, at which the existing actual value is communicated to the
control circuit RS, that actual value being generated by the rectified
oscillations at the secondary winding III;
Terminal 4 is
responsive to the occurrence of a maximum excursion i.e. when the
largest current flows through the first transistor T1 ;
Terminal 5
is a protective input which responds if the rectified line voltage
drops too sharply; Terminal 6 serves for the power supply of the control
process and, indeed, as ground terminal;
Terminal 7 supplies the
d-c component required for charging the coupling capacitor C2 leading
to the base of the first transistor T1 ;
Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and
Terminal 9 serves as the first terminal of the power supply of the control circuit RS.
Further details of the control circuit RS are described hereinbelow.
The
capacity C3 smoothes the positive half-wave pulses which are provided
by the secondary winding II, and simultaneously serves as an energy
storage device during the starting time. The secondary winding III
generates the control voltage and is simultaneously used
as
feedback. The time delay stage R2 /C4 keeps harmonics and fast
interference spikes away from the control circuit RS. The resistor R3 is
provided as a voltage divider for the second terminal of the control
circuit RS. The diode D2 rectifies the control pulses delivered by the
secondary winding III. The capacity C5 smoothes the control voltage. A
reference voltage Uref, which is referred to ground i.e. the potential
of terminal 6 is present at the terminal 1 of the control circuit RS.
The resistors R4 and R5 form a voltage divider of the input-difference
control amplifier at the terminal 3. The desired secondary voltage can
be set manually via the variable resistor R4. A time-delay stage R6 /C6
forms a sawtooth rise which corresponds to the collector current rise of
the first bipolar transistor T1 via the primary winding I of the
transformer Tr. The sawtooth present at the terminal 4 of the control
circuit RS is limited there between the reference voltage 2 V and 4 V.
The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the
control circuit RS the enabling voltage for the drive pulse at the
output 8 of the control circuit RS.
The diode D4, together with
the resistor R9 in cooperation with the diode D1 and the secondary
winding II, forms the starting circuit provided, in accordance with the
invention. The operation thereof is as follows:
After the
switching power supply is switched on, d-c voltages build up at the
collector of the switching transistor T1 and at the input 4 of the
control circuit RS, as a function in time of the predetermined time
constants. The positive sinusoidal half-waves charge the capacitor C3
via the starting diode D4 and the starting resistor R9 in dependence
upon the time constant R9.C3. Via the protective input terminal 5 and
the resisto
r
R11 not previously mentioned and forming the connection between the
resistor R9 and the diode D1, on the one hand, and the terminal 5 of the
control circuit RS, on the other hand, the control circuit RS is biased
ready for switching-on, and the capacitor C2 is charged via the output
7. When a predetermined voltage value at the capacitor C3 or the power
supply input 9 of the control circuit RS, respectively, is reached, the
reference voltage i.e. the nominal value for the operation of the
control voltage RS, is abruptly formed, which supplies all stages of the
control circuit and appears at the output 1 thereof. Simultaneously,
the switching transistor T1 is switched into conduction via the output
8. The switching of the transistor T1 at the primary winding T of the
transformer Tr is transformed to the second secondary winding II, the
capacity C3 being thereby charged up again via the diode D1. If
sufficient energy is stored in the capacitor C3 and if the re-charge via
the diode D1 is sufficient so that the voltage at a supply input 9 does
not fall below the given minimum operating voltage, the switching power
supply then remains connected, so that the starting process is
completed. Otherwise, the starting process described is repeated several
times.
In FIG. 2, there is shown a further embodiment of the
circuit for a blocking oscillator type switching power supply, according
to the invention, as shown in FIG. 1. Essential for this circuit of
FIG. 2 is the presence of a second bipolar transistor T2 of the type of
the first bipolar transistor T1 (i.e. in the embodiments of the
invention, an npn-transistor), which forms a further component of the
starting circuit and is connected with the collector-emitter path
thereof between the resistor R9 of the starting circuit and the current
supply input 9 of the control circuit RS. The base of this second
transistor T2 is connected to a node which leads, on the one hand, via a
resistor R10 to one electrode of a capacitor C7, the other electrode of
which is connected to the anode of the diode D4 of the starting circuit
and, accordingl
y,
to the terminal 1' of the supply input of the switching power supply G.
On the other hand, the last-mentioned node and, therefore, the base of
the second transistor T2 are connected to the cathode of a Zener diode
D3, the anode of which is connected to the output 3' of the rectifier G
and, whereby, to one pole of the capacitor C3, the second pole of which
is connected to the power supply input 9 of the control circuit RS as
well as to the cathode of the diode D1 and to the emitter of the second
transistor T2. In other respects, the circuit according to FIG. 2
corresponds to the circuit according to FIG. 1 except for the resistor
R11 which is not necessary in the embodiment of FIG. 2, and the missing
connection between the resistor R9 and the cathode of the diode D1,
respectively, and the protective input 5 of the control circuit RS.
Regarding the operation of the starting circuit according to FIG. 2,
it can be stated that the positive sinusoidal half-wave of the line
voltage, delayed by the time delay stage C7, R10 drives the base of the
transistor T2 in the starting circuit. The amplitude is limited by the
diode D3 which is provided for overvoltage protection of the control
circuit RS and which is preferably incorporated as a Zener diode. The
second transistor T2 is switched into conduction. The capacity C3 is
charged, via the serially connected diode D4 and the resistor R9 and the
collector-emitter path of the transistor T2, as soon as the voltage
between the terminal 9 and the terminal 6 of the control circuit RS i.e.
the voltage U9, meets the condition U9 <[UDs -UBE (T2)].
Because
of the time constant R9.C3, several positive half-waves are necessary
in order to increase the voltage U9 at the supply terminal 9 of the
control circuit RS to such an extent that the control circuit RS is
energized. During the negative sine half-wave, a partial energy
chargeback takes place from the capacitor C3 via the emitter-base path
of the transistor T2 of the starting circuit and via the resistor R10
and the capacitor C7, respectively, into the supply network. At
approximately 2/3 of the voltage U9, which is limited by the diode D3,
the control circuit RS is switched on. At the terminal 1 thereof, the
reference voltage Uref then appears. In addition, the voltage divider R5
/R4 becomes effective. At the terminal 3, the control amplifier
receives the voltage forming the actual value, while the first bipolar
transistor T1 of the blocking-oscillator type switching power supply is
addressed pulsewise via the terminal 8.
Because the capacitor C6
is charged via the resistor R6, a higher voltage than Uref is present at
the terminal 4 if the control circuit RS is activated. The control
voltage then discharges the capacitor C6 via the terminal 4 to half the
value of the reference voltage Uref, and immediately cuts off the
addressing input 8 of the control circuit RS. The first driving pulse of
the switching transistor T1 is thereby limited to a minimum of time.
The power for switching-on the control circuit RS and for driving the
transistor T1 is supplied by the capacitor C3. The voltage U9 at the
capacitor C3 then drops. If the voltage U9 drops below the switching-off
voltage value of the control circuit RS, the latter is then
inactivated. The next positive sine half-wave would initiate the
starting process again.
By switching the transistor T1, a voltage
is transformed in the secondary winding II of the transformer Tr. The
positive component is rectified by the diode D1, recharing of the
capacitor C3 being thereby provided. The voltage U9 at the output 9 does
not, therefore, drop below the minimum value required for the operation
of the control circuit RS, so that the control circuit RS remains
activated. The power supply continues to operate in the rhythm of the
existing conditions. In operation, the voltage U9 at the supply terminal
9 of the control circuit RS has a value which meets the condition U9
>[UDs -UBE (T2)], so that the transistor T2 of the starting circuit
remains cut off.
For the internal layout of the control circuit
RS, the construction shown, in particular, from FIG. 3 is advisable.
This construction is realized, for example, in the commercially
available type TDA 4600 (Siemens AG).
The block diagram of the control circuit according to FIG. 3
shows
the power supply thereof via the terminal 9, the output stage being
supplied directly whereas all other stages are supplied via Uref. In the
starting circuit, the individual subassemblies are supplied with power
sequentially. The d-c output voltage potential of the base current gain
i.e. the voltage for the terminal 8 of the control circuit RS, and the
charging of the capacitor C2 via the terminal 7 are formed even before
the reference voltage Uref appears. Variations of the supply voltage U9
at terminal 9 and the power fluctuations at the terminal 8/terminal 7
and at the terminal 1 of the control circuit RS are leveled or smoothed
out by the voltage control. The temperature sensitivity of the control
circuit RS and, in particular, the uneven heating of the output and
input stages and input stages on the semiconductor chip containing the
control circuit in monolithically integrated form are intercepted by the
temperature compensation provided. The output values are constant in a
specific temperature range. The message for blocking the output stage,
if the supply voltage at the terminal 9 is too low, is given also by
this subassembly to a provided control logic.
The outer voltage divider of the terminal 1 via the r
esistors
R5 and R4 to the control tap U forms, via terminal 3, the variable side
of the bridge for the control amplifier formed as a differential
amplifier. The fixed bridge side is formed by the reference voltage Uref
via an internal voltage divider. Similarly formed are circuit portions
serving for the detection of an overload short circuit and circuit
portions serving for the "standby" no-load detection, which can be
operated likewise via terminal 3.
Within a provided trigger
circuit, the driving pulse length is determined as a function of the
sawtooth rise at the terminal 4, and is transmitted to the control
logic. In the control logic, the commands of the trigger circuit are
processed. Through the zero-crossing identification at input 2 in the
control circuit RS, the control logic is enabled to start the control
input only at the zero point of the frequency oscillation. If the
voltages at the terminal 5 and at the terminal 9 are too low, the
control logic blocks the output amplifier at the terminal 8. The output
amplifier at the terminal 7 which is responsible for the base charge in
the capacitor C2, is not touched thereby.
The base current gain
for the transistor T1 i.e. for the first transistor in accordance with
the definition of the invention, is formed by two amplifiers which
mutually operate on the capacitor C2. The roof inclination of the base
driving current for the transistor T1 is impressed by the collector
current simulation at the terminal 4 to the amplifier at the terminal 8.
The control pulse for the transistor T1 at the terminal 8 is always
built up to the potential present at the terminal 7. The amplifier
working into the terminal 7 ensures that each new switching pulse at the
terminal 8 finds the required base level at terminal 7.
Supplementing
the comments regarding FIG. 1, it should also be mentioned that the
cathode of the diode D1 connected by the anode thereof to the one end of
the secondary winding II of the transformer Tr is connected via a
resistor R11 to the protective input 5 of the control circuit RS
whereas, in the circuit according to FIG. 2, the protective input 5 of
the control circuit RS is supplied via a voltage divider R8, R7 directly
from the output 3', 4' of the rectifier G delivering the rectified line
a-c voltage, and which obtains the voltage required for executing its
function. It is evident that the first possible manner of driving the
protective input 5 can be used also in the circuit according to FIG. 2,
and the second possibility also in a circuit in accordance with FIG. 1.
The
control circuit RS which is shown in FIG. 3 and is realized in detail
by the building block TDA 4600 and which is particularly well suited in
conjunction with the blocking oscillator type switching power supply
according to the invention has 9 terminals 1-9, which have the following
characteristics, as has been explained in essence hereinabove:
Terminal
1 delivers a reference voltage Uref which serves as the
constant-current source of a voltage divider R5.R4 which supplies the
required d-c voltages for the differential amplifiers provided for the
functions control, overload detection, short-circuit detection and
"standby"-no load detection. The dividing point of the voltage divider
R5 -R4 is connected to the terminal 3 of the control circuit RS. The
terminal 3 provided as the control input of RS is controlled in the
manner described hereinabove as input for the actual value of the
voltage to be controlled or regulated by the secondary winding III of
the transformer Tr. With this input, the lengths of the control pulses
for the switching transistor T1 are determined.
Via the input
provided by the terminal 2 of the control circuit RS, the zero-point
identification in the control circuit is addressed for detecting the
zero-point o
f
the oscillations respectively applied to the terminal 2. If this
oscillation changes over to the positive part, then the addressing pulse
controlling the switching transistor T1 via the terminal 8 is released
in the control logic provided in the control circuit.
A
sawtooth-shaped voltage, the rise of which corresponds to the collector
current of the switching transistor T1, is present at the terminal 4 and
is minimally and maximally limited by two reference voltages. The
sawtooth voltage serves, on the one hand as a comparator for the pulse
length while, on the other hand, the slope or rise thereof is used to
obtain in the base current amplification for the switching transistor
T1, via the terminal 8, a base drive of this switching transistor T1
which is proportional to the collector current.
The terminal 7 of
the control circuit RS as explained hereinbefore, determines the
voltage potential for the addressing pulses of the transistor T2. The
base of the switching transistor T1 is pulse-controlled via the terminal
8, as described hereinbefore. Terminal 9 is connected as the power
supply input of the control circuit RS. If a voltage level falls below a
given value, the terminal 8 is blocked. If a given positive value of
the voltage level is exceeded, the control circuit is activated. The
terminal 5 releases the terminal 8 only if a given voltage potential is
present.
Forei
gn References:
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.
Inventors:
Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)
TDA3562A (Philips)PAL/NTSC ONE-CHIP DECODER
GENERAL DESCRIPTION
The TDA3562A is a monolithic integrated decoder for the PAL and/or NTSC colour television standards. It combines all functions required for the identification and demodulation of PAL/NTSC signals. Furthermore it contains a ftuminance amplifier, an RGB-matrix and amplifier. These amplifiers supply output signals up to 4 V peak-to-peak (picture information) enabling direct drive of the discrete output stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for text display systerns (e.g. Teletext/broadcast Antiope), channel number display, etc.
Features
@ A black-current stabilizer which controls the black-currents of the three electron-guns to a level low enough to omit the black-level adjustrnent
@ Contrast control of inserted RGB signals
@ No black-level disturbance when non-synchronized external RGB signals are available on the inputs
® NTSC capability with hue control
FUNCTIONAL DESCRIPTION
Luminance amplifier The lurninance amplifier is voltage driven and requires an input signal of 450 mV peak-to-peak (positive video).
The luminance delay line must be connected between the i.f. amplifier and the decoder. The input signal is a.c. coupled to the input (pin 8). After amplification, the black level at the output of the preamplifier is clamped to a fixed d.c. level by the black level clarnping circuit. During three line periods after vertical blanking, the luminance signal is blanked out and the black tevel reference voitage is inserted by a switching circuit. This black level reference voltage is controlled via pin 11 (brightness). At the same tirne the RGB signals are clamped. Noise and residual signals have no influence during clamping thus simple internal clamping circuitry is used. Chrominance amplifiers The chrominance amplifier has ari asymmetrical input.
The input signa! must be a.c. coupled (pin 4) and have a minimum amplitude of 40 mV peak-to-peak. The gain control stage has a control range in excess of 30 dB, the maximum input signal must not exceed 1,1 V peak-to-peak, otherwise clipping of the input signal will occur. From the gain control stage the chrominance signal is fed to the saturation control stage. Saturation is linear controlled via pin 5. The control voltage range is 2 to 4 V, the input impedance is high and the saturation control range is in excess of 50 dB. The burst signal is not affected by saturation control. The signal is then fed to a gated amplifier which has a 12 dB higher gain during the chrominance signal. As a result the signal at the output (pin 28) has a burst to chrominance ratio which is 6 dB lower than that of the input signal when the saturation control is set at —6 dB. The chrominance output signal is fed tc the delay line and, after matrixing, is applied to the demodulator input pins (pins 22 and 23). These signals are fed to the burst phase detector. Oscillator and identification circuit
The burst phase detector is gatecl with the narrow part of the sandcastle pulse (pin 7). In the detector the (R-Y) and (B-Y) signals are added to provide the composite burst signal again. This composite signal is compared with the oscillator signal divided-by-2 (R-Y) reference signal. The control voltage is available at pins 24 and 25, and is also applied to the 8,8 MHz oscillator. The 4,4 MHz signal is obtained via the divide-by-2 circuit, which generates both the (B-Y) and (R-Y} reference signals and provides a 90° phase shift between them. The flip-flop is driven by pulses obtained from the sandcastle detector. For the identification of the phase at PAL mode, the (R-Y) reference signal coming from the PAL switch, is compared to the vertical signal (R-Y) of the PAL delay line. This is carried out in the H/2 detector, which is gated during burst.
When the phase is incorrect, the flip-flop gets a reset from the identification circuit. When the phase is correct, the output voltage of the H/2 detector is directly related to the burst amplitude so that this voltage can be used for the a.c.c. To avoid ‘blooming-up’ of the picture under weak input signal conditions the a.c.c. voltage is generated by peak detection of the H/2 detector output signal. The killer and identification circuits get their information from a gated output signal of the H/2 detector. Killing is obtained via the saturation control stage and the demodulators to obtain good suppression. The time constant of the saturation contro! (pin 5) provides a delayed switch-on after killing. Adjustrnent of the oscillator is achieved by variation of the burst phase detector load resistance between pins 24 and 25 (see Fig. 7). With this application the trimmer capacitor in series with the 8,8 MHz crystal (pin 26) can be replaced by a fixed value capacitor to compensate for unbalance of the phase detector.
Demodulator The (R-Y) and (B-Y) demodulators are driven by the colour difference signals from the delay-line matrix circuit and the reference signals from the 8,8 MHz divider circuit. The (R-Y) reference signal is fed via the PAL-switch.
The output signals are fed to the R and B matrix circuits and to the (G-Y) matrix to provide the (G-Y) signal which is applied to the G-matrix. The demodulation circuits are killed and blanked by by-passing the input signals. NTSC mode The NTSC mode is switched on when the voltage at the burst phase detector outputs (pins 24 and 25) is adjusted below 9 V. To ensure reliable application the phase detector load resistors are external. When the TDA3562A is used only for PAL these two 33 kQ resistors must be connected to +12 V (see Fig. 7). For PAL/NTSC application the value of each resistor must be recluced to 10 k& and connected to the slider of a potentiometer (see Fig. 8). The switching transistor brings the voltage at pins 24 and 25 below 9 V which switches the circuit to the NTSC mode.
The position of the PAL flip- flop ensures that the correct phase of the (R-Y) reference signal is supplied to the (R-Y) dernodulator. The drive to the H/2 detector is now provided by the (B-Y) reference signal. In the PAL. mode it is driven by the (R-Y) reference signal. Hue control is realized by changing the phase of the reference drive to the burst phase cletector. This is achieved by varying the voltage at pins 24 and 25 between 7,5 and 8,5 V, nominal position 8,0 V. The hue control characteristic is shown in Fig. 5. RGB matrix and amplifiers The three matrix and amplifier circuits are identical and only one circuit will be described.
The luminance and the colour difference signals are added in the matrix circuit to obtain the colour signal, which is then fed to the contrast control stage. The contrast control voltage is supplied to pin 6 (high-input impedance). The control range is +5 dB to —15 dB nominal. The relationship between the control voltage and the gain is linear (see Fig. 2). During the 3-line period after blanking a pulse is inserted at the output of the contrast control stage. The amplitude of this pulse is varied by a control voltage at pin 11. This applies a variable offset to the normai black level, thus provicling brightness control.
The brightness control range is 1 V to 3 V. While this offset level is present, the ‘black-current’ input impedance (pin 18) is high and the internal clamp circuit is activated. The clamp circuit then compares the reference voltage at pin 19 with the voltage developed across the external resistor network RA and Rp (pin 18) which is provided by picture tube beam current. The output of the comparator is stored in capacitors connected from pins 10, 20 and 21 to ground which controls the black level at the output. The reference voltage is composed by the resistor divider network and the leakage current of the picture tube into this bleeder. During vertical blanking, this voltage is stored in the capacitor connected to pin 19, which ensures that the leakage current of the CRT does not influence the black current measurement. The FGB output signals can never exceed a level of 10 V. When the signal tends to exceed this level the output signal is clipped. The black level at the outputs (pins 13, 15 and 17) will be about 3 V.
This tevel depends on the spread of the guns of the picture tube. If a beam current stabilizer is not used it is possible to stabilize the biack levels at the outputs, which in this application must be connected to the black current measuring input (pin 18} via a resistor network.
Data insertion
Each colour amplifier has a separate input for data insertion. A 1 V peak-to-peak input signal provides
a4 V peak-to-peak output signal. To avoid the ‘black-level’ of the inserted signal differing from the
black level of the normal video signal, the data is clamped to the black level of the luminance signal.
Therefore a.c. coupling is required for the data inputs.
To avoid a disturbance of the blanking level due to the clamping circuit, the source impedance of the driver circuit must not exceed 150 22.
The data insertion circuit is activated by the data blanking input (pin 9). When the voltage at this pin
exceeds a level of 0,9 V, the RGB matrix circuits are switched off and the data amplifiers are switched
on. To avoid coloured edges, the clata blanking switching time is short.
The amplitude of the data output signals is controlled by the contrast control at pin 6. The black level
is equal to the video black level and can be varied between 2 and 4 V (nominal condition) by the brightness control voltage at pin 11.
Non-synchronized data signals do not disturb the black level of the internal signals.
Blanking of RGB and data signals
Both the RGB and data signals can be blanked via the sandcastle input (pin 7). A slicing level of 1,5 V
is used for this blanking function, so that the wide part of the sandcastle pulse is separated from the
remainder of the pulse. During blanking a level of + 1 V is available at the output.
THE PHILIPS TDA3562A Circuit arrangement for the control of a picture tube :
Other References:
The TDA3562A by Joseph Cieszynski, Television Oct. 1987 pp. 834-835.
An Automatic Kinescope Biasing System, by J. C. Tallent, II, et al.
TDA3562A,
eine Farbdecoderschaltung mit Sperrpunktregelung-Technische Information
820705", May 7, 1982, Valvo, Hamburg, Germany, pp. 1-6, 9-14, 23-28.
1. Circuit arrangement for the control of at least one beam current in a picture tube by a picture comprising
a control loop which in one sampling interval obtains a measuring
signal from the value of the beam current on the occurrence of a given
reference level in the picture signal, stores a control signal derived
therefrom until the next sampling interval and thereby adjusts the beam
current to a value preset by a reference signal.
and a trigger circuit which suppresses auxiliary pulses used to
generate the beam current after the picture tube has been started up
and issues a switching signal for the purpose of closing the control
loop during the sampling intervals and for releasing the control of the
beam current by the picture signal after the measuring signal has
exceeded the threshold value,
a change detection arrangement which delivers a change signal when the stored signal has assumed a largely constant value, and
a
logic network which does not release the control of the beam current
by the picture signal outside the sampling intervals until the change
signal has also been issued after the switching signal.
2. Circuit arrangement as set forth in claim 1, in which the picture
signal comprises several color signals for the control of a
corresponding number of beam currents for the display of a color
picture in the picture tube and the control loop stores a part measuring
signal or a part control signal derived therefrom for each color
signal, characterized in that the change detection arrangement includes a
change detector for each color signal which delivers a part change
signal when the relevant stored signal has assumed a largely constant
value, and the logic network does not release the control of the beam
currents by the color signals outside the sampling intervals until the
part change signals have been delivered by all change detectors.
3. Circuit arrangement as set forth in claim 1, including a comparator
arrangement which compares the measuring signal with the reference
signal and derives the control signal from this comparison,
characterized in that the change detection arrangement detects a change
in the control signal with respect to time and issues the change
signal when the control signal has assumed a largely constant value.
4. Circuit arrangement as set forth in claims 1, 2, 3 including a
control signal memory which contains at least one capacitor,
characterized in that the change detection arrangement delivers the
change signal when a charge-reversing current of the capacitor occuring
during the starting up of the picture tube falls below a limit value.
5. Circuit arrangement as set forth in claim 2, including a comparator
arrangement which compares the measuring signal with the reference
signal and derives the control signal from this comparison,
characterized in that the change detection arrangement detects a change
in the control signal with respect to time and issues the change
signal when the control signal has assumed a largely constant value.
Description:
BACKGROUND OF THE INVENTION
The invention r
elates
to a circuit arrangement for the control of at least one beam current
in a picture tube by a picture signal with a control loop which in one
sampling interval obtains a measuring signal from the value of the beam
current on the occurrence of a given reference level in the picture
signal, stores a control signal derived therefrom until the next
sampling interval and by this means adjusts the beam current to a value
preset by a reference signal, and with a trigger circuit which
suppresses auxiliary pulses used to generate the beam current after the
picture tube is turned on and issues a switching signal for the purpose
of closing the control loop during the sampling intervals and
releasing the control of the beam current by the picture signal after
the measuring signal has exceeded a threshold value.
Such a circuit arrangement has been described in Valvo Technische
Information 820705 with regard to the integrated color decoder circuit
PHILIPS TDA3562A and is used in this as a so-called cut-off point
control. In the known circuit arrangement, such a cut-off point control
provides automatic compensation of the so-called cut-off point of the
picture tube, i.e. it regulates the beam current in the picture tube in
such a way that for a given reference level in the picture signal the
beam current has a constant value despite tolerances and changes with
time (aging, thermal modifications) in the picture tube and the circuit
arrangement, thereby ensuring correct picture reproduction.
Such a blocking point control is particularly advantageous for the
operation of a picture tube for the display of color pictures because
in this case there are several beam currents for different color
components of the color picture which have to be in a fixed ratio with
one another. If this ratio changes, for example, as the result of
manufacturing tolerances or ageing processes, distortions of the colors
occur in the reproduction of the color picture. The beam currents,
therefore, have to be very accurately balanced. The said cut-off point
control prevents expensive adjustment and maintenance time which is
otherwise necessary.
Conventional picutre tubes are constructed as cathode-ray tubes with
hot cathodes which require a certain time after being turned on for the
hot cathodes to heat up. Not until a final operating temperature has
been reached do these hot cathodes emit the desired beam currents to
the full extent, while gradually rising beam currents occur in the time
interval when the hot cathodes are heating up. The instantaneous
values of these beam currents depend on the instantaneous temperatures
of the hot cathodes and on the accelerating voltages for the picture
tube which build up simultaneously with the heating process and are
undefined until the end of the heating time. After the picture tube is
turned on, these values initially produce a highly distorted picture
until the beam currents have attained their final value. These picture
distortions after the picture tube is turned on are even further
intensified by the fact that the cut-off point control is not yet
adjusted to the beam currents which flow after the heating time is
over.
For the purpose of suppressing distorted pictures during the heating
time of the hot cathodes, the known circuit arrangement has a turn-on
delay element
operating
as a trigger circuit which, in essence, contains a bistable flip-flop.
When the picture tube and the circuit arrangement controlling the beam
currents flowing in it are turned on, the flip-flop is switched into a
first state in which it interrupts the supply of the picture signal to
the picture tube. Thus, during the heating time the beam currents are
suppressed, and the picture tube does not yet display any picture. In
sampling intervals which are provided subsequent to flybacks of the
cathode beam into an initial position on the changeover from the
display of one picture to the display of a subsequent picture and even
within the changeover, that is outside the display of pictures, the
picture tube is controlled for a short time in such a way that beam
currents occur when the hot cathodes are sufficiently heated up and an
accelerating voltage is resent. If these currents exceed a certain
threshold value, the flip-flop circuit switches into a second state and
releases the picture signal for the control of the beam currents and
the cut-off point control.
It is found, however, that the picture displayed in the picture tube
immediately after the switching over of the flip-flop is still not
fault-free. Because, in fact, the beam currents are supported during
the heating time of the hot cathodes, the cut-off point control cannot
respond yet. This response of the cut-off point control takes place
only after the beam currents are switched on, i.e. after the flip-flop
is switched into the second state and therefore at a time in which the
picture signal already controls the beam currents. In this way the
response of the blocking point control makes its presence felt in the
picture displayed.
With the known circuit arrangement the brightness of the picture
gradually increases, during the response of the cut-off point control,
from black to the final value.
This slow increase in the picture brightness after the tube is turned
on is disturbing to the eyes of the viewer not only in the case of the
black-and-white picture tubes with one hot cathode, but especially so
in the case of colour picture tubes which usually have three hot
cathodes. With a color picture tube, color purity errors can also
occur
in addition to the change in the picture brightness if, as a result of
different speeds of response of the cut-off point control for the
three beam currents, there are found to be intermittent variations from
the interrelation between the beam currents required for a correct
picture reproduction.
In a cathode ray tube, an electron gun comprises a cathode heated by a
heater filament, a first grid, a second grid, and further grids for
focussing an electron beam emitted by the cathode. In a color cathode
ray tube, three electron guns may be present, each of which generates an
electron beam which is deflected to hit the corresponding one of three
phosphors which emit light of different colors. The beam current (the
number of electrons in the electron beam, also referred to as cathode
current) is largely dependent on a voltage difference between the
cathode and the first grid. However, the second grid voltage also has an
influence on the beam current, but this influence is substantially less
pronounced. The beam current may be modulated by varying the cathode
voltage in dependence on the video information to be displayed. At a
voltage difference of zero volts between the cathode and the first grid,
the maximal beam current flows. When the voltage on the cathode becomes
more positive with respect to the first grid, the beam current
decreases. At a certain value of the cathode voltage the beam current
becomes exactly zero. The corresponding voltage difference between the
cathode and the first grid is generally referred to as the cut-off
voltage or black level voltage. The corresponding voltage level on the
cathode is referred to as the cut-off drive voltage level. Varying the
second grid voltage changes this cut-off voltage. Consequently, the
second grid voltage also determines the maximum beam current which can
be generated by the electron gun.
It is conventional practice in the television industry to adjust the
G2 voltage of a receiver's CRT (cathode ray tube) so that the electron
gun with the highest cut-off point is barely emissive. Prior to making
such adjustment, the output voltages of each of the three video
amplifiers are set to a common voltage level.
In a color television receiver having a color image reproducing
kinescope with plural electron guns, the black level bias voltage of the
electron guns establishes the peak beam current available from the
electron guns. The black level voltage of each electron gun is related
to the magnitude of the bias voltage applied to the kinescope G2 grid,
also referred to as the screen grid. A color kinescope with an "in-line"
electron gun structure has a G2 grid electrode energized in common to
all three electron guns, while a kinescope with separate "delta-type"
electron guns has separately energized G2 grid electrodes for each gun.
In either case, the G2 bias voltage is often set at a value between 400
and 600 volts so that a desired cathode-to-G1 grid voltage produces a
black level condition.
High brightness and high resolution in a
reproduced image require a high kinescope peak beam current capability
and small spot size. For each gun, peak beam current capability
increases with increasing black level voltage, which is related to the
G2 bias voltage. The need for high brightness and high resolution
suggests that the highest available G2 bias voltage should be used,
consistent with other requirements and constraints of the receiver
design.
Some television receivers also employ automatic kinescope
bias (AKB) control systems for maintaining a desired black level
kinescope cathode bias. Such systems operate to maintain desired
cathode-to-G1 grid bias for each electron gun, and should be capable of
operating over a range of black level bias voltages at least as great as
the maximum difference in black level voltage between any two kinescope
electron guns, which can be on the order of 50 volts. To compensate for
other system parameter tolerances as well, the operating range of the
AKB system may be as great as 100 volts. The choice of an operating
point within that range is determined by the G2 grid bias voltage.
Consequently, the G2 bias voltage must be manually adjusted on each
receiver to insure that the black level bias voltage of each kinescope
electron gun is within the operating range of the AKB system.
Furthermore, to obtain high brightness and resolution in a displayed
image, the G2 bias voltage should be adjusted so as to make the black
level bias voltage of the electron gun with the highest (i.e., most
positive) black level voltage nearly equal to the highest useable black
level bias voltage capable of being produced by the kinescope driver
stages.
This invention relates to apparatus for automatically controlling the bias of an image reproducing kinescope in a video signal processing system such as a color television receiver or an equivalent system, in order to establish proper cut-off blanking levels for each of the electron guns of the kinescope.
a color image reproducing kinescope included in a color television receiver comprises a plurality of electron guns each energized by red, blue and green color representative signals derived from a received composite color television signal. Since a reproduced color image is defined by individual ones of these signals or a combination thereof, optimum reproduction of a color image requires that the relative proportions of these color signals be correct at all drive levels from white through gray to black, at which point the three electron guns should exhibit significantly reduced conduction or be cut-off.
the optimum reproduction of a color image and gray scale tracking of the kinescope can be adversely affected when the bias of the electron guns varies from a predetermined level, causing undesirable kinescope cut-off errors to be produced.
These cut-off errors are visible as a color tint on a displayed monochrome image, and also upset the color fidelity of a displayed color image.
the cut-off errors can be caused by a variety of factors, including variations in the operating characteristics of the kinescope and associated circuits (e.g., due to aging), temperature effects and momentary kinescope "flashovers.”
color television receivers commonly include provisions for adjusting the kinescope and associated circuits in a set-up or service operating mode of the receiver in accordance with well known procedures.
a service switch having "normal” and “service” positions is operatively associated with the receiver signal processing circuits and the kinescope. In the "service” position, video signals are decoupled from the kinescope and vertical scan is collapsed. The bias of each electron gun is adjusted to establish a desired blanking or cut-off current (e.g., a few microamperes) for each electron gun.
This adjustment ensures that the kinescope is properly blanked or cut-off in the absence of an applied video signal or in response to a black reference level of the video signal, and also ensures a proper proportion of color signals at all brightness levels.
the kinescope driver circuits associated with each electron gun are then adjusted for a desired gain (e.g., to compensate for kinescope phosphor inefficiencies) to assure a proper proportion of red, blue and green signal drive when the receiver operates normally.
the kinescope cut-off adjustment is time-consuming and inconvenient and typically must be performed several times during the life of the kinescope.
the kinescope cut-off and gain adjustments often interact with each other, thereby requiring that successive adjustments be made. Therefore, it is advantageous to eliminate the need for this adjustment such as by having this adjustment performed automatically by circuits within the receiver.
An automatic kinescope bias control arrangement preferably should be capable of generating a kinescope bias control voltage and applying this voltage to appropriate kinescope bias control circuits in a manner which produces minimum interaction between the control voltage and the video signals coupled to the kinescope.
SUMMARY OF THE INVENTION
The aim of the invention is to create a circuit arrangement which
suppresses the above-described disturbances of brightness and color of
the displayed picture when the picture tube is being started.
The invention achieves this aim in that
a circuit arrangement of the type mentioned in the preamble contains a
change detection arrangement which emits a change signal when the
stored signal has assumed an essentially constant value, and a logic
network which does not release the control of the beam current by the
picture signal until the change signal has also been emitted after the
switching signal.
In the circuit arrangement according to the invention, therefore, the
display of the picture is suppressed after the picture tube is turned
on until the cut-off point control has responded. If the picture signal
then starts to control the beam current, a perfect picture is
displayed immediately. In this way, all the disturbances of the picture
which affect the viewer's pleasure are suppressed. The circuit
arrangement of the invention is of simple design and can be combined on
one semiconductor wafer with the existing picture signal processing
circuits and also, for example, with the known circuit arrangement for
cut-off point control. Such an integrated circuit arrangement not only
requires very little space on the semiconductor wafer, but also needs
no additional external leads. Thus the circuit arrangement of the
invention can be arranged, for example, in an integrated circuit which
has precisely the same external connections as known integrated
circuits. This means that an integrated circuit containing the circuit
arrangement of the invention can be directly incorporated in existing
equipment without the need for additional measures.
In one embodiment of the said circuit arrangement, in which the picture
signal contains several color signals for the control of a
corresponding number of beam currents for representing a color picture
in the picture tube and, for each color signal, the control loop stores
a part measuring signal or a part control signal derived from it, the
change detection arrangement contains a change detector for each color
signal which emits a part change signal when the relevant stored signal
has assumed an essentially constant value, and the logic network does
not release the control of the beam currents by the color signals
outside the sampling intervals until the part change signals have been
emitted from all change detectors.
In principle, therefore, such a circuit arrangement has three cut-off
point controls for the three beam currents controlled by the individual
color signals. To reduce the cost of the circuitry, the measuring
stage is common to all the cut-off point controls, as in the known
circuit arrangement. All three beam currents are then measured
successively by this measuring stage. In this way, a part measuring
signal or a part control signal derived from it is obtained for each
beam current and is stored sesparately according to which of the beam
currents it belongs. Changes in the part measuring signal or part
control signal are detected for each beam current by one of the change
detectors each time. Each of these change detectors issues a part change
signal to the logic network. The latter does not release the control
of the beam currents by the picture signal outside the sampling
intervals until all the part change signals indicate that the part
measuring signal or the part control signal, as the case may be,
remains constant. This ensures that the cut-off point controls for the
beam currents of all color signals have responded when the picture
appears in the picture tube.
In a further embodiment of the circuit arrangement according to the
invention with a comparator arrangement which compares the measuring
signal with the reference signal and derives the control signal from
this comparison, the change detection arrangement detects a change in
the control signal with respect to time and issues the change signal
when the control signal has assumed an essentially constant value. In
the case of the representation of a color signal the comparator
arrangement derives several part control signals, whose changes with
time are detected by the change detectors, from a corresponding
comparison of the part measuring signals with the reference signal. In
this embodiment of the circuit arrangement of the invention, preference
is given to storage of only the control signal or the part control
signals for the purpose of controlling the beam currents.
In another embodiment of the circuit arrangement of the invention which
includes a control signal memory which contains at least one capacitor
in which a charge or voltage corresponding to the control signal is
stored, the change detection arrangement issues the change signal when a
charge-reversing current of the capacitor occurring during the turning
on of the picture tube has fallen below a limit value and has thus at
least largely decayed. Such a detection of the steady state of the
cut-off point control is independent of the actual magnitude of the
control signal and therefore independent of, for example, the level of
the picture tube cut-off voltage, circuit tolerances or ageing
processes in the circuit arrangement or the picture tube.
Detection of whether or not the charge-reversing current exceeds the
limit value is performed preferentially by a current detector which is
designed with a current mirror system which is arranged in a supply
line to a capacitor acting as a control signal store. A current mirror
arrangement of this kind supplies a current which coincides very
precisely with the charging current of the capacitor. This current is
then compared, preferably in a further device contained in the change
detection arrangement, with a current representing a limit value or,
after conversion into a voltage, with a voltage representing the limit
value. The change signal is obtained from the result of this
comparison.
On the other hand, digital memories may also be used as control signal
memories, especially when the picture signal is supplied as a digital
signal and the blocking point control is constructed as a digital
control loop. In such a case, the comparator arrangement, the change
detection arrangement and the trigger circuit are also designed as
digital circuits. Then, the change detection arrangement advantageously
forms the difference of the signals stored in the control signal
memory in two successive sampling intervals and compares this with the
limit value formed by a digital value. If the difference falls short of
the limit value, the change signal is issued.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the invention is described in greater detail below with the aid of the drawings in which:
FIG. 1 shows a block circuit diagram of the embodiment,
FIG. 2 shows a somewhat more detailed block circuit diagram of the embodiment,
FIG. 3 shows time-dependency diagrams of some signals occurring in the circuit diagram shown in FIG. 2, and
FIG. 4 shows a somewhat moredetailed block circuit diagram of a part of the circuit diagram shown in FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a block circuit diagram of a circuit arrangement to which a
picture signal is fed via a first input 1 of a combinatorial stage 2.
From the output 3 of the combinatorial stage 2 the picture signal is
fed to the picture signal input of a controllable amplifier 5 which at
an output 6 issues a current controlled by the picture signal. This
current is fed via a measuring stage 7 to a hot cathode 8 in a picture
tube 9 and forms therein a beam current of a cathode ray by means of
which a picture defined by the picture signal is displayed on a
fluorescent screen of the picture tube 9.
The measuring stage 7 measures the current fed to the hot cathode 8,
i.e. the the beam current in the picture tube 9, and at a measuring
signal output 10, issues a measuring signal corresponding to the
magnitude of this current. This is fed to a measuring signal input 11
of a comparator arrangement 12 to which a reference signal is supplied
at a reference signal input 13. In a preferably periodically recurring
sampling interval during the occurrence of a given reference level in
the picture signal, the comparator arrangement 12 forms a control
signal from the value of the measuring signal fed to the measuring
signal input 11 at this time, on the one hand, and the reference
signal, on the other, by means of substraction and delivers this at a
control signal output 14. From there the control signal is fed to an
input 15 of a control signal memory 16 and is stored in the latter. The
control signal is fed via an output 17 of the control signal memory 16
to a second input 18 of combinatorial stage 2 in which it is combined
with the picture signal, e.g. added to it.
The combinatorial stage 2, the controllable amplifier 5, the measuring
stage 7, the comparator arrangement 12 and the control signal memory 16
form a control loop with which the beam current is guided towards the
reference signal in the sampling interval during the occurrence of the
reference level in the picture signal. For the reference level, use is
made in particular of a black level or a level with small, fixed
distance from the black level, i.e. a value in the picture signal w
hich
produces a black or almost back picture area in the displayed picture
in the picture tube. In this case the control loop, as described, forms
a cut-off point control for the picture tube. If the reference level
is away from the black level, the control loop is also designated as
quasi-cut-off-point control.
The circuit arrangement as shown in FIG. 1 also has a trigger circuit
19 to which the measuring signal from the measuring signal output 10 of
measuring stage 7 is fed at a measuring signal input 20. When the
circuit arrangement and therefore the picture tube are turned on, the
trigger circuit 19 is set in a first state in which by means of a first
connection 21 it blocks the comparator arrangement 12 in such a way
that the latter delivers no control signal or a control signal with the
value zero at its control signal output 14. This prevents the control
signal memory 16 from storing undefined values for the control signal
at the moment of turning on or immediately thereafter.
The circuit arrangement shown in FIG. 1 also has a logic network 22
which is connected via a second connection 23, by means of which a
switching signal is supplied, with the trigger circuit 10 and via a
third connection 24 with the controllable amplifier 5. Like the trigger
circuit 19, the logic network 22 also finds itself controlled, when
the circuit arrangement is being turned on, by the switching signal in a
first stage in which by way of the third connection 24 it blocks the
controllable amplifier 5 with a blocking signal in such a way that no
beam currents controlled by the picture signal can yet flow in the
picture tube 9. Thus the picture tube 9 is blanked; no picture is
displayed yet.
When picture tube 9 is turned on, the hot cathode 8 is still cold so
that no beam current can flow anyhow. The hot cathode 8 is then heated
up and, after a certain time, begins gradually to emit electrons as the
result of which a cathode ray and therefore a beam current can form.
However, during the heating up of the hot cathode 8, and because the
cut-off point control has not yet responded, this would be undefined
and is therefore suppressed by the controllable amplifier 5. Only in
time intervals which are provided immediately subsequent to flybacks of
the cathode rays into an initial position at the changeover from the
display of one image to that of a subsequent image, but even before the
start of the display of the subsequent image, the controllable
amplifier 5 delivers a voltage in the form of an auxiliary pulse for a
short time at its output 6, and when the hot cathode 8 in the picture
tube 9 is heated up sufficiently, this voltage produces a beam current.
The time interval for the delivery of this voltage is selected in such
a way that a cathode ray produced by its does not produce a visible
image in the picture tube 9, and coincides for example with the
sampling interval.
The measuring stage 7 measures the short-time cathode current produced
in the manner described and, at its measuring signal output 10,
delivers a corresponding measuring signal which is passed via measuring
signal output 20 to the trigger circuit 19. If the measuring signal
exceeds a definite preset threshold value, the trigger circuit 19 is
switched into a second state in which it releases the comparator
arrangement 12 via the first connection 12 and, by means of the second
connection 23, uses the switching signal to also bring the logic
network 22 into a second state. The comparator arrangement 12 now
evaluates the measuring signal supplied to it via the measuring signal
input 11, i.e. it forms the control signal as the difference between
the measuring signal and the reference signal supplied via the
reference signal input 13. The control signal is transferred via the
control signal output 14 and the input 15 into the control signal
memory 16. It is subsequently fed via the output 17 of the control
signal memory 16 to the second input 18 of the combinatorial stage 2
and is there combined with the picture signal at the first input 1,
e.g. is superimposed on it by addition. This superimposed picture
signal is fed to the picture signal input 4 of the controllable
amplifier 5 via the output 3 of the combinatorial stage 2.
In the second state of the logic network 22 the controllable amplifier 5
is switched via the third connection 24 by the blocking signal in such
a way that the picture signal controls the beam currents only during
the sampling intervals and that, for the rest, no image appears yet in
the picture tube. The cut-off point control now gebins to respond, i.e.
the value of the control signal is changed by the control loop
comprising the combinato
rial
stage 2, the controllable amplifier 5, the measuring stage 7, the
comparator arrangement 12 and the control signal memory 16 until such
time as the beam current in the picture tube 9 at the blocking point or
at a fixed level with respect to it is adjusted to a value preset by
the reference signal. For this purpose the sampling interval, in which
the picture signal controls the beam current via the controllable
amplifier 5 is selected in such a way that within it the picture signal
just assumes a value corresponding to the cut-off point or to a fixed
level with respect to it.
During the response of the cut-off point control the control signal fed
to the control signal memory 16 changes continuously. Between the
control signal output 14 of the comparator arrangement 12 and the input
15 of the control signal memory 16 is inserted a changed detection
arrangement 25 which detects the variations of the control signal. When
the cut-off point control has responded, i.e. the control signal has
assumed a constant value, the change detection arrangement 25 delivers a
change signal at an output 26 which indicates that the steady stage of
the cut-off point control is achieved and the said signal is fed to a
change signal input 27 of the logic network 22. The logic network then
switches into a third state in which via the third connection 24 it
enables the controllable amplifier 5 in such a way that the beam
currents are now controlled without restriction by the picture signal.
Thus a correctly represented picture appears in the picture tube 9.
A shadow-like representation of individual constituents of the circuit
arrangement in FIG. 1 is used to indicate a modification by which this
circuit arrangement is equipped for the representation of color
pictures in the picture tube 9. For example, three color signals are
fed in this case as the picture signal via the input 1 to the
combinatorial stage 2. Accordingly, the input 1 is shown in triplicate,
and the combinatorial stage 2 has a logic element, e.g. an adder, for
example of these color signals. The controllable amplifier 5 now has
three amplifier stages, one for each of the color signals, and the
picture tube now contains three hot cathodes 8 instead of one so that
three independent cathode rays are available for the three color
signals.
However,
to simplify the circuit arrangement and to save on components, only
one measuring stage 7 is provided which measures all three beam
currents successively. Also, the comparator arrangement 12 forms part
control signals from the successively arriving part measuring signals
for the individual beam currents with the reference signal, and these
part control signals are allocated to the individual color signals and
passed on to three storage units which are contained in the control
signal memory 16. From there, the part control signals are sent via the
second input 18 of the combinatorial stage 2 to the assigned logic
elements.
The circuit arrangement thus forms three independently acting control
loops for the cut-off point control of the individual color signals, in
which case only the measuring stage 7 and to some extent at least the
comparator arrangement 12 are common to these control loops.
The change detection arrangement 25 now has three change detectors each
of which detects the changes with time of the part control signals
relating to a color signal. Then via the output 26 each of these change
detectors delivers a part change signal to the change signal input 27
of the logic network 22. These part change signals occur independently
of one another when the relevent control loop has responded. The logic
network 22 evaluates all three part change signals and does not switch
into its third stage until all part change signals indicate a steady
state of the control loops. Only then, in fact, is it ensured that all
the color signals from the beam currents controlled by them are
correctly reproduced in the picture tube, and thus no distortions of
the displayed image, especially no color purity errors, occur. The
color picture displayed then immediately has the correct brightness and
color on its appearance when the picture tube is turned on.
FIG. 2 shows a somewhat more detailed block circuit diagram of an
embodiment of a circuit arrangement equipped for the processing of a
picture signal containing three colour signals. Three color signals for
the representation of the colors red, green and blue are fed to this
circuit arrangement via three input terminals 101, 102, 103. A red
color signal is fed via the first input terminal 101 to a first adder
201, a green colour signal is fed via the second input terminal to a
second adder 202, and a blue colour signal is fed via the third input
terminal 103 to a third adder 203. From outputs 301, 302 and 303 of the
adders 201, 202, 203 the color signals are fed to amplifier stages
501, 502 and 503 respectively. Each of the amplifier stages contains a
switchable amplifier 511, 512 and 513, an output amplifier 521, 522 and
523 as well as a measuring transistor 531, 532 and 533 respectively.
The emitters of these measuring transistors 531, 532, 533 are each
connected to a hot cathode 801, 802, 803 of the picture tube 9 and
deliver the cathode currents, whereas the collectors of measuring
transistors 521, 532, 533 are connected to one another and to a first
terminal 701 of a measuring resistor 702 the second terminal of which
703 is connected to earth. Th
e
current gain of the measuring transistors 531, 532 and 533 is so great
that their collector currents coincide almost with the cathode
currents. By measuring the voltage drop produced by the cathode
currents at the measuring resistor 802 it is then possible to measure
the cathode currents and therefore the beam currents in the picture
tube 9 with great accuracy.
The falling voltage at the measuring resistor 702 is fed as a measuring
signal to an input 121 of a buffer amplifier 120 with a gain factor of
one, at the output 122 of which the unchanged measuring signal is
therefore available at low impedance. From there it is fed to a first
terminal 131 of a reference voltage source 130 which is connected with
its second terminal 132 to inverting inputs 111, 112 and 113 of three
differential amplifiers 123, 124, 125 respectively. The differential
amplifiers 123, 124, 125 also each have a non-inverting input 114, 115,
and 116 respectively. These are connected to each other at a junction
117, to earth via a leakage current storage capacitor 126 and to the
output 122 of the buffer amplifier 120 via decoupling resistor 118 and a
leakage current sampling switch 119. In addition, the input 121 of the
buffer amplifier 120 can be connected to earth via a short-circuiting
switch 127.
From outputs 141, 142, and 143 respectively of the differential
amplifiers 123, 124 and 125, part control signals relating to the
individual color signals are fed in the form of electrical voltages
(or, in some cases, charge-reversing currents) via control signal
sampling switches 154, 155 and 156, in the one instance, to first
terminals 151, 152 and 153 respectively of control signal storage
capacitors 161, 162, 163 which form the storage units of the control
signal memory 16 and store inside them charges corresponding to these
voltages (or formed by the charge-reversing currents). In the other
instance, the part control signals are fed to second inputs 181, 182
and 183 of the first, second or third adders 201, 202, 203 respectively
and are added therein to the color signals from the first, second or
third input terminals 101, 102 or 103 respectively.
The operation of the comparator arrangement 12 which consists mainly of
the buffer amplifier 120, the reference voltage source 130 and
differential amplifiers 123, 124, 125 will be explained below with the
aid of the pulse diagrams in FIG. 3. FIG. 3a shows a horizontal blanking
signal for a television signal which, as the picture signal, controls
the beam currents in the picture tube 9. In this diagram, H represents
horizontal blanking pulses which follow one another in the picture
signal at the time interval of one line duration and by means of which
the beam currents are switched off during line flyback between the
display of the individual picture lines in the picture tube. FIG. 3b
shows a vertical blanking pulse V by means of which the beam currents
are switched off during the change ober from the display of one picture
to the display of the next picture. FIG. 3c shows a measuring signal
control pulse VH which is formed from a vertical blanking pulse
lengthened by three line duration.
The short-circuiting switch 127 is now controlled in such a way that it
is non-conducting only throughout the duration of the measuring signal
control pulse VH and during the remaining time short-circuits the
input 121 of the buffer amplifier 120 to earth. This means that a
measuring signal only reaches the comparator arrangement 12 during
frame change so that the parts of the picture signal which control the
beam currents producing the picture in the picture tube exert no
influence on comparator arrangement 12 and therefore on the blocking
point control.
Throughout the duration of the measuring signal control pulse VH, the
measuring signal from output 122, reduced by a reference voltage issued
by the reference voltage source 130 between its first 131 and its
second terminal 132, is present at the inverting inputs 111, 112, 113
of differential amplifiers 123, 124, 125. If the differential
amplifiers 123, 124, 125 were not present, this difference would be fed
directly as part control signals to the control signal storage
capacitors 161,
162, 162. The differential amplifiers 123, 124, 125 amplify the
difference and thus form the control amplifiers of the control loops.
The comparator arrangement 12 further contains a device for
compensation of the influence of any leakage currents occurring in the
picture tube 9. For this purpose, a voltage to which the leakage
current storage capacitor 126 is charged is fed to the non-inverting
inputs 114, 115, 116 of the three differential amplifiers 123, 124 and
125. The charging is performed by the measuring signal from output 122
of the buffer amplifier 120 via the decoupling resistor 118 and the
leakage current sampling switch 119 which is closed only within the
period of the vertical blanking pulse V, and in certain cases only
during part of the latter. Within this time the beam currents are, in
fact, totally switched off by the picture signal so that in certain
cases only a leakage current flows through the measuring resistor 702.
Consequently, throughout the duration of the vertical blanking pulse V
the measuring signal corresponds to this leakage current. Because the
leakage current also flows during the remaining time, even outside the
duration of the vertical blanking pulse the measuring signal contains a
component originating from the leakage current which therefore is also
contained in the voltage fed to the inverting inputs 111, 112, 113 of
differential amplifiers 123, 124, 125 and is subtracted out in the
differential amplifiers 123, 124, 125.
The part control signal is fed from output 141 of differential
amplifier 123 by the first control signal sampling switch 154 to the
first terminal 151 of the first control signal storage capacitor 161
during the period of a storage pulse L1 and is stored in the said
capacitor. Similarly, the part control signal from output 143 of
differential amplifier 125 is fed to the third control signal storage
capacitor 163 during the period of a storage pulse L2 and the part
control signal from output 142 of differential amplifier 124 is fed to
the second control signal storage capacitor 162 during a storage pulse
L3. The storage pulses L1, L2 and L3 are illustrated in FIGS. 3d, e and
f. They lie in sequence in one of the three line periods by which the
measuring signal control pulse VH is longer than the vertical blan
king
pulse V. These three line periods form the sampling interval for the
measuring signal or the part measuring signals, as the case may be.
During the remaining periods the outputs, 141, 152, 143 of the
differential amplifiers 123, 124, 125 are isolated from the control
signal storage capacitors 161, 162, 163 so that no interference can be
transmitted from there and any distortion of the stored part control
signals caused thereby is eliminated. For the duration of storage
pulses L1, L2 and L3 the color signals at the input terminals 101, 102,
103 are at their reference level i.e. in the present embodiment at a
level, corresponding to the blocking point or at a fixed level with
respect to it so that the control loops can adjust to this level.
The switchable amplifiers 511, 512, and 513 each receive at each input
241, 242, 243 a blanking signal BL1, BL2, BL3 respectively, the curves
of which are shown in FIGS. 3g, h, i. These blanking signals interrupt
the supply of the color signals during line flybacks and frame change,
i.e. during the period of the measuring signal control pulse VH, and
thus the beam currents in these time intervals are switched off.
Naturally, the red color signal is let through during the first line
period after the end of the vertical blanking pulse V, the blue color
signal during the second line period after the end of the vertical
blanking pulse V and the green color signal during the third line
period after the end of the vertical blanking pulse V by the switchable
amplifiers 511, 512, 513 respectively so that they can control the
beam currents. Blanking signals BL1, BL2 and BL3 also provide for
interruptions in the frame change blanking pulse, which corresponds to
the measuring signal control pulse, in the corresponding time
intervals. In these time intervals the beam currents are measured and
part control signals are determined from the part measuring signals and
stored in the control signal storage capacitors 161, 162, 163.
The circuit arrangement shown in FIG. 2 further contains a trigger
circuit 19 to which a supply voltage is fed via a supply terminal 190.
Via a reset input 191 a voltage is also
supplied
to the trigger circuit 19 from a third terminal 133 of the reference
voltage source 130. When the circuit arrangement is turned on, this
voltage is designed so as to be delayed with respect to the supply
voltage so that when the circuit arrangement is brought into operation
the interplay of the two voltages produces a switch-on reset signal such
that a low-value voltage pulse occurs at the reset input 191 during
turn on, which means that the trigger circuit 19 is set in its first
state. The reset input 191 can also be connected to another circuit of
any configuration which generates a switch-on reset signal when the
picture tube is turned on.
The trigger circuit 19 is further connected via a second connection 23
to a logic network 22 which, when the circuit arrangement is turned on,
is also set into a first state via the second connection 23. In this
first state the logic network 22 delivers a blocking signal at a
blocking output 240 which is fed to the three switchable amplifiers
511, 512, 513. By this means the supply of the color signals to the
output amplifiers 521, 522, 523 is interrupted completely so that no
beam currents can be generated by these. No picture is therefore
displayed.
An insertion signal EL which extends over the three line periods by
which the measuring signal control pulse VH is longer than the vertical
blanking pulse V, i.e. over the sampling interval, is also fed via a
line 233 to the trigger circuit 19 and the logic network 22. As long as
the trigger circuit 19 is in its first state, this insertion pulse EL
is issued via a control output 192 from the trigger circuit 19 and fed
to the pulse generator 244. During the period of the insertion pulse EL
this generator produces a voltage pulse of a definite magnitude and
passes this to output amplfiiers 521, 522, 523 as an auxiliary pulse
via switching diodes 245, 246, 247. By this means the beam currents are
switched on for a short time so as to receive a measuring signal
despite the disconnected color signals as soon as at least one of the
hot cathodes 801, 802, 803 delivers a beam current.
In its first state the trigger circuit 19 also delivers a signal via a
control line 211, and this signal is used to switch the outputs 141,
142, 143 of the differential amplifiers 123, 124, 125 to earth
potential or practically to earth potential. This suppresses effects of
voltages at the inputs 111 to 116 of the differential amplifiers 123,
124, 125, especially effects of the reference voltage source 130 which
may in some cases initiate incorrect charging of the control signal
storage capacitors 161, 162, 163.
The measuring signal produced by means of the pulse generator 244 at
the input 121 of the buffer amplifier 120 is also fed to the trigger
circuit 19 via a measuring signal input 20. If it exceeds a preset
threshold value, the trigger circuit 19 switched into its second state.
The logic network 22 is then also switched into its second state via
the second connection 23. The differential amplifiers 123, 124, 125,
too, are triggered by th
e
signal along the control line 211 into issuing a control signal
defined by the difference in the voltages at its inputs 111 to 116. The
pulse generator 244 is blocked by the control output 192. The blocking
signal issued from the blocking output 240 of the logic network 22 now
turns on the switchable amplifiers 511, 512, 513 in the time intervals
defined by the storage pulses L1, L2, L3 in such a way that in these
time intervals the color signals can produce beam currents to form a
measuring signal by which the control loops respond. However, the
display of the picture is still suppressed. The control signal storage
capacitors 161, 162, 163 are charged up in this process. In the leads
to the first terminals 151, 152, 153 there are change detectors 251,
252, 253 which detect the changes of the charging currents of the
control signal storage capacitors 161, 162, 163 and at their outputs
261, 262, 263 in each case deliver a part change signal when the
charging current of the control signal storage capacitor in question
has decayed and thus the relevant control loop has responded. The part
change signals are fed to three terminals 271, 272, 273 of the change
signal input 27 of the logic network 22.
When part change signals are present from all change detectors 251,
252, 253, when therefore all control loops have responded, the logic
network 22 switches from its second to its third state. The blocking
signal from the blocking output 240 is now completely disconnected such
that the switchable amplifiers 511, 512, 513 are now switched only by
the blanking signals BL1, BL2, BL3. The colour signals are then
switched through to the output amplifiers 521, 522, 523 and the picture
is displayed in the picture tube.
FIG. 4 shows an embodiment for a trigger circuit 19 and a logic network
22 of the circuit arrangements as shown in FIGS. 1 or 2. The trigger
circuit 19 contains a flip-flop circuit formed from two NAND-gates 194,
195 to which the switch-on reset signal, by which the trigger circuit
19 is returned to its first stage, is fed via the reset input 191. All
the elements of the circuit arrangement in FIG. 4 are shown in positive
logic. Thus, a short-time low voltage at the reset input 191
immediately after the circuit arrangement is started up is used to set
the flip-flop circuit 194, 195 in such a way that a high voltage occurs
at the output of the second NAND gate 194 and a low voltage at the
output of the second NAND gate 195. The low voltage at the output of
the second NAND gate 195 blocks differential amplifiers 123, 124, 125
via the control line 211 in the manner described.
The insertion pulse EL is fed via the line 233 to the trigger circuit
19, is combined via an AND gate 196 with the signal from the output of
the first NAND gate 194 and is delivered at the control output 192 for
the purpose of controlling the pulse generator 244.
The signals from the outputs of the NAND-gates 194, 195 are fed via a
first line 231 and a second line 232 of the second connection 23 as a
switching signal to the logic network 22. The first line 231 is
connected to reset inputs R of three part change signal memories 221,
222, 223 in the form of bistable flip-flop circuits which when the
circuit arrangement is started up are reset via the first line 231 in
such a way that they carry a low voltage at their outputs Q. The second
line 232 of the second connection 23 leads via three AND gates 224,
225, 226 to setting inputs S of the three part change signal memories
221, 222, 223. By means of the AND gates 224, 225, 226 the signal on
the second line 232 of the second connection 23 is combined each tim
e
with one of the part change signals supplied via the terminals 271,
272, 273. The signals from the outputs Q of the part change signal
memories 221, 222, 223 are combined by means of a collecting gate 227
in the form of an NAND gate and are held ready at its output 228.
The measuring signal is fed to the trigger circuit 19 via the measuring
signal input 20 and passed to a first input 197 of a threshold
detector 198 to which at a second input a threshold value, in the form
of a threshold voltage for example, produced by a threshold generator
199 is also supplied. When the voltage at the first input 197 of the
threshold detector 198 is smaller than the voltage delivered by the
threshold generator 199, the threshold detector 198 delivers a high
voltage at its output 200. When, on the other hand, the voltage at the
first input 197 is greater than the voltage of the threshold generator
199, the voltage at the output 200 jumps to a low value. This voltage
is supplied as the setting signal of the flip-flop circuit 194, 195,
reverses the latter and thereby switches the trigger circuit 19 into
its second state when the voltage at the first input 197 exceeds the
voltage of the threshold generator 199.
Between the output 200 and the flip-flop circuit 194, 195 in the circuit arrangem
ent
shown in FIG. 4 there is inserted an inquiry gate 181 in the form of
an OR gate to which an inquiry pulse is fed via an inquiry input 193 of
the trigger circuit 19. This ensures that the flip-flop circuit 194,
195 is switched over only at a time fixed by the inquiry pulse--in the
present case a negative voltage pulse--and not at any other times due
to disturbances. As such an inquiry pulse it is possible to use, for
example, a pulse which occurs in the second line period after the end of
the vertical blanking pulse V, i.e. one which largely corresponds to
the storage pulse L2.
After the switching over of the flip-flop circuit 194, 195
corresponding to the setting of the trigger circuit 19 into the second
state, appropriately modified signals are supplied via the control line
211 and the output 192 for the purpose of controlling the pulse
generator 244 and the differential amplifiers 123, 124, 125. Modified
voltages also appear on the lines 231, 232 of the second connection 23,
and these voltages release the part change signal memories 221, 222,
223 such that they can each be set when the part change signals reach
the terminals 271, 272, 273.
In certain cases, a further flip-flop circuit
234
is inserted in the lines 231, 232 to delay the signals passing along
these lines; this is reset via the first line 231 when the circuit
arrangement is started up and thus it also resets the part change
signal memories 221, 222, 223. However, after the trigger circuit 19 is
switched into the second state the further flip-flop circuit 234 is
not set via the second line 232 of the second connection 23 until a
release pulse arrives via a release input 235 and another AND gate 236,
for example a period of approximately the interval of two vertical
blanking pulses V after the switching of the trigger circuit 19 into
the second state. In this way it is possible to bridge a period of time
in which no defined signal values are present at the terminals 271,
272, 273.
The signal at the output 228 of the collecting gate 227 changes its
state when the last of the three part change signals has also arrived
and has set the last of the three part change signal memories. The
signal is then combined via a gate arrangement 229 of two NAND gates
and one AND gate with the insertion pulse EL of line 223 and with the
signal on the second line 232 of the second connection 23 or from the
output Q of the further flip-flop circuit 234 to the blocking signal
delivered at the blocking output 24 which is fed to the switchable
amplifiers 511, 512, 513.
FIGS. 31, m, n show the combinations of the blocking signal with the
blanking signals BL1, BL2, and BL3 at the blanking inputs 241, 242, 243
of the switchable amplifiers 511, 512, 513 in the form of logic AND
operations. The dot-dash lines show resulting insertion signals A1, A2,
A3 formed by these operations after the starting up of the circuit
arrangement and before the occurrence of a beam current, i.e. in the
first state of the logic network 22. Here the resulting insertion
signals A1, A2, A3 are constant at low level. The dash curves show the
resulting insertion signals A1, A2, A3 after the appearance of a beam
current and before the steady state of the cut-off point control is
reached, i.e. in the second state of the logic network 22, while the
continuous curves represent the resulting insertion signals A1, A2, A3
in the steady state of the cut-off point control, i.e. in the third
state of logic network 22. The dash curves have similar shapes to
storage pulses L1, L2, L3, whereas the continuous curves correspond in
shape to the inverses of the blanking signals BL1, BL2, BL3. In this
case a high level of the resulting insertion signals A1, A2 or A3 means
that the switchable amplifier 511, 512 or 513 feeds the colour signal
to the relevant output amplifier 521, 522 or 523 respectively, whereas a
low level in the resulting insertion signal A1, A2 or A3 means that
the relevant switchable amplifier 511, 512 or 513 is blocked for the
color signal.
The circuit arrangement described is designed in such a way that the
trigger circuit 19 remains in its second state and logic network 22
remains in its third state even if charging currents reappear at the
difference signal storage cpacitors 161, 162, 163 due to disturbances
during the operation of the circuit arrangement. The cutoff point
control then makes readjustments without the displayed picture being
disturbed.
In the circuit arrangement shown in F
IG.
2, the green color signal can also be let through during the second
line period after the end of the vertical blanking pulse V and the blue
color signal during the third line period after the end of the
vertical blanking pulse V by the switchable amplifiers 511, 512, 513
for the purpose of controlling the beam currents. The storage pulses L2
and L3 at the control signal sampling switches 155 and 156 and the
second and third blanking signals BL2 and BL3 at the blanking inputs
242 and 243 are then to be interchanged. The resulting insertion
signals A2 and A3 as shown in FIGS. 3m and n are also interchanged then
accordingly.
In FIG. 2 a dashed line is used to indicate which components of the
circuit arrangement can be combined advantageously to form an
integrated circuit. The first terminals 151, 152, 153 of the difference
signal storage capacitors 161, 162, 163, one terminal 128 of leakage
current storage capacitor 126, three terminals 524, 525, 526 in the
leads to the output amplifiers 521, 522, 523 as well as a line
connection 704 between the first terminal 701 of the measuring resistor
702 and the input 121 of the buffer amplifier 120 will then form the
connecting contacts of this integrated circuit.
Other References:
Jensen, "Permanent Colour Truth", Elektronic, Apr. 1975 (Danish).
Lavigne, "Towards True Color Stability in
Television", Videocolor S. A., Paris, France, No. 1600, Jun. 1978 pp.
11-20.
Gublass, "Bildrohrenasteuerung mit
automatischer Dunkelstrom-Ragelung", Funkschau, 1979, Heft 12, pp.
674-678.
Jensen, "Colour receiver design", Wireless World, Jul., 1978, pp. 51-54.
US Patent References:
4347528 G2 Set-up circuit for a television receiver 1982-08-31 Johnson 358/10
4331982 Sample and hold circuit particularly for small signals 1982-05-25 Parker 358/74
4331981 Linear high gain sampling amplifier 1982-05-25 Parker 358/74
4309718 Service switch arrangement for low level matrixing type television receiver 1982-01-05 Johnson 358/10
4277798 Automatic kinescope biasing system with increased interference immunity 1981-07-07 Hinn 358/33
4263622 Automatic kinescope biasing system 1981-04-21 Hinn 358/74
3670095 CATHODE RAY TUBE "SET-UP" CIRCUITRY 1972-06-13 Arumugham 358/10
PLL Device for 125 kHz Resolution for TV Application SIEMENS SDA2112-2 Bipolar circuit
The SDA 2112-2 is fabricated in ASBC technology. In connection with a VCO (tuner) and a high-speed 1:64 divider, it forms a digitally programmable phase-locked loop for producing TV sets with PLL frequency-synthesis tuning. The PLL enables crystal-controlled setting of the tuner oscillator frequency for a 125 kHz rsolution in the frequency bands I/IIl, IV, and V.
A serial interface provides for simple connection to a microprocessor. The latter loads the programmable divider and the band-selection outputs with the appropriate information.
Features
@ No external integrator necessary
@ Internal buffer
@ Microprocessor compatible
SDA 2112-2 description (refer to block diagram) A switchable 16/17 counter is triggered by the ECL signal inputs F/F. The counter, in connection with a 4-bit and a 9-bit programmable, synchronous counter, forms a programmable, 13-bit synchronous divider using the dual-modulus technique, the 4-bit counter controlling the switchover from 16 to 17. Divider ratios of N = 256 to 8191 are possible. For test purposes the carry of the synchronous divider is available at the LDM output (open collector). The 16-bit shift register and latch is subdivided into 13 bits for storing the divider ratio N and 3 bits for controlling the three band-selection outputs. The telegram is shifted in via the serial data input IFO with the HL edge of the shift clock CPL when the enable input PLE is also on high level. First the complement of the divider ratio N, beginning with the LSB, is inserted in binary code, followed by the three control bits for the band-selection switching (see truth table). The 16-bit latch takes the data from
the shift register when the enable input PLE is on low level. The IC includes a crystal-controlled, 3-MHz clock oscillator.
The output signal is divided down to 1.953125 kHz (reference signal) by a 1/1536 reference divider. The oscillator frequency appears at the TTL output OSC. The clock of 62.5 kHz is available at the open-collector output CL. The divided input signal is compared with the reference signal in a digital phase detector. If the falling edge of the input signal appears prior to the falling edge of the reference signal, the DOWN output of the phase detector turns to high level for the duration of this phase difference. In the reverse case the UP output turns to high level. If the two signals are in phase, both outputs remain at low level. The UP/DOWN outputs control the two current sources I+ und! (charge pump). If the two outputs are low (PLL locked), the charge-pump output PD will turn to the high-impedance state (TRISTATE). An L signal appears at the LOCK IND output if frequency and phase are synchronous.
The current sources I+ and I~ are then reduced from 300 to 100 pA. The current pulses generated by the charge pump are integrated to form the tuning voltage by means of an active lowpass filter (external pull-up resistor to supply Vso and external RC circuitry). The dc output signal appears at Viy, and serves as a tuning voltage for the VCO. The band-selection outputs (UHF, VHF, Bd I/II) contain current drains with open collectors. In this way PNP transistors working as band-selection switches can be connected directly without current-limiting resistors (see application circuit).
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Digital phase locked loop tuning system / PLL FREQUENCY SYNTHESIZER:
A phase locked loop circuit for use in an automatic frequency
synthesizing system. The system includes a programmer circuit which is
responsive to a channel number input signal and generates a first
digital control signal which is representative of the selected channel
number and a second digital control signal which is representative of a
predetermined group of channel numbers. A programmable divider is
controlled by the programming circuit and generates a digital output
signal which causes the phase locked loop circuit to generate a desired
system output frequency corresponding to the selected channel number
input signal. The phase locked loop circuit includes automatic fine
tuning and manual fine tuning features.
1. A digital phase locked loop tuning system responsive to a local
oscillator signal for producing a frequency synthesized digital output
signal which is utilized to control the frequency of the local
oscillator, the local oscillator having a plurality of frequencies
associated therewith corresponding, respectively, to a plurality of
selectable channels, each of the channels being allocated to one of at
least two channel groups with each channel in a particular channel group
being separated from an adjacent channel in the particular channel
group by a predetermined frequency spacing of the local oscillator,
comprising:
programming means responsive to an input signal representing a selected
channel number of a particular channel group for generating a first
digital control signal having a value corresponding to the selected
channel number and for generating a second digital control signal
representative of said particular channel group, said second digital
control signal being a constant predetermined value for all of said
channel numbers that are within said group; and
programmable divider means coupled to said programming means being
responsive to said first, second digital control signals and the local
oscillator signal, in a local oscillator mode, for generating the
digital output signal which is representative of a desired frequency
corresponding to said selected channel number, said programmable divider
means including means for dividing the local oscillator signal by first
and second factors, said first factor being related to the frequency
separation between local oscillator signals by an integral number, the
local oscillator signal being divided by said first factor during a
first interval for a first number of periods of the output signal and
being divided by said second factor for a second number of periods of
the output signal, said first number of periods being related to the
number of the channel selected, said second number being related to the
channel group within which the selected channel lies.
2. Phase locked loop system according to claim 1, wherein said
programming means including means coupled to said programming means for
receiving an MFT signal and being responsive to said MFT signal for
altering said first and second digital control signals, and said
programmable divider means being responsive to said altered digital
control signals for generating an altered system output frequency.
3. Phase locked loop system according to claim 2, wherein said
programming means includes first terminal means coupled to said
programming means for receiving an AFT control signal, and first logic
means responsive to the input signal and the AFT control signal for
generating the first digital control signal.
4. Phase locked loop system according to claim 3, wherein said
programming means includes second logic means coupled to said first
logic means and responsive to the AFT control signal for generating the
second digital control signal.
5. Phase locked loop system according to claim 4, wherein said second
logic means includes group decoder means coupled to said first logic
means.
6. Phase locked loop circuit means according to claim 5, wherein said
second logic means includes memory means coupled to said group decoder
means and to said first terminal means.
7. Phase locked loop system according to claim 6, wherein said second
logic means includes second terminal means for receiving an MFT signal,
and up/down counter latch means coupled to said memory means and to said
second terminal means for altering said first and second digital
control signals in response to said MFT signal.
8. Phase locked loop system according to claim 7, wherein said second
logic means includes adder means coupled to said up/down counter latch
means to said memory means.
9. Phase locked loop system according to claim 3, wherein said first
logic means includes channel number generator means coupled to said
first terminal means and responsive to said input signal.
10. Phase locked loop system according to claim 9, wherein said channel
number generator means includes first and second data selector means
coupled to said first terminal means, and adder means coupled to said
second data selector means and to said up/down counter latch means.
11. Phase locked loop system according to claim 1, wherein said means
for dividing the local oscillator signal includes programmable counter
means for generating a modulus control output signal, and variable
modulus prescaler divider means coupled to and responsive to said
programmable counter means, said variable modulus prescaler divider
means dividing the local oscillator signal by said first and second
factors.
12. Phase locked loop system according to claim 11, wherein said
programmable counter means includes third data selector means coupled to
receive said first and second digital control signals and said modulus
control signal.
13. Phase locked loop system according to claim 12, wherein said
programmable counter means includes a programmable counter coupled to
said third data selector means and to said variable modulus prescaler
divider means.
14. Phase locked loop system according to claim 13, wherein said
programmable counter means includes look ahead circuit means coupled to
said programmable counter, and divide by two circuit means coupled to
said look ahead circuit means for generating said modulus control output
signal.
15. Phase locked loop tuning system according to claim 1 including digital automatic fine tuning (AFT) means wherein:
said programmable divider means includes switching means responsive to
an AFT control signal to inhibit the local oscillator signal to said
programmable divider means and to provide an input signal thereto of a
different frequency than the local oscillator signal; and
said programming means including logic means responsive to said AFT
control signal for altering said first and second digital control
signals to predetermined values to cause the phase locked loop tuning
system to be operable in an automatic fine tuning mode.
16. Phase locked loop tuning system of claim 15 wherein said programmable divider means includes:
programmable counter means for generating first and second modulus control signals; and
dual modulus prescaler means responsive to said first modulus control
signal for dividing the local oscillator signal in said local oscillator
mode and said input signal of a different frequency in said automatic
fine tuning mode by said first factor which is equal to the integer six
and being responsive to said second modulus control signal for dividing
said local oscillator signal and said input signal of a different
frequency by said second factor which is equal to the integer five
respectively.
17. Phase locked loop tuning system of claim 16 wherein said signal of a
different frequency is an intermediate frequency signal provided by the
tuning system and supplied to said switching means.
18. In a phase locked loop tuning system for receiving a channel number
input signal and a local oscillator signal having groups of selectable
frequencies wherein the frequency spacing between each adjacent local
oscillator frequency within a single group is uniform, the improvement
comprising programmable divider means for generating a digital output
signal representative of a desired tuning system output frequency
including variable modulus prescaler divider means having a prescaler
division ratio being equal to P = S/Y' for dividing the local oscillator
frequency by said prescaler division ratio during a first interval for a
first number of periods of the digital output signal and for dividing
the local oscillator frequency by a second prescaler division ratio
during a second interval for a second number of periods, said second
ratio being related to said first ratio, where S is the frequency
spacing between each adjacent local oscillator frequency within a single
group (i), Y
i =D
i -X
i S, where D
i is said desired tuning system output frequency within said selected group; X
i =D
i /S rounded off to the nearest integer; Y' is chosen such that Y
i /Y' is an integer and S/Y' is an integer and Y' is the smallest value of all values of Y
i.
19. In a receiver including a tuning apparatus for providing a plurality
of local oscillator signals each corresponding to a respective one of a
plurality of selectable channels, each of the channels being allocated
to one of at least two channel groups wherein each channel is separated
from an adjacent channel in the respective channel group by a
predetermined frequency spacing, a phase locked loop tuning system for
producing a frequency synthesized output signal for controlling the
frequency of the local oscillator, comprising:
variable modulus divider means for selectively dividing the frequency of
the local oscillator signal by first and second factors in response to a
modulus control signal to provide an output signal, said first factor
being related to the frequency separation between local oscillator
signals by an integral number; and
programmable means for generating said modulus control signal to cause
said variable modulus divider means to divide by said first factor
during a first interval for a first number of periods of said output
signal and to divide by said second factor during a second interval for a
second number of periods of said output signal, said first number of
periods being related to the number of the channel selected, said second
number of periods being related to the channel group corresponding to
the selected channel.
20. The phase locked loop tuning system of claim 19 wherein said programmable means includes:
programming means responsive to a selected channel input signal for
producing first and second digital output signals, said first digital
output signal being related to the selected channel number plus one of
two constant values which are determined in accordance within which
channel group the selected channel input signal lies, said second
digital signal being a constant value for all selected channels within a
channel group; and
programmable divider means responsive to said first and second digital
output signals from said programming means for providing said variable
modulus control signal and the frequency synthesized output signal.
21. The phase locked loop tuning system of claim 20 wherein said
programming means includes automatic fine tuning (AFT) means responsive
to a AFT control signal being applied thereto when the receiver is
placed in an AFT mode wherein:
said variable modulus divider means is caused to receive a input signal different from the local oscillator signal;
said programming means being responsive to the AFT control signal for
altering said first and second digital signals such that the receiver is
finely tuned to the frequency of the received signal applied to the
receiver.
22. The phase locked loop tuning system of claim 21 wherein said
programming means includes means for receiving a manual fine tuning
(MFT) signal for altering said first and second digital output signals,
and said programmable divider means being responsive to said altered
digital control signals for generating an altered output signal.
23. The phase locked loop tuning system of claim 19 wherein the one of
said first and second factors is an even number and the other is an odd
number.
24. The phase locked loop tuning system of claim 23 wherein said first
factor is the integer six and said second factor is the integer five.
Description:
BACKGROUND OF THE INVENTION
This invention relates to digital tuning systems, and more particularly,
to a simplified digital phase locked loop (PLL) tuning system
incorporating unique digital automatic fine tuning and manual fine
tuning schemes.
Since the appearance of varactor tuners for television, many tuning
address schemes have evolved for controlling them. PLL techniques have
maintained a performance advantage but have suffered a cost disadvantage
due to complexity, the high frequencies involved, the need for
automatic fine tuning and in some localities, the need for a manual fine
tuning arrangement. With the advances that have taken place in
semiconductor technology in the last several years, the high operating
frequencies no longer present a significant problem.
Prior art PLL systems for use in television tuners have not yet been
able to incorporate an automatic fine tuning feature, nor have they been
able to incorporate a manual fine tuning system which would enable the
PLL tuning system to be intentionally offset in predetermined
increments. Television sets normally have an automatic fine tuning (AFT)
feature, but this is normally incorporated as a separate circuit which
is not directly incorporated into the television tuner.
An additional disadvantage of prior art PLL systems which are designed
for use in a television tuner environment is that they are highly
complex and relatively expensive. In order to convert the channel number
input into the proper digital control signals for the PLL, a relatively
large ROM having a capacity on the order of 82 words by 12 bits was
required. The best prior art PLL tuning systems require two high speed
programmable counters which greatly increase the system complexity. This
together with the large ROM which the system required, greatly
decreased the cost effectiveness of the system so that commercial
manufacturers were able to use these prior art PLL systems only in their
most expensive commercial television receivers.
Therefore, it is a feature of this invention to provide a digital PLL
tuning system which incorporates design techniques that vastly simplify
the complexity of the PLL while at the same time allowing the system to
meet the latest needs of a television tuning system or any other PLL
tuning system which is addressed by a channel number.
It is another feature of this invention to provide a digital PLL tuning
system that has the ability to automatically tune nonprecise station
frequencies and the ability to be manually fine tuned.
It is yet another feature of the present invention to provide a digital
PLL tuning system having only a single high speed programmable counter
and requiring a ROM capacity of only 5 words by 9 bits.
It is still another feature of this invention to provide a digital PLL
tuning system which performs the automatic fine tuning feature by
utilizing the PLL tuning system as a digital discriminator.
It is yet another feature of this invention to provide a digital PLL
tuning system incorporating a manual fine tuning (MFT) arrangement which
is capable of intentionally offsetting the local oscillator frequency
of a TV tuner in one megahertz steps or of offsetting TV IF frequency in
steps of 125 kilohertz.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention includes a phase
locked loop circuit means for an automatic frequency synthesizing
system. The phase locked loop circuit means includes programming means
which is responsive to an input signal representing a selected channel
number for generating a first digital control signal representative of
the selected channel number and for generating a second digital control
signal representative of a predetermined group of channel numbers. A
programmable divider means is coupled to the first and second digital
control signals and generates a digital output signal representative of a
desired system output frequency corresponding to the selected channel
number.
The phase locked loop circuit means further includes an automatic fine
tuning feature for fine tuning the phase locked loop output frequency to
the exact frequency of the received signal. The system further includes
a manual fine tuning provision which allows the phase locked loop
operating frequency to be intentionally offset in predetermined
increments.
--------------------------
Static LED Display Driver with Blanking Capability SIEMENS SDA2131
The SDA 2131 includes a static display driver for 16 LEDs featuring a 10 mA output current, each. The serial data interface enables a simple connection to the microcomputer.
Features
@ Integrated load resistances, thus few external components are required
@ Number of LEDs software-selectable
@ Blanking capability through DC-controlled input
@ Simple connection to a microcomputer.
The anode voltage of the LEDs and the number of simultaneously active outputs should be selected so that a total power dissipation of 800 mW in the IC is not exceeded.
Circuit description
A serial interface consisting of data input D, enable input E, and clock input CLK, to connect the IC to a microprocessor. The 16 bit information (“H” at input D corresponds to the current flow at outputs A1 to A16) is loaded into a 16 bit shift register via the serial data input, beginning with LSB. Data transfer is initiated by the HL slope of the clock pulse at CLK. The data transfer D can take place only during the H state of the enable input E. A buffer accepts the data from the shift register during the HL slope of the enable input. The buffer directly drives the outputs A1 to A16.
The output is limited by an internal resistor of 290 Q.
Through input C the outputs can be switched off (Vcg =0 V).
The inputs D, E, and CLK, and the input C are TTL-compatible.
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PHILIPS TDA3653B TDA3653C Vertical deflection and guard circuit (90 ̊)
GENERAL DESCRIPTION
The
TDA3653B/C is a vertical deflection output circuit for drive of various
deflection systems with currents up to 1.5 A peak-to-peak.
Features
• Driver
• Output stage
• Thermal protection and output stage protection
• Flyback generator
• Voltage stabilizer
• Guard circuit
FUNCTIONAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the o
utput stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
Flyback generator
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
Guard circuit
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.
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PHILIPS TDA2579 Horizontal/vertical synchronization circuit
PHILIPS TDA2579
GENERAL DESCRIPTION
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
• Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
• Triple current source in the phase detector with automatic selection
• Second phase detector for storage compensation of the horizontal output
• Stabilized direct starting of the horizontal oscillator and output stage from mains supply
• Horizontal output pulse with constant duty cycle value of 29 μs
• Internal vertical sync separator, and two integration selection times
• Divider system with three different reset enable windows
• Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
• Vertical comparator with a low DC feedback signal
• 50/60 Hz identification output combined with mute function
• Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
• Automatic adaption of the burst-key pulsewidth
PACKAGE OUTLINE
18-lead dual in line; plastic (SOT 102); SOT102-1; 1996 November 19.
FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The
IC embodies a synchronized divider system for generating the vertical
sawtooth at pin 3. The divider system has an internal frequency doubling
circuit, so the horizontal oscillator is working at its normal line
frequency and one line period equals 2 clock pulses. Due to the divider
system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to
50 Hz system. The divider system operates with 3 different divider reset
windows for maximum interference/disturbance protection. The windows
are activated via an up/down counter. The counter increases its counter
value by 1 for each time the separated vertical sync pulse is within the
searched window. The count is decreased by 1 when the vertical sync
pulse is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kΩ to earth or connecting a 3.6 V
diode
stabistor between pin 18 and ground. Narrow window: divider ratio
between 522-528 (60 Hz) or 622-628 (50 Hz). The divider system switches
over to this mode when the up/down counter has reached its maximum value
of 12 approved vertical sync pulses. When the divider operates in this
mode and a vertical sync pulse is missing within the window the divider
is reset at the end of the window and the counter value is decreased by
1. At a counter value below count 1 the divider system switches over to
the large window mode.
Standard TV-norm
When
the up/down counter has reached its maximum value of 12 in the narrow
window mode, the information applied to the up/down counter is changed
such that the standard divider ratio value is tested. When the counter
has reached a value of 14 the divider system is changed over to the
standard divider ratio mode. In this mode the divider is always reset at
the standard value even if the vertical sync pulse is missing. A missed
vertical sync pulse decreases the counter value by 1. When the counter
reaches the value of 10 the divider system is switched over to the large
window mode. The standard TV-norm condition gives maximum protection
for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 < 1.2 V) In this condition, only
noise is present, the divider is rest to count 628. In this way a stable
picture display at normal height is achieved.
Video tape recorders in feature mode
It
should be noted that some VTRs operating in the feature modes, such as
picture search, generate such distorted pictures that the
no-TV-transmitter detection circuit can be activated as pin V18 drops
below 1.2 V. This would imply a rolling picture (see Phase detector, sub
paragraph d). In general VTR-machines use a re-inserted vertical sync
pulse in the feature mode. Therefore the divider system has been made
such that the automatic reset of the divider at count 628 when V18 is
below 1.2 V is inhibited when a vertical sync pulse is detected. The
divider system also generates the anti-top-flutter pulse which inhibits
the Phase 1 detector during the vertical sync. pulse. The width of this
pulse depends on the divider mode. For the divider mode a the start is
generated at the reset of the divider. In mode b and c the
anti-top-flutter pulse starts at the beginning of the first equalizing
pulse.
The
anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60
Hz. The vertical blanking pulse is also generated via the divider
system. The start is at the reset of the divider while the pulse ends at
count 34 (17 lines) for 60 Hz, and at count 44 (22 lines) for 50 Hz
systems. The vertical blanking pulse generated at the sandcastle output
pin 17 is made by adding the anti-top-flutter pulse and the blanking
pulse. In this way the vertical blanking pulse starts at the beginning
of the first equalizing pulse when the divider operates in the b or c
mode. For generating a vertical linear sawtooth voltage a capacitor
should be connected to pin 3. The recommended value is 150 nF to 330 nF
(see Fig.1).
The capacitor is charged via an internal current source
starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset.
When the capacitor has reached a voltage value of 5.85 V for the 50 Hz
system or 4.85 V for the 60 Hz system the voltage is kept constant until
the charging period ends.
The charge period width is 26 clock
pulses. At clock pulse 26 the comparator is switched off and the
capacitor is discharged by an npn transistor current source, the value
of which can be set by an external resistor between pin 4 and ground
(pin 9). Pin 4 is connected to a pnp transistor current source which
determines the current of the npn current source at pin 3. The pnp
current source on pin 4 is connected to an internal zener diode
reference voltage which has a typical voltage of ≈ 7.5 volts.
The
recommended operating current range is 10 to 75 μA. The resistance at
pin R4 should be 100 to 770 kΩ. By using a double current mirror concept
the vertical sawtooth pre-correction can be set on the desired value by
means of external components between pin 4 and pin 3, or by connecting
the pin 4 resistor to the vertical current measuring resistor of the
vertical output stage. The vertical amplitude is set by the current of
pin 4.
The vertical feedback voltage of the output stage has to be
applied to pin 2. For the normal amplitude adjustment the values are DC =
1 V and AC = 0.8 V. Due to the automatic system adaption both values
are valid for 50 Hz and 60 Hz. The low DC voltage value improves the
picture bounce behaviour as less parabola compensation is necessary.
Even a fully DC coupled feedback circuit is possible.
Vertical guard
The
IC also contains a vertical guard circuit. This circuit monitors the
vertical feedback signal on pin 2. When the level on pin 2 is below 0.35
V or higher than 1.85 V the guard circuit inserts a continuous level of
2.5 V in the sandcastle output signal of pin 17. This results in the
blanking of the picture displayed, thus preventing a burnt-in horizontal
line. The guard levels specified refer to the zener diode reference
voltage source level.
Driver output
The driver output is at
pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The
internal impedance is approximately 170 Ω. The output pin is also
connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins
5,6,7,8 and 18) The video input signal is connected to pin 5. The sync
separator is designed such that the slicing level is independent of the
amplitude of the sync pulse. The black level is measured and stored in
the capacitor at pin 7. The slicing level value is stored in the
capacitor at pin 6. The slicing level value can be chosen by the value
of the external resistor between pins 6 and 7. The value is given by the
formula:
Rs
P = -------------------- -
× 100 ( R s value in kΩ )
5.3 + Rs
Where Rs is the resistor between pins 6 and 7 and top sync level equals 100%. The recommended resistor value
is 5.6 kΩ.
Black level detector
A
gating signal is used for the black level detector. This signal is
composed of an internal horizontal reference pulse with a duty factor of
50% and the flyback pulse at pin 12. In this way the TV-transmitter
identification operates also for all DC conditions at input pin 5 (no
video modulation, plain carrier only). During the frame interval the
slicing level detector is inhibited by a signal which starts with the
anti-top flutter pulse and ends with the reset vertical divider circuit.
In this way shift of the slicing level due to the vertical sync signal
is reduced and separation of the vertical sync pulse is improved.
Noise level detector
An
internal noise inverter is activated when the video level at pin 5
decreases below 0.7 V. The IC also embodies a built-in sync pulse noise
level detection circuit. This circuit is directly connected to pin 5 and
measures the noise level at the middle of the horizontal sync pulse.
When a signal-to-noise level of 19 dB is detected a counter circuit is
activated. A video input signal is processed as “acceptable noise free”
when 12 out of 15 sync pulses have a noise level below 19 dB for two
successive frame periods. The sync pulses are processed during a 15 line
width gating period generated by the divider system. The measuring
circuit has a built-in noise level hysteresis of approximately 3 dB.
When the “acceptable noise free” condition is found the phase detector
of pin 8 is switched to not gated and normal time constant. When a
higher sync pulse noise level is found the phase detector is switched
over to slow time constant and gated sync pulse phase detection. At the
same time the integration time of the vertical sync pulse separator is
adapted.
Video voltage ( black to whitep-p )
S ⁄ N = 20 Log --------------------------------------------------------------------------------------------------
-
Noiserms
Phase detector
The
phase detector circuit is connected to pin 8. This circuit consists of 3
separate phase detectors which are activated depending on the voltage
of pin 18 and the state of the sync pulse noise detection circuit. For
normal and fast time constants all three phase detectors are activated
during the vertical blanking period, this with the exception of the
anti-top-flutter pulse period, and the separated vertical sync-pulse
time. As a result, phase jumps in the video signal related to the video
head, take over of video recorders are quickly restored within the
vertical blanking period. At the end of the blanking period the phase
director time constant is increased by 1.5 times. In this way there is
no requirement for external VTR time constant switching, and so all
station numbers are suitable for signals from VTR, video games or home
computers. For quick locking of a new TV station starting from a noise
only signal condition (normal time constant) a special circuit is
incorporated. A new TV station which is not locked to the horizontal
oscillator will result in a voltage decrease below 0.1 V at pin 18. This
will activate a frame period counter which switches the phase detector
to fast for 3 frame periods during the vertical scan period. The
horizontal oscillator will now lock to the new TV-station and as a
result, the voltage on pin 18 will increase to approximately 6.5 V. When
pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is
switched OFF and the divider is set to the large window. In general the
mute signal is switched OFF within 5 ms (pin C18 = 47 nF) after
reception of a new TV-signal. When the voltage on pin 18 reaches a level
of 5 V, usually within 15 ms, the frame counter is switched OFF and the
time constant is switched from fast to normal during the vertical scan
period.
If the new TV station is weak, the sync-noise detector is
activated. This will result in a change over of pin 18 voltage from 6.5
V to ≈10 V. When pin 18 exceeds the level of 7.8 V the phase detector
is switched to slow time constant and gated sync pulse condition. The
current is also reduced during the vertical blanking period by 1 mA.
When desired, most conditions of the phase detector can also be set by
external means in the following way:
a. Fast time constant TV transmitter identification circuit not active, connect pin 18 to earth (pin 9).
b. Fast time constant TV transmitter identification circuit active, connect a resistor of 220 kΩ between pin 18 and ground.
This condition can also be set by using a 3.6 V stabistor diode instead of a resistor.
c. Slow time constant, (with exception of frame blanking period), connect pin 18 via a resistor of 10 kΩ to + 12 V, pin 10.
In this condition the transmitter identification circuit is not active.
d.
No switching to slow time constant desired (transmitter identification
circuit active), connect a 6.8 V zener diode between pin 18 and ground.
Supply (pins 9, 10 and 16)
The IC has been designed such that the horizontal oscillator and output stage can start operating by application of a very
low
supply current into pin 16. The horizontal oscillator starts at a
supply current of approximately 4 mA. The horizontal output stage is
forced into the non-conducting stage until the supply current has a
typical value of 5 mA. The circuit has been designed so that after
starting the horizontal output function a current drop of ≈ 1 mA is
allowed. The starting circuit has the ability to derive the main supply
(pin 10) from the horizontal output stage. The horizontal output signal
can also be used as the oscillator signal for synchronized switched mode
power supplies. The maximum allowed starting current is 9.7 mA (Tamb =
25 °C). The main supply should be connected to pin 10, and pin 9 should
be used as ground. When the voltage on pin 10 increases from zero to its
final value (typically 12 V) a part of the supply current of the
starting circuit is taken from pin 10 via internal diodes, and the
voltage on pin 16 will stabilize to a typical value of 9.4 V. In a
stabilized condition (pin V10 > 10 V) the minimum required supply
current to pin 16 is ≈ 2.5 mA. All other IC functions are switched on
via the main supply voltage on pin 10. When the voltage on pin 10
reaches a value of ≈ 7 V the horizontal phase detector circuit is
activated and the vertical ramp on pin 3 is started. The second phase
detector circuit and burst pulse circuit are started when the voltage on
pin 10 reaches the stabilized voltage value of pin 16 which is
typically 9.4 V. To close the second phase detector loop, a flyback
pulse must be applied to pin 12. When no flyback pulse is detected the
duty factor of the horizontal output stage is 50%. For remote switch-off
pin 16 can be connected to ground (via a npn transistor with a series
resistor of ≈ 500 Ω) which switches off the horizontal output.
Horizontal oscillator, horizontal output transistor, and second phase detector (pins 11, 12, 14 and 15)
The
horizontal oscillator is connected to pin 15. The frequency is set by
an external RC combination between pin 15 and ground, pin 9. The open
collector horizontal output stage is connected to pin 11. An internal
zener diode configuration limits the open voltage of pin 11 to ≈ 14.5 V.
The horizontal output transistor at pin 11 is blocked until the current
into pin 16 reaches a value of ≈ 5 mA. A higher current results in a
horizontal output signal at pin 11, which starts with a duty factor of ≈
40% HIGH. The duty factor is set by an internal current-source-loaded
npn emitter follower stage connected to pin 14 during starting. When pin
16 changes over to voltage stabilization the npn emitter follower and
current source load at pin 14 are switched OFF and the second phase
detector circuit is activated, provided a horizontal flyback pulse is
present at pin 12. When no flyback pulse is detected at pin 12 the duty
factor of the horizontal output stage is set to 50%. The phase detector
circuit at pin 14 compensates for storage time in the horizontal
deflection output stage. The horizontal output pulse duration is 29 μs
HIGH for storage times between 1 μs and 17 μs (flyback pulse of 12 μs). A
higher storage time increases the HIGH time. Horizontal picture shift
is possible by forcing an external charge or discharge current into the
capacitor at pin 14.
Mute output and 50/60 Hz identification (pin 13)
The
collector of an npn transistor is connected to pin 13. When the voltage
on pin 18 drops below 1.2 V (no TV-transmitter) the npn transistor is
switched ON. When the voltage on pin 18 increases to a level of ≈ 1.8 V
(new TV-transmitter found) the npn transistor is switched OFF. Pin 13
has also the possibility for 50/60 Hz identification. This function is
available when pin 13 is connected to pin 10 (+ 12 V) via an external
pull-up resistor of 10 to 20 kΩ. When no TV-transmitter is identified
the voltage on pin 13 will be LOW (< 0.5 V). When a TV-transmitter
with a divider ratio > 576 (50 Hz) is detected the output voltage of
pin 13 is HIGH (+ 12 V). When a TV-transmitter with a divider ratio <
576 (60 Hz) is found an internal pnp transistor with its emitter
connected to pin 13 will force this pin output voltage down to ≈ 7.6 V.
Sandcastle output (pin 17)
The
sandcastle output pulse generated at pin 17, has three different
voltage levels. The highest level, (10.4 V), can be used for burst
gating and black level clamping. The second level (4.5 V) is obtained
from the horizontal flyback pulse at pin 12, and is used for horizontal
blanking. The third level (2.5 V) is used for vertical blanking and is
derived via the vertical divider system. For 50 Hz the blanking pulse
duration is 44 clock pulses and for 60 Hz it is 34 clock pulses started
from the vertical divider reset. For TV-signals which have a divider
ratio between 622 and 628 or between 522 and 528 the pulse is started at
the first equalizing pulse. With the 50/60 Hz information the burst-key
pulse width is switched to improve the behaviour in multi-norm
concepts.
