SANYO CEP2177T YEAR 1989.

The SANYO CEP2177T is a 21 inches color screen DIGITAL television with 6 speaker sound system.

It has 60 programs with OSD and many features for a 21 Inches tellye including multistandard and CTI (DTI) Color transient improvement and teletext, furthermore even 2 AV SCART connectors and external louspeakers jacks and SHVS socket are present.


SANYO CEP2177T DIGITAL Colour television receiver or set , are known in which the majority of signal processing that takes place therein is carried out digitally. That is, a video or television signal is received in a conventional fashion using a known analog tuning circuit and then, following the tuning operation, the received analog television signal is converted into a digital signal and digitally processed before subsequently being converted back to an analog signal for display on a colour cathode ray tube.
In a conventional television receiver, all signals are analog-processed. Analog signal processing, however, has the problems at the video stage and thereafter. These problems stem from the general drawbacks of analog signal processing with regard to time-base operation, specifically, incomplete Y/C separation (which causes cross color and dot interference), various types of problems resulting in low picture quality, and low precision of synchronization. Furthermore, from the viewpoints of cost and ease of manufacturing the analog circuit, a hybrid configuration must be employed even if the main circuit comprises an IC. In addition to these disadvantages, many adjustments must be performed.

In order to solve the above problems, it is proposed to process all signals in a digital form from the video stage to the chrominance signal demodulation stage. In such a digital television receiver, various improvements in picture quality should result due to the advantages of digital signal processing.
Therefore digital television signal processing system introduced in 1984 by the Worldwide Semiconductor Group (Freiburg, West Germany) of International Telephone and Telegraph Corporation is described in an ITT Corporation publication titled "VLSI Digital TV System--DIGIT 2000." In that system color video signals, after being processed in digital (binary) form, are converted to analog form by means of digital-to-analog converters before being coupled to an image displaying kinescope. The analog color video signals are coupled to the kinescope via analog buffer amplifiers and video output kinescope driver amplifiers which provide video output signals at a high level suitable for driving intensity control electrodes of the kinescope.

The SANYO CEP2177T   Is a multistandard set and relates to a digital multistandard decoder for video signals and to a method for decoding video signals.
Colour video signals, so-called composite video, blanking and sync signals (CVBS) are essentially composed of a brightness signal or luminance component (Y), two colour difference signals or chrominance components (U, V or I, Q), vertical and horizontal sync signals (VS, HS) and a blanking signal (BL).
The different coding processes, e.g. NTSC, PAL and SECAM, introduced into the known colour television standards, differ in the nature of the chrominance transmission and in particular the different systems make use of different colour subcarrier frequencies and different line frequencies.
The following explanations relate to the PAL and NTSC systems, but correspondingly apply to video signals of other standards and non-standardized signals.
The colour subcarrier frequency (fsc) of a PAL system and a NTSC system is fsc(NTSC) = 3.58 MHz or fsc(PAL) = 4.43 MHz.
In addition, in PAL and NTSC systems the relationships of the colour subcarrier frequency (fsc) to the line frequency (fh) are given by fsc(NTSC) = 227.50 * fh or 4•fsc(NTSC) = 910 • fh fsc(PAL) = 283.75 * fh or 4•fsc(PAL) = 1135 • fh so that the phase of the colour subcarrier in the case of NTSC is changed by 180°/line and in PAL by 270°/line.
In the case of digital video signal processing and decoding the prior art fundamentally distinguishes between two system architectures. These are the burst-locked architecture and the line-locked architecture, i.e. systems which operate with sampling frequencies for the video signal, which are produced in phase-locked manner to the colour subcarrier frequency transmitted with the burst pulse or in phase-locked manner with the line frequency, respectively.

The principal advantage of the present invention is a color television receiver is provided having a fully digital color demodulator wherein the luminance signal and the chrominance signals are separated and digitally processed prior to being converted to analog signals in that the all-digital signal processing largely eliminates the need for nonintegratable circuit elements, i.e., particularly coils and capacitors, and that the subcircuits can be preferably implemented using integrated insulated-gate field-effect transistor circuits, i.e., so-called MOS technology. This technology is better suited for implementing digital circuits than the so-called bipolar technology.

Digital Signal Processing DIGVISION ITT in Brief:

 FOR several years now the use of digital techniques in television has been growing. A considerable impetus came initially from the need for high -quality Tv standards conversion. The IBA's DICE (Digital Intercontinental Conversion Equipment) standards converter came into operational use in 1972. It's success demonstrated convincingly the advantages of processing video signals in digital form - digital signals are neither phase nor level dependent. The trend since then has been towards the all - digital studio: digital effects generators have been in use for some time, and digital telecines were announced earlier this year. An earlier example of the application of digital techniques to television was the BBC's sound-in-syncs system, in which the sound signal is converted to digital form so that it can be added to the video signal for network distribution. The sound-in-syncs system first came into use in 1969, and is was  widely employed in pay tv systems alongside with video scrambling methods in the 80's.  Digital techniques have already appeared on the domestic TV scene. The teletext signals are digital, and require digital processing. In modern remote control systems the commands from the remote control transmitter are in digital form, and require digital decoding and digital - to -analogue conversion in the receiver before the required control action can be put into effect. Allied to this, digital techniques are used for the more sophisticated channel tuning systems. The basic TV receiver itself continues to use analogue techniques however. Are we about to see major changes here? 
ITT Semiconductors in W. Germany have been working on the application of digital techniques to basic TV receiver signal processing since 1977 with the supervision of the Engineer Micic Ljubomir, and at the recent Berlin Radio Show presented a set of digital chips for processing the video, audio and deflection signals in a TV receiver. The set consists of a' couple of l.s.i. and six v.l.s.i. chips - and by very large scale integration (v.l.s.i.) we're talking about chips that contain some more 200,000 transistors. What are the advantages? 
For the setmaker, there's reduction in the component count and simpler, automated receiver alignment - alignment data is simply fed into a programmable memory in the receiver, which then adjusts itself. Subsequently, the use of feedback enables the set to maintain its performance as it ages. From the user's viewpoint, the advantages are improved performance and the fact that extra features such as picture -within -a -picture (two pictures on the screen at the same time) and still pictures become relatively simple to incorporate. The disadvantage of course is the need for a lot of extra circuitry. Since the received signals remain in analogue form, analogue -to -digital conversion is required before signal processing is undertaken. As the c.r.t. requires analogue drive signals, digital -to -analogue conversion is required prior to the RGB output stages - the situation is somewhat different in the timebase and audio departments, since the line drive is basically digital anyway and class D amplifier techniques can be used in the field and audio output stages. In between the A -D conversion and the various output stages, handling the signals in digital form calls for much more elaborate circuitry - hence those chips with 200,000 or so transistors. The extra circuitry is all incorporated within a handful of chips of course, but the big question is if and when the use of these chips will become an economic proposition, taking into account reduced receiver assembly/setting up costs, compared to the use of the present analogue technology - after all, colour receiver component counts are already very low. With the present digital technology, it's not feasible to convert the signals to digital form at i.f. So conversion takes place following video and sound demodulation. Fig. 1 shows in simple block diagram form the basic video and deflection signal processing arrangement used in the system devised by ITT Semiconductors. Before going into detail, two basic points have to be considered - the rate at which the incoming analogue signals are sampled for conversion to digital form, and the number of digits required for signal coding. Consider the example shown in Fig. 2. At both (a) and (b) the signals are sampled at times Ti, T2 etc. In (a) the signal is changing at a much faster rate than the sampling rate. So very little of the signal information would be present in the samples. In (b) the rate at which the signal is changing is much slower, and since the sampling rate is the same the samples will contain the signal information accurately. In practice, the sampling rate has to be at least twice the bandwidth of the signal being sampled. Once you've got your samples, the next question is how many digits are required for adequate resolution of the signal, i.e. how many steps are required on the vertical (signal level) scale in Fig. 2 The use of a four -digit code, i.e. 0000, 0001 etc., gives 16 possible signal levels. Doubling the number of digits to eight gives 256 signal levels and so on. ITT's experience shows that the luminance signal requires 8 bits (digits), the colour -difference signals require 6 bits, the audio signal requires 12 bits (14 for hi-fi quality) while 13 bits are required for a linear horizontal scan on a 26inch tube. These digital signals are handled as parallel data streams in the subsequent signal processing. Returning to Fig. 1, the A -D and D -A conversion required in the video channel is carried out by a single chip which ITT call the video codec (coder/decoder). A clock pulse generator i.c. is required to produce the various pulse trains necessary for the digital signal processing, and a control i.c. is used to act as a computer for the whole digital system and also to provide interfacing to enable the external controls (brightness, volume, colour etc.) to produce the desired effects. In addition, the control i.c. incorporates the digital channel selection system. The video codec i.c. uses parallel A-D/D-A conversion, i.e. a string of voltage comparators connected in parallel. This system places a high premium on the number of bits used to code the signal in digital form, so ITT have devised a technique of biasing the converter to achieve 8 -bit resolution using only 7 bits (the viewer's eye does some averaging on alternate lines, as with Simple PAL, but this time averaging luminance levels). The A -D comparators provide grey -encoded outputs, so the first stage in the video processor i.c. is a grey -to -binary transcoder. As Fig. 3 shows, the processes carried out in the video processor i.c. then follow the normal practice, though everything's done in digital form. The key to this processing is the use of digital filters. These are clocked at rates up to 18MHz, and provide delays, addition and multiplication. The glass chroma delay line required for PAL decoding in a conventional analogue decoder consists of blocks of RAM (random-access memory) occupying only three square millimeters of chip area each. As an example of the ingenuity of the ITT design, the digital delay line used for chroma signal averaging/separation in the PAL system is used in the NTSC version of the chip as a luminance/chrominance signal separating comb filter. Fig. 4 shows the basic processes carried out in the deflection processor i.c. This employs the sorts of techniques we're becoming used to in the latest generation of sync processor i.c.s. Digital video goes in, and the main outputs consist of a horizontal drive pulse plus drives to the field output and EW modulator circuits. The latter are produced by a pulse -width modulator arrangement, i.e. the sort of thing employed with class D output stages. The necessary gating and blanking pulses are also provided. A further chip provides audio signal processing. One might wonder why the relatively simple audio department calls for this sort of treatment. The W. German networks are already equipping themselves for dual -channel sound however, and the audio processor i.c. contains the circuitry required to sort out the two -carrier sound signals. These chips represent a major step in digitalizing the domestic TV receiver. It seems likely that some enterprising setmaker will in due course announce a "digital TV set". The interesting point then will be whether the chip yields, and the chip prices as production increases, will eventually make it worthwhile for all setmakers to follow this path (in 1984).



The  SANYO CEP2177T   is a multisound tv digital sound processing.

A SCART Connector (which stands for Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs) is a standard for connecting audio-visual equipment together. The official standard for SCART is CENELEC document number EN 50049-1. SCART is also known as Péritel (especially in France) and Euroconnector but the name SCART will be used exclusively herein. The standard defines a 21-pin connector (herein after a SCART connector) for carrying analog television signals. Various pieces of equipment may be connected by cables having a plug fitting the SCART connectors. Television apparatuses commonly include one or more SCART connectors.

Although a SCART connector is bidirectional, the present invention is concerned with the use of a SCART connector as an input connector for receiving signals into a television apparatus. A SCART connector can receive input television signals either in an RGB format in which the red, green and blue signals are received on Pins 15, 11 and 7, respectively, or alternatively in an S-Video format in which the luminance (Y) and chroma (C) signals are received on Pins 20 and 15. As a result of the common usage of Pin 15 in accordance with the SCART standard, a SCART connector cannot receive input television signals in an RGB format and in an S-Video format at the same time.

Consequently many commercially available television apparatuses include a separate SCART connectors each dedicated to receive input television signals in one of an RGB format and an S-Video format. This limits the functionality of the SCART connectors. In practical terms, the number of SCART connectors which can be provided on a television apparatus is limited by cost and space considerations. However, different users wish the input a wide range of different combinations of formats of television signals, depending on the equipment they personally own and use. However, the provision of SCART connectors dedicated to input television signals in one of an RGB format and an S-Video format limits the overall connectivity of the television apparatus. Furthermore, for many users the different RGB format and S-Video format are confusing. Some users may not understand or may mistake the format of a television signal being supplied on a given cable from a given piece of equipment. This can result in the supply of input television signals of an inappropriate format for the SCART connector concerned.

This kind of connector is todays obsoleted !

On Top of all it's based around the DIGIVISION ITT TECHNOLOGY which is quite particular for a small screen format offering therefore superb pictures toghether with super sound.

This high class Digital Television from Japanese SANYO was designed by GIUGIARO design.

(Needless to say that the set in 22 Years was never serviced and runs good, QUALITY RULES !)


(To see the Internal Chassis Just click on Older Post Button on bottom page, that's simple !)

One more comment about digital in 2000..............

Over the years we have learnt that one of the most important things in video/ TV technology is selecting the best system to use. We have also seen how difficult this can be. Prior to the start of the colour TV era in Europe there was an great to-do about the best system to adopt. The US NTSC system seemed an obvious choice to start with. It had been proved in use, and refine- ments had been devised. But alternative, better solutions were proposed - PAL and Secam. PAL proved to be a great success, in fact a good choice. 

The French Secam system seems to have worked just as well. Apart from the video tape battles of the Seventies, the next really big debate concerned digital TV. When it came to digital terrestrial TV (DTT), Europe and the USA again adopted different standards. 

One major difference is the modulation system used for transmission. Coded orthogonal frequency   division multiplexing (COFDM) was selected for the European DVB system, while in the USA a system called 8VSB was adopted. COFDM uses quadrature amplitude modulation of a number of orthogonal carriers that are spread across the channel bandwidth. Because of their number, each carrier has a relatively low bit rate. 

The main advantage of the system is its excellent behaviour under multipath reception conditions. 8VSB represents a rather older,  pre phase modulation technoogy: eight  state amplitude modulation of a single carrier, with a vestigial sideband. The decision on the US system was assigned to the Advanced Television Systems Committee (ATSC), reporting to the FCC. The system it proposed was approved by the FCC on December 26th, 1996. The curious date might suggest that there had been a certain amount of politicking. In fact there had been an almighty row between the TV and computer industries about the video standard to adopt, the two fearing that one or other would gain an advantage as the technologies converged. It was 'resolved' by adopting a sort of   "open standard"  we are talking about resolution and scanning standards here - the idea apparently being that the technology would somehow sort itself out.

 There seems to have been rather less concern about the modulation standard. 8VSB was adopted because it was assumed to be able to provide a larger service area than the alternatives, including COFDM, for a given transmitter power. Well, the USA is a very large place! But the US TV industry, or at least some parts of it, is now having second thoughts. Once the FCC had made its decision, there was pressure to get on with digital TV. In early 1998 there were announce- ments about the start of transmissions and broadcasters assured the FCC that DTT would be available in the ten areas of greatest population concentration by May 1999. Rapid advances were expected, with an anticipated analogue TV switch -off in 2006. So far however things have not gone like that. At the end of 1999 some seventy DTI' transmitters were in operation, but Consumer Electronics Manufacturers Association estimates suggest that only some 50,000 sets and 5,000 STBs had been sold.

 There have been many reports of technical problems, in particular with reception in urban and hilly areas and the use of indoor aerials, also with video/audio sync and other matters. Poor reception with indoor aerials in urban conditions is of particular concern: that's how much of the population receives its TV. The UK was the first European country to start DTI', in late 1998 - at much the same time as in the USA. The contrast is striking. ONdigital had signed up well over 500,000 subscribers by the end of 1999, a much higher proportion of viewers than in the USA. Free STBs have played a part of course, but it's notable that DTT 's reception in the UK has been relatively hassle -free. In making this comparison it should also be remembered that the main aim of DTT technology differs in Europe and the USA. 

The main concern in Europe has been to provide additional channels. In the USA it has been to move to HDTV, in particular to provide a successor the NTSC system. There have been plenty of channels in the USA for many a year. For example the DirecTV satellite service started in mid 1994 and offers some 200 channels. Internationally, various countries have been comparing the US and European digital systems. They have overwhelmingly come down in favour of the DVB system. There have been some very damaging assessments of the ATSC standard. The present concern in the US TV industry results from this poor domestic take up and lack of international success. Did the FCC make a boob, in particular in the choice of 8VSB? Following compara- tive tests carried out by Sinclair Broadcasting Group Inc., the company has petitioned the FCC to adopt COFDM as an option in the ATSC standard. Not only did its tests confirm poor reception with indoor aerials: they also established that the greater coverage predicted for 8VSB failed to materialise in practice. Could the USA have two DTT transmission standards? It seems unlikely. It would involve dual standard receivers and non  standardisation of transmitters. In the all important business of system selection, it looks as if the FCC got it wrong.

              ....................................   It is obviously wasteful to duplicate terrestrial TV transmissions in analogue and digital form. Sooner or later transmissions will all be digital, since this is a more efficient use of spectrum space. The question is when? It would suit some to switch off the analogue transmitters as soon as possible. 2006 has been suggested as a time to start, with ana- logue transmissions finally ending in 2010. All very neat and tidy. Whether it will work out in that way is another matter. Strong doubts are already beginning to be aired. 

 The government has, quite properly, laid down conditions to be met before the switch off occurs. Basically that the digital signal coverage should equal that achieved for analogue TV, currently 99.4 per cent of the population, and that digital receiving equipment should be available at an affordable price. The real problem is that there is a difference between a coverage of 99.4 per cent and 99.4 per cent of the population actually having digital receiving equipment. Why should those who are interested in only free - to -air channels go out and buy/rent a digital receiver? It is already becoming evident that this represents a fair chunk of the population. 

The ITC has warned the government that the 2006-2010 timetable is in jeopardy. Peter Rogers, the ITC's chief executive, has said "we need to persuade people only interested in watching free -to -air television to switch to digital. "

Unless we do, there will be no switch - over." Well not quite, because the analogue receivers will eventually wear out and have to be replaced. But that could take a long, long time. Meanwhile many people will expect to be able to continue to watch their usual TV fare using their existing analogue receivers. 

Research carried out by Culture Secretary Chris Smith's department has established that between forty and fifty per cent of the population expects the BBC licence to cover their TV viewing, which means what they get at present in analogue form. A substantial percentage of the population simply isn't interested in going digital. In fact take up of integrated receiver -decoders, as opposed to the free digital set -top boxes, has so far been very slow. 

Of five million TV sets sold in the UK year 1999 , only 10,000 were digital. There are important factors apart from overall coverage and how many people have sets. There is the extension of coverage, which becomes more difficult to achieve eco- nomically as the number of those not covered decreases. There is the problem of reception quality. And there is the question of domestic arrangements and convenience. Extending coverage to the last ten fifteen per cent of the population by means of conventional terrestrial transmitters will be expensive. Mr Smith's department seems to have conceded that other methods of signal delivery may have to be adopted - by satellite, by microwave links or by cable. The latter has of course never been economic where few households are involved. 

The frequency planners have been trying to find ways of increasing coverage even to well populated areas. There are so many areas where problems of one sort or another make the provision of DTT difficult. Satellite TV is the obvious solution. 

The time may well come when it is wondered why anyone bothered with DTT. Signal quality is becoming an increasingly important factor as the digital roll out continues. In areas where the signal is marginal, viewers could experience the extreme irritation of picture break up or complete loss like even todays. This is quite apart from the actual quality of the channel, which depends on the number of bits per second used. There is a maximum number of bits per multiplex, the total being shared by several channels. The fewer the bits, the poorer the picture in terms of definition and rendering. 

There have already been complaints about poor quality. The question of domestic arrangements is one that has not so far received adequate public attention. Most households 2000 nowadays don't have just one TV set that the family watches. They have a main one, probably, almost certainly one or more VCRs, and several other sets around the house to serve various purposes. What 'the percentage of households that have digital TV' should really mean is the percentage willing to replace all this equipment. It will be expensive, and people would not be happy if they were told to throw away their other equipment when they get a single nice new all  singing all dancing widescreen digital TV set. It fact there would be uproar. The move from analogue to digital is not like that from 405 to 625 lines, which went fairly smoothly.

In those days few people had video equipment or a multitude of sets. The transition to digital is not going to be smooth, and the suggestion of a switch off during 2006-2010 already looks totally unrealistic. Unless the government subsidises or gives away digital TV sets - and why should it? - people will expect their existing equipment to continue to be usable.  

So it's likely that analogue TV will be with us for many years yet. But that would be the end of analogue too. 

.............................Indeed...............................

----------------------------------------------------------------------------



SANYO Electric Co., Ltd. (San'yō Denki Kabushiki-gaisha) (TYO: 6764, Pink Sheets: SANYY) is a major electronics company and member of the Fortune 500 whose headquarters is located in Moriguchi, Osaka prefecture, Japan. Sanyo targets the middle of the market and has over 230 Subsidiaries and Affiliates.



On December 21, 2009, Panasonic completed a 400 billion yen ($4.5 billion) acquisition of a 50.2% stake in Sanyo, making Sanyo a subsidiary of Panasonic.

 In July 2010, Panasonic announced to acquire the remaining shares of Sanyo.


Corporate culture

Sanyo utilizes an extensive socialization process for new employees, so that they will be acclimatized to Sanyo's corporate culture.

New employees take a five-month course during which they eat together and share company-provided sleeping accommodation. They learn everything from basic job requirements to company expectations for personal grooming and the appropriate way in which to address their coworkers and superiors.

History

Sanyo was founded when Toshio Iue (Iue Toshio, 1902–1969), the brother-in-law of Konosuke Matsushita and also a former Matsushita employee, was lent an unused Matsushita plant in 1947 and used it to make bicycle generator lamps. Sanyo was incorporated in 1950; in 1952 it made Japan's first plastic radio and in 1954 Japan's first pulsator-type washing machine.

 The company's name means three oceans in Japanese, referring to the founder's ambition to sell their products worldwide, across the Atlantic, Pacific and Indian oceans.


Technologically Sanyo has had good ties with Sony, supporting the Betamax video format from invention until the mid 1980s (the best selling video recorder in the UK in 1983 was the Sanyo VTC5000), and later being an early adopter of the highly successful Video8 camcorder format. More recently, though, Sanyo decided against supporting Sony's format, the Blu-ray Disc, and instead gave its backing to Toshiba's HD DVD. This was ultimately unsuccessful, however, as Sony's Blu-ray triumphed.


In North America, Sanyo manufactures CDMA cellular phones exclusively for Sprint-Nextel corporation's Sprint PCS brand in the United States, and for Bell Mobility in Canada.


The 2004 Chūetsu earthquake severely damaged Sanyo's semiconductor plant and as a result Sanyo recorded a huge financial loss for that year. The 2005 fiscal year financial results saw a 205 billion yen net income loss. The same year the company announced a restructuring plan called the Sanyo Evolution Project, launching a new corporate vision to make the corporation into an environmental company, plowing investment into strong products like rechargeable batteries, solar photovoltaics, air conditioning, hybrid car batteries and key consumer electronics such as the Xacti camera, projectors and mobile phones.

Sanyo's 3-year restructuring project


Sanyo posted signs of recovery after the announcement of positive operating income of 2.6 billion yen. Sanyo remains the world number one producer of rechargeable batteries. Recent product innovations in this area include the Eneloop Low self-discharge NiMH battery, a "hybrid" rechargeable NiMH (Nickel-metal hydride battery) which, unlike typical NiMH cells, can be used from-the-package without an initial recharge cycle and retain a charge significantly longer than batteries using standard NiMH battery design. The Eneloop line competes against similar products such as Rayovac's "Hybrid Rechargeable" line.


In December 2005 Sanyo had their new Super Sharp Technology patented.


In January 2006 Sanyo received a massive capital injection from Goldman Sachs, Sumitomo Mitsui Banking Corporation and Daiwa Securities which resulted in five members of the banks represented joining the nine-person Board of Directors.


On 24 November 2006, Sanyo announced heavy losses and job cuts.


Tomoyo Nonaka, a former NHK anchorwoman who was appointed Chairman of the company, stepped down in March 2007. The President, Toshimasa Iue, also stepped down in April of that year; Seiichiro Sano was appointed to head the company effective April 2007. In October 2007, Sanyo cancelled a 110 billion yen ($942 million) sale of its semiconducter business, blaming the global credit crisis for the decision and stating that after exploring its other options, it had decided to keep the business and develop it as part of its portfolio.


On April 1, 2008, they merged their cell phone division with Kyocera.


On November 2, 2008, Sanyo and Panasonic announced that they have agreed on the main points of a proposed buyout that would make Sanyo a subsidiary of Panasonic  and a formal announcement of the acquisition was made on Sanyo's web site on December 19, 2008.

They became a subsidiary of Panasonic on December 21, 2009.


On July 15, 2010 Sanyo agreed to sell its semiconductor operations to ON Semiconductor for $366 million to be completed before the end of 2010.

On July 29. 2010 Panasonic reached an agreement to acquire the remaining shares of Panasonic Electric Works and Sanyo shares for $9.4 billion.


By April 2012, parent company Panasonic plans to terminate the Sanyo brand, however it will be remain on some of the products where the Sanyo brand still hold value to consumers.

JAPAN IS STRANGE

Strange how situations change. It seems not so long ago that Japan and its industries, particularly electronics, could do no wrong. They taught us how to make cars and TV sets properly. They invested heavily and came up with a seem- ingly endless stream of desirable, innova- tive products. Both outsiders and insiders could see no end to this success story. We were told, by more than one leading Japanese electronics industrialist, that the 21st century would be the Japanese one, when Japan became predominant industri- ally and culturally. For the last couple of years the situation has been somewhat different. Japan is still the world's second largest economy, but the previous confidence has gone. The econo- my has stalled, and doesn't look like getting going again for some time. Profitability has become appalling, and the talk now is all of restructuring and job losses. Sony has announced that some 17,000 jobs will be lost worldwide, ten per cent of its workforce, while fifteen of its seventy factories are to be closed. Mighty Hitachi, whose activities span a much wider field and whose turnover is equivalent to over two per cent of Japan's gross domestic product, has launched a detailed review of its businesses. 6,500 of its 66,000 parent company employees are to be made redun- dant by March next year. On a consolidat- ed basis Hitachi is Japan's largest employ- er, with 330,000 staff. Businesses are to be dropped or reorganised. The story from Mitsubishi Electric is similar: there is to be a "sweeping restructuring of its portfolio of businesses". In the UK, the latest manifes- tation of this is the closure of Mitsubishi's VCR plant at Livingston. 14,500 jobs will go (8,400 in Japan) at Mitsubishi Electric, nearly ten per cent of the workforce. Other manufacturers who have announced poor results and restructuring recently include NEC, Matsushita, Sharp and Toshiba. It's all a long way since the time when, it seemed, all the Japanese had to do was to get the product right and produce more and more of it. Some of this was foreseeable. Markets reach saturation point; new products are not always a runaway success; if investment in new plant is excessive you end up with too much capacity; and so on. Then there is the fact that Japan is not isolated from econom- ic problems elsewhere: no economy that is heavily dependent on exports can be. But there are also more specific Japanese prob- lems. The banking system is beset by non- performing loans that Japanese bankers are reluctant to write off. The bubble economy of a few years ago, when asset values rose to unrealistic levels, collapsed. This is part of the cause of the banking system difficul- ties. Then there is the practice of cross - ownership, with firms owning substantial stakes in each other. This can work nicely when everything is doing well: when reces- sion looms, it aggravates the problems. Japan's unemployment rate hit a new high of 4.8 per cent (3.39m) in March, part- ly because of the corporate sector restructur- ing. Japanese industrialists hope to improve their profitability in the second half of the year, and will be helped by improved condi- tions in SE Asia. But it will be hard going, particularly to improve domestic market conditions. The Japanese have always had a high propensity to save. This increases when the economic climate is poor, with unemployment a threat. Right now Japanese consumers are saving rather than buying. No one seems to know how to alter their behaviour. There is also a demographic problem: the Japanese population is ageing. Japanese interest rates are negligible. So borrowing is not a problem. But conversely all those savings are bringing in little income. In the Western world interest rate changes often have a considerable impact on the economy. This economic tool is not available when interest rates are negligible. The Japanese have been advised to get their banking system sorted out, but that's not the sort of thing that can be done overnight. Right now the best opportunity for Japan seems to be to export its way out of its dif- ficulties, something that shouldn't be too difficult once worldwide expansion has resumed. But the high value of the yen is a drawback. From the economic viewpoint it's an extremely interesting situation, one in which the laws of economics have little to offer. This could be because such laws are, basically, descriptive rather than prescrip- tive. In the real world you can't always ini- tiate economic activity through monetary or fiscal means. Some commentators have gone so far as to suggest that the Japanese government should spend, spend, spend and print money to kick-start the economy. This is a dangerous course that can go badly wrong. It has already been tried by the Japanese government to a limited extent, with similarly limited success. The one thing that we do know is that economies are not stable. Change is ever present in one form or another. The prob- lem lies in trying to control it. This is all rather humbling, and certainly something of a comeuppance for the rather arrogant Japanese industrialists who had talked about the century of Japanese economic hegemony.

See also:

Osaka portalCompanies portal Kyocera Communications

List of digital camera brands
Mitsubishi Heavy Industries
Panasonic Wild Knights
Primearth EV Energy Co

Some References:

"Financial Results for FY 2011" (PDF). panasonic.net. Retrieved 19 April 2018.
"Consumer Market Research - Business Solutions - npd.com". npd.com. Retrieved 19 February 2015.

"Outline". panasonic.net. Retrieved 19 February 2015.

"Sanyo Electric Co., Ltd. - Panasonic". sanyo.com. Retrieved 19 February 2015.

Daisuke Wakabayashi (5 February 2010). "Sanyo Deal Hits Panasonic Results". WSJ. Retrieved 19 February 2015.

J. Impoco, "Basic Training, Sanyo Style". U.S. News & World Report, July 13, 1992, pp. 46–48.

http://assets.whirlpoolcorp.com/wp-content/uploads/history_100years_factsheet.pdf

Myer, Edwin W. (29 November 1982). "Hardware Review: Sanyo MBC 1000 Small Business Computer". InfoWorld. InfoWorld Media Group. p. 101. Retrieved 14 Feb 2017.

Shea, Tom (11 July 1983). "Sanyo Developing IBM Clone". InfoWorld. InfoWorld Media Group. p. 1. Retrieved 14 Feb 2017.

"Sanyo 555, small business computers. (evaluation)".

"Toshiba to give up on HD DVD, end format war: source". Reuters. February 16, 2008.

"The Japan Times - News on Japan, Business News, Opinion, Sports, Entertainment and More". The Japan Times. Retrieved 19 February 2015.

"Sanyo Chairwoman Tomoyo Nonaka resigns". UPI. Retrieved 19 February 2015.

"Login". timesonline.co.uk. Retrieved 19 February 2015.

NHKニュース　三洋電機 子会社化で大筋合意 Archived 2009-10-15 at the Portuguese Web Archive (NHK News: Agreement to Main Points to make Sanyo Electric a Subsidiary) Retrieved on November 2, 2008

Sanyo Press Release Retrieved on May 14, 2009

"www.sanyosemi.com has been integrated into www.onsemi.com".

"Panasonic Electric Works - Panasonic" (PDF). panasonic-electric-works.net. Archived from the original (PDF) on 14 December 2011. Retrieved 19 February 2015.

"Panasonic buying Sanyo and other unit for $9.4 billion". reuters.com. Retrieved 19 February 2015.

"Consolidation Continues: Panasonic To Buy Sanyo". Renewable Energy World. Retrieved 19 February 2015.

Brand name of Sanyo to be basically terminated in April 2012^{[permanent dead link]}

Rohit T. K. in Bangalore and James B. Kelleher (13 August 2013). "Whirlpool buys 51 percent stake in China appliance maker". Reuters.

http://solar.sanyo.com/hit.html

"404 Error - Page Not Found". www.imedinews.ge. Retrieved 19 April 2018.

"Power & Energy Technology - IHS Technology".

"Toshiba : Press Releases 27 April, 2001".

"Sanyo completes construction of lithium-ion battery facility in Japan" (Press release). Sanyo via Autoblog Green. 2010-08-10. Retrieved 2010-08-10.

BioAge Media. "Green Car Congress: Sanyo to More than Double NiMH Battery Production Based on Hybrid Demand".

"Sanyo India Launch". Financial Express. Retrieved 11 August 2016.

"Sanyo Smart TV Launch". Amazon Press Release. Retrieved 10 July 2017.

"Sanyo NXT Series". Economic Times. Retrieved 9 August 2017.

"Sanyo 4K Smart Series". Digit. Retrieved 6 December 2017.

"Sanyo EESL AC". Economic Times. Retrieved 24 May 2017.

"Sanyo LCD". TopTenREVIEWS. Retrieved 19 February 2015.

"Sanyo FVF5044". PCMAG. Retrieved 19 February 2015.

"Sanyo introduces 65-inch LCD TV for $998". CNET. CBS Interactive. Retrieved 19 February 2015.

SANYO CEP2177T CHASSIS 2021 (ED 2021) INTERNAL VIEW.

The SANYO CHASSIS 2021 is based around the DIGIVISION ITT TECHNOLOGY and is therefore a digital chassis.

On a monocarrier are fitted all circuits and the digital board is left postioned in a metal shield box.

On the front side is fitted a PCB carrying the system control.

Micom - SAB8032B-P
Memory -    NVM3060
SMPS - TEA2260 & 2SC4429
TR Chopper - AE0195
SAW - F5315 & B5308

Vertical - TDA8172

Sound - TDA2822M
Stereo -    TDA8425
Tuner - TD0122EA TERE2-005A
TV/AV -    TEA2014A
Tube - A59ECF10X01 AND OTHERS
FBT - FDB01 (HR7712)
HOT -    2SD1555 RGB Amp. - TDA6100Q

Other ICs - ADC2301E APU2471 DPU2553 DTI2223 LA7210 MC14066BCP MC14175BCP MC74HC573AN MCU2600 TDA8341 TDA2556 TDA1521 SAA3035 SPU2243 TPU2735 PVPU2204 VCU2136 TMS4256-12NL

 SANYO CEP2177T  CHASSIS 2021 (ED 2021) DESCRIPTION:

 This new chassis was  intended for cover the high range of TVC, incorporating the most advanced technology available for obtain elevated benefits, both in terms of control and quality of image AND stereophonic sound . further allows the incorporation direct from different TVC standards and peripheral circuits through two scart connectors (SCART).

As a novelty, it incorporates a treatment of the audio and video signals in  digital technic, plus a PIP system (Image in Image). The control system is by a microcontroller AND Program stored in EEPROM memory. All the settings minus the source voltage, NICAM and F.I. can be made from the M.D. in service mode. From what i know refers to the sound is prepared for receive in NICAM 728 and in German system IRG. It is also possible by adding circuits decoding signals SECAM. The functions performed by each of circuits are determined by the circuit characteristics integrated employees.

briefly...............

MAIN CHASSIS PCB
IC-100   (SAB 3035)  CITAC. Interface tuning control (via I2C bus)
IC -150   (TDA 8341)  Amplifier F.I. video with demodulator and circuit by CAG.
IC - 200  (TDA 2556)  Amplifier "QUASI PARALLEL" sound, with demodulator 5.5 MHz and 5.74 MHz.

IC-301 (TEA 2260)  Controller-power supply regulator
IC-350  (PQ12R04I) Stabilizer 12V voltage.
IC-352  (SI3052) Stabilizer voltage of 5 V.
IC-353-354 (PQ05R04I) Stabilizers voltage of 5 V.
IC-355  (L7805CV) Stabilizer voltage 5 V.
IC-390 (TDA 1521)  Amplifier audio power.
IC-401  (TDA 8172)  Amplifier vertical deflection power
D-350  (PC 113B)  Optocoupler. Controller   source current feeding.

PCB  TRC IC-601-611-621  (TDA 6100) Amplifier RGB signals output
IC-350  (L7812CV)  Stabilizer voltage of 5 V.
 
 CONTROLS-PUSH BUTTON PCB
IC-701  (SAB 8032 A)  Microcontroller 8 bits with a working frequency of  12  MHz.  and  32  lines of Entrance exit. Controls the I2C bus and IM
IC-703  (74HC573)  3-state LATCH, multiplexer  of the   bus of  data/ addresses
IC-704 (27C512)  64K EPROM memory 8-bit positions each contain the TV operating program.
IC-705  (TDA8425)   Processor  and headphone controller.
IC-706  (TDA 2822 M)  Amplifier headphone power.
IC-707 (LA 7210 ') FTZ Audio Mute

DIGITAL SIGNAL PROCESSOR PCB
IC-1  (MCU 2600)  Clock generator of operation of the C.I. of the plate, synchronize the clock with the chroma of the main image.
IC-2  (DPU 2553TC02DM)  Unit of deflection process deals digitally the whole deflection issue. (checked by IM bus)
IC-3  (TPU 2735TC20)  Process unit teletext) receives the TXT and generates characters on screen. (Checked by IM bus)
IC-4  (PVPU 2204TC03DM)  Unit of video process separates chroma and luminance  and  perform the  adjustment automatic cut-off and blank. (controlled by IM bus)
IC-6-19  (MVM 3060)  Memories no volatile, are used to memorize the data referring to the settings of the TV  So  as the  schedule of program. (Controlled by the IM bus)
IC-7  (DTI 2223TC06DM)  Improves transitions  digital signal Colour. (controlled by IM bus)
IC-8  (VCU 2136TCl9DM)  Make the A / D and D / A conversions of the signal video and RGB insertion on screen.
IC-11-12-13  (TDA 8440)  Switches video and sound for SCART connectors controlled via I2C bus.
I C - 1  4 (ADC230lETClO) A / D Converter audio (controlled by IM bus)
IC-15 (APU 247lTC78) Processing unitaudio (controlled by IM bus)

IC-17  (HY53C256)  32K DRAM memory by 8, store pages  teletext.

PCB P.I.P. OPTIONAL IC-1201 (VAD 2150 TCOl) Of video . A / D converter
IC-1203  (VPU 2203TC30)  Unit of PIP video process.  (checked by IM bus)
IC-1204  (DPU 2553 TC02DM)  Unit of process of  deflection  of the  PIP (controlled by IM bus)
IC-1205 (MCU 2600 TC 53) Generator PIP board clock, phase the clock with the chroma of the signal PIP.
IC-1206 -  (PIP 2250/12)  Controller PIP image, perform insert of the PIP in the main image as well as  Image stop effects, strobe and window situation. (checked
by IM bus).
IC-1207-8  (TMM 41464P-12)  Memories 64K DRAMs by 4, each, stores the digital image of the PIP.

NICAM PCB
IC-1510 (TA 8662 N) QPSK demodulator
IC-1540  -  (LC 3664NL-12)  RAM 64K high speed static with an 8K by 8 configuration.
IC-1541 (TC 6011N) PCM Decoder
IC-1550  (TD6710 AN) D / A Converter 14 bits.
IC-1560  (SN74LSl5N)  AND gates of 3 tickets
IC-1570  (LA6462D)  Amplifier operational
IC-1571-72  (LA6462S)  Amplifier operational

K-1590 (CD4066BE) Four analog switches.

 

CHASSIS 2021 (ED 2021) DETAILED VIEW:

 CHASSIS 2021 (ED 2021)  POWER SUPPLY:
This chassis incorporates a power supply power based on the internal circuit IC-301 TEA 2260 grade which uses the beginning of an SMPS font. His principal main characteristics are: limitation of the 4303 current on two levels, slow start, protection against short circuits and overvoltage. The working frequency is 30 KHz .; regulation is done by an optocoupler to stabilize the t 155 v .. The switching is carried out at through transistor Q303. Energy necessary for operation is obtained has the network from the rectification cator bridge formed by D301 to D304. The source stabilizes the voltage of output against voltage variations network and load and incorporates a protection against short circuits. The R313 supplies the initial current of start, when the supply voltage tion reaches the starting voltage (typically 10.5 V.) the circuit co begins to generate output pulses in the softstarting mode. Is that is, the generation of the departure is not abrupt but is done gently in three staggered steps ascendingly.

Once the source has started the voltage circuit power Integrated is obtained through the voltage recovered by D308 and R314. The PIN 16 supplies the voltage of supply to the power part of the IC 301, while pin 15 a through the R306 supplies the power to the low consumption part of the same. Pin 14 generates the pulse pulses departure to him transistor switching, these pulses go through a low pass filter to shape the shape signal and by a zener to limit the base voltage of 4303, R312 is the base exhaust resistance of 4303. When the Q303 she drives, circulate current through the primary of the choper; this stored energy will produce a voltage on the secondaries. The circuit consisting of R315, D309 and C315 serves as protection against f.c.e.m. of the primary of the chopper, so that no Let's overload the 4303. The 4304 is in charge of controlling the LED of the optocoupler D-385 (PC-1130); he actuation point is set by VR301, with which the voltages of the secondary ones. The reference signal is inserted into
pin 6, which is the error amplifier input. He integrated circuit compares internally the reference pulses with the pulses output by correcting the conduction of the transistor in order to obtain the stable output voltage zada * The R317 takes a sample from the 4303 output current so that introduces voltage on pin 3. This acts as protection against overload by eliminating the output pulses of pin 14 when it detects an excess consumption by the transistor. The components connected to the Call 10 and ll C311 and R307 determine the oscillator frequency in operation I lie normal. Yes a short occurs circuit at the output, it will produce a reference voltage drop (6) with which pin 7 will pass been high making the transistor Q302. This in turn will connect to ground the R309 causing the oscillator time constant and by Therefore, its frequency, activated thus varying protection.

The IC 301 itself generates the three pulses you are from soft starting after four them if the source is not able to start because the short circuit persists goes to come to a complete stop by pressing the mains switch in the case of make a new attempt. The source has five output outputs secondary: 155V for power lines, 33V tuning, 22v power sound 12V for C.I. and four 5V outputs for C.I. digital. The voltages of 12 and 5V are stabilized for a circuit integrated type PQl2R04I and PQ5R04I which act also as controlled switches by 4351 which in turn is controlled on the ON / Stand-by line.

 CHASSIS 2021 (ED 2021)  TUNING CIRCUIT AND TUNER SYNTHESIZER:
THe tuner used this ready to receive channels in CCIR standard, and designed to operate with a tuning by frequency synthesis whereby includes a departure from prescaler (divides the frequency of the local oscillator by 256). Terminals of the tuner correspond to the following functions: Terminal 1 - (FI) Intermediate frequency output Terminal 2 - not used Terminal 3 - (MB) Mixer supply + l2V Terminal 4 - (SB Feeding the prescaler + 5V Terminal 5 - (LB) Band 1 power supply, + l2V Terminal 6 - (AGC) AGC voltage Terminal 7 - (HB) Belt feed III, + l2V Terminal 8 - (TU) Tuning voltage Terminal 9 - (UB) Belt feed UHF, + l2V Tuning is done by integrated circuit IC 100 (Computer Interface for Tuning And Control) SAB 3035 this performs the functions of tuning control by frequency synthesis, band switching of the tuner as well as the selection of standard. The CITAC It is controlled via I2C bus by the IC 701 microcontroller. It has a frequency table with frequencies corresponding to each channel located in memory EPROM 

IC 704. Tuning is achieved from following form. The microprocessor via I2C bus sends information regarding the frequency of the channel to be tuned, he CITAC depending on the frequency assigns the tuning voltage; the tuner in turn generates the frequency prescaler (F.o.l./ 256) which the CITAC 'compares it with the desired value and corrects the tuning tension, repeating itself continuously ' said cycle, this principle is very similar to the fun- tion of a PLL. The channel frequency measurement has a resolution of 50 KHZ. Pins 5 and 6 are the managers to communicate with the microcontroller via I2c bus, the pin 16 is the 12V power supply. for him functioning internal of the IC-100, while pin 17 is the 33V supply. for tuning. Pin ll takes a reference for the AFT (approx. 6V.), while pin 12 is the AFT voltage input from the I.F. Of video. The Pin 23 is the input for the frequency of prescaler from the tuner, this latter supplies a typical voltage of 1Vpp. CITAC also has a series of input and output ports which are programmable via I2C bus from the microcontroller, these outputs are used as expansion paths of the same to control or receive data referring to the NICAM, scart and standard of reception. The information regarding NICAM (stereo, mono, dual) is present on pins 7 and 10 of CITAC from the NICAM module. The information information regarding the connection or disconnection of the scart connectors (pin 8 scart) enters pins 8 and 9 of the CITAC. The reference information to the receiving standard (B / G, D / K, 1) it exits pins 25, 28 and 26 respectively. These signs go towards the F.I. sound and video to perform the norm switching, depending on the application . CITAC uses a 4MHz oscillator as a clock. controlled by a crystal connected to pin 24.

 CHASSIS 2021 (ED 2021)  SOUND I.F. FREQUENCY:

The fi. audio consists of the integrated circuit IC-200 TDA 2556 el which is designed to demodulate two FM carriers for TV. stereo. Int ernament e has two stages of F.I .. The first treats jointly the video carrier and sound carrier with the in order to obtain the carriers of 5.5 MHz. And 5.74 MHz. Then we have a second stage which has two separate channels to demodulate the signals in F.M. . . The signal corresponding to the carriers of 33.4 MHz., 33.16 MHz. And 38.9 MHz. Are applied symmetrically to the IC200 pins 3 and 4 from the surface wave filter transducer Xl2S through capacitor C202 and transformer T201. Both carriers are amplified by the stage controlled by the AGC and internally applied to the 38.9 demodulator MHz.,, Whose resonant circuit, formed by T203 and C210 is connected to pins 21 and 22. The resulting signal It is composed of two intercarriers, one of 5.5 MHz. and another of 5.74 MHz. and appears on pins 19 and 6 of I C200 passing to the band-pass filters of 5.5MHz. (X212-3) and 5.74MHz. (
X201-2). The 5.5MHz intercarrier. is introduced to through pin 17 to amp limiter and from here to the FM demodulator corresponding, whose resonant circuit (T204 and C214) is connected to pins 13 and 14. On pin 15 we get the output signal corresponding to the L + R information (monophonic signal). On the other hand, the intercarrier of 5.74 MHz. Passes through pin 8 to limiting amplifier and demodulator of FM, whose resonant circuit (T202, C207) is connected to pins 11 and 12. On pin 10 of IC200 we obtain the corresponding output signal tooth to the 2R information and the 54.6875KHz pilot carrier. , which is modulated in AM by a signal of low frequency encoding mode of transmission.

 CHASSIS 2021 (ED 2021)  RGB FINAL STAGE CRT DRIVE:

The final video amplifiers IC-601-11-2 is it so compounds mainly by integrated circuits TDA 6100, this apart from performing the amplification of the video signal supply a current sample of each barrel to perform automatic adjustment of barrel shear and white together with the digital plate. Then we proceed to perform the description of the circuit. Pin 1 is the non-inverting input. This pin it is set at a voltage level to conveniently attack the cathode of the tube. Pin 2 performs power supply the bipolar part of the chip. Pin 3 is the inverting input, for use the integrated in inverter mode a feedback resistor is connected between pins 3 and 9 t said resistance determines the gain of the stage. Pin 5 reflects a sample of current flowing through the cathode during the cut-off time of the Canyon; during that time a pulse from the VCU of the digital board to the final video amplifier for ob have the current reading. The transmission of said pulses is carried out sequentially by each gun. This information is
sent to the signal processor circuit (digital board) and this to its once control the input signal with in order to correct the cut-off point of the Canyon. Pin 6 performs the power tion of the MOS output part of the integrated. This tension must be higher than the maximum expected to control the cathode, in our case feeding of this pin is approx. 200Vdc .. The Pin 8 is the output that attacks the all through a protection resistor of downloads. Pin 9 supplies an exit separate for perform feedback to pin 3 (inverting input).

 CHASSIS 2021 (ED 2021)  SOUND POWER AMPLIFIER:

The audio power amplifier consists of the integrated circuit IC-309 (TDA1521) and has configuration power operational amplifier The circuit is capable of supplying a musical power of 16 W / channel on an 8 Ohm load. Internally the circuit fix your profit maximum at 30dB per channel. This circuit has two types of muting one internal and other external. In the case of muting internal is the integrated circuit itself the one that inhibits non-investing inputs when it detects that the supply voltage drops below 6V. If of the mute external, these tickets (normally to ground) are disconnected by middle of the electronic switch for- by Q390 and Q391. These transis tors are controlled by pin 3 of CITAC (IC100). The description of the circuit is as follows: next. Pin 1 is input no left channel inverter and pin 2 is the inverting input. In this application and for asymmetric feeding said pin is connected to ground. Pin 4 is the power output left channel. Pin 5 is negative supply in case of symmetrical power supply and
in this application it is connected to ground l Pin 6 is the power output of the right channel. Pin 7 is the power supply, 22Vdc. from the power supply. The Pin 8 is the inverting input in this application going to ground. Pin 9 is the non-inverting input and in turn the right channel input.

 CHASSIS 2021 (ED 2021)  FRAME DEFLECTION:

 THE stage OF vertical Deflection is composed of the TDA8172 integrated circuit  and performs the functions of power amplifier and feedback generator. chunk. The input signal of the vertical comes from digital plate (pin 8 connector K51F). This sign comes out of the digital board properly shaped to drive the amp vertical sweep. The inverting input of the circuit integrated the we have on pin 1 and it is enter the sawtooth signal vertical. To the sideburns 2 and 4se apply power. This is obtained of the rectification of a symmetrical voltage recovered from the line. On the pin 3 the reverse generator is connected. During the fallback time charges capacitor C404 through D401 and during the sweep time the accumulated charge in the C404 adds to the feed through pin 6, thus obtaining an increase in voltage to obtain the peak-peak voltage of output during sweep time. The pin 5 is the output and applies directly to the vertical baffles. The R-C network applied between pin 5 (output) and pin 1 (input) determine the gain of the amplifier as well as its frequency response. In the output there is also a protection; when the deflection stage does not work vertical and no output pulses the D402 and R404 do not send a sample rectification of these impulses to the digital board (pin 7 connector K51F). With this will result in a decrease in voltage on the RGB outputs towards the amplifiers video endings, with in order to protect the tube.

 
 
 CHASSIS 2021 (ED 2021)  LINE DEFLECTION AND EHT:
 
 The lines stage is basically a stage of a conventional T.V.  although its controls and adjustments are made from the digital plate and through service mode. Initially we find two transistors Q452 and 4453 which are in charge of disconnecting the power of the Q451 line driver while the TV. is on stand-by. This control is performs through the order that gives them pin 11 of the IC701 microcontroller. Signal line deflection comes out of the digital PCB (pin 3 connector K5lF) already formed in correction in "S" and in width, this signal controls 4451 which through the transformer T450 conveniently attacks the base of the final transistor of, lines 4450. In the collector of the 4450 we find all the elements in charge of modulating the current deflection horizontal. The parabola signal required for E / W correction is generated by the digital PCB (pin 5 of the connector K5lF), through 4401 and Q402 to perform diode modulation. In the lines stage, has also a selector to alter the magnetic phase (deflection centering); this is done by placing the diodes D451 or D450 to + l55V. The digital PCB needs an H-FLY line reference BACK (pin 4 of K5lF), and a sample of the BCL beam current (pin 1 of K5lF) to control the phase of the line and on the other to limit the current beam entity. The T460 induce in the secondary of the diode-split acceleration voltage for the anode of the CRT. From the first section of this secondary is obtained using a resistive network I have them sions for focus and adjustment grille G2 (Screen). The T460 also incorporates the windings for the auxiliary impulses of the voltages of: + - 13Vdc. (Power supply picture), 200Vdc. (final video feed) and feeding the TRC filament.

 CHASSIS 2021 (ED 2021)  CONTROLS CIRCUIT:
 
 The control circuit performs the management of all the chassis functions, Digital PCB and PIP PCB. This is done through a microcontroller IC701 which has a stored program stored in an EPROM memory (IC704). The microcontroller action on the The rest of the integrated is carried out using two types of buses: the I2C and the IM. The information corresponding to both ap- pray on the same lines in full time match. On the control board there is we put in addition to: an in- LATCH (IC703), an integrated circuit degree to mute FTZ from audio (IC707), and two integrated circuits to control and amplify the audio of headphones (IC705) and (IC706). He integrated of control (microcontroller, IC701) is 8 bit and its frequency working time is 12MHz .. It has 32 input / output lines divided into 4 buses of 8 bits each; internally it has a memory for 256 by 8 bit RAM data. Initially, in stand-by, the microcontroller is powered by the 5V voltage. (pin 40), but does not start work until you receive an order reset. The reset
circuit is the made up of the 4701 and peripheral components and generates a pulse at the initial boot time. Once the device is started, either pressing the panel stand-by key controls or remote control, the microcontroller pin ll, change status, making the power supply voltages necessary for the operation of the chassis. (this process is explained in the FA.) He microcontroller needs a Program specific stored in a EPROM memory (IC704) which has a 512 Kbit capacity, or 64K positions of 8 bits each. This implies that we will need 16 bit for address memory and 8 data bits. EPROM memory (IC704) is 16 bit input addresses AO-A7 (8 bit low) and A8-Al5 (8 bit high). The 8 bit data appear on pins 00-07. 

The microcontroller uses the bus of the 8 bit less weight as address bus tions-data. For it, uses a integrated LATCH (IC703) in series with the bus as multiplexer, so that, at through pin 30 of the ALE micro (Address Latch Enable), the information that appears on the bus, be addresses or data. The process of reading a data from the program stored in memory is as follows: the microcontroller places by bus 0 (8 low bits) and bus 2 (8 high bits), the 16 bit addresses necessary to find the data in the memory. The highest weight 8 bits go directly to: memory, while the 8 least significant bits pass through of LATCH, being memorized in your departure. The LATCH then receives the multiplex signal (pin 11) making your inputs dispense with the data that will appear in the EPROM output on bus 0, to read by the microcontroller. On the other hand, the EPROM receives the order to OE (Output enable), pin 22 of IC704, doing that with a response time (read) of 200 nsec. the data appears addressed above and this is read by the microcontroller. The microcontroller has two buses more, bus 1 and bus 3. Bus 1 is used exclusively to read the information formation of the keyboard matrix. This reading is carried out at discrete intervals. time cough. Bus 3 (or por-t 3) lo uses the microcontroller as a communication with the rest of the integrated circuits whether they are from the main PCB signal or signal processor PCB by using the communication between integrated I2C and IM. Bus 3 also reads the information training from the recipient of infrared and it is internally the microcontroller that is responsible for encode and execute the commands. On the pushbutton control PCB there is also an integrated to perform a FTZ sound mute (IC707) .This IC takes a sample (pin 6) of the composite video signal at the output of the video detector and when detects absence of signal, acts on its pin 10, making it go to high level. Then the 4704 drives making pin 1 of the mic (IC701) is grounded, whereby the microcontroller by program will interpret that it has to effect a mute of Audio. This mute is done via I 2 C bus the order leaves bus 3 (SDA line) towards pin 5 of the CITAC. The latter will interpret that you must mute the audio by doing that its pin 3 goes high and will cause the Q391 to saturate. This one to the turn will cut Q390, which will determine that the non-inverting inputs of the sound IC are disconnected from ground causing the mute audio. This mute is also done to the same time on scart (SCART).
 

 On the control board we have two integrated circuits for control of the headphones. On the one hand the IC 705 as processor and controller audio and the IC706 as a headphone power. The TC705 performs the following functions tions: selection of two signal sources, balance control, volume, mute, treble and bass. All these functions are controlled via bus I2C by the micro- controller, bliss communication is set across pins ll and 12 of the IC705, SDA and SCL respectively. He circuit integrated has the possibility to be able to select two input audio signal sources Ll- Rl and L2-R2. Internally the integrated a via the I2C bus selects the audio signals that they arrive from the plate digital (PIP sound or sound from main image). The 4707 and components townhouses have the mission to carry out a soft connection and disconnection taking advantage of the time constant of the C758, so that the snap on the headphones when turning on and turn off the TV. Once the IC705 has performed the relevant controls of the sound of the headphones, the output signal (pin 13 and 20) is input to the amplifier power IC706. This amplifier has a gain of 36 dB sufficient to conveniently excite the headphones.

 SIMPLE QUICK WAY TO EXPLANE DIGITAL PROCESSING OF AUDIO AND VIDEO SIGNALS:

 
 The process of handling the audio and video signals on this TV is digital, that is, what in analog process receivers is a continuous signal over time transforms into a discrete and encoded signal at known intervals of time. This has a number of advantages already that allows to increase the versatility of controls over the signal and perform most of the settings automatically.
 
The functions it performs to the signal processor PCB are as follows:
1- Digital processing of the video signal (chroma in PAL)
2- Digital processing of the synchronisms.
3- Digital processing of the teletext signal.
4- Digital audio processing.
5- Digital processing of the chroma signal for SECAM B / G (Optional)
6 - Switching of the scart inputs.

As an introduction to functioning of the digital processor PCB we will say that internally there are the following main communication buses between Integrated: Digital Video Bus, Bus digital luma, digital chroma bus and IM-12C bus. Then we will go to explanation of the functionality of each one of the integrated circuits that make up the digital board.

THE VCU
The VCU, IC 8 (Video Codec Unit), unit encoding and decoding video signal, can be divided into two stages, the first stage converts the signal analog in digital, inter- openly we have a treatment of the signal digitized by a series of integrated circuits that we will comment on later (DPU, TPU, VPU, DTI) and finally a stage where the signal is converts to analog.

The VCU needs on its video input composite (pin 35) an amplitude signal 2 Vpp. to make the most of the ability to quantify with- versor A / D, the signal is encoded with 7 bits which gives us a differentiation 128 levels, on the other hand it is necessary that the entry be centered between 5 and 7V. in order to match the 5V level. with the coding (0000000) and make the most of the quantization, adjusting the level of 5V. is carried out with the help of the DPU which has a clamping circuit that supplies a signal to the VCU so that match the 5V level. with the encoding (0000000). The signal once digitized (encoded with 7 bits) leaves the VCU (pin 2-8) as information through the Video Bus to the DPU, TPU, VPU and SPU, to be processed in these circuits. Once the signal has been processed is reintroduced into the VCU: for a side the digital luma Bus (pin 10-17) and on the other the digital chroma bus (pin 18-21) from the DTI. Internally the VCU converts signals from luminance and chroma and performs the matrixing in order to obtain the signals RGB (pin 26-28) which go to the TRC socket. The VCU has a entrance that collects a sample of the beam current (pin 34) for current limiter operation beam. The VCU together with the VPU carry out the white balance as well as adjustment automatic cutting of the cannons. The pins 30-33 are arranged as inputs analog which through the Bus RGB coming from the TPU is harnessed to insert the teletext characters with the RGB signal of the image. The insertion of the PIP on the main image is done by the Chroma Bus and digital luma which also arrive of the PIP.

  DIGITAL DEFLECTION PROCESSING:

DPU, IC 2 (Deflection Processor Unit), is the processing unit of the deflection. The DPU is responsible for the following functions: separation of synchronism, generation and synchronization, of the frequencies of vertical and horizontal, E / W corrections and tooth generation, vertical saw including correction in "S". The DPU communicates with the microcontroller (IC701) on the control board via IM bus (pin 16-18 of IC2), in order to make all the settings of the image corrections using the remote control and being previously in service mode and the TV with a fit letter in the picture. The procedure is explained at the end of this Handbook. When there is no station reception, the deflection is obtained from a 4 MHz oscillator; that also works when the appliance is in stand-by. The DPU takes a reference from the stage of lines (pin 23, H-FLY BACK) to put in phase the frequency of lines with the station synchronism. The DPU generates erase pulses V and H for the DTI and TPU circuits. The signal vertical
sawtooth exits through pin 27, vertical stage An exit sample is collected by the pin 25; this acts as protection as it cuts the beam when it detects a level less than 2 V .. The output of the parabola signal appears on the pin 28 and is programmable (setting geometry). The DPU also has a similar output (color-key, pin 19) on the sandcastle impulse, said signal they use the VPU and VCU. The DPU communicates with the microcontroller via bus I2C (pin 16-18). The internal operation of the DPU is controlled by the 17.734 MHz frequency. (PAL or SECAM) which is supplied by the clock frequency generator (IC-l), in function of transmission standard.

DIGITAL TELETEXT PROCESSING:

The TPU, IC 3 (Teletext Processor Unit), it in charge of perform the teletext decoder functions and character generator that is used also as an on-screen display. The signal enters the video bus digital (pins l-4 and 40-39). The TPU uses only 6 bits of the video bus, neglecting the lighter bit since the teletext signal is digital and only takes the values "1" AND "0". Internally the TPU begins the period data acquisition on line 7 and ends on line 22, is also capable of make up for reflections of short period of time (from 0 to 0.8 useg.). On pins 11 and 12 are inserted H and V reference for teletext sync. Pins 10 and 32-34 are RGB inputs from scart Pins 6-9 are the analog RGB teletext outputs to the VCU. RGB selection teletext / RGB scart is performed via IM bus from the microcontroller. TPU needs an external memory to store teletext pages, these are stored in the IC-17, which is a 32K by 8 DRAM memory TPU is controlled via IM bus (pin 14-16) by the microcontroller.

DIGITAL VIDEO PROCESSING:
The VPU, IC 4 (Video Processor Unit) performs PAL processing of the video enabling saturation controls color, brightness and contrast, it is also responsible for separating digital chrominance and digital luminance. The VPU together with the VCU carry out automatic control of cut-off and White. Communication between these integrated circuits takes place during the vertical return via bus chrominance, the data sent is the / cut-off and white levels. The digital video signal enters the VPU through the corresponding port (pins 5-ll); internally the VPU separates the luminance minance by treating them down two different paths. The signal chrominance digital passes initially through a digital chroma band pass filter, then through a automatic color control. This circuit needs the color-key signal to separate the burst, so said signal enters through pin 1 from pin 19 of the DPU. Next, PAL decoding is carried out. having the digital signals (R-Y) and (B-Y). The reference signal for the chrominance is sent to the MCU
through of pins 25 and 26 to put 17.734 MHz in phase with the signal of chrominance, so that all Integrated circuits through the OM signal work at 17.734 MHz. in phase with the chrominance signal (in PAL). The digital chrominance signals (B-Y) and (R-Y) are corrected for saturation and come out through pins 27-30 of the VPU towards the VCU, where the matrix will be carried out together with the luminance signal. On the other hand, the light signal nance is internally modified in brightness and contrast before exiting through the digital luminance bus (pin 32-39). This signal goes to the VCU where the matrixing with the signals (B-Y) and (R-Y) will be carried out to obtain the outputs of RGB. The VPU also has the following input pins: Pin 13, V and H reference input from DPU, pin 15 input from reference for automatic adjustment of cut-off, pin 16 reference input for automatic white adjustment. Communication with the microcontroller It is carried out via IM bus through the pins 2-4.

DIGITAL TRANSIENT IMPROVEMENT PROCESSING:
The DTI, IC 7 (Digital Transient Improvement) is responsible for improving color signal transitions. For This uses two delay lines (with adjustable delay via IM bus 0-6luseg.) one for chrominance and one for luminance, so that it retards both signals to reduce the chrominance transmission time. This wants say that the signals are delayed by time equal to the improvement of the transition. Both signals, luminance and chrominance, are output on two separate buses towards the VCU. On these exit buses the chrominance and luminance bus of the PIP are also connected to make the inserting this into the main image. The input buses to the DTI come from of the VPU and they are: chrominance bus digital (pin 17-20), digital luma bus (pins 6-13). Internally these signals are processed in the manner described above and exit to the VCU through the buses of: digital chrominance (pins 22-25) and digital luminance (pins 27-34). The DTI is controlled by the microcontroller via IM bus through the pins 3-5. Reference signals of the clock, V and H enter through the pins 2.38.39.

DIGITAL SECAM VIDEO PROCESSING:
SPU (Option1) The SPU, IC 18 (Secam processor Unit), chrominance processing unit in SECAM is optional on the digital PCB. In the application is not listed, although the PCB you are ready to insert it. The SPU takes care of the entire process chroma treatment in SECAM. The input signal is taken from the digital video (output the VCU) and processes chrominance in SECAM by demodulating the signals (B-y> Y (R-Y) l Then these signals are multiplexed in a compatible way to output from the digital chrominance bus output to the VPU. The SPU also includes an automatic identification of the SECAM signal. The processing time of the signal chroma in SECAM is higher than in PAL or NTSC signals. To compensate for this re I delay the SPU delay the video signal compound that there is in its entrance a time what is approximately 5.5 useg. (only in SECAM mode). The output signal of the SPU (bus digital chroma) 'can be inhibited or uninhibited via pin 22. In In the case of uninhibiting the bus, it remains in high impedance state. The SPU it is also controlled by the microcontroller via IM bus and receives the signal clock (OM).

MAIN CLOCK UNIT:
The MCU, IC 1 is a clock generator, which is used for the rest of integrated circuits. Operation is based on the PLL concept. The VCO is controlled by a quartz crystal multiple of the chroma frequency F. (OM) = 4 by 4.43361875 MHz = 17.734475 MHz. (in the case of PAL and SECAM signals). The phase comparator and digital filter are placed on the VPU. The signal phase difference is supplied by the VPU to pin 6 of the MCU; this sign is controlled in turn by the signal of clock reference (4.43MHz.) which is entered into the MCU through the pin 5. The output signal (Clock OM, 17.734 MHz.) Put in phase with the chrominance we have it present in pin 3.

DIGITAL AUDIO PROCESSING:

The audio processing on the digital signal processor PCB is composed of by two integrated circuits the ADC (IC 14) and the APU (IC 15). These integrated are in charge of converting the signal audio in digital and process it digitally. On the one hand the audio signal (L + R, 2R and pilot) in the case of IRG transmission 6 L and R in the case of NICAM transmission enters the ADC integrated circuit, IC 14 (analog / digital converter) by pins 5.4 and 8 l The ADC has the ability to power switch their inputs with two signals Auxiliaries (Scart 1 and 2) which are inserted to pins 21 and 24 and exit through the exits to the APU, or through pins 22 and 23, towards the Integrated input switches. The ADC internally converts the signal analog into digital and encodes it in PDM, (Pulse Density Modulation), pulse density modulation. The output of these PDMl and PDM2 signals (pins 10 and ll) go to the APU (pin 16 and 17) where will be digitally processed. The APU, IC 15 (Audio Processor Unit), is in charge of processing
audio, digitally performing the following tasks: volume control and balance, bass and treble control, loudness control and pseudostereo. Internally the APU controls the signals via IM bus (pin 3-5) from the microcontroller in order to perform the functions described above. Once the signal is processed, goes through a D / A converter which has attached at his exits some emitter followers (Q7-8-9-10). The APU has four channels of Output: 2 speaker outputs and monitor out outputs, and 2 auxiliary outputs for the integrated circuit of headphone control (IC 705).

SIGNAL INPUTS SWITCHING:

Video and audio signals in the two scart sockets (SCART) and on the camera and S-VHS connectors, they are switched through IC-11-12-13 integrated, which are controlled in turn by the microcontroller via I2C bus, it is i.e., the input source selection is performs from microcontroller.

DIGITAL PIP FUNCTION:

The functions performed by the PCB of the PIP are as follows: 1- A / D conversion of the video signal. 2 - Digital processing of the PIP video signal (chrominance in PAL) 3- Digital processing of the synchronisms. 4- Timer storage of the video signal. In the PIP they can enter: composite video from the IF, composite video from the connectors SCART, and S-VHS signal. In the case of a S-VHS video chrominance and luminance they come separated, is necessary mix them to get composite video. This is the mission of the circuit formed by Ql202-1203-1204-1205.

The composite video signal enter to Integrated VAD (Video A / D Converter) through pin 12 with a level of 2 Vpp. , while the composite signal of the S-VHS video enters at pin 16 with a level of 1 Vpp .. Internally the VAD selects by pin 10 (SV) the signal source that will pass to the converter , pin 10 goes to the circuit integrated PIP and is controlled via IM bus from the microcontroller. Since remote control can be controlled this selection. The VAD converts the video signal (analog) to digital, encoded with 7 bit. This signal goes out through the port (pin 3-9) towards the entrance of the VPU and the DPU. The operation of the VPU is totally similar to that of the digital board base (but not are interchangeable with each other). The VPU separates the chrominance and digital luminance that output on pins 39-34 Digital Luminance Bus and 27-30 Chroma Bus digital. These 'buses go to the integrated PIP where the controls these signals before storing them in memory. The VPU, on the other hand, also performs video signal control (brightness, contrast, saturation) of the PIP. The VPU provides the carrier reference chrominance to the MCU via the pins 25 and 26 for the MCU to synchronize the clock (OM) with the chroma of the PIP. A feature to consider is that the luminance bus coming out of the VPU is only 6 bits / sample. This It is done to occupy less memory than h a c e r picture stop and at the strobe function.

The digital video bus is also connects to the DPU where the synchronisms The operation is basically the same as that of the DPU of the digital PCB. Both the digital chrominance bus and the digital luminance bus coming out of the VPU go towards the integrated PIP. This integrated has the primary function of insert the image of the PIP on the main TV picture., in addition to performing the functions of image stop, strobe and magnification of image. Below is a block diagram of the integrated circuit of the PIP.

On the other side there are signals of input what are they :: chrominance bus digital (4 bit) pin 63-66, luminance bus digital (6 bit) pin 57-62, signal MSKW pin 44 (comes from the DPU of the PCB digital and provides the information for the information phase adjustment video signal from the TV.), MHVB signal pin 45 (Horizontal / Vertical Blanking) comes from also from the DPU of the digital PCB and used to insert the window into the desired place. The PSKEW signals (pin 56) and PHVB (pin 55) supply the same information than the previous ones but coming from the DPU of the PIP. On the other hand are the signs of memory control. The memory required to store the video signal in the most unfaborable condition that is strobe function is 256K times 2 that is, two memories are necessary; 64K DRAMs for 4 each. IC-1208-1207 integrated circuits are memo- dynamic rias that they need some refresh cycles of stored data. The storage system is by rows and columns, since it is only has an addressing bus of data (pins 2-9), are also needed two signals that inform when steering a row or a column. These signals are CAS (pin 20) and RAS (pin 21). 

On the other side, the reading and writing order is given by pin 22 (WE). The bus memory data is input-out and is between pins 10-17. The data that has been read into memory, previously processed come out of integrated PIP by digital chrominance bus (pins 31-34) and by bus digital luminance (pins 36-43). These buses are connected to the digital PCB where they are connected in parallel with the same as the main image. The integrated PIP provides a high level on pin 47 (ODQUT, which goes to pin 36 of the DTI) during the time line in which there is PIP. During this time the chromimance buses and luminance of the main image remain inactive giving way to the PIP buses. When pin 47 is at low state, the process is reverse making the information circulate by the chrominance and luminance buses of the digital PCB is that of the image principal. On the board we have an MCU the which supplies the clock (OM) in phase with the chroma of the PIP to all the integrated ones of the plate.


DIGITAL NICAM PROCESSING:
The NICAM module used is from analog type since the demodulation process is makes by methods analog. It is physically available in two modules that can be inserted into the chassis, that are interconnected with each other. A brief description of it follows. The signal from F.I. of sound enters the NICAM module by K15C connector from the sound part of the IC200. This signal is initially introduced by a stage tuned to 5.85 MHZ. (Q1502 and peripheral components) which makes a first selection of the NICAM signal. Then pass by an impedance adapter (Ql503) and by an amplifier stage (41530) to compensate the losses produced by L1530. Said coil is adjustable and performs a band pass filter which is tune to 5.85 MHz. to make a better signal selection before enter the QPSK demodulator (IC 1510). This integrated circuit takes care of demodulate the signal in quadrature, and needs a reference frequency of 5.85 MHz. to demodulate the signal. 

This reference is extracted from the glass x1510,, the fine adjustment of the frequency it is done using the VCl510 trimmer. The demodulated signal (digital pulses) is output from IC1510 pin 29 to the PCM (Pulse codec Modulation) decoder ICl541, which performs the digital demodulation of the pulses. For To carry out this process, the IC 1541 needs a RAM memory (IC1540) to to stock data temporarily, bliss memory is a high speed static RAM with a capacity of 8K by 8. IC 1541 supplies the digital signal audio (pin 8-11) to the converter analog / digital (IC 1550), also supplies the signals encoding the type of transmission (dual, stereo, mono> (pins 23-25). These signals are apply to 3-input AND gates (IC1560) which together with the Ql565-6 transistors perform the switching transmission mode. This information is entered into the chassis by middle of the Kl5F connector. Signs of audio (L and R) are output from pins 1 and 12 of IC1550 and go through some filters 15 KHz low pass. (Ll570-1) the which are responsible for shaping and limit bandwidth. The sign of audio once conformed goes through operational amplifiers (IC-1570-l-2) which perform an equalization signal (for each channel) with object to recover the frequency response of the original signal, the outputs of said equalizers (L and R) go through a few emitter followers Ql590-1 before of come into integrated switch (ICl590) which is responsible for performing a jumper on channels L + R and 2R when no NICAM (IRG or mono transmission), or inserting the L and R channels into the nest when it detects NICAM.


REMOTE CONTROL:

This chassis uses as a transmitter for remote control IC-O1 (M5046 -46FP). For transmission is used infrared radiation with a length of 950 nm waveform .. Transmitted commands consist of a start pulse (duration 13.5 msec.), 16 bits for a user code (customer code, de duration 27 msec.) and finally 16 bits for the data code (duration 27 msec.). While holding a key pressed, the command is repeated intervals of approximately 108 msec. (1 command duration is 67.5 msec.). For better timing of the reception uses a P.P.M. (modulation by pulse position) so that a '1' or a '0' is detected depending on the time between pulses.
The encoded information is modulated with a 38 KHz carrier. before the transmission. The transmitter has the possibility to decode 64 function keys in addition to being able to provide three functions different per key. On the other hand, the reception has an infrared receiver degree (IR-701) that is responsible for capturing and treating the signal (AGC, filtered, limiter). The integrated receiver output signal goes to pin 12 of the IC-701 where the demodulation process is carried out, decoding and executing the command.

EEPROM CIRCUIT:

The EEPROMs on the Signal Processor PCB (I C - 1 9 and IC-6) are two reprogrammable non-volatile memories. Your ability to memory is 8192 bits. Character data is stored in these memories variable such as referents adjustments to corrections and geometry, TV memorizations, program memory, etc. The broadcast (data reading and writing) is carried out through the IM BUS. Important note : When EEPROMs (IC-19, IC-6), care should be taken to perform the initialization of the same; from the local keyboard press the service mode and volume keys (+) at the same time, then on screen the text WRITE NVM will appear, the routine it will end when the t e x t or END is output. Then go to service mode and use the remote control to enter the code corresponding to the model. Then press the button service mode and volume t.

CIRCUITS DESCRIPTIONS:

TEA2260 SWITCH MODE POWER SUPPLY CONTROLLER:



.POSITIVE AND NEGATIVE CURRENT UP TO
1.2A and – 2A
.LOW START-UP CURRENT
.DIRECT DRIVE OF THE POWER TRANSISTOR
.TWO LEVELS TRANSISTOR CURRENT LIMITATION
.DOUBLE PULSE SUPPRESSION
.SOFT-STARTING
.UNDER AND OVERVOLTAGE LOCK-OUT
.AUTOMATIC STAND-BY MODE RECOGNITION
.LARGE POWER RANGE CAPABILITY IN
STAND-BY (Burst mode)
.INTERNAL PWM SIGNAL GENERATOR


DESCRIPTION
The TEA2260/61 is a monolithic integrated circuit
for the use in primary part of an off-line switching
mode power supply.
All functions required for SMPS control under normal
operating,transient or abnormal conditions are
provided.
The capability of working according to the ”masterslave”
concept, or according to the ”primary regulation”
mode makes the TEA2260/61 very flexible
and easy to use. This is particularly true for TV
receivers where the IC provides an attractive and
low cost solution (no need of stand-by auxiliary
power supply).

GENERAL DESCRIPTION
The TEA2260/61 is an off-line switch mode power
supply controller. The synchronization functionand
the specificoperationin stand-bymodemake itwell
adapted to video applications such as TV sets,
VCRs, monitors, etc...
The TEA2260/61 can be used in two types of
architectures :
- Master/slave architecture. In this case, the
TEA2260/61 drives the power transistor according
to the pulse width modulated signals generated
by the secondary located master circuit. A
pulse transformer provides the feedback (see
Figure 1).
- Conventional architecture with linear feedback
signal (feedback sources : optocoupler or transformer
winding) (see Figure 2).
Using the TEA2260/61, the stand-by auxiliary
power supply, often realized with a small but costly
50Hz transformer, is no longer necessary. The
burst mode operation of the TEA2260/61 makes
possible the control of very low output power (down
to less than 1W) with the main power transformer.
When used in a master/slave architecture, the
TEA2260/61and also the power transistor turn-off
can be easily synchronized with the line transformer.
The switching noise cannot disturb the
picture in this case.
As an S.M.P.S.controller, the TEA2260/61features
the following functions :
- Power supply start-up (with soft-start)
- PWM generator
- Direct power transistor drive (+1.2A, -2.0A)
- Safety functions : pulse by pulse current limitation,
output power limitation, over and under voltage
lock-out.
S.M.P.S. OPERATING DESCRIPTION
Starting Mode - Stand By Mode
Power for circuit supply is taken from the mains
through a high value resistor before starting. As
long as VCC of the TEA2260/61 is below VCC start,
the quiescent current is very low (typically 0.7mA)
and the electrolytic capacitor across VCC is linearly
charged. When VCC reaches VCC start (typically
10.3V), the circuit starts, generating output pulses
with a soft-starting. Then the SMPS goes into the
stand-bymode and the output voltage is a percentage
of the nominal output voltage (eg. 80%).
For this the TEA2260/61 contains all the functions
required for primary mode regulation : a fixed frequency
oscillator, a voltage reference, an error
amplifier and a pulse width modulator (PWM).
For transmission of low power with a good efficiency
in stand-by, an automatic burst generation
system is used, in order to avoid audible noise.
Normal Mode (secondary regulation)
The normal operating of the TV set is obtained by
sending to the TEA2260/61regulation pulses generated
by a regulator located in the secondary side
of the power supply.
This architectureuses the ”Master-slave Concept”,
advantages of which are now well-known especially
the very high efficiency in stand-bymode, and
the accurate regulation in normal mode.
Stand-by mode or normal mode are obtained by
supplying or not the secondary regulator. This can
be ordonneredfor exemple by a microprocessor in
relation with the remote control unit.
Regulation pulses are applied to the TEA2260/61
through a small pulse-transformer to the IN input
(Pin 2). This input is sensitive to positive square
pulses. The typical threshold of this input is 0.85V.
The frequency of pulses coming from the secondary
regulator can be lower or higher than the
frequency of the starting oscillator.
The TEA2260/61has no soft-starting system when
it receives pulses from the secondary. The softstarting
has to be located in the secondary regulator.
Due to the principle of the primary regulation,
pulses generated by the starting system automatically
disappear when the voltage delivered by the
SMPS increases.
Stand-by Mode - Normal Mode Transition
During the transition there are simultaneously
pulses coming from the primary and secondary
regulators.
These signals are not synchronizedand some care
has to betaken toensure the safety of theswitching
power transistor.
Avery sure and simple way consist in checking the
transformer demagnetization state.
- A primary pulse is taken in account only if the
transformer is demagnetized after a conduction
of the power transistor required by the secondary
regulator.
- A secondary pulse is taken in account only if the
transformer is demagnetized after a conduction
of the power transistor required by the primary
regulator.
With this arrangement the switching safety area of
the power transistor is respected and there is no
risk of transformer magnetization.
The magnetization state of the transformer is
checked by sensing the voltage across a winding
of the transformer (generally the same which supplies
the TEA2261). This is made by connecting a
resistor between this winding and the demagnetization
sensing input of the circuit (Pin 1).


SECURITY FUNCTIONS OF THE TEA2260 (see flow-chart below)
- Undervoltage detection. This protection works
in association with the starting device ”VCC
switch” (see paragraph Starting-mode - standby
mode). If VCC is lower than VCCstop (typically
7.4V) output pulses are inhibited, in order to avoid
wrong operation of the power supply or bad
power transistor drive.
- Overvoltage detection. If VCC exceedsVCCmax
(typically 15.7V) output pulses are inhibited. Restarting
of the power supply is obtained by reducing
VCC below VCCstop.
- Current limitation of the power transistor. The
current is measured by a shunt resistor. Adouble
threshold system is used :
- When the first threshold (VIM1) is reached, the
conduction of the power transistor is stopped
until the end of the period : a new conduction
signal is needed to obtain conduction again.
- Furthermore as long as the first threshold is
reached (it means during several periods), an
external capacitor C2 is charged. When the
voltage across the capacitor reaches VC2 (typically
2.55V) the output is inhibited.This is called
the ”repetitive overload protection”. If the overload
diseappears before VC2 is reached, C2 is
discharged, so transient overloads are tolerated.
- Second current limitation threshold (VIM2).
When this thresholdis reached the output of the
circuit is immediatly inhibited. This protection is
helpfull in case of hard overload for example to
avoid the magnetization of the transformer.
- Restart of the power supply. After stopping due
to VC2, VIM2, VCCMax or VCCstop triggering, restart
of the power supply can be obtained by the
normal operating of the ”VCC switch” but thanks
to an integrted counter, if normal restart cannot
be obtained after three trials, the circuit is definitively
stopped. In this case it is necessary to
reduce VCC below approximately 5V to reset the
circuit. From a practical point of view, it means
that the power supply has to be temporarily disconnected
from any power source to get the
restart.


TDA8172 TV VERTICAL DEFLECTION OUTPUT CIRCUIT

DESCRIPTION
The TDA8172 is a monolithic integrated circuit in
HEPTAWATTTM package. It is a high efficiency
power booster for direct driving of vertical windings
of TV yokes. It is intended for use in Color and B &
W television as well as in monitors and displays.


SAB3035 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)

GENERAL DESCRIPTION
The SAB3035 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver

FUNCTIONAL DESCRIPTION
The SAB3035 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).

The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50 .


TDA8341 Television IF amplifier and demodulator

DESCRIPTION
The TDA8340;Q and TDA8341;Q are integrated IF
amplifier and demodulator circuits for colour or black/white
television receivers, the TDA8340;Q is for application with
n-p-n tuners and the TDA8341;Q for p-n-p tuners.
The TDA8340;Q and TDA8341;Q are pin-compatible
successors with improved performance to types
TDA2540/2541;Q and TDA3540/3541;Q.
Features
· Full range gain-controlled wide-band IF amplifier
· Linear synchronous demodulator with excellent
intermodulation performance
· White spot inverter
· Wide-band video amplifier with noise protection
· AFC circuit with AFC on/off switching and
sample-and-hold function
· Low impedance AFC output
· AGC circuit with noise gating
· Tuner AGC output for n-p-n tuners (TDA8340) or p-n-p
tuners (TDA8341)
· External video switch for switching-off the video output
· Reduced sensitivity for high sound carriers
· Integrated filter to limit second harmonic IF signals
· Wide supply voltage range
· Requires few external components.

PHILIPS TDA2556 QUASI-SPLIT-SOUND CIRCUIT WITH DUAL SOUND DEMODULATORS

GENERAL DESCRIPTION
The TDA2556 is a monolithic integrated circuit for quasi-split-sound processing, including two FM
demodulators, for two carrier stereo TV receivers and VTR.
Features
First IF (vision carrier plus sound carrier).
0 3 stage gain controlled IF amplifier
0 AGC circuit
0 Reference amplifier and limiter amplifier for vision carrier (V.C.) processing
0 Linear multiplier for quadrature demodulation
Second IF (two separate channels for both FM sound signals).
0 4-stage-limiting amplifier
0 Ouadrature demodulator
0 AF amplifier with de-emphasis
O Output buffer
0 Muting for one or both AF outputs

TDA1521 TDA1521Q 2 x 12 W hi-fi audio power amplifier:
GENERAL DESCRIPTION
The TDA1521/TDA1521Q is a dual hi-fi audio power amplifier encapsulated in a 9-lead plastic power package.
The device is especially designed for mains fed applications (e.g. stereo tv sound and stereo radio).
Features
· Requires very few external components
· Input muted during power-on and off
(no switch-on or switch-off clicks)
· Low offset voltage between output and ground
· Excellent gain balance between channels
· Hi-fi according to IEC 268 and DIN 45500
· Short-circuit-proof
· Thermally protected

THROUBLESHOOTING  SANYO CHASSIS ED1 CHASSIS  2021 (ED 2021)

Sanyo     ED1
    Unable to change chans via front or r/c    Adjust G2 volts - micro tied up due to low emiss crt        

Sanyo    ED1 CBP2872
    No colour    PVPU2204 chip        

Sanyo    ED1 CBP2572
    Service mode access    1). Press and release memory key (diamond) on front panel. (Factory shows on screen) 2). Press Index/Menu key on remote control within 5 seconds. The first tab on the serv.. menu was highlighted allowing me to enter the configuration code (I had been told 02014 was required) directly from the keypad. Pressing the remote menu key again changed the on screen display to the next tab heading "Geometry" with a list of features HO, SO, SI, AO, YO, etc............ with the top one HO being highlighted and vertical amplitude and a number written alongside. Sure enough operating either VOL+ or VOL- enabled adjustment of the on screen number and the vertical size of the picture displayed. To alter the next parameter, press the sound button [under the volume + button] to highlight the next tab down. The recommended values are as follows; CONFIGURATION NO. 02014 SETS SOUND INTERCARRIER/STANDARD ETC. HO 02140; SO 01012; S1 00081; AO 00186 YO 00050; PO 15861; ZO 01369; P1 01665 Z1 00087; SP 00009        

Sanyo    ED1 CBP2572
    Field collapse at top of screen    C460/461 1000µ 25v, C408 4µ7 50v, IC401 TDA8172 & R464 1R 1w  

     
Sanyo    ED1
    Trips 4 times then dead    R314 10R in psu - LT supply once set has fired up        

Sanyo    ED1
    Pic blanked out at sw on except for 2" strip at bottom    Dry joints Q453 in st/by sw cct        

Sanyo    ED1
    No pic - just bright glow at top of screen    DPU2553 IC508 on digital pcb pt no 409 211 87 01   

    
Sanyo    ED1
    Mosaic - like pic    IC502 PVPU2204 (PAL vid proc unit)        

Sanyo    CBP2872 ED1
    No sound when sw on if still warm    IC560 ADC2301E on sigs panel pt no 409 211 9404  

     
Sanyo    CBP2872 ED1
    No sound - comes on briefly when cold sometimes with crackle/hiss    OK from scart socket - IC561 APU2471 could be faulty        

Sanyo    CBP2872 ED1
    Lines when cold with shading as warms up    C404 (100mfd 50v) in the frame stage was the culprit, although its ESR reading was OK, and there were no signs of leakage       

 
Sanyo    CBP2572 ED1
    WHITE DOT PATTERN    DTI2223-06 , ON DIGITAL PCB   

    
Sanyo    CBP2572 ED1
    To reprog NVM memory chips    Press service button (thro' hole in set front) & VOL+ together - be careful - all previous data will be lost!        

Sanyo    CBP2572 ED1
    STRANGE E/W FAULT    CHECK DPU2553/75 ON DIGI BOARD       

 
Sanyo    CBP2572 ED1
    Q903 s/c R301 ( 3R9 ) o/c    Check R3165 D/J and TEA2260

Sanyo    CBP2572 ED1
    Int loss off air signals    Q173 D/J   
   
Sanyo    CBP2572 ED1
    EW faulty    DPU2553/75 deflection proc chip       
   
Sanyo    CBP2572 ED1
    Dead    R301 3R9 15w surge res o/c, Q303 2SC4429 chopper tr s/c, R315 dry joints caused it-also IC301 TEA2260 faulty       
   
Sanyo    CBP2572 ED1
    Dark & lacking contrast    Unable to get "OK" indication when adj A1 volts in service mode. IC501 VCU2136 on digital pcb faulty - pt no 409 212 0608       
Sanyo    CBP2572 ED1
    Blank raster, no sound or OSD    2 x NVM chips on sigs panel sus; can be replaced or reprog       
   
Sanyo    CBP2572 ED1
    BLANK RASTER NO SOUND NO ON SCREEN DISPLAYS . MEMO    REPLACE OR TRY RE-PROGGRAMMING BY PRESSING THE SERVICE SWITCH AND VOLUME PLUS BUTTON TOGETHER . SERVICE SWITCH BEHIND SMALL H