SYNCHRONIZATION WITH TDA 2595.
The TDA2595 is a monolithic integrated circuit intended for use in colour television receivers.
· Positive video input; capacitively coupled (source impedance < 200 W)
· Adaptive sync separator; slicing level at 50% of sync amplitude
· Internal vertical pulse separator with double slope integrator
· Output stage for vertical sync pulse or composite sync depending on the load; both are switched off at muting
· j1 phase control between horizontal sync and oscillator
· Coincidence detector j3 for automatic time-constant switching; overruled by the VCR switch
· Time-constant switch between two external time-constants or loop-gain; both controlled by the coincidence detector j3
· j1 gating pulse controlled by coincidence detector j3
· Mute circuit depending on TV transmitter identification
· j2 phase control between line flyback and oscillator; the slicing levels for j2 control and horizontal blanking can be set
· Burst keying and horizontal blanking pulse generation, in combination with clamping of the vertical blanking pulse
· Horizontal drive output with constant duty cycle inhibited by the protection circuit or the supply voltage sensor
· Detector for too low supply voltage
· Protection circuit for switching off the horizontal drive output continuously if the input voltage is below 4 V or higher
than 8 V
· Line flyback control causing the horizontal blanking level at the sandcastle output continuously in case of a missing
· Spot-suppressor controlled by the line flyback control.
QUICK REFERENCE DATA
Supply voltage (pin 15) V15-5 = VP typ. 12 V
Sync pulse amplitude (positive video) Vi(p-p) min. 50 mV
Horizontal output current I4 typ. 50 mA.
In, for example, a television monitor, a deflection current produced by a deflection circuit output stage is synchronized to the horizontal sync pulses that are derived, using a conventional sync separator, from the incoming television signal. Direct synchronization of the deflection oscillator from the sync pulses may not be desirable due to excessive tendency of the deflection current generated by the output stage to be affected by disturbances, caused by, for example, noise that is present in the sync pulses. Instead, a phase-locked loop (PLL) is typically used for eliminating such disturbances. A PLL of this kind may comprise a tunable oscillator and a phase discriminator with a downstream low-pass filter. The phase discriminator provides comparison of a certain assigned reference edge of the oscillator output signal with the sync pulse leading edge or center. A control voltage, or a control current, arising from the phase deviation is integrated in the low-pass filter and supplied to the oscillator as a DC voltage, or DC current, that varies the oscillator frequency and phase until the phase of the oscillator output signal and that of the corresponding sync pulse are the same. The remaining residual error depends on the control steepness or the loop gain.
It may be desirable that the response time of the PLL to phase, or frequency, variation of the sync pulses will not be too fast, in order to avoid scan line jitter due to disturbance caused by noise in the sync pulses. This is, typically, achieved by means of a relatively large time constant of the low-pass filter and a small total gain. However, such large filter reduces, by itself, the capture, or lock-in, range of the oscillator of the PLL. Such capture range is defined, for example, as the maximum difference between the oscillator free running frequency and the frequency of the synchronizing input signal that enables lock-in of the oscillator to the sync pulses. Moreover, to avoid unnecessary lengthening of the capture or lock-in time, it may be desirable to specify that the capture range be limited to substantially not more than the maximum necessary in view of the maximum difference between the frequency of the sync pulses and the free running frequency of the oscillator that is encountered in operation. Limitation of the capture range to the maximum necessary may be achieved, for example, by limitation of the maximum range of variation of the control current that controls the oscillator frequency.
Frequency variations of the sync pulses, that occur in the course of, for example, receiving an incoming television signal in a conventional television receiver, generally are small relative to the frequency of the sync pulses. Therefore, in such application, imposing a limitation on the maximum control range of the control current that controls the oscillator frequency does not pose a problem. However, in some other applications, such as in television monitors that are designed for receiving incoming signals having diverse sync frequencies, a given frequency of the sync pulses may be one that is selected from a possible wide span of frequencies. For example, the frequency of the sync pulses may be a frequency selected from a span of frequencies between 15,750 to 31,500 Hz. Therefore, a desirable narrow capture range that straddles, or lies, from a frequency that is below, to a frequency that is above, a fixed free running frequency of the oscillator, is not sufficiently wide to permit synchronizing the oscillator over the entire possible span of frequencies of the sync pulses.
In accordance with an aspect of the invention, a source of an output signal has a frequency that is controlled in accordance with a combined control current flowing at a control terminal of the source. The combined control current includes a first control current that is produced by a phase detector. The phase detector is responsive to the output signal and to a synchronizing input signal. The first control current controls the phase of the output signal in accordance with the phase of the input signal. A frequency-to-current converter that includes a frequency-to-voltage converter in responsive to the synchronizing input signal. The frequency-to-voltage converter generates a voltage that is indicative of the frequency of the synchronizing input signal. The voltage generated by the frequency-to-voltage converter is coupled to a voltage-to-current converter that generates a second control current that is indicative of the frequency of the synchronizing input signal.
In a circuit embodying the invention, the output signal is produced by an oscillator (OSC) of a PLL. When synchronized, the OSC oscillates at the horizontal frequency. The OSC output signal controls the timing of the deflection cycles formed by a deflection circuit output stage. The first control current signal that controls the frequency of the OSC is indicative of the phase difference between the horizontal sync pulses and the output signal of the OSC. Illustratively, the first control current signal synchronizes the phase of the output signal to coincide with the phase of the horizontal sync pulses. The second control current signal establishes the free running frequency of the OSC. A given capture range of the OSC corresponds with a given value of the second control current signal. The capture range may extend, for a given free running frequency of the OSC, from a frequency that is, a fraction of the horizontal frequency below, to a fraction of the horizontal frequency above such free running frequency. Thus the capture range is narrow relative to the free running frequency of the OSC.
The second control current signal can assume a value from a spread of values. Such value, advantageously, causes the free running frequency of the OSC to be approximately equal to the frequency of the sync pulses. Thus, the frequency of the sync pulses may be selected from a required wide span of frequencies. Such span of frequencies may lie, for example, between 15,750 and 31,500 Hz. Thus, the frequency of the sync pulses that may be selected from the wide span of frequencies may lie within the narrow capture range of the OSC that is established by the second control current signal.
The capture range associated with a given value of the second control current signal is substantially narrower than the entire span of frequencies, any value of which can be assumed by the sync pulses. It follows that a relatively narrow capture range is associated with each given frequency of the sync pulses. In this way, a short capture, or lock-in time of the OSC to the phase and frequency of the sync input signal is maintained. The second control current signal is capable of varying or shifting the capture range, illustratively, anywhere within the entire required span of frequencies, any of which may be assumed by the sync pulses. The second control current signal maintains the capture range relatively narrow by adjusting the free running frequency of the OSC to be approximately equal the frequency of the sync pulses.
The frequency detector may include a filter having a large time constant for, advantageously, eliminating noise from the second control current signal. Such filter that is responsive to the sync pulses is situated outside the feed-back loop of the PLL. Therefore, such filter, advantageously, does not affect the transient response to the PLL to phase variations of the sync pulses that do not amount to a steady state frequency change.
In accordance with yet another aspect of the invention, the voltage-to-current converter of the frequency detector includes a transistor that generates the second control current signal at the collector electrode of the transistor. The collector electrode of the transistor is coupled to the control terminal of the OSC for supplying the second control current signal that is combined at the control terminal with the first control current signal to provide the combined control current signal. The impedance at the collector electrode of the transistor is substantially higher than that at the control terminal. Therefore, advantageously, the transistor does not affect the impedance at the control terminal of the OSC. Moreover, because the transistor operates as a nearly ideal current source, the second control current signal, advantageously, is independent of the voltage at the control terminal.
In, for example, some television receivers, the retract pulses produced by the horizontal deflection circuit output stage are coupled to a power supply that produces therefrom an energizing voltage that energizes other circuits of the receiver. To prevent faulty modes of operation of such other circuits that may cause harm to such circuits and also to avoid possible harm to the deflection circuits, it may be desirable to maintain the frequency of the deflection current and that of the retrace pulses higher than a predetermined minimum frequency. Operation with a deflection frequency that is above such predetermined minimum frequency will prevent possible harm to some television circuits that may occur if the deflection frequency is lower.
In accordance with yet another aspect of the invention, the frequency of the OSC output signal is maintained above the predetermined minimum frequency even when the frequency of the sync pulses is lower. Thus, for example, when the incoming television signal is not received, the OSC output signal has a frequency that is maintained above the predetermined minimum frequency.