REX (Zanussi) 20RA374.2 COLUMBIA (T53845000) (013129900) CHASSIS BS700.4 INTERNAL VIEW.

The Zanussi CHASSIS BS700.4 is a monocarrier chassis and it's the brother of the BS700 which differs basically in few parts.

The main difference in CHASSIS BS700.4 is the implementation of the CCU ITT TVPO2066-SAM04 which features all the controls of the set and basic type of OSD (On Screen Display).

The Power supply is based on TDA4601 (Siemens)

TDA4601 Operation.

* The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600
device, the TDA4601 however has improved switching, better protection and cooler running.

The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type,
which operates on the same basic principle as a line output stage. It is turned on and off by a
square wave drive pulse, when switched on energy is stored in the chopper transformer
primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic
flux collapses, causing a large back emf to be produced. At the secondary side of the chopper
transformer this is rectified and smoothed for H.T. supply purposes.
The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz
according to load) allows the use of relatively small H.T. smoothing capacitors making
smoothing easier. Also should the chopper device go short circuit there is no H.T. output.


In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage
is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5
requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby
switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v
and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing
circuit.

PIN DESCRIPTIONS
Pin 1 This is a 4v reference produced within the I.C.
Pin 2 This pin detects the exact point at which energy stored in the chopper transformer
collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the
chopper transistor. It also opens the switch at pin 4 allowing the external capacitor
C813 to charge from its external feed resistor R810.
Pin 3 H.T. control/feedback via photo coupler D830.
The voltage at this pin controls the on time of the chopper transistor and hence the
output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a
proportion of the +4v reference at pin 1, offset by conduction of the photo coupler
D830 which acts like a variable resistor. An increase in the conduction of transistor
D830 and therefor a reduction of its resistance will cause a corresponding reduction
of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter
on time for the chopper transistor and therefor a lowering of the output voltage and
vice versa, oscillation frequency also varies according to load, the higher the load the
lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip
flop is triggered causing the chopper drive mark space ratio to extend to 244 (off
time) to 1 (on time), the chip is now in over volts trip condition.
Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is
produced by a time constant network R810 and C813. C813 charges when the
chopper is on and is discharged when the chopper is off, by an internal switch
strapping pin 4 to the internal +2v reference, see Fig 2.
The amplitude of the ramp is proportional to chopper drive. In an overload
condition it reaches 4v amplitude at which point chopper drive is reduced to a
mark-space ratio of 13 to 1, the chip is then in over current trip.

The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the
power supply simply squegs quietly. Pin 4 is protected by internal protection
components which limit the maximum voltage at this pin to 6.5v.
Should a fault occur in either of the time constant components, then the chopper
transistor will probably be destroyed.
Pin 5 This pin can be used for remote control on/off switching of the power supply, it is
normally held at about +7v and will cause the chip to enter standby mode if it falls
below 2v.
Pin 6 Ground.
Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to
switch off the chopper.
Pin 8 Chopper base current output drive pin.
Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running,
Current consumption of the I.C. is typically 135mA. The voltage at this pin must
reach 6.7v in order for the chip to start-up.


The Video processing is based on TDA3301 (MOTOROLA)

The IF stage and synchronization are based on TDA4504B (PHILIPS)



Small signal combination for multistandard colour TV
FEATURES
· Gain controlled vision IF amplifier
· Synchronous demodulator for negative and positive
demodulation
· AGC detector operating on peak sync amplitude for
negative demodulation and on peak white level for
positive demodulation
· Tuner AGC
· AFC circuit with two control polarities and on/off-switch
· Video preamplifier
· Video switch to select either the internal video signal or
an external video signal
· Horizontal oscillator and synchronization circuit with two
control loops
· Vertical synchronization (divider system), ramp
generator and driver with automatic amplitude
adjustment for 50 and 60 Hz
· Transmitter identification (mute)
· Sandcastle pulse generation
· VCR/auto VCR switch
· Start-up circuit
· Vertical guard

GENERAL DESCRIPTION

Having the capability to demodulate IF signals with either
positive or negative-going video information, the
TDA4504B (Fig.1) is contained within a 32 pin
encapsulation. It includes a three-stage vision IF amplifier,
mute circuit, AFC and AGC circuitry, fully synchronised
horizontal and vertical timebases with drive circuits and
integral three-level sandcastle pulse generator.
A functional colour tv receiver can thus be realized with the
addition of a tuner, audio demodulator and amplifier,
chroma decoder and respective line and field deflection
circuitry.


FUNCTIONAL DESCRIPTION

Vision IF amplifier, demodulator
and video amplifier
Each of the three AC-coupled IF
stages permit the omission of DC
feedback and possess a control
range in excess of 20 dB.
The IF amplifier, which is completely
symmetrical, is followed by a passive
synchronous demodulator providing a
regenerated carrier signal. This is
limited by a logarithmic limiter circuit
prior to its application to the
demodulator.
A noise clamp circuit is provided at
the video input (pin 16) to limit
interference pulses below the sync tip
level and is more efficient than a
noise inverter in providing improved
picture stability during the presence of
interference.
The video amplifier has good linearity
and bandwidth figures.
AFC-circuit
Obtaining the AFC reference signal
from the demodulator tuned circuit
presents the advantage of utilizing a
single tuned circuit and one
adjustment. However, since the
frequency spectrum of the signal
applied to the demodulator is
determined by the characteristic of
the SAW filter, the resultant
asymmetrical spectrum with respect
to the vision carrier causes the AFC
output voltage to be dependent upon
the video signal. The TDA4504B thus
contains a sample-and-hold circuit.
With negative-going vision signals the
AFC is active only during the sync
pulse period. When positive-going
signals are applied to the device,
however, the AFC is continuously
active but filtered to ensure only a
small by-pass current is present in the
sample-and-hold circuit.
With weak input signals the drive
signal will contain considerable noise
which also possesses an
asymmetrical frequency spectrum
and could create an offset in the AFC
output voltage. The inclusion of a
notch in the demodulator tuned circuit
minimises this effect.
The sample-and-hold circuit is
followed by a high impedance output
amplifier. Thus the AFC control
gradient depends upon the load
impedance.
The AFC polarity switch is combined
with the start circuit (pin 12). It has a
negative slope when pin 12 is open or
connected to the main supply and a
positive slope when pin 12 is
grounded. The AFC is disabled when
the sample connection (pin 22) is
grounded.




The sound part is based on TDA8191.
TDA8191 TV SOUND CHANNEL

DESCRIPTION
The TDA8191 is a monolithic integrated circuit that
includes all the functionsneeded fora completeTV
sound channel.TheTDA8191 is assembled in a 20
pin dual in line power package.

HIGH SENSITIVITY
.EXCELLENTAM REJECTION
.DC VOLUME CONTROL
.PERITELEVISION FACILITY
.4W OUTPUTPOWER
.LOW DISTORTION
.THERMAL PROTECTION
.TURN-ON AND TURN-OFF MUTING








- VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)


TDA3300 3301 TV COLOR PROCESSOR

This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).

Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.

The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.

It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.


90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.

ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.

4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.

Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.

Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.







TV–Controller with Integrated On–Screen Display
Ability
1. Introduction
In comparison to the older TVPO 2065 hardware, the
port 3 of the TVPO 2066 consists of 6 x 12 V/2 mA open–
drain outputs instead of 5 V/25 mA open–drain outputs.
“TVPO 2066” is the name of the unprogrammed hardware.
The programmed versions will be called:
– TVPO 2066–Axx for analog TV–sets
– TVPO 2066–Dxx for digital TV–sets
with the version–no. xx. Application diagrams and descriptions
of different software versions are available in
additional data sheets.
The TVPO 2066 is an intelligent microcomputer in N–
channel MOS technology. On one silicon chip, it contains
all operating and tuning functions of a modern TV
receiver. Thus, along with the non–volatile memory
(MDA 2062, NVM 3060), the SAA 1250, IRT 1250 or IRT
1260 remote–control transmitter and the TBA 2800 preamplifier
this offers a very economic solution for TV receivers
with on–screen display and voltage synthesizer.
The device is available in 44–pin PLCC package and
40–pin DIL package. The PLCC version has 4 pins more
for digital combined inputs/outputs.
2. The Functional Blocks of the TVPO 2066
The hardware components of the TVPO 2066 are:
– 8048–core, fully compatible to 8048 instruction set
– 10K ROM, 256 byte RAM
– four 64 steps analog output to control vol., color etc.
– single 4032 steps analog output for controlling of a
VS–tuner
– IR decoder for ITT–IR (remote control with IRT
1250/60)
– mains flip–flop for standby mode
– IM–bus interface for non–volatile memory and devices
of DIGIT 2000 system for digital video–processing.
– fast counter input (T1) for automatic search (for analog
TV–sets)
– 12 digital combined inputs/outputs (8 or 10 for DIL–
package)
– 8 digital outputs
– integrated 12–digit on–screen display