LOEWE CANTUS 3872ZP (59460U72) CHASSIS 110Q414 V6.XX (LOEWE Q4140) INTERNAL VIEW.

The LOEWE CHASSIS Q4140 is (WAS) the top chassis series for 100HZ Digital Scan Technology.

This is the maximum expression of power in Digital Signal Processing quality.

The chassis is based on a monocarrier combining all functions from power supply to deflections and sound amplification.

Only the little ST-BY Unit is fitted on front.



On right side Line transformer on E/W Correction.

On left side 2 Tuner for Multi PIP / power supply / sound amplifiers

The metal box is containing all DIGITAL CORE.


NOTE This CHASSIS was suffering due to dry joints WITH a dangerous FLAMES/ burning possibilty in the Line deflection section located in the Line transformer / EHT / E-W / HOT PCB zone causing a self destruction and flames of the tellye itself.

If You have one of these you SHOULD do IMMEDIATELY the COMPLETE REWORK of all Solder Joint in the Line deflection Parts to avoid dangerous uncontrolled SELF-BURNS !!!!!!!!!!!!!!!!!!!!



CIRCUITS DESCRIPTIONS:

LOEWE CANTUS 3872ZP (59460U72)  CHASSIS  110Q414  V6.XX  (LOEWE Q4140) Switched-mode power supply control circuit: Siemens Function and Application of the Switch Mode Powersupply IC TDA4605;

 

 A controller for a switch mode power supply includes an undervoltage protection circuit responsive to an input supply voltage indicative signal. The input supply voltage indicative signal is also coupled to a foldback point correction circuit. The correction circuit causes a decrease in a maximum duty cycle of a control signal when the input supply voltage increases and is still smaller than a predetermined magnitude. A zener diode limits the input supply voltage indicative signal in a manner to prevent a further decrease in the duty cycle when the input supply voltage exceeds the predetermined magnitude.

 

 1. A switch mode power supply, comprising: a source of an input supply voltage;
a switch responsive to a first control signal having a controllable duty cycle and coupled to said source of input supply voltage for generating an output supply voltage, in accordance with said duty cycle of said first control signal;
a duty cycle modulator responsive to a second control signal for generating said first control signal and for controlling said duty cycle of said first control signal in accordance therewith, said modulator being responsive to a signal that is indicative of said input supply voltage for decreasing said duty cycle when said input supply voltage increases; and
a limiter coupled to said modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when said input supply voltage exceeds a first magnitude.


2. A power supply according to claim 1, wherein said duty cycle of said first control signal varies within a control range, in accordance with said second control signal, and wherein said limiter limits a decrease of said duty cycle when said duty cycle is at an end of said control range.

3. A power supply according to claim 1, wherein said limiter comprises a clamper coupled in a signal path of said input supply voltage indicative signal for clamping said input voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping thereof, when said input supply voltage does not exceed said first magnitude.

4. A power supply according to claim 3, wherein said voltage clamper comprises a diode.

5. A power supply according to claim 3, further comprising a disabling circuit responsive to said input supply voltage indicative signal for disabling said output supply voltage, when said input supply voltage is smaller than a second magnitude and wherein said voltage clamper is coupled in a common signal path of said input supply voltage indicative signal with respect to each of an input of said disabling circuit and an input of said limiter.

6. A power supply according to claim 1, wherein said modulator comprises a foldback point corrector for decreasing said duty cycle, when said input supply voltage increases and wherein said limiter is coupled to said corrector.

7. A power supply according to claim 1, wherein said second control signal is produced in a feedback path for regulating said output supply voltage.

8. A power supply according to claim 1, wherein said input supply voltage indicative signal is coupled to said modulator from said source of input supply voltage via a signal path that bypasses said switch.

9. A power supply according to claim 8, wherein said limiter comprises a clamp coupled in said signal path for clamping said input supply voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping operation, when said input supply voltage does not exceed said first magnitude.

10. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal for limiting a duty cycle of said switch, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.


11. A power supply according to claim 10 wherein said voltage monitor circuit comprises a clamp coupled in a signal path of said second control signal.

12. A power supply according to claim 11, wherein said second signal is coupled to said modulator from said input supply voltage via a signal path that bypasses said switch.

13. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values, such that as long as said input supply voltage is in said first range of input supply voltage values, said second control signal varies when said input supply voltage varies and said modulator operates in said first mode of operation.


14. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a nonlinear voltage divider circuit coupled to said input supply voltage for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.

Description:

The invention relates to a switch mode power supply control circuit.
Switched-mode power supplies efficiently generate a variety of regulated voltages from a single line voltage level (e.g., 220 volts AC). One important use of these power supplies is within a television signal receiver where they are used to produce a regulated B+ voltage for the horizontal deflection circuit as well as other regulated voltages for powering various digital and analog circuits.
Typically, a switched-mode power supply contains a full-wave rectifier, a power supply controller, a switch, and an output transformer. The switch is typically a high-power transistor such as a MOSFET. To regulate the output voltages, the controller activates and deactivates (e.g., pulse width modulates) the gate of the transistor in response to power supply loading and other control parameters. The switched voltage from the transistor drives a primary winding of the transformer, while various power supply loads are connected to one or more secondary windings. As such, the power supply converts an AC input voltage into one or more DC voltages.
One particular controller is an integrated circuit available from Siemens as Model TDA 4605. This power supply controller is typically used to drive the MOSFET transistor, which in turn drives the primary coil of the transformer. This specific integrated circuit, as well as others used in the art, typically contain a control mechanism that disables the power supply when the input voltage drops below a pre-defined voltage level. Such protection is necessary because, to produce regulated output voltages, the switched-mode power supply increases the duty cycle of the control signal driving the transistor as the input voltage decreases. At some point, the input voltage decreases to a level where the output of the power supply is unregulated (e.g., the maximum pulse length is used to drive the transistor). Such unregulated operation can damage the power supply electronics, but is more likely to damage the load electronics.

For the integrated circuit (IC) TDA4605, as defined in the TDA4605 Technical Manual available from Siemens AG, dated Jul. 27, 1989, pin 3 of the integrated circuit is used for sensing or monitoring the primary input voltage (vp) for the power supply (e.g., the rectified AC voltage). The threshold voltage for disabling or deactivating the integrated circuit, and thus the power supply, is pre-established by the controller at one volt. As such, the primary input voltage (vp) is reduced using a voltage divider at the input of pin 3. By selecting appropriate resistor values within the voltage divider, a nominal value of monitoring voltage is applied to pin 3. Typically, this voltage is approximately 2.0 volts for a primary input voltage of 120 volts. When the primary input voltage falls to a level that causes the monitoring voltage at pin 3 to fall below one volt, the power supply is deactivated to avoid unregulated operation.
As stated above, this form of switched-mode power supply has been finding use within television signal receivers. However, television receivers, in particular, present peculiar loading characteristics to a power supply. Specifically, a television receiver power supply is called upon to produce a regulated B+ voltage, typically of approximately 140 volts, as well as a low voltage DC level of 16 volts for powering all of the digital and analog circuitry within the receiver. When the television receiver is switched from stand-by to run mode, a heavy load is produced by the in-rush of current into filter capacitors connected to the regulated B+ voltage. This heavy load causes the power supply to temporarily operate in an unregulated (maximum pulse width) mode, and may cause the primary input voltage to drop to a low level. Furthermore, when the degaussing circuit is activated to degauss the cathode ray tube (CRT), the main AC supply voltage is depressed due to the substantial load presented by the degaussing circuit. Consequently, the drop in line voltage could typically cause the monitoring voltage to drop below the 1 volt, first threshold level, and as such, to disable the power supply.
Therefore, there it is desirable to produce a monitoring voltage indicative of the primary input voltage, but to insure that the power supply will not be deactivated for the expected heavy loads found in a television receiver.

The IC TDA 4605 includes a foldback point correction circuit that reduces the maximum duty cycle of the MOSFET control signal, when the monitoring voltage exceeds a second threshold level of approximately 1.7 V. The monitoring voltage is applied to the correction circuit also via pin 3.
In a circuit embodying an inventive feature, a resistive voltage divider that produces the monitoring input or sense signal from the primary input voltage is designed such that the first threshold level is not attained during the expected temporary loading of the primary input voltage. However, such a voltage divider results in a higher voltage being applied to the monitoring voltage input of the controller during normal operation of the power supply. As such, an increase of the primary input voltage to a higher level, which is still within the acceptable tolerance range of the AC line voltage, can cause the monitoring voltage to rise to a level that exceeds the second threshold level at which the integrated circuit begins to limit the maximum duty cycle of the control signal that controls the MOSFET, i.e., the controller applies a foldback correction technique. When the second threshold level is exceeded, the power supply automatically limits the output power of the power supply for an increase in the primary voltage. As a result of the voltage divider design that provides sufficient headroom to overcome loading generated drop outs in the primary input voltage, the maximum power supply output could be, undesirably, significantly reduced at high primary input voltage.
In carrying out an inventive feature, to insure that such inconsequential increase in the primary input voltage does not cause the power supply to significantly reduce the maximum duty cycle of the control signal and thereby, the power output of the power supply, a zener diode is coupled to the voltage divider. The zener diode limits the magnitude of the monitoring voltage to a level that avoids further maximum duty cycle limiting when the primary input voltage further increases. Consequently, when the power supply is used in a television signal receiver, the voltage divider provides enough head room for the primary voltage to drop substantially due to degaussing circuit activation or other loading conditions, while the zener diode insures that the primary voltage can rise above its nominal voltage without causing a significant power limitation of the power supply output.
A switch mode power supply, embodying an aspect of the invention, includes a source of an input supply voltage. A switch is responsive to a first control signal having a controllable duty cycle and coupled to the source of input supply voltage for generating an output supply voltage, in accordance with the duty cycle of the first control signal. A duty cycle modulator is responsive to a second control signal for generating the first control signal and for controlling the duty cycle of the first control signal in accordance therewith in a manner to control the current pulses. An increase in the duty cycle produces an increase in a magnitude of the current pulses. The modulator is responsive to a signal that is indicative of the input supply voltage for decreasing the duty cycle when the input supply voltage increases. A limiter is coupled to the modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when the input supply voltage exceeds a first magnitude.

FIG. 1 depicts a schematic diagram of a switched-mode power supply incorporating the teachings of the present invention.

FIG. 1 depicts a schematic diagram of a switched-mode power supply 100 incorporating the present invention. The embodiment shown is designed for use as a power supply for a television signal receiver, wherein the power supply generates a regulated B+ voltage (e.g., 140 volts) and a low voltage (e.g., 16 volts). The regulated B+ voltage is used to power a horizontal deflection circuit and the regulated low voltage is used to power the digital and analog electronics (continuous load 118). Other applications for the power supply may require slight variation in the depicted components and their interconnections; however, such variations are well within the scope of the present invention.
The power supply contains a number of major components, including a full-wave rectifier 102, the power supply controller 106, a MOSFET transistor Q1, a monitor voltage generator 110, an output transformer 112, and a plurality of circuit components used to complete the power supply electronics. Illustratively, the input to the power supply is a 110-volt AC, 60 hertz voltage.
Rectifier 102 is a conventional full-wave bridge rectifier coupled to an AC input voltage source 101. The output of the bridge rectifier 102 is coupled to capacitor C1 approximately 680 μF). A voltage RAW B+ forms raw (unregulated) B+ voltage (also referred to herein as the primary input voltage vp) having a nominal value of approximately 150 volts. Capacitor C1, connected from the output of the rectifier to ground, smoothes the voltage from the bridge rectifier such that a DC voltage, i.e., the primary input voltage vp, is available at the upper terminal of the transformer's primary winding W₁.
The primary input voltage forms an input to the monitor voltage generator 110 which produces a monitor voltage VZ1 for the controller 106. The monitor voltage generator is discussed in detail below.
The controller is illustratively a TDA 4605 power supply controller available from Siemens AG of Munich, Germany. The eight pins of the controller are connected to signals and voltages that enable the controller to produce a pulse width or duty cycle modulated signal at pin five for controlling the duty cycle of the transistor Q1. Specifically, pin 4 of controller 106 is grounded. Pin 3 is coupled to the monitor voltage.
Pin 2 is supplied information concerning the primary current. A primary current increase in the primary winding W₁ is simulated as a voltage rise of a periodical, ramp voltage VC2 at pin 2 using an external RC element formed by resistor R3, capacitor C2, and resistor R4 (where R3 is approximately 360 kΩ, C2 is approximately 6,800 pF; and R4 is approximately 220 Ω). These elements are connected in series from the primary input voltage to ground. Pin 2 of the controller 106 is coupled to the junction of R3 and C2. A pulse width modulator 106c of the controller 106 controls the duration of the forward phase, and thus, the primary peak current, using ramp voltage VC2 that is proportional to the drain current of the transistor Q1. As indicated before, the ramp voltage is derived from the primary input voltage using the RC elements connected to pin 2, i.e., the ramp voltage simulates the primary current. Controller pin 1 is supplied secondary voltage information which internally compares the control voltage sampled from the regulating winding W3 of the transformer 112 and compares that sample voltage with an internal reference voltage.
Pin 5 generates a duty cycle modulated control signal or voltage VOUT via a push-pull output driver for rapid charge and discharge of the input capacitance of a MOSFET power transistor Q1 (Model IRF740).
Pin 6 is coupled to the supply voltage for the controller. Pin 7 forms a soft start input terminal. Capacitor C5 (0.1 μF) is connected from pin 7 to ground to reduce the pulse duration during start-up. Lastly, pin 8 is the input pin for the oscillator feedback.
In operation, the transistor Q1 is used as a power switch controlled by the controller 106. A snubber circuit is connected to the drain of the transistor Q1. The snubber circuit contains a combination of diode D3, resistor R16 and capacitor C12, which together limit the voltage overshoot when the transistor is turned off. D3 is a MUR450 diode, C12 is a 1000 pF capacitor, and R16 is a 2-watt, 30 kΩ resistor.
Together with the stray capacitance of the transformer, capacitor C7 (470 pF connected from drain terminal to ground) determines the no-load frequency, and consequently, the maximum slew rate of the drain voltage for a transistor Q1.
Transistor Q1 is driven with pulse width modulated signal VOUT produced at pin 5 of controller 106 and coupled to the gate terminal of the transistor via resistor R11 (35 Ω). Furthermore, a capacitor C6 (4700 pF) is coupled from the source terminal to the drain terminal. The source terminal is coupled to ground through resistor R13 (0.27 KΩ). Resistor R12 (10 kΩ) is optionally connected between the source terminal and gate terminal to ensure that the transistor will not be activated if power is applied to the power supply without the controller 106 being installed. The drain terminal is coupled to one terminal of the primary winding W1 of transformer 112. Consequently, the transistor Q1 controls the current flow from the primary input voltage through the primary winding.
The secondary circuit of the transformer 112 consists of several windings, each of which has a different number of turns, polarity, and load capacity. Specifically, winding W2 forms the output voltage for the regulated B+, while winding W4 forms the output winding for the regulated 16-volt low voltage output, and winding W3 generates the feedback voltage for the controller 106.
The load circuitry includes, connected to winding W2, an output diode D4 and capacitor C13 that couple power to the horizontal deflection circuit 116. Additionally, the center tap of the output secondary winding is connected to ground, and winding W4 is coupled to diode D5 and capacitor C14. This output is the 16 volts that powers the continuous load 118 of the television receiver, e.g., all of the electronics and integrated circuits. This circuit 118 also controls the timing of when the degaussing circuit 114 is activated using degaussing control line 120. The control line for the continuous load is the run/standby control signal that essentially turns the television receiver on and off. The continuous load circuitry 118 is also coupled to the horizontal deflection circuit 116 to provide control signals therefor.
The controller 106 is started up using resistor R17 (100 KΩ) as a start resistor. As such, capacitor C11 (100 μF) is charged with half-wave currents at the voltage supply pin of the controller 106, e.g., pin 6. These half-wave currents are supplied from the primary input voltage through resistor R17 (100 KΩ) to ground through series connected resistor R14 (202 Ω), diode D2 (148 Ω) and regulating winding W3. When the voltage at C11 reaches the switch-on threshold, the switched-mode power supply begins to function and supplies the feedback voltage, via winding W3, resistor R14 and diode D2. This feedback voltage, when rectified by diode D2 and smoothed by capacitor C11, forms the supply voltage (v_cc) for the controller 106 via pin 6.
A control signal or voltage VCT for pin 1 is generated in a circuit parallel to the controller supply voltage circuit. The control voltage is produced by diode D1 (ERB43) charging capacitor C3 (1.5 μF) through resistor R8 (10 Ω). The RC element, consisting of series connected R15 (30 Ω) and C10 (0.01 μF), prevents peak value rectification of high frequency components of the feedback signal.
More specifically, regulating winding W3 is coupled to one terminal of resistor R15. The other terminal of resistor R15 is coupled to capacitor C10 to ground. Diode D1 is connected at the junction of resistor R15 and capacitor C10. Capacitor C9 (1000 pF) is connected in parallel with diode D1. Diode D1 has an output voltage that is coupled to series connected R8 and C3 which couples the output of the diode to ground. The output of the diode is also coupled through resistive divider network R6 and R7 which are respectively connected in series to ground. The voltage at the junction of R6 and R7 forms control voltage VCT and is coupled to pin 1 of the controller 106. These resistors define the no-load frequency of oscillation of the controller 106. Therefore, they are typically 0.1% accurate resistors having R6 being 5.49 KΩ, and R7 being 174 Ω. Control voltage VCT is coupled to a pulse-width modulator 106c within controller 106 that controls the duty cycle modulation of voltage VOUT for regulating, for example, voltage REGB+.
During the power supply start-up, capacitor C5 at the soft-start pin (e.g., pin 7), influences the duration of the forward phase by controlling the error voltage of the pulse width modulator. The controller detects the end of the transformer discharge phase via resistor R10 (20 KΩ) that is coupled at one end to controller pin 8 and at the other end to resistor R14, and ultimately to the regulating winding W3. Additionally, capacitor C8 (0.022 μF) is coupled from the junction of R10 and R14 to ground. At this point, the voltage changes polarity from positive to negative, i.e., the voltage represents zero crossings.
A voltage VZ1, embodying an inventive feature, is generated by the monitor voltage generator 110 and is coupled to pin 3 of the controller 106. Voltage VZ1 is used both for determining the minimum line voltage that will allow the power supply to operate and for controlling a foldback point correction circuit 106b within the controller 106.
The monitor voltage generator 110 contains resistor R1 (270 kΩ) coupled in series with resistor R2 (5100 Ω) to form a resistive voltage divider network with respect to primary input voltage RAW B+. The junction of the two resistors is coupled to the pin 3 of controller 106. Furthermore, a zener diode Z1 (B2X55/C3VO), embodying an inventive feature, is connected in parallel with resistor R2 from the junction point to ground. Zener diode Z1 forms a limiter for limiting the maximum voltage across R2 to the breakdown voltage of the zener diode Z1. Consequently, the voltage at the output of the monitor voltage generator 110 tracks the primary input voltage RAW B+ up to the threshold point where the zener diode Z1 begins to conduct.
The controller 106 includes an under-voltage detector 106a that uses a fixed, internal voltage threshold that causes the controller to disable the power supply whenever the monitor voltage VZ1 drops below a first threshold voltage. For the TDA 4605 integrated circuit, this first threshold voltage is one volt. As such, the divider network of R1 and R2 defines a voltage at the output that under typical operation would not cause the controller to deactivate the power supply.
In one particular application, e.g., a television signal receiver, a degaussing circuit 114 for a television signal receiver is typically connected directly across the input AC power. Consequently, when the degaussing circuit is activated, it will typically cause a drop in the AC voltage that is applied to the input of the voltage rectifier 102. Consequently, the primary input voltage RAW B+ will drop significantly during the degaussing period. Since this is a normal behavior of a conventional television receiver circuit, it is desirable that the monitor voltage generator 110 be designed such that the controller 106 will not deactivate the power supply during the degaussing period.
For a primary input voltage of 120 volts and using a resistive divider of 270 KΩ for R1 and 5100 Ω for R2, the nominal voltage VZ1 at the voltage monitor input pin is 2 volts. Such a value for the voltage monitor voltage will avoid power supply deactivation during the degaussing period or other heavy load period.
When the duty cycle of voltage VOUT is at the maximum as a result of an overload condition, an increase in voltage RAW B+, produced by an increase in the AC line voltage, causes the voltage across primary winding w₁ to increase. As the primary input voltage RAW B+ rises, the available input power to the power supply increases which could damage the power supply when the power supply is overloaded. During a period of overloaded, unregulated output, the modulator 106c generates the voltage VOUT having a maximum duty cycle for driving transistor Q1. As a result, a primary current IP in winding W₁ of transformer 112 has also a maximum duty cycle. Therefore, undesirably an increase in voltage RAW B+ can produce a large voltage across the transistor that could damage the transistor or other circuitry.
To maintain the power supply within a safe operation range, the controller 106 includes what is known as a foldback or overload point correction circuit 106b. This foldback point correction circuit reduces the maximum duty cycle of voltage VOUT when the primary input voltage exceeds a predetermined magnitude. An increase above the predetermined magnitude causes the foldback point correction circuit 106b to decrease the maximum duty cycle of signal VOUT as voltage RAW B+ increases. The decrease is done by generating a correction current ICOR that is coupled to capacitor C2 causing an increase in the rate of change of voltage VC2 at pin 2 of controller 106 when voltage VZ1 exceeds a second threshold voltage.
When voltage RAW B+ increases and causes voltage VZ1 to further increase above the second threshold voltage an increase in current ICOR produces a decrease in the maximum duty cycle of signal VOUT, in a well know manner. The second threshold voltage occurs when voltage VZ1 is above a voltage level of approximately 1.7 V. The result is that, when voltage RAW B+ further increases the maximum duty cycle decreases proportionally. The decrease in the maximum duty cycle tends to stabilize the maximum power produced in the power supply against an increase of voltage RAW B+. On the other hand, an increase of voltage VZ1 when voltage VZ1 is below the 1.7 V level, does not affect current ICOR and the duty cycle of voltage VOUT.
Because the divider network (R1 and R2) establishes a sufficiently large monitor voltage VZ1 that provides sufficient headroom for preventing power supply shutdown when the degaussing circuit is activated, primary input voltage RAW B+ may be at a level that causes voltage VZ1 to exceed the second threshold voltage of circuit 106b by an excessive amount even when voltage RAW B+ is within the normal tolerance range. Therefore, disadvantageously, the maximum duty cycle may further decrease by a significant amount in a manner to lower the maximum power that can be derived. Such significant reduction in power capability can occur even though primary input voltage is not truly at such a high level that could damage the power supply.
In accordance with an inventive feature, to prevent current ICOR from further reducing the maximum duty cycle of voltage VOUT when voltage RAW B+ increases above a threshold magnitude that corresponds to voltage VZ1 being equal to 3 V, the monitor voltage generator 110 contains the zener diode Z1 operating as a limiter which limits the primary input voltage indicative voltage VZ1 to 3 V. Consequently, the monitor voltage VZ1 can never rise above a pre-defined level (e.g., 3 volts) that would otherwise cause the foldback point correction circuit 106b within the controller 106 to further decrease the maximum duty cycle. In this way, advantageously, the decrease in the maximum duty cycle as a function of an increase in voltage RAW B+ is limited.
The decrease in the duty cycle of voltage VOUT produced by current ICOR, for a given increase in voltage RAW B+, is limited when voltage RAW B+ is greater than a threshold magnitude that corresponds to voltage VZ1 equal to 3 V. In contrast, the decrease in the duty cycle produced by current ICOR is not limited but varies proportionally to voltage RAW B+ when voltage VZ1 is between 1.7 V and 3 V. Thus, zener diode Z1 operates as a limiter for limiting the decrease in the duty cycle when the voltage RAW B+ exceeds the threshold magnitude relative to when voltage RAW B+ does not exceed the threshold magnitude. An increase in voltage RAW B+ that produces voltage VZ1 below the second threshold voltage of 1.7 V, does not affect current ICOR.
Specifically, for the TDA 4605 integrated circuit control, the zener diode has a value of three volts. Consequently, the input signal to the monitor voltage generator cannot rise above the three volt level before the zener diode will begin to conduct current to ground. As such, the monitor voltage generator establishes a range of voltages that pre-defines a range of primary input voltages at which the controller 106 operates in a normal manner that avoids both an undervoltage power supply deactivation and a further decrease in the maximum duty cycle. The input voltage dynamic range is thereby extended.

siemens TDA4605-3Control IC for Switched-Mode Power Supplies using MOS-Transistor


The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and
protection functions in free running flyback converters. Because of the fact that a wide load range
is achieved, this IC is applicable for consumer as well as industrial power supplies.
The serial circuit and primary winding of the flyback transformer are connected in series to the input
voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the
switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time
of the power transistor, the IC controls each portion of energy transferred to the secondary side
such that the output voltage remains nearly independent of load variations. The required control
information is taken from the input voltage during the switch-on period and from a regulation winding
during the switch-off period. A new cycle will start if the transformer has transferred the stored
energy completely into the load.

Features
- Fold-back characteristics provides overload protection for
external components
- Burst operation under secondary short-circuit condition
implemented
- Protection against open or a short of the control loop Switch-off if line voltage is too low (undervoltage switch-off)
- Line voltage depending compensation of fold-back point
- Soft-start for quiet start-up without noise generated by the
transformer
- Chip-over temperature protection implemented (thermal
shutdown)
- On-chip ringing suppression circuit against parasitic
oscillations of the transformer
- AGC-voltage reduction at low load.

In the different load ranges the switched-mode power supply (SMPS) behaves as follows:
No load operation
The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be
a little bit higher or lower than the nominal value depending of the design of the transformer and the
resistors of the control voltage divider.
Nominal operation
The switching frequency is reduced with increasing load and decreasing AC-voltage.
The output voltage is only dependent on the load.
Overload point
Maximal output power is available at this point of the output characteristic.
Overload
The energy transferred per operation cycle is limited at the top. Therefore the output voltages
declines by secondary overloading.

Application Circuit
The application circuit shows a flyback converter for video recorders with an output power rating of
70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V.
The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits
the rush-in current.
In the period before the switch-on threshold is reached the IC is suppled via resistor R 1 ; during the
start-up phase it uses the energy stored in C2 , under steady state conditions the IC receives its
supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel connected capacitor C3 and the inductance of primary winding n 2 determine the
system resonance frequency. The R 2-C4-D2 circuitry limits overshoot peaks, and R 3 protects the
gate of T1 against static charges.
During the conductive phase of the power transistor T1 the current rise in the primary winding
depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used
to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage
is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that
driving the transistor core into saturation is avoided.
The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the
switching power supply shall stop operation because of the low mains voltage. The control voltage
present at pin 3 also determines the correction current for the fold-back point. This current added to
the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turnon
phase of T1. This is done to stabilize the fold-back point even under higher mains voltages.
Regulation of the switched-mode power supplies via pin 1. The control voltage of winding n1 during
the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by
R 5 , R 6 and R 7 . The R 8-C7 network suppresses parasitic overshoots (transformer oscillation). The
peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage
applied across the control winding, and hence the output voltages, are at the desired level.
When the transformer has supplied its energy to the load, the control voltage passes through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are
also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore
the IC ignores zero crossings occurring within a specified period of time after T1 turn-off.
The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to
keep the operating frequency outside the audible range during start-up.
On the secondary side, five output voltages are produced across winding n3 to n7 rectified by D4 to
D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which
are designed to supply only small loads.

Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR
in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If
the control voltage is rather small at pin 1 an additional current is added by means of current source
which is controlled according the level at pin 7. This additional current is virtually reducing the
control voltage present at pin 1.
Pin 2
A voltage proportional to the drain current of the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output of this
transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage
V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator
and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage
are the output for the start impulse generator with the stable reference potential VST and the
supply voltage motor.
Pin 3
The down divided primary voltage applied there stabilizes the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary
voltage monitor block.
Pin 4
Ground
Pin 5
In the output stage the output signals produced by the logic are shifted to a level suitable for MOSpower
transistors.
Pin 6
From the supply voltage V6 are derived a stable internal references VREF and the switching
threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All references values (VR ,
V2B , VST) are derived from VREF . If V6 > VVE , the VREF is switched on and switched off when V6 <
V 6A . In addition, the logic is released only for V6 min < V6 < V6 max .
Pin 7
The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is
connected to ground by a capacitor.


Pin 8
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 88 is represented an sheet 90 for a line
voltage barely above the lower acceptable limit time t0 the following voltages built up:
– V6 corresponding to the half-wave charge current over R1
– V2 to V2 max (typically 6.6 V)
– V3 to the value determined by the divider R 10/R 11 .
The current drawn by the IC in this case is less than 1.6 mA.
If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The
current draw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2B
and the starting impulse generator generates the starting impulses from time point t5 to t6 . The
feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
controlled in width by regulating voltage of pin 1. When switching on this corresponds to a shortcircuit
event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting
attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases
to V6 . The IC switches off; V6 can rise again (time point t4) and a new start-up attempt begins at
time point t1 . If the rectified alternating Iine voltage (primary voltage) collapses during load, V3 can
fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The
primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new startup
attempt begins at time point t1 .

Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is
400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak
voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the
overload amplifier begins to regulate the pulse width downward. This point is referred to as the
overload point of the power supply. As the IC-supply voltage V6 is directly proportional to the
secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls
below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave
charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up
without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If
the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency
increases up to the resonance frequency of the system. If the load is further reduced, the secondary
voltages and V6 increase. When V6 = V6 max the logic is blocked. The IC converts to burst
operation.This renders the circuit absolutely safe under no-load conditions.
Behaviour when Temperature Exceeds Limit
An integrated temperature protection disables the logic when the chip temperature becomes too
high. The IC automatically interrogates the temperature and starts as soon as the temperature
decreases to permissible values.

Pin Definitions and Functions
Pin No. Function
1 Information Input Concerning Secondary Voltage. By comparing the
regulating voltage - obtained trom the regulating winding of the transformer - with
the internal reference voltage, the output impulse width on pin 5 is adjusted to the
load of the secondary side (normal, overload, short-circuit, no load).
2 Information Input Regarding the Primary Current. The primary current rise in
the primary winding is simulated at pin 2 as a voltage rise by means of external
RC-element. When a voltage level is reached thats derived from the regulating
voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves
to set the maximum power at the overload point set.
3 Input for Primary Voltage Monitoring: In the normal operation V3 is moving
between the thresholds V3H and V3L (V3H > V3 > V3L).
V3 < V3L: SMPS is switched OFF (line voltage too low).
V3 > V3H : Compensation of the overload point regulation (controlled by pin 2)
starts at V3H : V3L = 1.7.
4 Ground
5 Output: Push-pull output provides ± 1 A for rapid charge and discharge of the
gate capacitance of the power MOS-transistor.
6 Supply Voltage Input: A stable internal reference voltage VREF is derived from
the supply voltage also the switching thresholds V6A , V6E , V6 max and V6 min for
the supply voltage detector. If V6 > V6E then VREF is switched on and swiched off
when V6 < V6A . In addition the logic is only enable for V6 min < V6 < V6 max.
7 Input for Soft-Start. Start-up will begin with short pulses by connecting a
capacitor from pin 7 to ground.
8 Input for the Oscillation Feedback. After starting oscillation, every zero
transition of the feedback voltage (falling edge) through zero (falling edge)
triggers an output pulse at pin 5. The trigger threshold is at + 50 mV typical.



TDA8177 VERTICAL DEFLECTION BOOSTER


-DESCRIPTION
Designed for monitors and high performance TVs,
the TDA8177 vertical deflection booster delivers
flyback voltages up to 70V.
The TDA8177 operates with supplies up to 35V and
provides up to 3APP output current to drive the yoke.
The TDA8177 is offered in HEPTAWATT package.

.POWER AMPLIFIER
.FLYBACK GENERATOR
.THERMAL PROTECTION
.OUTPUT CURRENT UP TO 3.0APP
.FLYBACK VOLTAGE UP TO 70V (on Pin 5)
.SUITABLE FOR DC COUPLING APPLICATION



TDA7296 70V - 60W DMOS AUDIO AMPLIFIER WITH MUTE/ST-BY

- DESCRIPTION
The TDA7296 is a monolithic integrated circuit in
Multiwatt15 package, intended for use as audio
class AB amplifier in Hi-Fi field applications
(Home Stereo, self powered loudspeakers, Topclass
TV). Thanks to the wide voltage range and
to the high out current capability it is able to supply
the highest power into both 4W and 8W loads
even in presence of poor supply regulation, with
high Supply Voltage Rejection.
The built in muting function with turn on delay
simplifies the remote operation avoiding switching
on-off noises.

VERY HIGH OPERATING VOLTAGE RANGE
(±35V)
DMOS POWER STAGE
HIGH OUTPUT POWER (UP TO 60W MUSIC
POWER)
MUTING/STAND-BY FUNCTIONS
NO SWITCH ON/OFF NOISE
NO BOUCHEROT CELLS
VERYLOW DISTORTION
VERYLOW NOISE
SHORT CIRCUIT PROTECTION
THERMAL SHUTDOWN

INTRODUCTION
In consumer electronics, an increasing demand
has arisen for very high power monolithic audio
amplifiers able to match, with a low cost the performance
obtained from the best discrete designs.
The task of realizing this linear integrated circuit
in conventional bipolar technology is made extremely
difficult by the occurence of 2nd breakdown
phenomenon. It limits the safe operating
area (SOA) of the power devices, and as a consequence,
the maximum attainable output power,
especially in presence of highly reactive loads.
Moreover, full exploitation of the SOA translates
into a substantial increase in circuit and layout
complexity due to the need for sophisticated protection
circuits.
To overcome these substantial drawbacks, the
use of power MOS devices, which are immune
from secondary breakdown is highly desirable.
The device described has therefore been developed
in a mixed bipolar-MOS high voltage technology
called BCD 80.
1) Output Stage
The main design task one is confronted with while
developing an integrated circuit as a power operational
amplifier, independently of the technology
used, is that of realising the output stage.
The solution shown as a principle schematic by
Fig 15 represents the DMOS unity-gain output
buffer of the TDA7296.
This large-signal, high-power buffer must be capable
of handling extremely high current and voltage
levels while maintaining acceptably low harmonic
distortion and good behaviour over frequency
response; moreover, an accurate control
of quiescent current is required.
A local linearizing feedback, provided by differential
amplifier A, is used to fullfil the above requirements,
allowing a simple and effective quiescent
current setting.
Proper biasing of the power output transistors
alone is however not enough to guarantee the absence
of crossover distortion.
While a linearization of the DC transfer characteristic
of the stage is obtained, the dynamic behaviour
of the system must be taken into account.
A significant aid in keeping the distortion contributed
by the final stage as low as possible is provided
by the compensation scheme, which exploits
the direct connection of the Miller capacitor
at the amplifier’s output to introduce a local AC
feedback path enclosing the output stage itself.
2) Protections
In designing a power IC, particular attention must
be reserved to the circuits devoted to protection
of the device from short circuit or overload conditions.
Due to the absence of the 2nd breakdown phenomenon,
the SOA of the power DMOS transistors
is delimited only by a maximum dissipation
curve dependent on the duration of the applied
stimulus.
In order to fully exploit the capabilities of the
power transistors, the protection scheme implemented
in this device combines a conventional
SOA protection circuit with a novel local temperature
sensing technique which ” dynamically” controls
the maximum dissipation.

3) Other Features
The device is provided with both stand-by and
mute functions, independently driven by two
CMOS logic compatible input pins.
The circuits dedicated to the switching on and off
of the amplifier have been carefully optimized to
avoid any kind of uncontrolled audible transient at
the output.
The sequence that we recommend during the
ON/OFF transients is shown by Figure 16.
The application of figure 17 shows the possibility
of using only one command for both st-by and
mute functions. On both the pins, the maximum
applicable range corresponds to the operating
supply voltage.

BRIDGE APPLICATION
Another application suggestion is the BRIDGE
configuration, where two TDA7296 are used, as
shown by the schematic diagram of figure 25.
In this application, the value of the load must not
be lower than 8 Ohm for dissipation and current
capability reasons.
A suitable field of application includes HI-FI/TV
subwoofers realizations.
The main advantagesoffered by this solution are:
- High power performances with limited supply
voltage level.
- Considerably high output power even with high
load values (i.e. 16 Ohm).
The characteristics shown by figures 20 and 21,
measured with loads respectively 8 Ohm and 16
Ohm.
With Rl= 8 Ohm, Vs = ±18V the maximum output
power obtainable is 60W, while with Rl=16 Ohm,
Vs = ±24V the maximum Pout is 60W.