LOEWE CANTUS 3872ZP (59460U72) CHASSIS 110Q414 V6.XX (LOEWE Q4140) DIGITAL SIGNAL PROCESSING BOARD OVERVIEW.

The DIGITAL BOARD in LOEWE CHASSIS Q4140 is the most advanced type in that kind of application.

The speed of computing in this system is near 1GBit (ONE GIGABIT) which is sligtly better than your ADSL for sure and even some LAN !! !! !!

Mainly based around ITT DIGIVISION DIGIT3000 COMBINED WITH THE SIEMENS MEGAVISION CHIPSET.

The signal is completely high speed computed in the digital domain in stages featuring improvements stage by stage adding further features and quality to reach the maximum performance and perfection dynamic UNTIL "going to the CRT".

All functions are performed and controlled by a sophisticated Controller with dedicated Firmware ,for high graphics menu and controls.


To learn more see below the circuits descriptions:


VPC3210A Comb Filter Video Processor

1. Introduction
On a single chip, the VPC 32xx contains a high-quality
video front-end which is targeted for 4:3 and 16:9, 50/60
and 100/120 Hz TV sets. It can be combined with other
members of the DIGIT3000 IC family (such as CIP
3250A, DDP 3300A, TPU 3040) and/or it can be used
with 3rd-party products.
The main features of the VPC 32xx are
– all-digital video processing
– adaptive 2H comb filter Y/C separator (VPC 32x0)
– multi-standard color decoder PAL/NTSC/SECAM including
all substandards
– 3 composite, 1 S-VHS input, 1 composite output
– integrated high-quality A/D converters
– sync processing
– horizontal scaling (0.25...4)
– panorama vision
– PAL+ preprocessing (VPC 321x)
– various digital interfaces
– line-locked clock/data output
– embedded RISC controller (80 MIPS)
– display/deflection control (VPC320x)
– one crystal, few external components
– 0.8 m CMOS technology
– 68-pin PLCC package
1.1. System Architecture
Fig. 1–1 shows the block diagram of the video processor.
1.2. Video Processor Family
The VPC32xx is available with and without 2H comb filter
and also for 50/100 Hz systems. The 50 Hz version
provides controlling for the display and the vertical/east
west deflection of DDP 3300A. The 100 Hz version has
a line-locked clock output interface and the PAL+ preprocessing
option. Table 1–1 gives an overview over the
VPC video processor family.


VPC Applications
Fig. 1–2 depicts several VPC applications. Since the
VPC functions as a video front-end, it must be complemented
with additional functionality to form a complete TV
set.
The DDP 3300/3310 contains the video back-end with
video postprocessing (contrast, peaking, DTI,...), H/Vdeflection,
RGB insertion (SCART, Text, PIP,...) and tube
control (cutoff, white drive, beam current limiter). It generates
a beam scan velocity modulation output from the
digital YCrCb and RGB signals. Note that this signal is
not generated from the external analog RGB inputs.
The CIP 3250A provides a high quality analog RGB interface
with character insertion capability. This allows
appropriate processing of external sources, such as
MPEG2 set-top boxes in transparent (4:2:2) quality. Furthermore,
it translates RGB/Fastblank signals to the
common digital video bus and makes those signals
available for 100 Hz processing. In some European
countries (Italy), this feature is mandatory.
The IP indicates memory based image processing, such
as scan rate conversion, vertical processing (Zoom), or
PAL+ reconstruction.
Examples:
– Europe: 15 kHz/50 Hz " 32 kHz/100 Hz interlaced
– US: 15 kHz/60 Hz " 31 kHz/60 Hz non-interlaced
Note that the VPC supports memory based applications
through line locked clocks, syncs, and data. CIP may run
either with the native DIGIT3000 clock but also with a
line-locked clock system.

2. Functional Description
2.1. Analog Front-End
This block provides the analog interfaces to all video inputs
and mainly carries out analog-to digital conversion
for the following digital video processing. A block diagram
is given in Fig. 2–1.
Most of the functional blocks in the front-end are digitally
controlled (clamping, AGC, and clock-DCO). The control
loops are closed by the Fast Processor (‘FP’) embedded
in the decoder.
2.1.1. Input Selector
Up to four analog inputs can be connected. Three inputs
are for input of composite video or S-VHS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S-VHS carrier-chrominance signal.
This input is internally biased and has a fixed gain amplifier.
2.1.2. Clamping
The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling capacitors
and is generated by digitally controlled current
sources. The clamping level is the back porch of the video
signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.
2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in 64
logarithmic steps to the optimal range of the ADC. The
gain of the video input stage including the ADC is 213
steps/V with the AGC set to 0 dB.
2.1.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit resolution.
An integrated bandgap circuit generates the required
reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
2.1.5. ADC Range
The ADC input range for the various input signals and
the digital representation is given in Table 2–1 and Fig.
2–2. The corresponding output signal levels of the VPC
32xx are also shown.
2.1.6. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within ±150 ppm.
2.1.7. Analog Video Output
The input signal of the Luma ADC is available at the analog
video output pin. The signal at this pin must be buffered
by a source follower. The output voltage is 2 V, thus
the signal can be used to drive a 75 W line. The magnitude
is adjusted with an AGC in 8 steps together with the
main AGC.

2.2. Adaptive Comb Filter
The adaptive comb filter is used for high-quality luminance/
chrominance separation for PAL or NTSC signals.
The comb filter improves the luminance resolution
(bandwidth) and reduces interferences like cross-luminance
and cross-color artifacts. The adaptive algorithm
can eliminate most of the mentioned errors without
introducing new artifacts or noise.
A block diagram of the comb filter is shown in Fig. 2–3.
The filter uses two line delays to process the information
of three adjacent video lines. To have a fixed phase relationship
of the color subcarrier in the three channels, the
system clock (20.25 MHz) is fractionally locked to the
color subcarrier. This allows the processing of all color
standards and substandards using a single crystal frequency.
The CVBS signal in the three channels is filtered at the
subcarrier frequency by a set of bandpass/notch filters.
The output of the three channels is used by the adaption
logic to select the weighting that is used to reconstruct
the luminance/chrominance signal from the 4 bandpass/
notch filter signals. By using soft mixing of the 4 signals
switching artifacts of the adaption algorithm are completely
suppressed.
The comb filter uses the middle line as reference, therefore,
the comb filter delay is one line. If the comb filter is
switched off, the delay lines are used to pass the luma/
chroma signals from the A/D converters to the luma/
chroma outputs. Thus, the comb filter delay is always
one line.
Various parameters of the comb filter are adjustable,
hence giving to the user the ability to adjust his own desired
picture quality.
Two parameters (KY, KC) set the global gain of luma and
chroma comb separately; these values directly weigh
the adaption algorithm output. In this way, it is possible
to obtain a luma/chroma separation ranging from standard
notch/bandpass to full comb decoding.
The parameter KB allows to choose between the two
proposed comb booster modes. This so-called feature
widely improves vertical high to low frequency transitions
areas, the typical example being a multiburst to dc
change. For KB=0, this improvement is kept moderate,
whereas, in case of KB=1, it is maximum, but the risk to
increase the “hanging dots” amount for some given color
transitions is higher.
Using the default setting, the comb filter has separate
luma and chroma decision algorithms; it is however possible
to switch the chroma comb factor to the current
luma adaption output by setting CC to 1.
Another interesting feature is the programmable limitation
of the luma comb amount; proper limitation,
associated to adequate luma peaking, gives rise to an
enhanced 2-D resolution homogeneity. This limitation is
set by the parameter CLIM, ranging from 0 (no limitation)
to 31 (max. limitation).
The DAA parameter (1:off , 0:on) is used to disable/enable
a very efficient built-in “rain effect” suppressor;
many comb filters show this side effect which gives
some vertical correlation to a 2-D uniform random area,
due to the vertical filtering. This unnatural-looking phenomenon
is mostly visible on tuner images, since they
are always corrupted by some noise; and this looks like
rain.
2.3. Color Decoder
In this block, the standard luma/chroma separation and
multi-standard color demodulation is carried out. The
color demodulation uses an asynchronous clock, thus
allowing a unified architecture for all color standards.

If the adaptive comb filter is used for luma chroma separation,
the color decoder uses the S-VHS mode processing.
The output of the color decoder is YCrCb in a 4:2:2
format.
2.3.1. IF-Compensation
With off-air or mistuned reception, any attenuation at
higher frequencies or asymmetry around the color subcarrier
is compensated. Four different settings of the IFcompensation
are possible:
– flat (no compensation)
– 6 dB/octave
– 12 dB/octave
– 10 dB/MHz
The last setting gives a very large boost to high frequencies.
It is provided for SECAM signals that are decoded
using a SAW filter specified originally for the PAL standard.

2.3.2. Demodulator
The entire signal (which might still contain luma) is now
quadrature-mixed to the baseband. The mixing frequency
is equal to the subcarrier for PAL and NTSC, thus
achieving the chroma demodulation. For SECAM, the
mixing frequency is 4.286 MHz giving the quadrature
baseband components of the FM modulated chroma.
After the mixer, a lowpass filter selects the chroma components;
a downsampling stage converts the color difference
signals to a multiplexed half rate data stream.
The subcarrier frequency in the demodulator is generated
by direct digital synthesis; therefore, substandards
such as PAL 3.58 or NTSC 4.43 can also be demodulated.
2.3.3. Chrominance Filter
The demodulation is followed by a lowpass filter for the
color difference signals for PAL/NTSC. SECAM requires
a modified lowpass function with bell-filter characteristic.
At the output of the lowpass filter, all luma information is
eliminated.
The lowpass filters are calculated in time multiplex for
the two color signals. Three bandwidth settings (narrow,
normal, broad) are available for each standard. The filter
passband can be shaped with an extra peaking term at
1.25 MHz. For PAL/NTSC, a wide band chroma filter can
be selected. This filter is intended for high bandwidth
chroma signals, e.g. a nonstandard wide bandwidth
S-VHS signal.

2.3.5. Burst Detection
In the PAL/NTSC-system the burst is the reference for
the color signal. The phase and magnitude outputs of
the CORDIC are gated with the color key and used for
controlling the phase-lock-loop (APC) of the demodulator
and the automatic color control (ACC) in PAL/NTSC.
The ACC has a control range of +30...–6 dB.
For SECAM decoding, the frequency of the burst is measured.
Thus, the current chroma carrier frequency can
be identified and is used to control the SECAM processing.
The burst measurements also control the color killer
operation; they can be used for automatic standard
detection as well.
2.3.6. Color Killer Operation
The color killer uses the burst-phase/burst-frequency
measurement to identify a PAL/NTSC or SECAM color
signal. For PAL/NTSC, the color is switched off (killed)
as long as the color subcarrier PLL is not locked. For SECAM,
the killer is controlled by the toggle of the burst frequency.
The burst amplitude measurement is used to
switch-off the color if the burst amplitude is below a programmable
threshold. Thus, color will be killed for very
noisy signals. The color amplitude killer has a programmable
hysteresis.

2.3.4. Frequency Demodulator
The frequency demodulator for demodulating the SECAM
signal is implemented as a CORDIC-structure. It
calculates the phase and magnitude of the quadrature
components by coordinate rotation.
The phase output of the CORDIC processor is differentiated
to obtain the demodulated frequency. After a programmable
deemphasis filter, the Dr and Db signals are
scaled to standard CrCb amplitudes and fed to the crossover-
switch.
2.3.8. Luminance Notch Filter
If a composite video signal is applied, the color information
is suppressed by a programmable notch filter. The
position of the filter center frequency depends on the
subcarrier frequency for PAL/NTSC. For SECAM, the
notch is directly controlled by the chroma carrier frequency.
This considerably reduces the cross-luminance.

2.4. Horizontal Scaler
The 4:2:2 YCrCb signal from the color decoder is processed
by the horizontal scaler. The scaler block allows
a linear or nonlinear horizontal scaling of the input video
signal in the range of 0.25 to 4. Nonlinear scaling, also
called “panorama vision”, provides a geometrical distortion
of the input picture. It is used to fit a picture with 4:3
format on a 16:9 screen by stretching the picture geometry
at the borders. Also, the inverse effect can be produced
by the scaler. A summary of scaler modes is given
in Table 2–2.
The scaler contains a programmable decimation filter, a
1-line FIFO memory, and a programmable interpolation
filter. The scaler input filter is also used for pixel skew
correction, see 2.3.9. The decimator/interpolator structure
allows optimal use of the FIFO memory. The controlling
of the scaler is done by the internal Fast Processor.
2.5. Blackline Detector
In case of a letterbox format input video, e.g. Cinemascope,
PAL+ etc., black areas at the upper and lower
part of the picture are visible. It is suitable to remove or
reduce these areas by a vertical zoom and/or shift operation.
Table 2–2: Scaler modes
Mode Scale
Factor
Description
Compression
4:3 " 16:9
0.75
linear
4:3 source displayed on a
16:9 tube,
with side panels
Panorama
4:3 " 16:9
nonlinear
compr
4:3 source displayed on a
16:9 tube,
Borders distorted
Zoom
4:3 " 4:3
1.33
linear
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan with
cropping of side panels
Panorama
4:3 " 4:3
nonlinear
zoom
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan, borders
distorted, no cropping
20.25 "
13.5 MHz
0.66 sample rate conversion
to line-locked clock
The VPC 32xx supports this feature by a letterbox detector.
The circuitry detects black video lines by measuring
the signal amplitude during active video. For every field
the number of black lines at the upper and lower part of
the picture are measured, compared to the previous
measurement and the minima are stored in the I2C-register
BLKLIN. To adjust the picture amplitude, the external
controller reads this register, calculates the vertical
scaling coefficient and transfers the new settings, e.g.
vertical sawtooth parameters, horizontal scaling coefficient
etc., to the VPC.
Letterbox signals containing logos on the left or right
side of the black areas are processed as black lines,
while subtitles, inserted in the black areas, are processed
as non-black lines. Therefore the subtitles are
visible on the screen. To suppress the subtitles, the vertical
zoom coefficient is calculated by selecting the larger
number of black lines only. Dark video scenes with a low
contrast level compared to the letterbox area are indicated
by the BLKPIC bit.
2.6. Control and Data Output Signals
The VPC 32xx supports two output modes: In
DIGIT3000 mode, the output interfaces run at the main
system clock, in line-locked mode, the VPC generates
an asynchronous line-locked clock that is used for the
output interfaces.
2.6.1. Line-Locked Clock Generation
An on-chip rate multiplier will be used to synthesize any
desired output clock frequency of 13.5/16/18 MHz. A
double clock frequency output is available to support
100 Hz systems. The synthesizer is controlled by the
embedded RISC controller, which also controls all frontend
loops (clamp, AGC, PLL1, etc.). This allows the generation
of a line-locked output clock regardless of the
system clock (20.25 MHz) which is used for comb filter
operation and color decoding. The control of scaling and
output clock frequency is kept independent to allow aspect
ratio conversion combined with sample rate conversion.
The line-locked clock circuity generates control
signals, e.g. horizontal/vertical sync, active video output,
it is also the interface from the internal (20.25 MHz)
clock to the external line-locked clock system.
If no line-locked clock is required, i.e. in the DIGIT3000
mode, the system runs at the 20.25 MHz main clock. The
horizontal timing reference in this mode is provided by
the front-sync signal. In this case, the line-locked clock
block and all interfaces run from the 20.25 MHz main
clock. The synchronization signals from the line-locked
clock block are still available, but for every line the internal
counters are reset with the main-sync signal. A
double clock signal is not available in DIGIT3000 mode.
2.6.2. Sync Signals
The front end will provide a number of sync/control signals
which are output with the output clock. The sync signals
are generated in the line-locked clock block.
– Href : horizontal sync
– AVO: active video out (programmable)
– HC: horizontal clamp (programmable)
– Vref : vertical sync
– INTLC: interlace
– HELPER: PAL+ helper lines
All horizontal signals are not qualified with field information,
i.e. the signals are present on all lines. The horizontal
timing is shown in Fig. 2–14. Details of the horizontal/
vertical timing are given in Fig. 2–18.
The digital video interface allows insertion of digital data
in YCrCb format on the internal YCrCb data bus. The
orthogonal data structure of this bus is the ideal interface
point to external data sources and sinks.
2.6.3. DIGIT3000 Output Format
The picture bus format between all DIGIT3000 ICs is
4:2:2 YCrCb with 20.25 MHz samples/s. Only active video
is transferred, synchronized by the system main sync
signal (MSY) which indicates the start of valid data for
each scan line and which initializes the color multiplex.
The video data is orthogonally sampled YCrCb, the output
format is given in Table 2–3. The number of active
samples per line is 1080 for all standards (525 and 625).
The output can be switched to 4:1:1 mode with the output
format according to Table 2–4.
Via the MSY line, serial data is transferred which contains
information about the main picture such as current
line number, odd/even field etc.). It is generated by the
deflection circuitry and represents the orthogonal timebase
for the entire system.

2.8. Video Sync Processing
Fig. 2–16 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is separated
by a slicer; the sync phase is measured. A variable
window can be selected to improve the noise immunity
of the slicer. The phase comparator measures the
falling edge of sync, as well as the integrated sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is integrated.
The FP uses the integrator value to derive vertical
sync and field information.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and is distributed to the rest of the video processing system.
The format of the front sync signal is given in
Fig. 2–17.
The data for the vertical deflection, the sawtooth, and the
East-West correction signal is calculated by the
VPC32xx. The data is buffered in a FIFO and transferred
to the back-end IC DDP 3300A by a single wire interface.
Frequency and phase characteristics of the analog video
signal are derived from PLL1. The results are fed to
the scaler unit for data interpolation and orthogonalization
and to the clock synthesizer for line-locked clock
generation. Horizontal and vertical syncs are latched
with the line-locked clock.


SDA 9254-2 2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM) with
On-chip Noise Reduction Filter

Functional Description
General
The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive recursive filter to
achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of
the triple port memory is connected internally to the noise reduction filter. External access to this
port is not possible. The characteristic of the noise reduction filter is adjustable via three pins
(CLASS2, CLASS1, CLASS0).

Features
l Stores a complete video field (4:1:1)
l On chip adaptive recursive noise reduction filter (4:1:1)
l 4 noise reduction classes selectable
l Special noise reduction mode for 4:2:2 applications
l 212 ´ 64 ´ 16 ´ 12-bit organization
l Triple port architecture
l One 16 ´ 12-bit input shift register
l Two 16 ´ 12-bit output shift registers
l Shift registers independently and simultaneously
accessible (one output shift register is used internally for
noise reduction filtering)
l Continuous data flow even at maximum speed
l 40-MHz shift rate - 0.96-Gbit/s total data rate
l All inputs and outputs TTL-compatible
l Tristate outputs
l Random access of groups of 16 ´ 12 bits for a wide range
of applications
l Refresh-free operation possible
l 5 V ± 10 % power supply
l 0 … 70 °C operating temperature range
l Low power dissipation: 700 mW active, 28 mW standby
l Suitable for all common TV standards
l Allows flicker and noise reduction simultaneously
with only one field memory
l Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV

Noise Reduction Filtering
To avoid artefacts in moving parts of the picture a motion detector is implemented to control the filter
coefficient K according to detected changes between two adjacent fields. The motion detector
performs a low pass filtering of the field differences and builds the absolute values. The results
control the filter coefficient K by choosing one of 13 predefined values between 1/4 and 1. The
characteristic of this assignment influences the amount of noise reduction and is adjustable via the
CLASS-pins. The calculation of the filter coefficient is practised for each pixel of the field.

Memory
The memory has a capacity of 2605056 bit. It is organized as 212 rows by 64 columns by 16 arrays
by 12 bit and allows the storage of the active part of a complete 4:1:1-TV field using a 13.5 MHz
sample rate. The memory is fabricated using the same CMOS technology used for 4-Mbit standard
dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 x 12-bit input
shift register C to an addressed location of the memory array and from the memory array to one of
the 16 x 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address
(SAC) which contains the desired column address and an instruction code (mode bits) for transfer
and refresh.

Circuit Description
Memory Architecture
As shown in the block diagram of the memory part (see figure 7), the TV-SAM comprises 192
memory arrays, which are accessed in parallel. Each memory array has a size of 212 rows by 64
columns. The rows and columns of the 192 arrays can be randomly addressed, reading or writing
16 x 12 bits at a time. To obtain the extremely high data rate at the 12-bit wide data input (port C)
and outputs (port A and B), a parallel to serial conversion is done using shift registers of 16-bit
length and 12-bit width. In this way the memory speed is increased by a factor of 16. (This is
independent on the number of ports if the total data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 x 12-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.
Data Input (SDC, SCB)
The data pins SDC are connected to the input of the recursive filter. The delay time from SDC to
the memory port C caused by the filter amounts 8 periods of the clock SCB. The delay time is to be
considered for the generation of the signal WT (see diagram 8).
Data are shifted into the memory using the serial port C at the rising edge of the shift clock SCB.
After 16 clock pulses the data have to be transferred from shift register C to latch C. If more than
16 clock pulses occur before latching the data, only the last sixteen 12-bit data values are accepted.
Data Input (DLI), Data Output (DLO, OEDLO)
In 4:2:2-mode 4 bitplanes of the chrominance signals are connected to an internal delay line via the
pins DLI. After 8 periods of clock SCB the input data are supplied at the delay line output DLO.
Via the output enable OEDLO the output buffers can be switched into tristate. In 4:1:1-mode the DLI
pins should be connected to GND and pin OEDLO should be connected to VDD.
Data Transfer from Shift Register C to Latch C (WT)
The contents of the shift register C is transferred to latch C at the falling edge of the write transfer
signal WT. If the timing restrictions between WT and the clock SCB are respected, a continuous
data flow at input port C is possible without loosing data. This transfer operation may be
asynchronous to all other transfer operations except for a small forbidden window conditioned by
the latch C to memory transfer.

Write Transfer from Latch C to Memory (RE)
The data of latch C are transferred to the preaddressed location of the memory array at the rising
edge of RE, if the mode bits were set to H (M1) and L (M0), see “Addressing and Mode Control.”
Addressing and Mode Control (SAR, SAC, SCAD, RE)
The serial 8-bit row address SAR and the 8-bit column address/mode code SAC are serially shifted
into the TV-SAM (LSB first) at rising edge of the address clock SCAD. After 8 SCAD cycles, the
falling edge of RE internally latches SAR and SAC. The column address itself needs only 6 bits. The
last 2 bits of SAC are defined as mode bits and determine the read/write and refresh operation of
the memory arrays to be triggered by the RE signal.


SDA 9280 B22 Display Processor

General Description
The Display Processor SDA 9280 is an integrated triple 9 Bit D/A converter which
performs digital enhancements and manipulations of digital video component signals.
Multiple input data formats are accepted. Operation with normal as well as doubled
horizontal deflection frequency is supported. 4:3 or 16:9 display formats are possible.

Features
• 8-Bit amplitude resolution of each input component
Input sample frequency up to 30 MHz
Application in flicker reduction systems possible
• Four input data formats
4:1:1 luminance and chrominance parallel
(8 + 4 wires)
4:2:2 CCIR 656-format (8 wires)
4:2:2 luminance and chrominance parallel (2 x 8 wires)
4:4:4 all components parallel (3 x 8 wires)
• Two different representations of input data
Positive dual code
2’s complement code
• Three D/A converters on-chip
9-Bit amplitude resolution
80 MHz maximal clock frequency
• DCTI (digital color transient improvement)
A digital algorithm improves the sharpness of vertical color edges
avoiding the artifacts of analog CTI-circuits
• Luminance peaking
Separate programmable lowpass, bandpass, and highpass digital filters
• High performance digital interpolation for anti-imaging
Two-fold oversampling
Simplification of external analog postfiltering
• 16:9 compatibility
Signal compression for displaying 4:3-signals on16:9-screens
Signal expansion for displaying 16:9-signals on 4:3-screens
Full screen display of 4:3 letter box pictures
• Programmable delay for the luminance signal
Phase adjustment between luminance and chrominance signals
• Signal manipulations
Inverted display
Graphic display
• Insertion of colored areas
Programmable color and position
• Insertion of an arbitrary pattern
Control by an external signal
One of 4096 colors programmable
Frame insertion for multi picture display
• N-Fold zoom facility for image memory systems
• Programmable internal PLL for clock generation
Control of compression and expansion factors
• I2C-Bus control
• P-LCC-68-1 package
• 5 V supply voltage

The SDA 9280 accepts four different data input formats (I2C signal: INFOR). Three
sample frequency relations of Y:(B-Y):(R-Y) are possible (4:1:1 or 4:2:2 or 4:4:4).

The representation of the samples is programmable separately for luminance and
chrominance signals as positive dual code or 2’s complement code
(I2C signals: INCODL, INCODC)
The amplitude resolution for each input is 8 Bit, the maximal clock frequency is 30 MHz.
Consequently the SDA 9280 is dedicated for applications in high quality digital video
systems. The data input stages and the internal data multiplexer operate with a special
data input clock (SCA). For applications in the Siemens MEGAVISION® System the
SCA-clock is identical with the memory output clock. A separation of the data input clock
and the system clock is relevant to handle the special data format occurring at “zoom”
operation mode. For other applications SCA can be connected with CLL.

Luminance Peaking Filter
The luminance peaking filter improves the over all frequency response of the luminance
channel. It consists of three filters working in parallel. They have low pass (LP(z)), band
pass (BP(z)) and high pass (HP(z)) characteristics. Their gain factors are separately
programmable (I2C signals: LCOF, BCOF, HCOF) according to the following equations:
LCOF * LP(z) + BCOF * BP(z) + HCOF * HP(z)
with: LCOF = 0 ... [1/4] ... 3/2, 2
BCOF = 0 ... [1/4] ... 3, 7/2, 4, 5
HCOF = 0 ... [1/4] ... 3, 7/2, 4, 5
LP(z) = 1/16 * (1 + z-1)4
BP(z) = -1/8 * (1 - z-2)2
HP(z) = 1/16 * (1 - z-1)4
An amplification of up to 14 dB at the half of the sample frequency is available. The high
pass and band pass filters are equipped with a common coring algorithm. It is optimized
to achieve a smooth display of grey scales, not to improve the signal-to-noise ratio.
Therefore no artifacts are produced. Coring can be switched off (I2C signal: COR).
Note: The peaking filter may shift the black level of the signal. This has to be considered
for black level insertion (see Insertion Facilities).
A delay line for the luminance signal enables an adaption to the delay of the chrominance
signals. A range of -8 to +7 clock periods of the system clock CLL is programmable
(I2C signal: YDEL1).
An additional special filtering is available for compensating a non linear phase response
of the analog part of the signal path.
(1 + PHACOM) * z–1 - PHACOM
Three adjustments are I2C-Bus programmable: PHACOM = 0, 1/4, 1/8.

Digital Color Transient Improvement (DCTI)
A new digital algorithm is implemented to improve horizontal transitions of the
chrominance signals resulting in a better picture sharpness. A slow change from one
color to another by reason of small chrominance bandwidth is replaced by a steep
transition.
The exact position of a color transition (POS) is calculated by detecting the
corresponding zero transition of the second derivative of both chrominance signals. Low
pass filtering (LPU, LPV, LPUV) is performed to avoid noise sensitivity. The width of a
transition is derived from a threshold detector signal. It indicates an area around the
detected position where the first derivatives of the chrominance signals exceed a
programmable threshold (I2C signal: THRESH). The parameter THRESH modifies the
sensitivity of the DCTI-circuit. High values cause that only significant color transitions are
improved. Small color variations remain unchanged. The detected transition width can
be limited by the programmable parameter TRAWID. This parameter performs an
adaption to the input chrominance band width. For signals with small chrominance
bandwidth (e.g. video recorders) the DCTI-performance is optimized using high values
for TRAWID. Input signals with high chrominance bandwidth should be processed with
small values for TRAWID. If standard 4:1:1 video signals are processed, it is
recommended to choose values of the mid range for both parameters THRESH and
TRAWID.

Picture Manipulations
A graphic display effect is realized by programmable reduction of amplitude resolution
(I2C signals: YGR, YGRRES, CGR, CGRRES). A resolution of 1 to 4 bits is available. A
special characteristic avoids a reduction of picture brightness and color saturation.
The inverted display mode is attained by a programmable bit inversion for each signal
component (I2C signals: YINV, UINV, VINV).
Multiple combinations of both manipulations supply very amazing effects on the display.
2.6 16:9-Operation, Signal Compander
The compander enables a display with correct geometric proportions of 4:3 signals on
16:9-screens or 16:9-signals on 4:3-screens. A full screen display of 4:3-letterbox
signals on 16:9-screens is also practicable. Having a full screen display of such signals
on 4:3-screens only a part of the picture can be shown. In this operation mode a
horizontal shift of the picture part used for display is programmable (I2C signal: READD).
Expansion in vertical direction must be realized by manipulation of the vertical deflection
current.
To satisfy all these demands a horizontal compression or expansion of the video signals
is performed by raising or reducing the sample frequency. The data are written into a
memory using the system clock CLL and read with a clock of higher or lower frequency.

This realization does not effect the horizontal detail resolution of the picture because no
filtering is executed.
The highest read frequency is 4/3 of the CLL-frequency for signal compression, the
lowest is 3/4 of the CLL-frequency for signal expansion. The reading clock is supplied by
the internal PLL.
The compander operation mode is programmable via I2C signals COMP and COMEX.

In general D/A conversion requires postfiltering to avoid non-harmonic distortions
caused by intermodulations of the signal with its spectral images. These
intermodulations may come from non-linear characteristics of subsequent amplifier
stages or of the display. The spectral images are duplicates of the signal spectrum
around multiples of the sampling frequency. These images, a counterpart of aliasing in
the A/D conversion, become visible after D/A conversion. They are only reduced by the
sinx/x characteristic of the D/A converter.

Amplification, D/A Conversion
Before D/A conversion a fine adjustment of the phase of the luminance signal is
performed (I2C signal: YDEL2). The delay of the luminance signal can be varied by one
period of the D/A converter clock.
The amplification factors of each signal component can be reduced by a factor of 0.5
(I2C signals: AMPY, AMPU, AMPV). This reduction of nominal amplification reserves
one bit for D/A conversion of overshooting, resulting from strong peaking or interpolation
filtering. The input amplitude resolution of 8 Bit is not reduced. For conversion of signals
without or with only small overshooting a reduction of the amplification factor is not
necessary. A digital limiter circuit prevent the D/A converters from possible overdriving
by clipping.
Note: Clipping causes a non-linear deformation with interferences between multiples of
the signal frequency and the sample rate of the signal and should be avoided by
reducing the amplification factor.
A triple 9 Bit D/A converter is implemented on the SDA 9280. The DACs are short circuit
protected converters with current outputs.



SDA 9220-5 Memory Sync Controller III

Functional Description
The MSC III is a component of the TV-SAM Featurebox and is responsible for driving the picture
memory devices (TV-SAMs) and generating sync signals (figure 6). Together with the other
devices of the Featurebox it enhances picture quality and offers a number of special operating
modes.
The MSC III is set via the I2C Bus, it being possible to switch the I2C Bus address by hardware so
that implementation of a simple frame Featurebox is possible in conjunction with the signal MUX
supplied by the MSC III.
Other major output signals of the SDA 9220-5, in addition to the clocks LL3X (13.5 MHz) and LL1.5X
(27 MHz), are the memory-driving signals (RA, RB, WT, RE, SCAD, SCA) and the sync signal CSY
for the teletext device. The horizontal sync signals (HS2, BLN2) and the vertical sync signals (VS1,
VS2) are also generated.

Features
l Large area flicker elimination through field doubling
l Additional elimination of interline flicker in field mode
l Field switching and selection in field mode
l Noise and cross-color reduction
l Stills
l 9-image display, still-in-picture, picture-in-still
with different frame versions
l Zoom with selection of enlarged picture segment
(8 x 12 positions)
l Pin-programmable operation without standard
conversion.

Circuit Description
The MSC III can be divided into the following function blocks (figure 6):
– Sync-signal generator
– Memory controller
– Clock generator
– I2C Bus receiver
The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync
signals BLN2, HS2, VS1 and VS2. It supplies the composite sync signal CSY for the 100-Hz
teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal
FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal
CFH is output to prevent the bottom flutter effect in the video cassette recorder mode.
In operation without standard conversion (pin-programmable) signals BLN2, VS2 and FRM are
switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this
case.
The memory controller produces the driving signals (RA, RB, WT, RE) and the addresses (SAR,
SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for
requesting data from the picture processor during operation with reduced pictures. Two refresh
operations are performed in the memory for each TV line.
The clock generator consists essentially of a PLL which generates the internal and exported system
clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The
MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the
Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to
ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching
phases.
All modes (except switching off the standard conversion) are set by appropriate programming of the
I2C Bus data bytes. When the operating voltage is switched on, all bits of the associated control
registers are set to 0. The address of the I2C Bus is set with signal ADR (24H or 26H).

Picture Formats
The MSC forms part of a digital television system with line-locked scanning frequency. The nominal
word rate is 13.5 MHz for luminance and 3.375 MHz for each of the U and V color components. The
active region of a TV line is identified by the high time interval of BLN. It comprises 720 pixels for
luminance and 180 pixels each for U and V and is stored in its entirety. In the 50-Hz standard a field
consists of 287.5 lines and in the 60-Hz standard of 243.5 lines.
288 lines are stored in the 50-Hz standard (lines 23-310 of the first field, lines 336-623 of the second
field) and 243 lines in the 60-Hz standard (lines 17-259 of the first field, lines 280-522 of the second
field), (figure 1). In the 9-image mode a field without a frame consists of 208 pixels per line for
luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance and
2 x 1 for chrominance with memory or display frames. The number of lines without a frame is 84 for
the 50-Hz standard and 71 for the 60-Hz standard. Two lines less are displayed with a frame
(figures 2 and 3).
In the picture-in-still (PIS) and still-in-picture (SIP) modes a field without a frame or having a display
frame is of the same size as a 9-image window. With the memory frame, however, eight pixels are
lost for luminance and 2 x 2 for chrominance (figure 4).
For generating the windows in the modes 9-image display, PIS and SIP the picture data are filtered
horizontally and vertically in the picture processor and reduced by a factor of three.
In the zoom mode a segment of the stored picture is enlarged by a factor of two by displaying each
pixel twice as long and each line twice. The position of this picture segment is selectable.
Eight vertical and twelve horizontal positions can be set by the I2C Bus (figure 5).
Random Interlace
The phase of VS relative to HS and the active picture content is measured at the input. At the output
VS2 is generated in the same phase relation to HS2 and the picture content. Despite the random
interlacing this means that standard picture conversion is possible without any visible interference.
Display Raster
There are three ways of displaying the field sequence: one is without interlace and two are with
interlace, i.e. with a 50-Hz or 60-Hz interlace frequency or a 100-Hz or 120-Hz interlace frequency
respectively. In what follows these are referred to symbolically as aaaa, aabb or baba. They are
produced by a suitable sequence of the vertical sync pulses VS2 for the standard-converted video
signal. The symbols an, bn denote the vertical sync phases of the pulses (VS, VS2) referred to the
horizontal blanking signals (BLN, BLN2), i.e. an when the positive vertical sync edge falls within one
blanking half cycle and bn when it falls within the complementary blanking half cycle.
Normally the input signal will be as follows: (an–1, bn–1) (an, bn) (an+1, bn+1) with an and bn virtually
constant. Figures 15, 16, 17, 18 and 19 show the sequence obtained for output signal VS2 when
using one of the three operating modes.



SDA 9362 DDC-PLUS-Deflection Controller



General Description
The SDA 9362 is a highly integrated deflection controller for CTV receivers with doubled
line and standard or doubled field frequencies. It controls among others an horizontal
driver circuit for a flyback line output stage, a DC coupled vertical sawtooth output stage
and an East-West raster correction circuit. All adjustable output parameters are I2C Bus
controlled. Inputs are HSYNC, VSYNC and the line locked clock CLL.

Features
• Deflection - Protection - 16:9 / 4:3
• I2C Bus alignment of all deflection parameters
• All EW-, V- and H-functions (incl. F2)
• PW EHT compensation
• PH EHT compensation
• Compensation of H-phase deviation
(e.g. caused by white bar)
• Upper/lower EW-corner correction separately adjustable
• V-angle correction: Vertical frequent linear modulation of H-phase
• V-bow correction: Vertical frequent parabolic modulation of H-phase
• Three reduced V-scan modes (75 %, 66 %, 50 % V-size) selectable
• H- and V-blanking time adjustable
• Partial overscan adjustable to hide the cut off control measuring lines in the reduced
scan modes
• Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different
letterbox formats without annoying overscan
• Dynamic PH EHT-compensation (white bar)
• Self adaptation of V-frequency/number of lines per field between 192 and 680 for each
possible line frequency
• Protection against EHT run away (X-rays protection)
• Protection against missing V-deflection (CRT-protection)
• Two digital outputs for general purpose, controlled by I2C Bus
• Selectable softstart of the H-output stage
• P-MQFP-44-2 package
• 5 V supply voltage

Functional Description
The main input signals are HSYNC with doubled horizontal frequency, VSYNC with
vertical frequencies of 50/100 Hz or 60/120 Hz and the line locked clock CLL.
The output signals control the horizontal as well as the vertical deflection stages and the
East-West raster correction circuit.
The H-output signal HD compensates the delays of the line output stage and its phase
can be modulated vertical frequent to remove horizontal distortions of vertical raster lines
(V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line
flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift
is 2.25 ms.
Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the
aspect ratio of the source signal.
The V-output sawtooth signals VD- and VD+ controls a DC coupled output stage and can
be disabled. Suitable blanking signals are delivered by the IC.
The East-West output signal E/W is a vertical frequent parabola of 4th order, enabling
an additional corner correction, separately for the upper and lower part.
Two I2C Bus controlled digital outputs are available for general purpose.
The picture width and picture height compensation (PW/PH Comp) processes the beam
current dependent input signal IBEAM with effect to the outputs E/W and VD to keep
width and height constant and independent of brightness.
The alignment parameter Horizontal Shift Compensation enables to adjust the influence
of the input signal IBEAM on the horizontal phase.
The selectable start up circuit controls the energy supply of the H-output stage during the
receiver's run up time by smooth decreasing the line output transistors switching
frequency down to the normal operating value (softstart). HD starts with about 55 kHz
and converges within 85 ms to its final value. The high time is kept constant. The normal
operating pulse ratio H/L is 45/55. A watch dog function limits the period of the HD output
signal independent of the clock CLL to max 35.2 ms.
The protection circuit watches an EHT reference and the sawtooth of the vertical output
stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the
V-deflection fails (refer to page 36). The function of this circuit is based on the internal
quartz oscillator and therefore independent of the input clock CLL.

Circuit Description
The system clock for the SDA 9362 has to be generated externally (e.g. in the
SDA 9206) and applied to pin CLL. Its frequency must be always the line frequency
(defined by the horizontal time reference HSYNC) multiplied by 864. If no HSYNC signal
is available an internal horizontal synchronisation signal is derived from CLL (CLL
divided by 879).
The input signal at VSYNC is the vertical time reference. It has to pass a window
avoiding too short or long V-periods in the case of distorted or missing VSYNC pulses.
The window allows a VSYNC pulse only after a minimum number of lines from its
predecessor and sets an artificial one after a maximum number of lines. The window size
is programmable by I2C Bus.
The beam current dependent input signal IBEAM is A/D converted and then digitally
processed. The A/D Converter requires a clock frequency twice the frequency of CLL
which is generated by an internal analog PLL with an external loop filter at pin LF.
Values which influence shape and amplitude of the output signals are transmitted as
reduced binary values to the SDA 9362 via I2C Bus. A CPU which is designed for speed
reasons in a pipe line structure calculates in consideration of feedback signals (e.g.
IBEAM) values which exactly represent the output signals. These values control after
D/A conversion the external deflection and raster correction circuits. The CPU firmware
is stored in an internal ROM.



SDA 5275-2 MEGATEXT PLUS

MEGATEXT PLUS (SDA 5275-2) has been developed based on the original Megatext
(SDA 5273).

MEGATEXT PLUS is completely hardware compatible to the SDA 5273. However its
internal processing has been changed to enable reception of all level 2.5 related data
with only little external software support.
MEGATEXT PLUS is able to request, acquire and display HiText (teletext level 2.5)
pages automatically in real-time. The firmware processes objects, DRCS-characters,
parallel attributes, CLUT and sidepanel information for 16:9 applications.
The only remaining task for the user is to reserve enough external memory space for
higher level pages like MOTs, POPs, DRCS-pages and related pseudopackets. For
Level 2.5 transmission this number of additional pages should not exceed more than 500
packets. So the user should reserve appropriate memory for MOTs, POPs and DRCS -
pages (refer to [3]). Because some part of high level information is transmitted in
pseudopackets X/25, X/26, X/27, X/28 and X/29, enough memory should also be
reserved in the P40 and P80 chains.
The Serial/Parallel Conversion (S/P-C) is able to handle all teletext level 2.5 features
which are described in the “World Standard Teletext Norm”. For the evaluation of all
information stored in packets X/25, X/26, X/27, X/28, X/29 and in the linked pseudo
pages, the S/P-C needs additional temporary memory space in the external memory, the
so-called hidden display memory.


TDA4780 RGB video processor with automatic cut-off control and gamma adjust

GENERAL DESCRIPTION
The TDA4780 is a monolithic integrated circuit with a
luminance and a colour difference interface for video
processing in TV receivers. Its primary function is to
process the luminance and colour difference signals from
a colour decoder which is equipped e.g. with the
multistandard decoder TDA4655 or TDA9160 plus delay
line TDA4661 or TDA4665 and the Picture Signal
Improvement (PSI) IC TDA467X or from a feature module.
The required input signals are:
· Luminance and negative colour difference signals
· 2 or 3-level sandcastle pulse for internal timing pulse
generation
· I2C-bus data and clock signals.
Two sets of analog RGB colour signals can also be
inserted, e.g. one from a peritelevision connector
(SCART plug) and the other one from an On-Screen
Display (OSD) generator. The TDA4780 has I2C-bus
control of all parameters and functions with automatic
cut-off control of the picture tube cathode currents.
It provides RGB output signals for the video output stages.
In clamped output mode it can also be used as an RGB
source.
The main differences with the sister type TDA4680 are:
· Additional features, namely gamma adjust, adaptive
black, blue stretch and two different peak drive limiters
· The measurement lines are triggered by the trailing
edge of the vertical component of the sandcastle pulse
· I2C-bus receiver only. Automatic white level control is
not provided; the white levels are determined directly by
the I2C-bus data.
· The TDA4780 is pin compatible (except pin 18) with the
TDA4680. The I2C-bus slave address can be used for
both ICs. When a function of the TDA4780 is not
included in the TDA4680, the I2C-bus command is not
executed. Special commands (except control bit FSWL)
for the TDA4680 will be ignored by the TDA4780.

FEATURES
· Gamma adjust
· Dynamic black control (adaptive black)
· All input signals clamped on black-levels
· Automatic cut-off control, alternative: output clamping
on fixed levels
· Three adjustable reference voltage levels via I2C-bus for
automatic cut-off control
· Luminance/colour difference interface
· Two luminance input levels allowed
· Two RGB interfaces controlled by either fast switches or
by I2C-bus
· Two peak drive limiters, selection via I2C-bus
· Blue stretch, selection via I2C-bus
· Luminance output for scan velocity modulation
(SCAVEM)
· Extra luminance output; same pin can be used as hue
control output e.g. for the TDA4650 and TDA4655
· Non standard operations like 50 Hz/32 kHz are also
possible
· Either 2 or 3 level sandcastle pulse applicable
· High bandwidth for 32 kHz application
· White point adjusts via I2C-bus
· Average beam current and improved peak drive limiting
· Two switch-on delays to prevent discoloration during
start-up
· All functions and features programmable via I2C-bus
· PAL/SECAM or NTSC matrix selection.

Automatic cut-off control
During leakage measurement time the leakage current is
compensated in order to get a reference voltage at the
cut-off measurement info pin. This compensation value is
stored in an external capacitor. During cut-off current
measurement times for the R, G and B channels, the
voltage at this pin is compared with the reference voltage,
which is individually adjustable via I2C-bus for each colour
channel. The control voltages that are derived in this way
are stored in the external feedback capacitors. Shift stages
add these voltages to the corresponding output signals.
The automatic cut-off control may be disabled via the
I2C-bus. In this mode the output voltage is clamped to
2.5 V. Clamping periods are the same as the cut-off
measurement periods.
Signal limiting
The TDA4780 provides two kinds of signal limiting.
First, an average beam limiting, that reduces signal level if
a certain average is exceeded. Second, a peak drive
limiting, that is activated if one of the RGB signals even
shortly exceeds a via I2C-bus adjusted threshold.
The latter can be either referred to the cut-off
measurement level of the outputs or to ground.
When signal limiting occurs, contrast is reduced, and at
minimum contrast brightness is reduced additionally.
Sandcastle decoder and timer
A 3-level detector separates the sandcastle pulse into
combined line and field pulses, line pulses, and clamping
pulses. The timer contains a line counter and controls the
cut-off control measurement.
Application with a 2-level 5 V sandcastle pulse is possible.
Switch on delay circuit
After switch on all signals are blanked and a warm up test
pulse is fed to the outputs during the cut-off measurement
lines. If the voltage at the cut-off measurement input
exceeds an internal level the cut-off control is enabled but
the signal remains still blanked. In the event of output
clamping, the cut-off control is disabled and the switch on
procedure will be skipped.
Y output and hue adjust
The TDA4780 contains a D/A converter for hue adjust.
The analog information can be fed, e.g. to the
multistandard decoder TDA4650 or TDA4655. This output
pin may be switched to a Y output signal, which can be
used for scan velocity modulation (SCAVEM). The Y
output is the Y input signal or the matrixed (RGB) input
signal according to the switch position of the fast switch.
I2C-bus
The TDA4780 contains an I2C-bus receiver for control
function.
ESD protection
The Pins are provided with protection diodes against
ground and supply voltage (see Chapter “Internal pin
configurations”). I2C-bus input pins do not shunt the
I2C-bus signals in the event of missing supply voltage.

Notes to the characteristics
1. RGB signals controlled by saturation, adaptive black, contrast and brightness. Gamma affects the Y component of
the internal RGB signals.
2. Adaptive black control acts on Y signal, which is either Y input or Y output from RGB matrix. Negative set-up is not
affected. The level shift value is determined by the peak dark detector, operation selected by control bit ADBL. The
peak dark detector is inactive during blanking. Peak dark detector activated by internal line counter, which starts after
the end of the vertical blank of the sandcastle. Active from line 16 (after end of vertical sandcastle) to line 224
(NTSC mode, NMEN = 1) or line 272 (PAL mode, NMEN = 0). It is recommended to increase the contrast value
(subaddress 02H) by 15% if ADBL = 1. The line numbers are doubled if control bit HDTV = 1.
3. At minimum gamma (3FH) any differences in black level steps are amplified by 6 dB.
4. For nominal saturation the range of values is:
a) 1FH is the minimum value that can be used
b) 20H is the typical value that can be used
c) 21H is the maximum value that can be used.
5. For nominal contrast the range of values is:
a) 20H is the minimum value that can be used
b) 22H is the typical value that can be used
c) 24H is the maximum value that can be used.
6. . For meaning of actual nominal signal see
chapter “Characteristics”.
7. Series resistor in supply voltage should be less than 0.3 W.
8. At 1.0 V cut-off measurement level the function of the cut-off control loop is not guaranteed because the blanking
level is limited to the minimum output voltage. For proper working a guide number for the minimum cut-off
measurement level is 1.3 V.
9. For nominal AC gain settings the range of values is:
a) 21H is the minimum value that can be used
b) 22H is the typical value that can be used
c) 23H is the maximum value that can be used.
10. . For meaning of actual nominal signal see
chapter “Characteristics”.
11. Sandcastle pulse detector (pin 14)
The sandcastle pulse is compared with 3 (control bit SC5 = 0) or 2 (SC5 = 1) internal threshold levels to separate the
various pulses; the internal pulses are generated while the input is higher than the thresholds. The thresholds are
independent of supply voltage and temperature.

12. Blanking to ultra black level occurs during time DG except MR in R-channel, MG in G-channel, MB in B-channel (see
Fig.10).
a) Leakage current measuring time:
LM will start after the end of vertical sandcastle (see Fig.10).
b) Vertical blanking period and cut-off measurement lines (see Fig.10):
The vertical component will be identified if it contains 2 or more burst key pulses in the event of SC5 = 1 or two
or more line pulses (H) in the event of SC5 = 0. The line counter is triggered by the leading edge.
The blanking time is valid for a vertical pulse detected by the sandcastle decoder.
The internal blank pulse is OR gated with the sandcastle vertical pulse and the end of the measurement pulses.
c) Insertion time: full line period.
d) Measurement time: line period minus horizontal period (50/60 Hz).
e) Line sequence of measuring lines (see Fig.10):
First line after end of horizontal pulse which followed the end of vertical pulse: leakage measurement LM
First line after leakage measurement pulse: red measurement MR
Second line after leakage measurement pulse: green measurement MG
Third line after leakage measurement pulse: blue measurement MB.
13. Y output can be switched to hue adjust output via I2C-bus control bit YEXH. Output without sync pulse.
Recommendation: Hue adjust DAC set to 3FH. Black level adjustable via hue adjust DAC.
14. Output can be switched to Y output via I2C-bus control bit YEXH (via I2C-bus, resolution 6-bit, bus subaddress 03H).


MSP 3410D Multistandard Sound Processor


1. Introduction
The MSP 3410D is designed as a single-chip Multistandard
Sound Processor for applications in analog and
digital TV sets, satellite receivers, video recorders, and
PC-cards. As the successor of the MSP 3410B and MSP
3400C, the MSP 3410D combines all features of the two
and adds several new features.
The MSP 3410D, again, improves function integration:
The full TV sound processing, starting with analog
sound IF signal-in, down to processed analog AF-out, is
performed in a single chip. It covers all European TVStandards
(some examples are shown in Table 3–1).
The MSP 3400 1.0 m CMOS version is fully pin and software
compatible to the MSP 3410, but is not able to decode
NICAM. It is also compatible to the MSP 3400C
0.8 m CMOS version.
The IC is produced in submicron CMOS technology,
combined with high performance digital signal processing.
The MSP 3410D is available in a PLCC68,
PSDIP64, PSDIP52, and in a PQFP80 package.
Note: The MSP3410D version is fully downward compatible
to the MSP 3410B, the MSP 3400B, and the MSP
3400C. To achieve full software compatibility with MSP
3400C, MSP 3400B, and MSP 3410B, the demodulator
part must be programmed as described in the data sheet
of MSP 3410B.
1.1. MSP 3410D Additional Features and Major Improvements
compared with MSP 3410B (section 8.)
– AVC: Automatic Volume Correction
– Subwoofer Output
– 5-band graphic equalizer (as in MSP 3400C)
– Enhanced spatial effect (pseudostereo/basewidth enlargement
as in MSP 3400C)
– headphone channel with balance, bass, treble, loudness
– balance for loudspeaker and headphone channels in
dB units (optional)
– Additional pair of D/A converters for SCART2 out
– improved oversampling filters (as in MSP 3400C)
– Additional SCART input
– Full SCART in/out matrix without restrictions
– Scart volume in dB units (optional)
– Additional I2S input (as in MSP 3400C)
– New FM-identification (as in MSP 3400C)
– Demodulator short programming
– Autodetection for terrestrial TV-sound standards
– Precise bit-error rate indication
– Automatic switching from NICAM to FM/AM or vice
versa
– Improved NICAM synchronization algorithm
– Improved carrier mute algorithm
– Improved AM-demodulation
– ADR together with DRP 3510A
– Dolby Pro Logic together with DPL 35xx A
– Reduction of necessary controlling
– Less external components
– Significant reduction of radiation.

2. Basic Features of the MSP 3410D
2.1. Demodulator and NICAM Decoder Section
The MSP 3410D is designed to simultaneously perform
digital demodulation and decoding of NICAM-coded TV
stereo sound, as well as demodulation of FM or AMmono
TV sound. Alternatively, two carrier FM systems
according to the German or Korean terrestrial specs or
the satellite specs can be processed with the
MSP 3410D.
The MSP offers a powerful feature to calculate the carrier
field strength, which can be used for automatic standard
detection (terrestrial) and search algorithms (satellite).
Therefore, the IC facilitates a first step towards
multistandard capability. It may be used in TV-sets, as
well as in satellite tuners, and video recorders.
The MSP 3410D facilitates profitable multistandard capability,
offering the following advantages:
– two selectable analog inputs (TV and SAT-IF sources)
– Automatic Gain Control (AGC) for analog input: input
range: 0.10 – 3 Vpp
– integrated A/D converter for sound-IF inputs
– all demodulation and filtering is performed on chip and
is individually programmable
– easy realization of all digital NICAM standards (B/G,
I, L, and D/K)
– FM-demodulation of all terrestrial standards (incl.
identification decoding)
– FM-demodulation of all satellite standards
– no external filter hardware is required
– only one crystal clock (18.432 MHz) is necessary
– FM carrier level calculation for automatic search algorithms
and carrier mute function
– high deviation FM-mono mode (max. deviation:approx. ±360 kHz)


2.2. DSP-Section (Audio Baseband Processing)
– flexible selection of audio sources to be processed
– two digital input and one output interface via I2S-Bus
for external DSP-processors, featuring surround
sound, ADR etc.
– digital interface to process ADR (Astra Digital Radio)
together with DRP 3510A
– performance of all deemphasis systems including
adaptive Wegener Panda 1 without external components
or controlling
– digitally performed FM-identification decoding and dematrixing
– digital baseband processing: volume, bass, treble,
5-band equalizer, loudness, pseudostereo, and basewidth
enlargement
– simple controlling of volume, bass, treble, equalizer
etc.
2.3. Analog Section
– four selectable analog pairs of audio baseband inputs
(= four SCART inputs)
input level: 32 V RMS,
input impedance: .25 kW
– one selectable analog mono input (i.e. AM sound):
input level: 32 V RMS,
input impedance: .15 kW
– two high-quality A/D converters, S/N-Ratio: .85 dB
– 20 Hz to 20 kHz bandwidth for SCART-to-SCARTcopy
facilities
– MAIN (loudspeaker) and AUX (headphones): two
pairs of fourfold oversampled D/A-converters
output level per channel: max. 1.4 VRMS
output resistance: max. 5 kW
S/N-ratio: .85 dB at maximum volume
max. noise voltage in mute mode: 310 mV
(BW: 20 Hz ...16 kHz)
– two pairs of four-fold oversampled D/A converters
supplying two selectable pairs of SCART-outputs.
output level per channel: max. 2 V RMS,
output resistance: max. 0.5 kW,
S/N-Ratio: .85 dB (20 Hz...16 kHz)

3. Application Fields of the MSP 3410D
In the following sections, a brief overview about the two
main TV sound standards, NICAM 728 and German FMStereo,
demonstrates the complex requirements of a
multistandard audio IC.
3.1. NICAM plus FM/AM-Mono
According to the British, Scandinavian, Spanish, and
French TV-standards, high-quality stereo sound is
transmitted digitally. The systems allow two high-quality
digital sound channels to be added to the already existing
FM/AM-channel. The sound coding follows the format
of the so-called Near Instantaneous Companding
System (NICAM 728). Transmission is performed using
Differential Quadrature Phase Shift Keying (DQPSK).
Table 3–2 gives some specifications of the sound coding
(NICAM); Table 3–3 offers an overview of the modulation
parameters.
In the case of NICAM/FM (AM) mode, there are three different
audio channels available: NICAM A, NICAM B,
and FM/AM-mono. NICAM A and B may belong either to
a stereo or to a dual language transmission. Information
about operation mode and about the quality of the NICAM
signal can be read by the CCU via the control bus.
In the case of low quality (high bit error rate), the CCU
may decide to switch to the analog FM/AM-mono sound.
Alternatively, an automatic NICAM-FM/AM switching
may be applied.
3.2. German 2-Carrier System (DUAL FM System)
Since September 1981, stereo and dual sound programs
have been transmitted in Germany using the
2-carrier system. Sound transmission consists of the already
existing first sound carrier and a second sound
carrier additionally containing an identification signal.
More details of this standard are given in Tables 3–1 and
3–4. For D/K and M-Korea, very similar systems are used.

4.1.1. Analog Sound IF – Input Section
The input pins ANA_IN1+, ANA_IN2+, and ANA_IN– offer
the possibility to connect two different sound IF (SIF)
sources to the MSP 3410D. By means of bit [8] of
AD_CV (see Table 6–5), either terrestrial or satellite
sound IF signals can be selected. The analog-to-digital
conversion of the preselected sound IF signal is done by
an A/D-converter, whose output can be used to control
an analog automatic gain circuit (AGC), providing an optimal
level for a wide range of input levels. It is possible
to switch between automatic gain control and a fixed
(setable) input gain. In the optimal case, the input range
of the A/D converter is completely covered by the sound
IF source. Some combinations of SAW filters and sound
IF mixer ICs, however, show large picture components
on their outputs. In this case, filtering is recommended.
It was found, that the high pass filters formed by the coupling
capacitors at pins ANA_IN1+ and ANA_IN2+ (as
shown in the application diagram) are sufficient in most
cases.

Quadrature Mixers
The digital input coming from the integrated A/D converter
may contain audio information at a frequency range
of theoretically 0 to 9 MHz corresponding to the selected
standards. By means of two programmable quadrature
mixers, two different audio sources; for example, NICAM
and FM-mono, may be shifted into baseband position.
In the following, the two main channels are provided
to process either:
– NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2) simultaneously
or, alternatively,
– FM mono (channel 2)
– FM2 (MSP-Ch1) and FM1 (MSP-Ch2).
Two programmable registers, to be divided up into Low
and High Part, determine frequency of the oscillator,
which corresponds to the frequency of the desired audio
carrier.
4.1.3. Lowpass Filtering Block for Mixed Sound IF
Signals
Data shaping and/or FM bandwidth limitation is performed
by a linear phase Finite Impulse Response (FIRfilter).
Just like the oscillators’ frequency, the filter coefficients
are programmable and are written into the IC by
the CCU via the control bus. Thus, for example, different
NICAM versions can easily be implemented. Two not
necessarily different sets of coefficients are required,
one for MSP-Ch1 (NICAM or FM2) and one for MSPCh2
(FM1 = FM-mono). In a corresponding table several
coefficient sets are proposed.

4.1.4. Phase and AM Discrimination
The filtered sound IF signals are demodulated by means
of the phase and amplitude discriminator block. On the
output, the phase and amplitude is available for further
processing. AM signals are derived from the amplitude
information, whereas the phase information serves for
FM and NICAM (DQPSK) demodulation.
4.1.5. Differentiators
FM demodulation is completed by differentiating the
phase information output.
4.1.6. Lowpass Filter Block for Demodulated
Signals
The demodulated FM and AM signals are further lowpass
filtered and decimated to a final sampling frequency
of 32 kHz. The usable bandwidth of the final baseband
signals is about 15 kHz.
4.1.7. High Deviation FM Mode
By means of MODE_REG [9], the maximum FM-deviation
can be extended to approximately ±360 kHz. Since
this mode can be applied only for the MSP sound IF
channel 2, the corresponding matrices in the baseband
processing must be set to sound A. Apart from this, the
coefficient sets 380 kHz FIR2 or 500 kHz FIR2 must be
chosen for the FIR2. In relation to the normal FM-mode,
the audio level of the high-deviation mode is reduced by
6 dB. The FM-prescaler should be adjusted accordingly.
In high deviation FM-mode, neither FM-stereo nor FMidentification
nor NICAM processing is possible simultaneously.
4.1.8. FM Carrier-Mute Function in the Dual Carrier
FM Mode
To prevent noise effects or FM identification problems in
the absence of one of the two FM carriers, the
MSP 3410D offers a carrier detection feature, which
must be activated by means of AD_CV[9]. If no FM carrier
is available at the MSPD channel 1, the corresponding
channel FM2 is muted. If no FM carrier is available
at the MSPD channel 2, the corresponding channel FM1
is muted.
4.1.9. DQPSK-Decoder
In case of NICAM-mode, the phase samples are decoded
according the DQPSK-coding scheme. The output
of this block contains the original NICAM-bitstream.
4.1.10. NICAM-Decoder
Before any NICAM decoding can start, the MSP must
lock to the NICAM frame structure by searching and synchronizing
to the so-called Frame Alignment Words
(FAW).
To reconstruct the original digital sound samples, the NICAM-
bitstream has to be descrambled, deinterleaved,
and rescaled. Also, bit error detection and correction
(concealment) is performed in this NICAM specific
block.
To facilitate the Central Control Unit CCU to switch the
TV-set to the actual sound mode, control information on
the NICAM mode and bit error rate are supplied by the
the NICAM-Decoder. It can be read out via the I2C-Bus.

4.2.1. SCART Switching Facilities
The analog input and output sections include full matrix
switching facilities, which are shown in Fig. 4–3.To design
a TV set with 4 pairs of SCART-inputs and two pairs
of SCART-outputs, no external switching hardware is required.
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 7. Programming
the DSP Section).

4.3. DSP Section (Audio Baseband Processing)
All audio baseband functions are performed by digital
signal processing (DSP). The DSP functions are
grouped into three processing parts: input preprocessing,
channel source selection, and channel postprocessing
(see Fig. 4–5 and section 7.).
The input preprocessing is intended to prepare the various
signals of all input sources in order to form a standardized
signal at the input to the channel selector. The
signals can be adjusted in volume, are processed with
the appropriate deemphasis, and are dematrixed if necessary.
Having prepared the signals that way, the channel selector
makes it possible to distribute all possible source signals
to the desired output channels.
The ability to route in an external coprocessor for special
effects, like surround processing and sound field processing,
is of special importance. Routing can be done
with each input source and output channel via the I2S inputs
and outputs.
All input and output signals can be processed simultaneously
with the exception that FM2 cannot be processed
at the same time as NICAM. FM-identification
and adaptive deemphasis are also not possible simultaneously.
Note that the NICAM input signals are only
available in the MSP 3410B and MSP 3410D versions.
4.3.1. Dual Carrier FM Stereo/Bilingual Detection
For the terrestrial dual FM carrier systems, audio information
can be transmitted in three modes: Mono, stereo,
or bilingual. To obtain information about the current
audio operation mode, the MSP 3410D detects the socalled
identification signal. Information is supplied via
the Stereo Detection Register to an external CCU.