MIVAR 14BN2L CHASSIS TV2650/1 INTERNAL VIEW.

This chassis MIVAR TV2650/1 is an example of integration development for a B/w set of all needed stages in one monocarrier chassis type.

This chassis was even used from 9 to 14 inches screen formats types and models.

The tuning control box MIVAR GC4 is based around a SGS combination chipset, and discretes :

M293B MADE BY:

SGS is Società Generale Semiconduttori - Aquila Tubi E Semiconduttori (SGS-ATES, "Semiconductor General Society - Tubes and Semiconductors Aquila"), later SGS Microelettronica, a former Italian company now merged into STMicroelectronics
SGS Microelettronica and Thomson Semiconducteurs were both long-established semiconductor companies. SGS Microelettronica originated in 1972 from a previous merger of two companies:

• ATES (Aquila Tubi e Semiconduttori), a vacuum tube and semiconductor maker headquartered in the Abruzzese city of l'Aquila, who in 1961 changed its name into Azienda Tecnica ed Elettronica del Sud and relocated its manufacturing plant in the outskirts of the Sicilian city of Catania
• Società Generale Semiconduttori (founded in 1957 by Adriano Olivetti).

MIVAR 14BN2L  CHASSIS  TV2650/1CIRCUITS DESCRIPTIONS:
TDA2270 (SGS) TV VERTICAL DEFLECTION OUTPUT CIRCUIT:


DESCRIPTION

The TDA2270 is a high efficiency monolithic output
stage for vertical deflection circuits in TVs and
monitors. Driving the vertical windings directly, the
device contains a power amplifier, flyback generator,
voltage reference and thermal protection circuit.
The TDA2270 is supplied in a 16-pin DIP with the
four center pins connected together and used for
heatsinking.


DRIVES VERTICAL DEFLECTION WINDINGS DIRECTLY
.HIGH EFFICIENCY
.INTERNAL FLYBACK GENERATOR
.THERMAL PROTECTION
.ON-CHIP VOLTAGE REFERENCE
.HIGH OUTPUT CURRENT (2.2 A peak)
.16-LEADPOWERDIP PLASTIC PACKAGE


TDA3190 TV SOUND CHANNEL (sgs)

The TDA3190 is a monolithic integrated circuit in a
16-lead dual in-line plastic package. It performs all
the functions needed for the TV sound channel :

.IF LIMITER AMPLIFIER .ACTIVE LOW-PASS FILTER
.FM DETECTOR
.DC VOLUMECONTROL
.AF PREAMPLIFIER .AF OUTPUT STAGE

DESCRIPTION
The TDA3190 can give an output power of 4.2 W
(d = 10 %) into a 16 W load at VS = 24 V, or 1.5 W
(d = 10 %) into an 8 W load at VS = 12 V. This
performance, togetherwith the FM-IF section characteristics
of high sensitivity, highAM rejection and
low distortion, enables the device to be used in
almost every type of television receivers.
The device has no irradiation problems, hence no
external screening is needed.
The TDA3190 is a pin to pin replacement of
TDA1190Z.

The electrical characteristics of the TDA3190 remain
almost constant over the frequencyrange 4.5
to 6 MHz, therefore it can be used in all television
standards (FM mod.). The TDA3190 has a high
input impedance,so it can work with a ceramic filter
or with a tuned circuit that provide the necessary
input selectivity.
The value of the resistors connected to pin 9,
determine the AC gain of the audio frequency amplifier.
This enables the desired gain to be selected
in relation to the frequency deviation at which the
output stage of the AF amplifier, must enter into
clipping.
Capacitor C8, connected between pins 10 and 11,
determines the upper cutoff frequency of the audio
bandwidth.To increase the bandwidth
the values of C8 and C7 must be reduced, keeping the ratio
C7/C8 as shown in the table of fig. 16.
The capacitor connected between pin 16 and
ground, together with the internal resistor of 10 KW
forms the de-emphasis network. The Boucherot
cell eliminates the high frequency oscillations
caused by the inductiveload and thewires connecting
the loudspeaker.


MIVAR 14BN2L  CHASSIS  TV2650/1 MOTOROLA MC13009XP MONOMAX BLACK AND WHITE TV SUBSYSTEM:


The MONOMAX is a single chip IC that will perform the electronic
functions of a monochrome TV receiver, with the exception of the tuner,
sound channel, and power output stages. The MC13001XP and
MC13009XP will function as a drop–in replacement for the MC13001P and
MC13009P, but some external IF components can be removed for maximum
benefit. IF AGC range has been increased, video output impedance lowered,
and horizontal driver output current capability increased.
• Full Performance Monochrome Receiver with Noise and Video
Processing (Black Level Clamp, DC Contrast, Beam Limiter)
• Video IF Detection On–Chip (No Coils, No Pins, except Inputs)
• Noise Filtering On–Chip (Minimum Pins and Externals)
• Oscillator Components On–Chip (No Precision Capacitors Required)
• MC13001XP for 525 Line NTSC and MC13009XP for 625 Line CCIR
• Low Dissipation in All Circuit Sections
• High Performance Vertical Countdown
• 2–Loop Horizontal System with Low Power Startup Mode
• Noise Protected Sync and Gated AGC System
• Designed to work with TDA1190P or TDA3190P Sound IF and Audio
Output Devices.


MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

Power Supply Voltage – Pin 18 VCC +16 Vdc
Power Dissipation PD 1.0 W
Horizontal Driver Current – Pin 17 Ihor –20 mA
RF AGC Current – Pin 11 IRFAGC 20 mA
Video Detector Current – Pin 24 IVID 5.0 mA
Vertical Driver Current – Pin 22 Ivert 5.0 mA
Auxiliary Regulator Current – Pin 19 Ireg 35 mA
Thermal Resistance Junction–to–Case RqJC 60 °C/W
Maximum Junction Temperature TJ 150 °C
Storage Temperature Range Tstg –65 to + 150 °C
Operating Temperature Range TA 0° to + 70 °C




GENERAL DESCRIPTION
The Video IF Amplifier is a four–stage design with 80 mV,
sensitivity. It uses a 6.2 V supply decoupled at Pin 4. The first
two stages are gain controlled, and to ensure optimum noise
performance, the first stage control is delayed until the
second stage has been gain reduced by 15 dB. To bias the
amplifier, balanced dc feedback is used which is decoupled
at Pins 2 and 6 and then fed to the input Pins 3 and 5 by
internal 3.9 k resistors. The nominal bias voltage at these
input pins is approximately 4.2 Vdc. The input, because of the
high IF gain, should be driven from a balanced differential
source. For the same reason, care must be taken with the IF
decoupling.
The IF output is rectified in a full wave envelope detector
and detector nonlinearity is compensated by using a similar
nonlinear element in a feedback output buffer amplifier. The
detected 1.9 Vpp video at Pin 28 contains the sound
intercarrier signal, and Pin 28 is normally used as the sound
takeoff point. The video frequency response, detector to Pin
28, is shown in Figure 3 and the detector intermodulation
performance can be seen by reference to Figure 4. Typical
Pin 28 video waveforms and voltage levels are shown in
Figure 5.
The video processing section of Monomax contains a
contrast control, black level clamp, a beam current limiter and
composite blanking. The video signal first passes through the
contrast control. This has a range of 14:1 for a 0 V to 5.0 V
change of voltage on Pin 26, which corresponds to a change
of video amplitude at Pin 24 of 1.4 V to 0.1 V (black to white
level). The beam current limiter operates on the contrast
control, reducing the video signal when the beam current
exceeds the limit set by external components. As the beam
current increases, the voltage at Pin 27 moves negatively
from its normal value of 1.5 V, and at 1.0 V operates the
contrast control, thus initiating beam limiting action. After the
contrast control, the video is passed through a buffer amplifier
and dc is restored by the black level clamp circuit before
being fed to Pin 24 where it is blanked. The black level clamp,
which is gated “on” during the second half of the flyback,
maintains the video black level at 2.4 V ± 0.1 V under all
conditions, including changes in contrast, temperature and
power supply. The loop integrating capacitor is at Pin 25 and
is normally at a voltage of 3.3 V. The frequency response of
the video at Pin 24 is shown in Figure 3 and it is blanked to
within 0.5 V of ground.

The AGC loop is a gated system, and for all normal
variations of the IF input signal, maintains the sync tip of a
noise filtered video signal at a reference voltage (5.1 V
Pin 28). The strobe for the AGC error amplifier is formed by
gating together the flyback pulse with the separated sync
pulse. Integration of the error signal is performed by the
capacitor at Pin 8, which forms the dominant AGC time
constant. Improved noise performance is obtained by the use
of a gated AGC system, noise protected by a dc coupled
noise canceling circuit. The false AGC lock conditions, which
can result from this combination, are prevented by an
anti–lockout circuit connected to the sync separator at Pin 7.
AGC lockout conditions, which occur due to large rapid
changes of signal level are detected at Pin 7 and recovery is
ensured under these conditions by changing the AGC into a
mean level system. The voltage at Pin 10 sets the point at
which tuner AGC takeover occurs and positive going tuner
control, suitable for an NPN RF transistor, is available at
Pin 11. The maximum output is 5.5 V at 5.0 mA. A
feed–forward output is provided at Pin 9. This enables the
AGC control voltage to be ac coupled into the tuner takeover
control at Pin 10. The coupling allows additional IF gain
reduction during signal transient conditions, thus
compensating for variations of AGC loop gain at the tuner
AGC takeover point. In this way the AGC system stability and
response are not degraded.
The previously mentioned noise protection is effected by
detecting negative–going noise spikes at the video detector
output. A dc coupled detector is used which turns on when a
noise spike exceeds the video sync tip by 1.4 V. This pulse is
then stretched and used to cancel the noise present on the
delayed video at the input to the sync separator. Cancellation
is performed by blanking the video to ground. Complete
cancellation of the noise spike results from the stretching of
the blanking pulse and the delay of the noise spike at the
input to the sync separator. Protection of both the horizontal
PLL and the AGC stems from the fact that both circuits use
the noise cancelled sync for gating.



The composite sync is stripped from a delayed and filtered
video in a peak detecting type of sync separator. The
components connected to Pin 7 determine the slice and tilt
levels of the sync separator. For ideal horizontal sync
separation and to ensure correct operating of AGC anti–
lockup circuit, a relatively short time constant is required at
Pin 7. This time constant is less than optimum for good noise
free vertical separation, giving rise to a vertical slice level
near sync tip. An additional longer time–constant is therefore
coupled to the first via a diode. With the correct choice of time
constants, the diode is non–conducting during the horizontal
sync period, but conducts during the longer vertical period.
This connects the longer time constant to the sync separator
for the vertical period and stops the slice level from moving up
the sync tip. The separated composite sync is integrated
internally, and the time constant is such that only the longer
period vertical pulses produce a significant output pulse. The
output is then fed to the vertical sync separator, which further
processes the vertical pulse and provides increased noise
protection. The selection of the external components
connected to the vertical separator at Pin 23 permits a wide
range of performance options. A simple resistor divider from
the 8.2 V regulated supply gives adequate performance for
most conditions. The addition of an RC network will make the
slice level adapt to varying sync amplitude and give improved
weak signal performance. A resistor to the AGC voltage on
Pin 9 enables the sync slice level to be changed as a function
of signal level. This further improves the low signal level
separation while at the same time giving increased impulse
noise protection on strong signals.



Horizontal Oscillator
The horizontal PLL (see Figure 7) is a two–loop system
using a 31.5 kHz oscillator which after a divider stage is
locked to the sync pulse using Phase Detector 1. The control
signal derived from this phase detector on Pin 13 is fed via a
high–value resistor to the frequency–control point on Pin 12.
The same divided oscillator frequency is also fed to Phase
Detector 2, where the flyback pulse is compared with it and
the resulting error used to change a variable slice level on the
oscillator ramp waveform. This therefore changes the timing
of the output square wave from the slicer and hence the
timing of the buffered horizontal output on Pin 17 (see
Figure 8). The error on Phase Detector 2 is reduced until the
phasing of the flyback pulse is correct with respect to the
divided oscillator waveform, and hence with respect to the
sync pulse.



To improve the pull–in and noise characteristics of the first
PLL, the phase detector current is increased when the
vertical lock indicator signals an unlocked condition and is
decreased when locked. This increases the loop bandwidth
and pull–in range when out of lock, and decreases the loop
bandwidth when in lock, thus improving the noise
performance. In addition, the phase detector current during
the vertical period is reduced in order to minimize the
disturbance to the horizontal caused by the longer period
vertical phase detector pulses.




The oscillator itself is a novel design using an on–chip
50 pF silicon nitride capacitor which has a temperature drift
of only 70 ppm/°C and negligible long term drift. This, in
conjunction with an external resistor, gives a drift of horizontal
frequency of less than 1.0 Hz/°C – i.e., less than 100 Hz over
the full operating temperature range of the chip. The pull–in
range of the PLL is about ±750 Hz, so normally this would
eliminate the need for any customer adjustment of the
frequency.
The second significant feature of this design is the use of a
virtual ground at the frequency control point which floats at a
potential derived from a divider across the power supply and
this is the same divider which determines the end–points of
the oscillator ramp. The frequency adjustment which is
necessary to take up tolerances in the on–chip capacitor is
fed in as a current to this virtual ground, and when this
adjustment current is derived from an external potentiometer
across the same supply there is no frequency variation with
supply voltage. Moreover, using the voltage from a
potentiometer for the adjustment instead of the simple
variable resistor normally used in RC oscillators makes the
frequency independent of the value of the potentiometer and
hence its temperature coefficient. The frequency control
current from the first phase detector is fed into this same
virtual ground, and as the sensitivity of the control is about
230 Hz/mA, a high value resistor can be used (680 kW) which
can be directly connected to the phase detector filter without
significant loading.
This oscillator operates with almost constant frequency
to below 4.0 V and as the total PLL system consumes
less than 4.0 mA at this voltage, this gives an ideal
startup characteristic for receivers using deflection–derived
power supplies.
The flyback gating input is on Pin 15 which is internally
clamped to 0.7 V in both directions and requires a negative
input current of 0.6 mA to operate the gate circuit. This input
can be a raw flyback pulse simply fed via a suitable resistor.
Vertical System
An output switching signal is taken from the 31.5 kHz
oscillator to clock the vertical counter which is used in place
of a conventional vertical oscillator circuit. The counter is
reset by the vertical sync pulse, but the period during which it
is permitted to reset is controlled by the window control.
Normally, when the counter is running synchronously, the
window is narrow to give some protection against spurious
noise pulses in the sync signal. If the counter output is not
coincident with sync however, after a short period the window
opens to five reset over a much wider count range, leading to
a fast picture roll towards lock. At weak signal, i.e., less than
200 mV IF input, the vertical system is forced to narrow mode
to give a steadier picture for commonly occurring types of
noise. The vertical sync, gated by the counter, then resets a
ramp generator on Pin 20 and the 1.5 Vpp ramp is
buffered to Pin 22 by the vertical preamplifier. A differential
input to the preamp on Pin 21 compares the signal generated
across the resistor in series with the deflection coils with the
generated ramp and thus controls shape and amplitude of
the coil current.
The basic block diagram of the countdown system is
shown in Figure 9. The 31.5 kHz (2FH) clock from the
horizontal oscillator drives a 10–stage counter circuit which is
normally reset by the vertical sync pulse via the sync gate,
‘‘OR’’ gate and D flip–flop. This D input is also used to initiate
discharge of the ramp capacitor and hence causes picture
flyback.

The period during which sync can reset the counter and
cause flyback is determined by the window control which
defines a count range during which the gate is open. One of
two ranges is selected according to the condition of the
signal. The normal “narrow” range is 514 to 526 counts for a
525 line system and is selected after the coincidence
detector indicates that the reset is coincident, twice in
succession, with the 525 count from the counter. When the
detector indicates non–coincidence 8 times in succession,
then the window control switches to the “wide” mode (384 to
544 counts) to achieve rapid re–synchronization. For the 625
line version the counts are 614 to 626 for narrow mode and
484 to 644 for wide mode. Note that the OR gate after the
sync gate is used to terminate the count at the end of the
respective window if a sync pulse has not appeared.
This method accepts nonstandard signals almost in the
same way as a conventional triggered RC oscillator and has
a similar fast lock–in time. However, the use of a window
control on the counter reset ensures that when locked with a
normal standard broadcast signal the counter will reject most
spurious noise pulse.
The blanking output is provided from a latch which is set by
the counter reset pulse and terminated by count 20 from the
counter chain.



Power Supply
The power supply regulator, although of simple design,
provides two independent power supplies – one for the
horizontal PLL section and the other for the remainder of the
chip. The supplies share the same reference voltage but
the design of the main regulator is such that it can be
switched on independently to give minimum loading on the
“bleed” voltage source during startup phase of a
defection–derived supply system.


Power supply is realized with mains transformer and Linear transistorized power supply stabilizer, A DC power supply apparatus includes a rectifier circuit which rectifies an input commercial AC voltage. The rectifier output voltage is smoothed in a smoothing capacitor. Voltage stabilization is provided in the stabilizing circuits by the use of Zener diode circuits to provide biasing to control the collector-emitter paths of respective transistors.A linear regulator circuit according to an embodiment of the present invention has an input node receiving an unregulated voltage and an output node providing a regulated voltage. The linear regulator circuit includes a voltage regulator, a bias circuit, and a current control device.


Power Supply: The examples chosen are taken from manufacturers' circuit diagrams and are usually simplified to emphasise the fundamental nature of the circuit. For each example the particular transistor properties that are exploited to achieve the desired performance are made clear. As a rough and ready classification the circuits are arranged in order of frequency: this part is devoted to circuits used at zero frequency, field frequency and audio frequencies. Series Regulator Circuit Portable television receivers are designed to operate from batteries (usually 12V car batteries) and from the a.c. mains. The receiver usually has an 11V supply line, and circuitry is required to ensure that the supply line is at this voltage whether the power source is a battery or the mains. The supply line also needs to have good regulation, i.e. a low output resistance, to ensure that the voltage remains constant in spite of variations in the mean current taken by some of the stages in the receiver. Fig. 1 shows a typical circuit of the power -supply arrangements. The mains transformer and bridge rectifier are designed to deliver about 16V. The battery can be assumed to give just over 12V. Both feed the regulator circuit Trl, Tr2, Tr3, which gives an 11V output and can be regarded as a three -stage direct -coupled amplifier. The first stage Tr 1 is required to give an output current proportional to the difference between two voltages, one being a constant voltage derived from the voltage reference diode D I (which is biased via R3 from the stabilised supply). The second voltage is obtained from a preset potential divider connected across the output of the unit, and is therefore a sample of the output voltage. In effect therefore Tr 1 compares the output voltage of the unit with a fixed voltage and gives an output current proportional to the difference between them. Clearly a field-effect transistor could do this, but the low input resistance of a bipolar transistor is no disadvantage and it can give a current output many times that of a field-effect transistor and is generally preferred therefore. The output current of the first stage is amplified by the two subsequent stages and then becomes the output current of the unit. Clearly therefore Tr2 and Tr3 should be current amplifiers and they normally take the form of emitter followers or common emitter stages (which have the same current gain). By adjusting the preset control we can alter the fraction of the output voltage' applied to the first stage and can thus set the output voltage of the unit at any desired value within a certain range. By making assumptions about the current gain of the transistors we can calculate the degree of regulation obtainable. For example, suppose the gain of Tr2 and Tr3 in cascade is 1,000, and that the current output demanded from the unit changes by 0.1A (for example due to the disconnection of part of the load). The corresponding change in Tr l's collector current is 0.1mA and, if the standing collector current of Tr 1 is 1mA, then its mutual conductance is approximately 4OmA/V and the base voltage must change by 2.5mV to bring about the required change in collector current. If the preset potential divider feeds one half of the output voltage to Tr l's base, then the change in output voltage must be 5mV. Thus an 0.1A change in output current brings about only 5mV change in output voltage: this represents an output resistance of only 0.0552.

In one embodiment, the current control device is implemented as an NPN bipolar junction transistor (BJT) having a collector electrode forming the input node of the linear regulator circuit, an emitter electrode coupled to the input of the voltage regulator, and a base electrode coupled to the second terminal of the bias circuit. A first capacitor may be coupled between the input and reference terminals of the voltage regulator and a second capacitor may be coupled between the output and reference terminals of the voltage regulator. The voltage regulator may be implemented as known to those skilled in the art, such as an LDO or non-LDO 3-terminal regulator or the like.
The bias circuit may include a bias device and a current source. The bias device has a first terminal coupled to the output terminal of the voltage regulator and a second terminal coupled to the control electrode of the current control device. The current source has an input coupled to the first current electrode of the current control device and an output coupled to the second terminal of the bias device. A capacitor may be coupled between the first and second terminals of the bias device.
In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
A circuit is disclosed for improving operation of a linear regulator, having an input terminal, an output terminal, and a reference terminal. The circuit includes an input node, a transistor, a bias circuit, and first and second capacitors. The transistor has a first current electrode coupled to the input node, a second current electrode for coupling to the input terminal of the linear regulator, and a control electrode. The bias circuit has a first terminal for coupling to the output terminal of the linear regulator and a second terminal coupled to the control electrode of the transistor. The first capacitor is for coupling between the input and reference terminals of the linear regulator, and the second capacitor is for coupling between the output and reference terminals of the linear regulator. The bias circuit develops a voltage sufficient to drive the control terminal of the transistor and to operate the linear regulator. The bias circuit may be a battery, a bias device and a current source, a floating power supply, a charge pump, or any combination thereof. The transistor may be implemented as a BJT or FET or any other suitable current controlled device.