Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.


Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....
Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !
-----------------------

©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of
Engineer Frank Sharp. NOTHING HERE IS FOR SALE !

Thursday, December 8, 2011

PHILIPS 28DC2271/02R CHASSIS D16-MAC (D2MAC SATELLITE) (DIGI16-MAC) UNITS VIEW.






































- DIGITAL VIDEO PROCESSING UNIT 3104318 15750 DIGIVISION ITT DIGIT2000 BASED

- PIP UNIT 3122 128 08450 with SAA9068WP + SAA9069 +
TDA4555+TDA2579+PNA7509+TEA5114


- MAIN CONTROL UNIT with P80C31 Microprocessor + MK6116N RAM + 27C010 FIRMWARE EPROM


D2MAC SATELLITE RECEIVER BOARD:3122 128 68330


TDA4554 /5 / 6 Multistandard decoder.GENERAL DESCRIPTION
The TDA4555 / 4 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch



PHILIPS  28DC2271/02R  CHASSIS D16-MAC (D2MAC SATELLITE)  (DIGI16-MAC) Digital Signal Processing Overview / Description:

The entire video signal processing function for PAL and
SECAM, the videotext decoder and the deflection signal
generator, are located together on one board the CHASSIS C9000

This contains the VCU 2133 as an analog-digital converter for
the video signals, the PVPU 2203 and SPU 2220 for PAL and
SECAM signal processing respectively, the DTI 2222 for
improved reproduction of colour transitions, the TPU 2732 with
page buffer IC 645 for videotext decoding, the deflection
processor DPU 2543 and clock pulse generator MCU 2600 for
generating the working clock pulse for all processors.


After conversion of the FBAS (composite colour) signal selected
into digital form (7-bit gray code), this is passed from output
Pins 2-8 ofthe VCU to SPU 2220, IC 630, to TPU 2732, IC 640
and to DPU 2540.
The further path of the video signal leads first to the SECAM
processor SPU 2220. Here the signal standard is identified and
appropriately switched. In the case of a PAL signal, the input
information is passed unaltered to the video output (Pins 14-20),
and thus on to the input of PVPU 2203, Pins 5-11.
For further processing of the PAL signal, it is first split inside the
IC into luminance and chroma components. The conditioned
luminance signal, extended by 1 bit, appears on the output side
at Pins 32-39, and passes from here to DTI 2222, Pins 6-13.
The chroma signal component is demodulated, decoded and
converted into the colour difference signals in PVPU 2203;
these signals are then also passed (in multiplex mode, together
with picture tube beam current measured data), via output Pins
27-30 to DTI 2222, Pins 17-20.
At this point, the SECAM chroma signal path from SPU 2220,
output Pins 23-26, rejoins the main path. If the input signal is
identified as a SECAM signal in the SPU, the SECAM decoder
is activated, and the decoded signal appears at the output in the
same form as with the PAL processor.
In this case, the luminance signal component is passed through
an integrated delay circuit of 3.7 us, in order to compensate for
the corresponding travel time in the SECAM colour decoder,
and is then fed on the same path as the PAL signal (Pins 14-20,
SPU 2220, PVPU 2203) to DTI 2222, Pins 6-13. All adjustment
functions required for the signals, such as contrast, brightness,
colour intensity, etc. are of course controlled inside the IC via
the IM Bus.
Integrated circuit DTI 2222 serves solely to improve
reproduction of colour transitions on the screen. Since (owing to
the smaller transmission bandwidth with chroma) the signal
leading edges are very flat compared with Y-signals, a clear
improvement in the quality of colour reproduction can be
achieved by electronically increasing the steepness of the
edges. Since the signal manipulation involved increases travel
times in the chroma channel, this must be compensated by a
corresponding delay in the luminance channel. This function is
contained in DTI 2222, so that there are no differences in travel
time at the outputs of this circuit (Pins 27-34 for Y and Pins 22-25 for chroma).


VCU 2133 A (ITT VCU2133 A) (Video Codec Decodec Unit)
DPU 2543 (ITT DPU2543) (Digital Deflection Processor Unit)
PVPU 2203 (ITT PVPU2203) (PAL and Video Processor Unit)
DTI 2222 (ITT DTI2222) (Digital Transient Improvement [Chroma])
TPU 2732 (ITT TPU2732) (Teletext Processor Unit)
MCU 2600 (ITT MCU2600) (Main Clock Unit)



















































































































VCU 2133 Video Codec UNIT


High-speed coder/decoder IC for analog-to-digital and di-
gital-to-analog conversion of the video signal in digital TV
receivers based on the DIGIT 2000 concept. The VCU 2133
is a VLSI circuit in Cl technology, housed in a 40-pin Dil
plastic package. One single silicon chip combines the fol-
lowing functions and circuit details (Fig. 1):
- two input video amplifiers
- one A/D converter for the composite video signal
- the noise inverter
- one D/A converter for the luminance signal
- two D/A converters for the color difference signals
- one RGB matrix for converting the color difference sig-
nals and the luminance signal into RGB signals
- three RGB output amplifiers
- programmable auxiliary circuits for blanking, brightness
adjustment and picture tube alignment
- additional clamped RGB inputs for text and other analog
RGB signals
- programmable beam current limiting
1. Functional Description
The VCU 2133 Video Codec is intended for converting the
analog composite video signal from the video demodulator
into a digital signal. The latter is further processed


digitally
in the VPU 2203 Video Processor and in the DPU 2553 De-
flection Processor. After processing in the VPU 2203 (color
demodulation, PAL compensation, etc.), the VPU‘s digital
output signals (luminance and color difference) are recon-
verted into analog signals in the VCU 2133. From these an-
alog signals are derived the RGB signals by means of the
RGB matrix, and, after amplification in the integrated RGB
amplifiers, the RGB signals drive the RGB output amplifiers
of the color T\/ set.
For TV receivers using the NTSC standard the VPU 2203
may be replaced by the CVPU 2233 Comb Filter Video Pro-
cessor which is pin-compatible with the VPU 2203, but of-
fers better video performance. In the case of SECAM, the
SPU 2220 SECAM Chroma Processor must be connected
in parallel to the VPU 2203 for chroma processing, while
the luma processing remains inthe VPU 2203.
In a more sophisticated CTV receiver according to the Dl-
GIT 2000 concept, after the VPU Video Processor may be
placed the DTI 2223 Digital Transient Improvement Proces-
sor which serves for sharpening color transients on the
screen. The output signals of the DTI are fed to the VCU’s
luma and chroma inputs. To achieve the desired transient
improvement, the R-Y and B-Y D/A converters of the VCU
must be stopped for a certain time which is done by the
hold pulse supplied by the DTI and fed to the Reset pin 23
of the VCU. The pulse detector following this pin seperates
the (capacitively-coupled) hold pulse from the reset signal.
In addition, the VCU 2133 carries out the functions:
- brightness adjustment
- automatic CRT spot-cutoff control (black level)
- white balance control and beam current limiting
Further, the VCU 2133 offers direct inputs for text or other
analog RGB signals including adjustment of brightness and
contrast for these signals.
The RGB matrix and RGB amplifier circuits integrated in
the VCU 2133 are analog. The CRT spot-cutoff control is
carried out via the RGB amplifiers’ bias, and the white bal-
ance control is accomplished by varying the gain of these
amplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHz
clock signal supplied by the MCU 2632 Clock Generator IC.
1.1. The A/D Converter with Input Amplifiers and Bit
Enlargement
The video signal is input to the VCU 2133 via pins 35 and 37
which are intended for normal TV video signal (pin 35) and
for VCR or SCART video signal (pin 37) respectively. The
video amplifier whose action is required, is activated by the
CCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-
ware. The amplification of both video amplifiers is doubled
during the undelayed horizontal blanking pulse (at pin 36)
in order to obtain a higher digital resolution of the color
synchronization signal (burst). At D 2-MAC reception, the
doubled gain is switched off by means of bit p = 1 (Fig. 8).

The A/D converter is of the flash type, a circuit of 2" com-
parators connected in parallel. This means that the number
of comparators must be doubled if one additional bit is
needed. Thus it is important to have as few bits as possi-
ble. For a slowly varying video signal, 8 bits are required.

ln
order to achieve an 8-bit picture resolution using a 7-bit
converter, a trick is used: during every other line the refer-
ence voltage of the A/D converter is changed by an
amount corresponding to one half of the least significant
bit. ln this procedure, a grey value located between two 7-
bit steps is converted to the next lower value during one
line and to the next higher value during the next line. The
two grey values on the screen are averaged by the viewer’s
eye, thus producing the impression of grey values with
8-bit resolution. Synchronously to the changing reference
voltage of the A/D converter, to the output signal of the Y
D/A converter is added a half-bit step every second line.
The bit enlargement just described must be switched off in
the case of using the D2-MAC standard (q = 1 and r = 1
in Fig. 8). ln the case of using the comb filter CVPU instead
of the VPU, the half-bit adding in the Y D/A converter must
be switched off (r = 1 in Fig. 8).
The A/D converter’s sampling frequency is 17.7 MHZ for
PAL and 14.3 MHz for NTSC, the clock being supplied by
the MCU 2632 Clock Generator IC which is common to all
circuits for the digital T\/ system. The converter’s resolu-
tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded to
eliminate spikes and glitches resulting from different com-
parator speeds or from the coder itself. The output is fed to
the VPU 2203 and to the DPU 2553 in parallel form.
1.2. The Noise Inverter
The digitized composite video signal passes the noise in-
verter circuit before it is put out to the VPU 2203 and to the
DPU 2553. The noise inverter serves for suppressing bright
spots on the screen which can be generated by noise
VCU 2133
pulses, p. ex. produced by ignition sparks of cars etc. The
function of the noise inverter can be seen in Fig. 2. The
maximum white level corresponds with step 126 of the A/D
converter’s output signal (that means a voltage of 7 V at
pin 35). lf, due to an unwanted pulse on the composite
video signal, the voltage reaches 7.5 V (what means step
127 in digital) or more, the signal level is reduced by such
an amount, that a medium grey is obtained on the screen
(about 40 lFiE). The noise inverter circuit can be switched
off by software (address 16 in the VPU 2203, see there).
1.3. The Luminance D/A Converter (Y)
After having been processed in the VPU 2203 (color de-
modulation, PAL compensation, etc.), the different parts of
the digitized video signal are fed back to the VCU 2133 for
further processing to drive the RGB output amplifiers. The
luminance signal (Y) is routed from the VPU’s contrast mul-
tiplier to the Y D/A converter in the VCU 2133 in the form of
a parallel 8-bit signal with a resolution of 1/2 LSB of 9

bits.
This bit range provides a sufficient signal range for contrast
as well as positive and negative overshoot caused by the
peaking filter (see Fig. 3 and Data Sheet VPU 2203).


The luminance D/A converter is designed as an R-2R lad-
der network. lt is clocked with the 17.7 or the 14.3 MHz
clock signal applied to pin 22. The cutoff frequency of the
luminance signal is determined by the clock frequency.
1.4. The D/A Converters for the Color Difference Signals
R-Y and B-Y
ln order to save output pins at the VPU 2203 and input pins
at the VCU 2133 as well as connection lines, the two digital
color difference signals R-Y and B-Y are transferred in time
multiplex operation. This is possible because these signals’
bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3
MHz signal.
The two 8-bit D/A converters R-Y and B-Y are also built as
R-2R ladder networks. They are clocked with ‘A clock fre-
quency, but the clock for the multiplex data transfer is 17.7
or 14.3 MHz. Four times 4 bits are transferred sequentially,
giving a total of 16 bits. A sync signal coordinates the
multi-
plex operations in both the VCU 2133 and the VPU 2203.
Thus, only four lines are needed for 16 bits. Fig. 4 shows
the timing diagram of the data transfer described.
ln a CTV receiver with digital transient improvement (DTI
2223), the R-Y and B-Y D/A converters are stopped by the
hold pulse supplied by the DTI, and their output signal is
kept constant for the duration of the hold pulse. Thereafter,
the output signal jumps to the new value, as described in
the DTl’s data sheet.
Fig. 4:
Timing diagram of the multiplex data transfer of the chroma
channel between VPU 2203, VCU 2133 and SPU 2220
a) main clock signal QSM
b) valid data out of the VCU 2133’s video A/D converter.
AIAD is the delay time of this converter, about 40 ns.
c) valid data out of the VPU 2203.
d) MUX data transfer of the chroma signals from VPU 2203
to VCU 2133, upper line: sync pulse from pin 27 VPU to
pin 21 VCU during sync time in vertical blanking time,
see Fig. 8; lower line: valid data from pins 27 to 30
(VPU) to pins 18 to 21 (VCU)
1.5. The RGB Matrix and the RGB Output Amplifiers
ln the RGB matrix, the signals Y, R-Y and B-Y are dema-
trixed, the reduction coefficients of 0.88 and 0.49 being tak-
en into account. In addition, the matrix is supplied with a
signal produced by an 8-bit D/A converter for setting the
brightness of the picture. The brightness adjustment range
corresponds to 1/2 of the luminance signal range (see Fig.
3). It can be covered in 255 steps. The brightness is set by
commands fed from the CCU 2030, CCU 2050 or CCU 2070
Central Control Unit to the VPU 2203 via the IM bus.
There are available four different matrices: standard PAL,
matrix 2, 3 and 4, the latter for foreign markets. 'The re-
quired matrix must be mask-programmed during produc-
tion. The matrices are shown in Table 1, based on the for-
mulas:
R = r1~(R-Y)+ l'2~(B-Y) +Y
G = Q1-(Ft-Y)+ Q2 - (B-Y) +Y
B = b1-(Ft-Y)+ bg - (B-Y) +Y
The three RGB output amplifiers are impedance converters
having a low output impedance, an output voltage swing of
6 V (p-p), thereof 3 V for the video part and 3 V for bright-
ness and dark signal. The output current is 4 mA. Fig. 5
shows the recommended video output stage configuration.

For the purpose of white-balance control, the amplification
factor of each output amplifier can be varied stepwise in
127 steps (7 bits) by a factor of 1 to 2. Further, the CRT
spot-cutoff control is accomplished via these amplifiers’ bi-
as by adding the output signal of an 8-bit D/A converter to
the intelligence signal. The amplitude of the output signal
corresponds to one half of the luminance range. The eight
bits make it possible to adjust the dark voltage in 0.5 %
steps. By means of this circuit, the factory-set values for
the dark currents can be maintained and aging of the pic-
ture tube compensated.
1.6. The Beam Current and Peak Beam Current Limiter
The principle of this circuitry may be explained by means of
Fig. 6. Both facilities are carried out via pin 34 of the VCU
2133. For beam current limiting and peak beam current li-
miting, contrast and brightness are reduced by reducing
the reference voltages for the D/A converters Y, Ft-Y and
B-Y. At a voltage of more than +4 V at pin 34, contrast and
brightness are not affected. In the range of +4 V to +3 V,
the contrast is continuously reduced. At +3 V, the original
contrast is reduced to a programmable level, which is set
by the bits of address 16 of the VPU as shown in Table 2. A
further decrease of the voltage merely reduces brightness,
the contrast remains unchanged. At 2 V, the brightness is
reduced to zero. At voltages lower than 2 V, the output
goes to ultra black. This is provided for security purposes.
The beam current limiting is sensed at the ground end of
the EHT circuit, where the average value of the beam cur-
rent produces a certain voltage drop across a resistor in-
serted between EHT circuit and ground. The peak beam
current limiting can be provided additionally to avoid
“blooming” of white spots or letters on the screen. For
this, a fast peak current limitation is needed which is
sensed by three sensing transistors inserted between the
RGB amplifiers and the cathodes of the picture tube. One
of these three transistors is shown in Fig. 6. The sum of the
picture tube’s three cathode currents produces a voltage
drop across resistor R1. If this voltage exceeds that gen-
erated by the divider R2, B3 plus the base emitter voltage
of T2, this transistor will be turned on and the voltage at

pin
34 of the VCU 2133 sharply reduced. Time constants for
both beam current limiting and peak beam current limiting
can be set by the capacitors C1 and C2.
1.7. The Blanking Circuit
The blanking circuit coordinates blanking during vertical
and horizontal flyback. During the latter, the VCU 2133's
output amplifiers are switched to “ultra black”. Such
switching is different during vertical flyback, however, be-
cause at this time the measurements for picture tube align-
ment are Carried out. During vertical flyback, only the ca-
thode to be measured is switched to “black” during mea-
suring time, the other two are at ultra black so that only the
dark current of one cathode is measured at the same time.
For measuring the leakage current, all three cathodes are
switched to ultra black.
The sequence described is controlled by three code bits
contained in a train of 72 bits which is transferred from the
VPU 2203 to the VCU 2133 during each vertical blanking in-
terval. This transfer starts with the vertical blanking pulse.
During the transfer all three cathodes of the picture tube
are biased to ultra black. In the same manner, the white-
balance control is done.
The blanking circuit is controlled by two pulse combina-
tions supplied by the DPU 2553 Deflection Processor
(“sandcastle pulses"). Pin 39 of the VCU 2133 receives the
combined vertical blanking and delayed horizontal blanking
pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of the
VCU gets the combined undelayed horizontal blanking and
color key pulse from pin 19 of the DPU (Fig. 7 a). The two
outputs of the DPU are tristate-controlled, supplying the
output levels max. 0.4 V (low), min. 4.0 V (high), or high-im-
pedance, whereby the signal level in the high-impedance
mode is determined by the VCU’s input configuration, a
voltage divider of 3.6 KS! and 5 KQ between the +5 V sup-
ply and ground, to 2_8 V. The VCU’s input amplifier has two
thresholds of 2.0 V and 3.4 V for detecting the three levels
of the combined pulses. ln this way, two times two pulses
are transferred via only two lines.
1.8. The Circuitry for Picture Tube Alignment
During vertical flyback, a number of measurements are tak-
en and data is exchanged between the VCU 2133, the VPU
2203 and the CCU 2030 or CCU 2050. These measure-
ments deal with picture tube alignment, as white level and
dark current adjustment, and with the photo current sup-
plied by a photo resistor (Fig. 5) which serves for adapting
Fig. 8:
Data sequence during the transfer of test results from the
VPU 2203 to the VCU 2133. Nine Bytes are transferred, in
each case the LSB first. These 9 Bytes, 8 bits each, coin-
cide with the 72 pulses of 4.4 MHz that are transferred dur-
ing vertical flyback from pin 27 of the VPU 2203 to pin 21 of
the VCU 2133 (see Fig. 9).
l and mi beam current limiter range
l<: noise inverter on/off
n: video input switching bit
S: SECAM chroma sync bit; S = 1 means that the chroma
demultiplexer is synchronized every line. The switch-over
time from C0 to demux counter begins with the end of the
undelayed horizontal blanking pulse and remains valid for a
time of 12 Q M clock periods.
6
the contrast of the picture to the light in the room where
the TV set is operated. The circuitry for transferring the

pic-
ture tube alignment data, the sensed beam currents and
the photo current is clocked in compliance with the VPU
2203 by the vertical blanking pulse and the color key pulse.
To carry out the measurements, a quadruple cycle is pro-
vided (see Table 3). The timing of the data transfer during
the vertical flyback is shown in Fig. 9, and Fig. 8 shows the
data sequence during that data transfer.
Ft, G, B: code bits
p=1; no doubled gain in the input amplifier during horizon-
tal blanking (see section 1.1.)
q=1: no changing of the A/D converter’s reference vol-
tage during every other line (see section 1.1.)
r=1: when operating with the DMA D2-MAC decoder or
the CVPU comb filter video processor, the adding of
a step of ‘/2 LSB to the output signal of the Y D/A
converter is switched off (see section 1.1.).
s=1; the blankirig pulse in the analog video output signal
at pins 26 to 28 is switched off, as is required in
stand-alone applications.


1.9. The Additional RGB Inputs
The three additional analog RGB inputs are provided for
inputting text or other analog RGB signals. They are con-
nected to fast voltage-to-current converters whose output
current can be altered in 64 steps (6 bits) for contrast set-
ting between 100 % and 30 %. The three inputs are
clamped to a DC black level which corresponds to the level
of 31 steps in the luminance channel, by means of the color
key pulse. So, the same brightness level is achieved for
normal and for external RGB signals. The output currents
ofthe converters are then fed to the three RGB output am-
plifiers. Switchover to the external video signal is also

fast.
1.10. The Reset Circuit and Pulse Detector
The reset pulse produced by the external reset RC network
in common for the whole DIGIT 2000 system, switches the
RGB outputs to ultra black during the power-on routine of
the TV set. At other times, high level must be applied to the
reset input pin 23.
There is an additional facility with pin 23 which is used only
in conjunction with the DTl 2223 Digital Transient Improve-
ment Processor. The hold pulse produced by the latter
which serves for stopping the R-Y and B-Y D/A converters,
is also fed to pin 23, capacitively-coupled. The pulse detec-
tor responds on positive pulses which exceed the 5 V sup-
ply by about 1 V. The two DACs are stopped as long as the
hold pulse lasts, and supply a constant output signal of the
amplitude at the begin of the hold pulse.


5. Description of the Connections and the Signals
Pins 1, 9, and 25 - Supply Voltage, +5 V
The supply voltage is +5 V. Pins 1 and 25 supply the ana-
log part and must be filtered separately.
Pins 2 to 8 - Outputs V0 to V6
Via these pins the VCU 2133 supplies the digitized video
signal in a parallel 7-bit Gray code to the VPU 2203 and the
DPU 2553. The output configuration is shown in Fig. 16.
Pins 10 to 17 - Inputs L7 to L0
Fig. 17 shows these inputs’ configuration. Via these pins,
the VCU 2133 receives the digital luminance signal from the
VPU 2203 in a paraliel 8-bit code.
Pins 18 to 21 - Inputs C0 to C3
Via these inputs, whose circuitry and data correspond to
those of pins 10 to 17, the VCU 2133 is fed with the digi-
tized color difference signals R-Y and B-Y and with the
control and alignment signals described in section 1.8., in
multiplex operation. Pin 21 is additionally used for the

multi-
plex sync signal.
Pin 22 - QSM Main Clock Input
Via this pin, whose circuitry is shown in Fig. 18, the VCU
2133 is supplied with the clock signal QSM produced by the
MCU 2600 or MCU 2632 Clock Generator IC. The clock fre-
quency is 17.7 MHz for PAL and SECAM and 14.3 MHz for
NTSC. The clock signal must be DC-coupled.
Pin 23 - Reset and Hold Pulse Input (Fig. 19)
Via this pin, the VCU 2133 is supplied with the reset and
hold signals which are supplied by pin 21 of the DTI 2223
Digital Transient Improvement Processor for stopping the
R-Y and B-Y D/A converters, and for Reset.
Pins 24 and 29 - Analog Ground, 0
These pins serve as ground connections for the supply and
for the analog signals (GND pin 24 for RGB).
Pins 26 to 28 - RGB Outputs
These three analog outputs deliver an analog signal suit-
able for driving the RGB output transistors. Their diagram
is shown in Fig. 20. The output voltage swing is 6 V total,
3 V for the black-to-white signal and 3 V for adjusting
the brightness and the black level.
Pins 30 to 32 - Additional Analog Inputs R, G and B
Fig. 21 shows the configuration of these inputs. They serve
to feed analog RGB signals, for example for Teletext or si-
milar applications, and they are clamped during the color
key pulse. At a 1 V input, full brightness is reached. The
bandwidth extends from 0 to 8 MHz.
Pin 33 - Fast Switching Input
This input is connected as shown in Fig. 22. It ser\/es for
fast switchover of the video channel between an internally-
produced video signal and an externally-applied video sig-
nal via pins 30 to 32. With 0 V at pin 33, the RGB outputs
will supply the internal video signal, and at a 1 V input

level,
the RGB outputs are switched to the external video signal.
Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-
mum.
Pin 34 - Beam Current Limiter Input
The diagram of pin 34 is shown in Fig. 25. The input voltage
may be between +5 V and 0 V. The input impedance is 100
kQ. The function of pin 34 is described in section 1.6.
Pin 35 - Composite Video Signal Input 1
To fully drive the video A/D converter the following ampli-
tudes are required at pin 35: +5 V = sync pulse top level,
all bits low; +7 V = peak white, all bits high. Fig. 24 shows
the configuration of pin 35.
Pin 36 - Undelayed Horizontal Blanking and Color Key
Pulse Input
The circuitry of this pin is shown in Fig. 23. Pin 36 receives
the combined undelayed horizontal blanking and color key
pulse which are “sandcastled” and are supplied by pin 19
of the DPU 2553 Deflection Processor. During the undelay-
ed horizontal blanking pulse, the input amplifiers’ gain is
doubled, and the bit enlargement circuit is also switched
by this pulse, and the counter for the data transmission
gap started. The color key pulse is used for clamping the
RGB inputs pins 30 to 32.
Pin 37 - Composite Video Signal Input 2
This pin has the same function and properties as pin 35,
except the gain of the input amplifier which is twice the
gain as that of the amplifier at pin 35. This means an input
voltage range of +5 V to +6 V.
Pin 38 - Supply Voltage, +12 V »
The 12 V supply is needed for certain circuit parts to obtain
the required input or output voltage range, as the video in-
put and the RGB outputs (see Figs. 20 and 24).
Pin 39 - Vertical Blanking and Delayed Horizontal Blanking
Input
This pin receives the combined vertical blanking and delay-
ed horizontal blanking. pulse from pin 22 of the DPU 2553
Deflection Processor. Both pulses are “sandcastled” so
that only one connection is needed for the transfer of two
pulses. These two pulses are separated in the input circui-
try of the VCU 2133, and are used for blanking the picture
during vertical and horizontal flyback. Fig. 23 shows the cir-
cuitry of pin 39.
Pin 40 - Digital Ground, O
This pin is used as GND connection in conjunction with the
pins 2 to 8 and 10 to 21 which carry digital signals.

DPU 2553, DPU 2554 Deflection Processors UNIT

Note: lf not otherwise designated, the pin numbers
mentioned refer to the 40-pin Dil package.

1. Introduction
These programmable VLSI circuits in n-channel mOS
technology carry out the deflection functions in digital
colorTV receivers based onthe DiGiT 2000 system and
are also suitable for text and D2~mAC application. The
three types are basically identical, but are modified ac-
cording to the intended application:

DPU 2553
normal-scan horizontal deflection, standard CTV re-
ceivers, also equipped with Teletext and D2-mAC fa-
cility
DPU 2554
double-scan horizontal deflection, for CTV receivers
equipped with double-frequency horizontal deflection
and double-~frequency vertical deflection for improved
picture quality. At power-up, this version starts with
double horizontal frequency.

1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol-
lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture
tubes
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequen-
cies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode

and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection
ln this data sheet, all information given for double~scan
mode is available with the DPU 2554 only. Type DPU
2553 starts the horizontal deflection with 15.5 kHz ac-
cording to the normal TV standard, whereas type DPU
2554 starts with 31 kHz according to the double-scan
system.
The following characteristics are programmable:
~ selection ofthe TV standard (PAL, D2-mAC or NTSC)
- selection ofthe deflection standard (Teletext, horizon-
tal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position
for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal
correction for in-line, flat-screen and Trinitron picture
tubes
- switchover characteristics between the different syn-
chronization modes
~characteristic of the synchronism detector for PLL
switching and muting

1.2. Environment
Fig. 1-1 showsthe simplified block diagram ofthe video
and deflection section of a digital TV receiver based on
the DIGIT 2000 system. The analog video signal derived
from the video detector is digitized in the VCU 2133,
VCU 2134 or VCU 2136 Video Codec and supplied in a
parallel 7 bit Gray code. This digital video signal is fed to
the video section (PVPU, CVPU, SPU and DmA) and to
the DPU 2553/54 Deflection Processorwhich carries out
all functions required in conjunction with deflection, from
sync separation to the control of the deflection power
stages, as described in this data sheet.
3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors
perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and
the vertical deflection frequencies
-the various eastevvest corrections
- vertical savvtooth generation including S correction
as described hereafter. The DPU communicates, viathe
bidirectional serial lm bus, with the CCU 2050 or CCU
2070 Central Control Unit and, via this bus, is supplied
with the picture-correction alignment information stored
in the mDA 2062 EEPROM during set production, vvhen
the set is turned on. The DPU is normally clocked with
a trapezoidal 17.734 mHz (PAL or SECAm), or 14.3 mhz
(NTSC) or 20.25 mHz (D2-mAC) clock signal supplied
by the mCU 2600 or mCU 2632 Clock Generator IC.

The functional diagram of the DPU is shovvn in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse
Separation Circuit

The digitized composite video signal delivered as a 7»bit
parallel signal by the VCU 2133, VCU 2134 or VCU 2136
Video Codec is first noise-filtered by a 1 mHz digital lovv-
pass filter and, to improve the noise immunity ofthe
clamping circuit, is additionally filtered by a 0.2 mHz low-
pass filter before being routed to the minimum and back
porch level detectors (Fig. 3-3).
The DPU has tvvo different clamping outputs, no. 1 and
No. 2, one of vvhich supplies the required clamping
pulses to the video input of the VCU as shovvn in Fig.
3-1. The following values forthe clamping circuit apply
for Video Amp. l. since the gain of Video Amp. ll istwice
th at of Video Amp l, all clamping and signal levels of Vid-
eo Amp ll are halt those of Video Amp l referred to +5 V.
Afterthe TV set is switched on,thevideo clamping circuit
first of all ensures by means of horizontal-frequency
current pulses from the clamping output of the DPU to
the coupling capacitor of the analog composite video
signal, that the video signal atthe VCU’s input is optimal-
ly biased for the operation range of the A/D converter of
5 to 7 V. For this, the sync top level is digitally measured
and set to a constant level of 5.125 V by these current
pulses. The horizontal and vertical sync pulses are novv
separated by a fixed separation level of 5.250 V so that
the horizontal synchronization can lock to the correct
phase (see section 3.3. and Figs. 3-2 and 3-3).
vvith the color key pulse which is now present in syn-
chronism with the composite video signal, the video
clamping circuit measures the DC voltage level of the
porch and by means of the pulses from pin 21 (or pin4),
sets the DC level ofthe porch at a constant 5.5 V (5.25 V
for Video Amp ll). This level is also the reference black
to Video Processorffeletext Processor, D2-MAC Processor tc.


level for the PVPU 2204 or CvPU 2270 Video Proces-
sors.
When horizontal synchronization is achieved, the slice
level for the sync pulses is set to 50 % of the sync pulse
amplitude by averaging sync top and black level. This
ensures optimum pulse separation, even with small
sync pulse amplitudes (see application notes, section
4).
3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal syn-
chronization. The choice of mode depends on whether
or not the Tv station is transmitting a standard PAL or
NTSC signal, in which there is a fixed ratio between color
subcarrier frequency and horizontal frequency. ln the
first case we speak of “color-locked” operation and in
the second case of “non-color-locked” operation (e.g.
black-and-white programs). Switching between thetwo
modes is performed automatically by the standard sig-
nal detector.


3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation
where there is no standard fixed ratio between the color
subcarrier frequency and the horizontal frequency ofthe
transmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3
mHz for NTSC) in the programmable fre-
quency dmder (Fig. 3-4) until the correct horizontal
frequency is obtained. The correct adjustment of fre-
quency and phase is ensured by phase comparator l.
This determines the frequency and phase deviation by
means of a digital phase comparison between the sepa-
rated horizontal sync pulses and the output signal of the
programmable dmder and corrects the dmder accordingly. For
optimum adjustment of phase iitter, capture
behavior and transient response of the horizontal PLL
circuit, the measured phase deviation is filtered in a digi-
lowpass filter (PLL phase filter). ln the case of non-
OZMH synchronized horizontal PLL, this filter is set to
wideband PLL response with a pull-in range of 1800 Hz. if the
- sync sync PLL circuit is locked, the PLL filter is
automatically switched to narrow-band response by an internal
synchronism detector in order to limit the phase jitter to a
minimum, even in the case of weak and noisy signals.

A calculator circuit in phase comparator , which analyzes the
edges of the horizontal sync pulses, increases
the resolution of the phase measurement from 56 ns at
Fig. 3-3: Principle ofvideo clamping and pulse separa- 17.7

mHz clock frequency to approx. 6 ns, or from 70 ns
NON at 14.3 MHz clock frequency to approx. 2.2 ns.



The various key and gating pulses such as the color key
pulse (tKe(,), the normal-scan (1 H) and double-scan
(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-
zontal undelayed gating pulse (t/(Z) are derived from the
output signals ofthe programmable dmder and an addi-
tional counter forthe2H signals and the 1 H and 2H skew
data output. These pulses retain a fixed phase position
with respect to the 1 H inputvideo signal andthe double-
scan output video signal from the CvPU 2270 Video Pro-
cessor
Forthe purpose of equalizing phase changes in the hori-
zontal output stage due to switching response toler-
ances or video influence, a second phase control loop
is used which generates the horizontal output pulse at
pin 31 to drivethe horizontal output stage. ln phase com-
parator li (Fig. 3~4), the phase difference between the
output signal of the programmable dmder and the lead-
ing edge (or the center) of the horizontal flyback pulse
(pin 23) is measured by means of a balanced gate delay
line. The deviation from the desired phase difference is
used as an input to an adder. ln this, the information on
the horizontal frequency derived from phase com-
parator l is added to the phase deviation originating form
phase comparator ll. The result of this addition controls
a digital on-chip sinewave generator (about 1 mHz)
which acts as a phase shifter with a phase resolution of
1/128 of one main clock period m_
By means of control loop ll the horizontal output pulse
(pin 31) is shifted such that the horizontal flyback pulse
(pin 23) acquiresthe desired phase position with respect
to the output signal of the programmable dmder which,
in turn, due to phase comparator l, retains a fixed phase
position with respect to the video signal. The horizontal
output pulse itself is generated by dmding the frequency
ofthe 1 mHz sinewave oscillator by a fixed ratio of 64 in
the case of norm al scan and of 32 in the case of double-
scan operation.


3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the
phase position has been set in the non-color-locked
mode, the programmable dmder is set to the standard
dmsion ratio (1135:1 for PAL, 91O:1 for NTSC) and
phase comparator is disconnected so that interfering
pulses and noise cannot influence the horizontal deflec-
tion. Because phase comparator ll is still connected,
phase errors ofthe horizontal output stage are also cor-
rected in the color»locKed operating mode. The stan-
dard signal detector is so designed that it only switches
to color-locke
d operation when the ratio between color
subcarrier frequency and horizontal frequency deviates
no more than 1O'7 from the standard dmsion ratio. To
ascertain this requires about 8 s (NTSC). Switching off
color-locked operation takes place automatically, in the
_ case of a change of program for example, within approx-
imately 67 ms (e.g. two NTSC fields, 60 Hz).


3.3.3. Skew Data Output and Field Number Informa-
tion
with non-standard input signals, the TPU 2735 or TPU
2740 Teletext Processor produce a phase error vvith re-
spect to the deflection phase.
The DPU generates a digital data stream (skevv data,
pin 7 ofthe DPU), which informs the PSP and TPU on
the amount of phase delay (given in 2.2 ns increments)
used in the DPU for the 1H and 2h output pulse com-
pared With the Fm main clock signal of 17.7 mHz (PAL
or SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to
3-8. The skew data is used by the PSP and by the TPU
to adjust the double-scan video signal to the 1 H and 2H
phase of the horizontal deflection to correct these phase
errors.
For the vmC processor the skew data contains three additional

bits for information about frame number, 1 V
sync and 2 V sync start.


3.3.4. Synchronism Detector for PLL and Muting
Signal
To evaluate locking ofthe horizontal PLL and condition
of the signal, the DPU’s HSP high-speed processor
(Fig. 3~1) receives two items of information from the hor-
izontal PLL circuit (see Fig. 3-11).
a) the overall pulsevvidth of the separated sync pulses
during a 6.7 us phase window centered to the horizontal
sync pulse (value A in Fig. 3-11).
b) the overall pulsevvidth of the separated sync pulse
during one horizontal line but outside the phase window
(value B in Fig. 3-11).
Based on a) and b) and using the selectable coefficients
KS1 and KS2 and a digital lovi/pass filter, the HSP pro-
cessor evaluates an 8-bit item of information “SD” (see
Fig. 3-12). By means of a comparator and a selectable
level SLP, the switching threshold for the PLL signal
“UN” is generated. UN indicates Whether the PLL is in
the synchronous or in the asynchronous state.
To produce a muting signal in the CCU, the data SD can
be read by the CCU. The range ot SD extends from O
(asynchronous) to +127 (synchronous). Typical values
torthe comparator levels and their hysteresis B1 = 30/20
and for muting 40/30 (see also HSP Bam address Table
5-6).


DPU 2553, DPU 2554

3.4. Start Oscillator and Protection Circuit
To protect the horizontal output stage of the TV set dur-
ing changing the standard and for using the DPU as a
low power start oscillator, an additional oscillator is pro-
vided on-chip (Fig. 3-4), with the output connected to
pin 31. This oscillator is controlled by a 4 mHz signalin-
dependent trom the Fm main clock produced by the
MCU 2600 or mCU 2632 Clock Generator IC and is pow-
ered by a separate sup
ply connected to pin 35. Thefunc-
tion ofthis circuitry depends on the external standard se-
lection input pin 33 and on the start oscillator select input
pin 36, as described in Table 3-3. Using the protection
circuit as a start oscillator, the following operation modes
are available (see Table 3-3).
With pin 33 open-circuit, pin 36 at high potential (con-
nected to pin 35) and a 4 mHz clock applied to pin 34,
the protection circuit acts as a start oscillator. This pro-
duces a constant-frequency horizontal output pulse of
15.5 kHz in the case of DPU 2553, and of 31 khz in the
case of DPU 2554 while the Beset input pin 5 is at low
potential. The pulsewidth is 30 us with DPU 2553, and
16 us with DPU 2554. main clock at pin 2 or main power
supplies at pins 8, 32 and 40 are not required for this start
oscillator After the main power supply is stabilized and
the main clock generator has started, the reset input pin
5 must be switched to the high state. As long as the start
values from the CCU are invalid, the start oscillator will
continuously supply the output pulses of constant fre-
quency to pin 31 _ By means of the start values given by
the CCU via the lm bus, the register FL must be set to
zero to enable the stan oscillator to be triggered by the
horizontal PLL circuit. After that, the output frequency
and phase are controlled by the horizontal PLL only.
It the external standard selection input pin 33 is con-
nected to ground or to +5 V, the start oscillator is
switched off as soon as it ls in phase with PLL circuit. Pin
33to ground selects PAL or SECAm standard (17.7 mHz
main clock), and pin 33 to +5 V selects NTSC standard
(14.3 MHz main clock). After the main power supplies to
pins 8, 32 and 40 are stabilized, the start oscillator can
be used as a separate horizontal oscillator with a con-
stant frequency of 15.525 khz. For this option, pin 33
must be unconnected. By means ofthe lm bus register
SC the start oscillator can be switched on (SC = 0) or oft
(SC = 1). Setting SC =1 is recommended.
By means of pin 29 (horizontal output polarity selectin-
put and start oscillator pulsewidth select input), the out-
put pulsewidth and polarity ofthe start oscillator and pro-
tection circuit can be hardware-selected. Pin 29 at low
potential gives 30 us for DPU 2553 and 16 us for DPU
2554,with positive output pulses. Pin 29 at high potential
gives 36 us for DPU 2553 and 18 its for DPU 2554, with
negative output pulses. Both apply forthetime period in
which no start values are valid from the CCU. If pin 29
is intended to be in the high state, it must be connected
to pin 35 (standby power). Pin 29 must be connected to
ground or to +5 V in both cases.
Table 3-3: Operation modes ofthe start oscillator and
protection circuit


Operation Mode Pins
33 34 35 36
Horizontal output stage protected not connected 4 mHz Clock at

+5 V at ground
during main clock frequency changing
(for PAL and NTSC)
Horizontal output stage protected not connected 4 MHz Clock +5

V with connected to
and start oscillator function start oscilla- pin 35
(for PAL and NTSC) tor supply
Only start oscillator function with at +5 V 4 mHz Clock +5 V

with connected to
NTSC standard after Beset start oscilla- pin 35
tor supply
Only start oscillator function with at ground 4 mHz Clock +5 V

with connected to
PAL or SECAM standard after Beset start oscilla~ pin 35
5 tor supply
_ with 17.7 mHz clock at ground at ground at +5 V at ground
without protection.

3.5. Blanking and Color Key Pulses

Pin 19 supplies a combination ofthe color key pulse and
the undelayed horizontal blanking pulse in the form of a
three-level pulse as shown in Fig. 3-13. The high level
(4 V min.) and the low level (0.4 V max.) are controlled
by the DPU. During the low time of the undelayed hori-
zontal blanking pulse, pin 19 of the DPU i sin the high--
impedance mode and the output level at pin 19 is set to
2.8 V by the VCU.
At pin 22, the delayed horizontal blanking pulse in com-
bination with the vertical blanking pulse is available as
athree-level p
ulse as shown in Fig. 3-13. Output pin 22
is in high-impedance mode during the delayed horizon-
tal blanking pulse.
ln double-scan operation mode (DPU 2554), pin 22 sup-
plies the double-scan (2H) horizontal blanking pulse in-
stead ofthe 1H blanking pulse (DPU 2553). ln text dis-
play mode with increased deflection frequencies (see
section 1.), pin 22 ofthe respective DPU (DPU 2553, as
defined by register ZN) delivers the horizontal blanking
pulse with 18.7 kHz and the vertical blanking pulse with
60 Hz according to the display. At pin 24 the undelayed
horizontal blanking pulse is output.
normally,pin3suppliesthe samevertical blanking pulse
as pin 22. However, with“DVS” = 1, pin 3 will be in the
single-scan mode also with double-scan operation of
the system. The pulsewidth of the single-scan vertical
blanking pulse at pin 3 will be the same as.that of the
double-scan vertical blanking pulse at pin 22. The out-
put pulse of pin 3 is only valid if the COU register “VBE”
is set to 1 . The default value is set to 0 (high-impedance
state of pin 3).

Fig. 3-13: Shape of the output pulses at pins 19 and 22
*) The output level is externally defined
3.6. Output for Switching the Horizontal Power
Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz
(Text Display)
This output (pin 37) is designed as a tristate output. High
levels (4 V mln.) and low levels (0.4 V max.) are con-
trolled bythe DPU. During high-impedance state an ex-
ternal resistor network defines the output level,
For changing the horizontal frequency from 15 kHz to
18 kHz, the following sequence of output levels is
derived at pin 37 (see Fig. 3-14).
After register ZN is set from ZN = 2 (15 kHz) to ZN = 0
(18 kHz) by the CCU, pin 37 is switched from High level
to high-impedance state synchronously with the fre-
quency change at pin 31. Following a delay of 20ms, pin
37 is set to Low level and remains in this state forthetime
the horizontal frequency remains 18 kHz (with ZN == 0).
This 20 ms delay is required for switching-over the hori-
zontal power stage.
To change the horizontal frequency in the opposite di-
rection, from 18 kHz to 15.6 kHz, the sequence de-
scribed is reversed.
3.7. Text Display Mode with Increased Deflection
Frequencies
As already mentioned, the DPU 2553 provides the fea-
ture of increased deflection frequencies for text display
for improved picture quality in this mode of operation. To
achieve this, the processor acting as deflection proces-
sor has its register Zn set to 0. The horizontal output fre-
quency at pin 31 is then switched to a frequency of
18746.802 Hz which is generated by dmding the Fm
main clock frequency by 946 i 46. The horizontal PLL is
then able to synchronize to an external composite sync
signal offH = 18.746 kHzi 46. The horizontal PLL isthen
able to synchronizeto an external composite sync signal
of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can
be set to an independent horizontal and vertical sync
generator by setting register VE = 1 and register VB = 0.
That means a constant dmder of 946 for horizontal fre-
quency and constant 312 lines per frame.

The DPU working in this mode supplies the TPU 2740
Teletext Processor or the respective Viewdata Proces-
sor with the 18.7 kHz horizontal blanking pulses form pin
24 and the 60 Hz vertical blanking pulses form pin 22
(see Fig. 3-8).
To be able to receive and store data from an IF video sig-
nal at the same time, the Teletext or Viewdata Processor
requires horizontal and vertical sync pulses from this IF
signal. Therefore, the second DPU provides video
clamping and sync separation forthe external signal and
supplies the horizontal sync pulses (pin 24) and the ver-
tical sync pulses (pin 22) to the Teletext or viewdata Pro-
cessor. For this, the second DPU is set to the PAL stan-
dard by register ZN = 2, and the clamping pulses of the
other DPU are disabled by CLD = 1.
To change the output frequency ofthe DPU acting as de-
flection processor from 18.7 kHz to 15.6 kHz, the control
switch output pin 37 prepares the horizontal output
stage for 15.6 khz operation (pin 37 is in the high-impe-
dance state) beforethe DPU changesthe horizontal out-
put frequencyto 15.6 kHz, after a minimum delay of one
vertical period. Switching the horizontal deflection fre-
quency from 15.6 kHzto 18.7 kHz is done in the reverse
sequence. Firstly, the horizontaloutput frequency of pin
31 is switched to 1 8.7 khz, and after a delay of one verti-
cal period, pin 37 is set low.
3.8. D2-MAC Operation Mode
When receiving Tv signals having the D2-mAC stan-
dard (direct satellite reception), register ZN is set to 3.
The programmable dmder is set to a dmsion ratio of
1296 i48 to generate a horizontal frequency of 15.625
khz with the clock rate of 20.25 mHz used in the
D2-mAC standard. ln this operation mode, pin 6 acts as
input forthe composite sync signal supplied by the DmA
2271 D2-mAC Decoder. The DPU is synchronized to
this sync signal, and after locking-in (status register
UN = 0), the CCU switches the DPU to a clock-locked
mode between clock signal and horizontal frequency
(fm main
clock by 1024, during the vertical sync signal separated
from the received video signal. To use an 8-bit register,
the result of the count is dmded by 2 and given to the
DPU status register. ln the CCU, the vertical frequency
can be evaluated using the following equation:

fv I __lL1’_l\
1024- vP- 2
with
fm), = 17.734475 mHz with PAL and SECAm
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.

The interlace control output pin 39 supplies a 25 Hz (for
PAL and SECAm) or 80 Hz (for NTSC) signal for control-
ling an external interlace-off switch, which is required
with A.C.-coupled vertical output stages, becausethese
are not able to handle the internal interlace-off proce-
dure using register “ZS”.
For operation with the v
mC Processor the DPU 2554
hasthree interlace control modes in double vertical scan
mode (DVS = 1). These options can be selected with the
register “IOP” and can be used together with the control
output pin 39 only. This output has to be connected to the
vertical output stage, so that the vertical phase can be
shifted by 16 us (or 32 us with DPU 2553).

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ITT DIGIT2000 CATHODE RAY TUBE (Kinescope) driver with kinescope current sensing circuit:
A television receiver includes a kinescope and a current sensing transistor for conveying amplified video signals to the kinescope, and for providing at a sensing output terminal an output signal related to the magnitude of kinescope current conducted during given sensing intervals. A clamping circuit clamps the sensing output terminal during normal image intervals, and unclamps the sensing output terminal during the sensing intervals. The clamping circuit facilitates interfacing the sensing transistor with utilization circuits which process the sensed output signal, and assists to maintain a proper operating condition for the sensing transistor.


1. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage with a video signal input and a video signal output for providing an amplified video signal;
means for conveying said amplified video signal to said image reproducing display device, said conveying means having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said sensed signal representative of current conducted by said image reproducing display device is subject to processing by said utilization means; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed representative signal.
2. Apparatus according to claim 1, wherein:
said video output stage comprises a video amplifier with a video signal input and a video signal output for providing said amplified video signal; and
said conveying means comprises an active current conducting device with an input first terminal for receiving said amplified video signal, an output second terminal for conveying said amplified video signal to said image reproducing display device, and a third terminal for providing said sensed signal.
3. Apparatus according to claim 2, wherein
said active current conducting device is a transistor with a base input for receiving said amplified video signal, an emitter output for providing said amplified video signal to said image reproducing display device, and a collector output for providing said sensed signal.
4. Apparatus according to claim 1, wherein
said first and second electrodes define a main current conduction path of said clamping transistor means.
5. Apparatus according to claim 4, wherein
said clamping means includes resistive means coupled to said sensing output for providing a voltage in accordance with the magnitude of said sensed signal; and
said third electrode of said clamping transistor means is coupled to said resistive means.
6. Apparatus according to claim 1, and further comprising
filter means for bypassing high frequency signal components at said sensing output.
7. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage coupled to said image reproducing display device for providing an amplified video signal thereto, and having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
control means responsive to said sensed signal for developing a control signal;
means for coupling said control signal to said image reproducing display device to maintain a desired conduction characteristic of said image reproducing display device; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said control means operates to monitor said sensed signal; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed signal.
8. Apparatus according to claim 7, wherein
said control means includes digital signal processing circuits; and
said control means includes an input analog-to-digital signal converter network.
9. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video amplifier with a video signal input for receiving video signals, and a video signal output for providing an amplified video signal;
a signal coupling transistor with an input first electrode for receiving said amplified video signal from said video amplifier, an output second electrode for providing a further amplified video signal to said image reproducing display device, and a third electrode for providing a sensed signal representative of the magnitude of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said third electrode of said coupling transistor during normal image intervals, and for unclamping said third electrode during interval when said sensed representative signal is subject to processing by said utilization means, said clamping means comprising clamping transistor means with an output first electrode coupled to said third electrode of said signal coupling transistor, a second electrode coupled to an operating potential, and an input third electrode coupled to said third electrode of said signal coupling transistor, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said input third electrode of said clamping transistor means.
10. Apparatus according to claim 9, wherein
said coupling transistor is an emitter follower transistor with a base input electrode, an emitter output electrode, and a collector output electrode corresponding to said third electrode.
Description:
This invention concerns a video output display driver amplifier for supplying high level video output signals to an image display device such as a kinescope in a television receiver. In particular, this invention concerns a display driver stage associated with a sensing circuit for providing a signal representative of the magnitude of current conducted by the kinescope during prescribed intervals.
Video signal processing and display systems such as television receivers commonly include a video output display driver stage for supplying a high level video signal to an intensity control electrode, e.g., a cathode electrode, of an image display device such as a kinescope. Television receivers sometimes employ an automatic black current (bias) control system or an automatic white current (drive) control system for maintaining desired kinescope operating current levels. Such control systems typically operate during image blanking intervals, at which time the kinescope is caused to conduct a black image or a white image representative current. Such current is sensed by the control system, which generates a correction signal representing the difference between the magnitude of the sensed representative current and a desired current level. The correction signal is applied to video signal processing circuits for reducing the difference.
Various techniques are known for sensing the magnitude of the black or white kinescope current. One often used approach employs a PNP emitter follower current sensing transistor connected to the kinescope cathode signal coupling path. Such sensing transistor couples video signals to the kinescope via its base-to-emitter junction, and provides at a collector electrode a sensed current representative of the magnitude of the kinescope cathode current. The representative current from the collector electrode of the sensing transistor is conveyed to the control system and processed to develop a suitable correction signal.
In accordance with the principles of the present invention, there is disclosed a kinescope current sensing arrangement wherein a current sensing device is coupled to a kinescope for providing at an output terminal a signal representative of the magnitude of the kinescope current. A clamping circuit clamps the output terminal to a given voltage during normal image trace intervals. During prescribed kinescope current sensing intervals, however, the clamping circuit is inoperative and the sensed signal representative of the kinescope current is developed at the output terminal. The clamping circuit advantageously facilitates interfacing the current sensing device with control circuits for processing the sensed signal, and assists to maintain a proper operating condition for the current sensing device which, in a disclosed embodiment, also conveys video signals to the display device. In accordance with a feature of the invention, the clamping circuit is self-keyed between clamping and non-clamping states in response to the representative signal at the output terminal.
In the drawing:
FIG. 1 shows a circuit diagram of a kinescope driver stage with associated kinescope current sensing and clamping apparatus in accordance with the present invention; and
FIG. 2 depicts, in block diagram form, a portion of a color television receiver incorporating the current sensing and clamping apparatus of FIG. 1.
In FIG. 1, low level color image representative video signals r, g, b are provided by a source 10. The r, g and b color signals are coupled to similar kinescope driver stages. Only the red (r) color signal video driver stage is shown in schematic circuit diagram form.
Red kinescope driver stage 15 comprises a driver amplifier including an input common emitter amplifier transistor 20 arranged in a cascode amplifier configuration with a common base amplifier transistor 21. Red color signal r is coupled to the base input of transistor 20 via a current determining resistor 22. Base bias for transistor 20 is provided by a resistor 24 in association with a source of negative DC voltage (-V). Base bias for transistor 21 is provided from a source of positive DC voltage (+V) through a resistor 25. Resistor 25 in the base circuit of transistor 21 assists to stabilize transistor 21 against oscillation.
The output circuit of driver stage 15 includes a load resistor 27 in the collector output circuit of transistor 21 and across which a high level amplified video signal is developed, and opposite conductivity type emitter follower transistors 30 and 31 with base inputs coupled to the collector of transistor 21. A high level amplified video signal R is developed at the emitter output of follower transistor 30 and is coupled to a cathode electrode of an image reproducing kinescope via a kinescope arc current limiting resistor 33. A resistor 34 in the collector circuit of transistor 31 also serves as a kinescope arc current limiting resistor. Degenerative feedback for driver stage 15 is provided by series resistors 36 and 38, coupled from the emitter of transistor 31 to the base of transistor 20.
A diode 39 connected between the emitters of transistors 30 and 31 as shown is normally reverse biased and therefore nonconductive by the voltage difference across it equalling the sum of the two base-emitter voltage drops of transistors 30 and 31, but is forward biased and therefore rendered conductive under certain conditions in response to positive-going transients at the emitter of transistor 30, corresponding to the output terminal of driver stage 15. The arrangement of transistor 31 prevents the amplifier feedback loop including transistors 20, 21 and 31 and resistors 36 and 38 from being disrupted, thereby preventing feedback transients and signal ringing from occurring. Additional details of the arrangement including transistors 30 and 31 and diode 39 are found in my copending U.S. patent application Ser. No. 758,954 titled "FEEDBACK DISPLAY DRIVER STAGE".
The emitter voltage of transistor 30 follows the voltage developed across load resistor 27, and transistor 30 conducts the kinescope cathode current. Substantially all of the kinescope cathode current flows as collector current of transistor 30, through a kinescope arc current limiting protection resistor 37a, to a clamping network 40. Transistor 30 acts as a current sensing device in conjunction with network 40 as will be explained. Clamping network 40 in this example is self-keyed to exhibit clamping and non-clamping states in response to the magnitude of the current conducted by transistor 30.
Clamping network 40 is common to all three driver stages of the receiver, as will be seen subsequently in connection with FIG. 2, and is coupled to the green and blue signal driver stages via protection resistors 37b and 37c. Network 40 includes clamping transistors 41 and 42 arranged in a Darlington configuration, and series voltage divider resistors 43 and 44 which bias clamp transistors 41 and 42. A high frequency bypass capacitor 46 filters signals in the collector circuit of transistor 30 in a manner to be described below. The series combination of a mode control switch 49 and a scaling resistor 48 is coupled across resistors 43 and 44. A voltage related to the magnitude of kinescope current is developed at a terminal A and, as will be explained with reference to FIG. 2, the voltage at terminal A can be used in conjunction with a feedback control loop to maintain a desired kinescope operating current condition which is otherwise subject to deterioration due to kinescope aging and temperature effects, for example.
Assuming switch 49, the function of which will be explained below, is open, the kinescope cathode current flowing in the collector of transistor 30 is conducted to ground via resistors 43 and 44. When this current causes a voltage drop across resistor 44 to sufficiently forward bias the base-emitter junctions of transistors 41 and 42, transistor 42 will conduct in a linear region, and will clamp terminal A to a voltage VA according to the following expression, where V BE41 and V BE42 are the base-emitter junction voltage drops of transistors 41 and 42: VA=(V BE41 +V BE42 ) (R43+R44)/R44
During normal image intervals typically there are greater than approximately 25 microamperes of current conducted by transistor 30, which is sufficient to render transistors 41 and 42 conductive for developing clamping voltage VA at terminal A. At other times, as will be discussed, transistors 41 and 42 are rendered nonconductive whereby clamping action is inhibited and a (variable) voltage is developed at node A as a function of the magnitude of the kinescope cathode current, for processing by succeeding control circuits.
Illustratively, the arrangement of FIG. 1 can be used in connection with digital signal processing and control circuits in a color television receiver employing digital signal processing techniques, as will be seen in FIG. 2. Such control circuits include an input analog-to-digital converter (ADC) for converting analog voltages developed at terminal A to digital form for processing.
When the control circuits are to operate in an automatic kinescope black current (bias) control mode, wherein during image blanking intervals the kinescope conducts very small cathode currents on the order of a few microamperes, approximating a kinescope black image condition, clamp transistors 41 and 42 are rendered nonconductive because such small currents flowing through resistors 43 and 44 from the collector of transistor 30 are unable to produce a large enough voltage drop across resistor 44 to forward bias transistors 41 and 42. Consequently terminal A exhibits voltage variations, as developed across resistors 43 and 44, related to the magnitude of kinescope black current. The voltage variations are processed by the control circuits coupled to terminal A to develop a correction signal, if necessary, to maintain a desired level of kinescope black current conduction by feedback action. In this operating mode switch 49, e.g., a controlled electronic switch, is maintained in an open position as shown in response to a timing signal VT developed by the control circuits.
When the control circuits are to operate in an automatic kinescope white current (drive) control mode wherein during image blanking intervals the kinescope conducts much larger currents representing a white image condition, switch 49 closes in response to timing signal VT, thereby shunting resistor 48 across resistors 43 and 44. The value of resistor 48 is chosen relative to the combined values of resistors 43 and 44 so that the larger current conducted via the collector of transistor 30 divides between series resistors 43, 44 and resistor 48 such that the magnitude of current conducted by resistors 43 and 44 is insufficient to produce a large enough voltage drop across resistor 44 to render clamping transistors 43 and 44 conductive. Unclamped terminal A therefore exhibits voltage variations related to the magnitude of kinescope white current, which voltage variations are processed by the control circuits to develop a correction signal as required. As used herein, the expression "white current" refers to a high level of individual red, green or blue color image current, or to combined high level red, green and blue currents associated with a white image.
With the illustrated configuration of transistors 41 and 42 clamping voltage VA is relatively low, approximately +2.0 volts. The clamping voltage could be provided by a Zener diode rather than the disclosed arrangement of Darlington-connected transistors 41 and 42, but the disclosed clamping arrangement is preferred because Zener diodes with a voltage rating less than about 4 volts usually do not exhibit a predictable Zener threshold voltage characteristic, i.e., the "knee" transition region of the Zener voltage-vs-current characteristic is usually not very well defined. In addition, the disclosed transistor clamp operates with better linearity than a Zener diode clamp and radiates less radio frequency interference (RFI).
The relatively low clamping voltage is compatible with the analog input voltage requirements of the analog-to-digital converter (ADC) at the input of the control circuits which receive the sensed voltage at terminal A as will be explained in greater detail with respect to FIG. 2. In this example the ADC is intended to process analog voltages of from 0 volts to approximately +2.5 volts, and the clamping voltage assures that excessively high analog voltages are not presented to the ADC during normal video signal intervals.
The relatively low clamping voltage also assists to prevent transistor 30 from saturating, which is necessary since transistor 30 is intended to operate in a linear region. To achieve this result and to maximize the cathode current conduction capability of transistor 30, the clamping voltage should be as low as possible to maintain a suitably low bias voltage at the collector of transistor 30. On the other hand, the value of arc current limiting resistor 37a should be large enough to provide adequate arc protection without compromising the objective of maintaining the collector bias voltage of transistor 30 as low as possible. Operation of transistor 30 in a saturated state renders transistor 30 ineffective for its intended purpose of properly conveying video drive signals to the kinescope cathode, and for conveying accurate representations of cathode current to clamping network 40 particularly in the white current control mode when relatively high cathode current levels are sensed. In addition, undesirable radio frequency interference (RFI) can be generated by transistor 30 switching into and out of saturation. Also, when saturation occurs transistor base storage effects can result in video image streaking due to the time required for a transistor to come out of a saturated state.
Thus clamping network 40 advantageously limits the voltage at terminal A to a level tolerable by the analog-to-digital converter at the input of the control circuits coupled to terminal A, and protects the analog-to-digital converter input from damage due to signal overdrive. Network 40 also provides a collector reference bias for transistor 30 to prevent transistor 30 from saturating on large negative-going signal amplitude transitions at its emitter electrode. The clamping voltage level is readily adjusted simply by tailoring the values of resistors 43 and 44.
Capacitor 46 bypasses high frequency video signals to ground to prevent transistor 30 from saturating in response to such signals. Capacitor 46 also serves to smooth out undesirable high frequency variations at terminal A to prevent potentially troublesome signal components such as noise from interfering with the signal processing function of the input analog-to-digital converter of the control circuits, e.g., by smoothing the current sensed during the settling time of the analog-to-digital converter.
The latter noise reducing effect is particularly desirable, for example, when the input ADC of the control circuits coupled to terminal A is of the relatively inexpensive and uncomplicated "iterative approximation" type ADC, compared to a "flash" type ADC. The operation of an iterative ADC, wherein successive approximations are made from the most significant bit to the least significant bit, requires a relatively constant or slowly varying analog signal to be sampled during sampling intervals, uncontaminated by noise and similar effects.
The value of capacitor 46 should not be excessively large because a certain rate of current variation should be permitted at terminal A with respect to kinescope cathode currents being sensed. If the value of capacitor 46 is too small, excessive voltage variations, particularly high frequency video signal variations, will appear at terminal A, increasing the likelihood of transistor 30 saturating. The speed of operation of the clamp circuit itself is restricted by an RC low pass filter effect produced by the base capacitance of transistor 41 and the equivalent resistance of resistors 43 and 44.
FIG. 2 shows a portion of a color television receiver system employing digital video signal processing techniques. The FIG. 2 system utilizes kinescope driver amplifiers and a clamping network as disclosed in FIG. 1, wherein similar elements are identified by the same reference number. By way of example, the system of FIG. 2 includes a MAA 2100 VCU (Video Codec Unit) corresponding to video signal source 10 of FIG. 1, a MAA 2200 VPU (Video Processor Unit) 50, and a MAAA 2000 CCU (Central Control Unit) 60. The latter three units are associated with a digital television signal processing system offered by ITT Corporation as described in a technical bulletin titled "DIGIT 2000 VLSI DIGITAL TV SYSTEM" published by the Intermetall Semiconductors subsidiary of ITT Corporation.
In unit 10, a luminance signal and color difference signals in digital form are respectively converted to analog form by means of digital-to-analog converters (DACs) 70 and 71. The analog luminance signal (Y) and analog color difference signals r-y and b-y are combined in a matrix amplifier 73 to produce r, g and b color image representative signals which are processed by preamplifiers 75, 76 and 77, respectively, before being coupled to kinescope driver stages 15, 16 and 17 of the type shown in FIG. 1. A network 78 in unit 10 includes circuits associated with the automatic white current and black current control functions.
The high level R, G and B color signals from driver stages 15, 16 and 17 are coupled via respective current limiting resistors (i.e., resistor 33) to cathode intensity control electrodes of a color kinescope 80. Currents conducted by the red, green and blue kinescope cathodes are conveyed to network 40 via resistors 37a-37c, for producing at terminal A a voltage representative of kinescope cathode current conducted during measuring intervals, as discussed previously.
VPU unit 50 includes input terminals 15 and 16 coupled to terminal A. Through terminal 15 the VPU receives the analog signal from terminal A and, via an internal multiplex switching network 51, the analog signal is supplied to an analog-to-digital-converter (ADC) 52. Terminal 16 is connected to an internal switching device (corresponding to switch 49 in FIG. 1) which, in conjunction with scaling resistor 48, controls the impedance and therefore the sensitivity at input terminal 15. High sensitivity for black current measurement is obtained with resistor 48 ungrounded by internal switch 49, and low sensitivity for white current measurement is obtained with resistor 48 grounded by internal switch 49.
The digital signal from ADC 52 is coupled to an IM BUS INTERFACE unit 53 which coacts with CCU unit 60 and provides signals to an output data multiplex (MPX) unit 55. Multiplexed output signal data from unit 55 is conveyed to VCU unit 10, and particularly to control network 78. Control network 78 provides output signals for controlling the signal gain of preamplifiers 75, 76 and 77 to achieve a correct white current condition, and also provides output signals for controlling the DC bias of the preamplifiers to achieve a correct black current condition.
More specifically, during vertical image blanking intervals the three (red, green, blue) kinescope black currents subject to measurement and the three white currents subject to measurement are developed sequentially, sensed, and coupled to VPU 50 via terminal 15. The sensed values are sequenced, digitized and coupled to IM Bus Interface 53 which organizes the data communication with CCU 60. After being processed by CCU 60, control signals are routed back to interface 53 and from there to data multiplexer 55 which forwards the control signals to VCU 10.

PHILIPS  28DC2271/02R  CHASSIS D16-MAC (D2MAC SATELLITE)  (DIGI16-MAC) D-MAC

The MAC system was originally proposed as the analog standard for European HDTV, to be started in 1995. However, MAC never made it in Europe, but was insteda used for satellite broadcasts using standrd resolution. A d igital + analog system, used only for satellite TV broadcasts. There are five different versions of MAC: A-MAC, B-MAC, C-MAC, D-MAC and
D2-MAC.

B-MAC is used in North America, Australia and South Africa. C-MAC and D-MAC are used in the U.K. and parts of Scandinavia. D2-MAC is used in the rest of Western Europe.

MAC transmits luminance and chrominance data separately, i.e. separates them in time instead of frequency. Each line contains three components:
   a) Synch/data/sound, 198 bits, 10 us
b) Chrominance, 17.5 us
c) Luminance, 35 us
The luminance Y = R+G+B. The chrominance vaguely resembles SECAM: even lines carry V = R-Y and odd lines U = B-Y. MAC uses a line-sequential colour system, but sophisticated vertical filtering produces much better results than would be obtained by simply omitting alternate lines or taking the average value of adjacent lines.

(625-line version): each line of 64 microseconds contains:
Lines 1 to 623:
206 bits of synchronization, sound and data:
     1 run-in bit
     6 bits of line sync word
  198 bit of data, in two subframes of 99 bits each
    1 spare bit
4 clock periods for transition from end-of-data
15 clock periods - clamp period
10 clock periods, incl. 5 clocks for weighted transition to colour signal
349 clock periods of colour-difference component
5 clock periods for weighted transition btw colour and luminance signal
697 clock periods of luminance component
6 clock periods for weighted transition from luminance signal
4 clock periods for transition into data
--------------------------------------------------------------------------
1296 clock periods total per line, eack clock period ca 49.38 ns
Lines 624 and 625 are special:
Line 624:
174 bits  ???
32 bits  Clamp marker
1090 bits  Reference signals instead of video

Line 625 contains frame synchronization information:
1 bit   Demod run-in bit
6 bits  Line sync word
32 bits  Clock run-in bits
64 bits  Frame sync word bits
1193 bits  Service identification data
The MAC waveform can be considered an analogue signal sampled at a rate of 20.25 MHz.

MAC is especially dsigned to be used over the FM satellite channels. Its various parameters have been chosen so as to make the best possible use of the available spectrum. Chrominance and luminance signal/noise ratios have been well matched to the characteristics of an FM channel, so that a significant improvement in noise performance is noticeable on the image, compared to PAL/SECAM/NTSC satellite broadcasts. In addition, there is no crosstalk between the luminance and chrominance signals.
                     C-MAC      D-MAC    D2-MAC

Stereo channels        4         3         2
2x15 kHz each

Min bandwidth, MHz    15        10         5
On a 7 MHz channel, max luminance bandwidth becomes 4.6 Mhz and max chrominance bandwidth 1.2 MHz. On PAL, max luminance bandwitth is 3.8 MHz.
The DMA 2271, DMA 2280, and DMA 2281 C/D/
D2–MAC Decoders
1. Introduction
1.1. General Information
Digital real–time signal processor for processing C/D/
D2–MAC video, sound, and data signals digitized by the
VCU 2133 Video Codec in digital CTV receivers according
to INTERMETALL's DIGIT 2000 system of or in analog
CTV receivers or in stand–alone C/D/D2–MAC decoders
(see Figs. 1–1 to 1–3).
In order to receive TV channels transmitted via satellite
or cable network using the newly established C/D/
D2–MAC standards instead of PAL or SECAM, decoders
are required for decoding the TV video and sound
signals. The DMA 2271, DMA 2280, and DMA 2281 are
suitable for this purpose, in conjunction with the DIGIT
2000 digital TV system and also for stand–alone solutions.
The DMA 2271 is only able to decode D2–MAC/packet
signals, in contrast to the DMA 2280 which decodes D–
MAC/packet signals and the DMA 2281 which decodes
D2, D or C–MAC/packet signals.
The DMA 2271, DMA 2280, and DMA 2281 are a programmable
circuits, produced in CMOS technology and
housed in a 68–pin PLCC package. These decoders
contain on a single silicon chip the following functions
(see Fig. 1–4):
– code converter
– circuitry for clamping, AGC and PLL
– chroma and luma store for expansion of the MAC signal
– chroma and luma interpolating filter
– contrast multiplier with limiter for the luminance signal
– color saturation multiplier with multiplexer
– duobinary decoder (data slicer)
– synchronization
– descrambler and de–interleaver
– packet linker
– packet 0 buffer
– sound decoder and sound multiplexer
– IM bus interface circuit for communicating with the
CCU.

Pin Descriptions
Pin 1 – RAM Data Input/Output RDAT (Fig. 2–7)
serves as an output for writing data into the external
RAM and as an input for reading data from the external
RAM.
Pins 2 to 6 and 9 to 11 – RAM Address Outputs RA0 to
RA7 (Fig. 2–10)
These pins are used for addressing the external RAM.
Pin 7 – RAM Read/Write Output R/WQ (Fig. 2–10)
By means of this output the external RAM is switched to
read or write mode.
Pin 8 – Row Address Select Output RASQ (Fig. 2–10)
This pin supplies the Row Address Select signal to the
external RAM.
Pins 12 to 14 – IM Bus Connection IMC, IMI,IMD (Figs.
2–2 and 2–6)
These pins connect the DMA 2271, DMA 2280 and DMA
2281 to the IM bus. Via the IM bus the DMA 2271, DMA
2280 and DMA 2281 communicate with the CCU 3000
Central Control unit. The data transferred via the IM bus
are listed in tables 4–1 to 4–4.
Pin 15 – Reset Input RESQ (Fig. 2–5)
Pin 15 is used for hardware reset. Reset is actuated at
Low level, at High level the DMA 2271, DMA 2280, and
DMA 2281 are ready for operation.
Pins 16 and 17 – XTAL 1 Output and XTAL 2 Input (Fig.
2–11)
These oscillator pins are used to connect an 18.432
MHz crystal, which determines the ACLK audio clock
signal supplied by pin 65. Alternatively, an 18.432 MHz
clock may be fed to pin 17.
Pin 18 – Output Disable Input ODI
This input serves for fast switchover of the luma and
chroma outputs (L0 to L7 and C0 to C7) to high impedance,
which is required if the TV receiver is equipped
with Picture–in–picture. Low means outputs active, High
means outputs are disabled.
Pin 19 – leave vacant
Pin 20 – leave vacant
Pins 21 to 24 and 27 to 30 – Chroma Outputs C7 to C0
(Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280, and DMA
2281 deliver the digital chrominance signal (R–Y, B–Y)
in multiplexed operation to the VCU 2133 Video Codec
Unit, where it is converted to an analog signal.
Pin 25 – PLL Tuning Data Output PLLD (Fig. 2–8)
This pin supplies the 12–bit data word containing the
PLL tuning information from the PLL filter of the DMA
2271, DMA 2280, and DMA 2281. This information is
needed by the voltage controlled oscillator (VCO) contained
on the MCU 2600 Clock Generator IC and closes
the PLL which determines the main clock signal.
Pin 26 – PLL Tuning Clock Output PLLC (Fig. 2–8)
This pin supplies the data clock signal needed for the serial
data transfer of the 12–bit PLL tuning information.
Pins 31 to 38 – Luma Outputs L0 to L7 (Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280 and DMA
2281 deliver the digital luminance signal to the VCU
2133 Video Codec Unit, where it is converted to an analog
signal.
Pins 39 to 46 – Baseband Input BI7 to BI0 (Fig. 2–3)
Via these inputs, the DMA 2271, DMA 2280, and DMA
2281 receive the digitized baseband signal from the
VCU 2133 Video Codec.
Pin 47 – leave vacant
Pin 48 – Clamping Output CLMP (Fig. 2–9)
This pin supplies a PDM (Pulse Density Modulated) signal
for clamping the analog baseband signal at the input
of the analog to digital converter.

Pin 49 – AGC Output AGC (Fig. 2–9)
This tristate–controlled output allows automatic gain
control (AGC) with a three–level signal. High level
means that the input level of the baseband signal is too
low, low level means that the input level of the baseband
signal is too high. In the high impedance state the level
of the baseband signal is in the proper range.
Pin 50 – Combined Output for Horizontal Blanking and
Color KEY (Fig. 2–9)
This output is a tristate–controlled output. In conjunction
with the input load represented by the VCU 2133 Video
codec, the three level blanking and key is produced.
High level means active line, high impedance state
means horizontal blank and low level means color key.
Pin 51 – Combined Output for Horizontal Blanking and
Vertical Blanking CBL (Fig. 2–9)
In conjunction with the input load represented by the
VCU 2133 Video Codec, the three level combined blanking
pulse is produced. High level means active line, high
impedance means horizontal blanking and low level
means vertical blanking.
Pin 52 – Data Burst Window DBW (Fig. 2–9)
This output supplies the data burst window signal which
can be used to switch an external de–emphasis network.
This signal is active high in line 625 and during the
data burst in each line.
Pin 53 – Composite Sync Output CSYNC (Fig. 2–8)
This output supplies a composite synchronization signal
as it may be used by the DPU 25xx Deflection Processor
or by other units which need a composite synchronization
signal which is not contained in the MAC baseband
signal.
Pin 54 – Test Input/Output T0 (Fig. 2–8)
This pin is used for testing the DMA 2271, DMA 2280,
and DMA 2281 during production.
Pin 55 – Packet Data Output PDAT (Fig. 2–10)
PDAT is used to put out each received packet, de–interleaved,
with Golay corrected header and with error–corrected
BT Byte. This pin used to connect the DMA 2275,
DMA 2285 or DMA 2286 Descrambler IC.
Pin 56 – Descrambled Packet Data Input DPDAT (Fig.
2–2)
This pin is used in conjunction with PDAT, if conditional
access signals must be descrambled, DPDAT receives
the descrambled packet data from the DMA 2275, DMA
2285 or DMA 2286 Descrambler IC.
Pin 57 – Teletext Sync Output TSYNC (Fig. 2–9)
This pin supplies a signal which marks the part of the VBI
lines containing Teletext data.
Pin 58 – Burst Sync Output BSYNC (Fig. 2–4)
This connection supplies a synchronization signal for
the Burst Data Output. The Sync Pulse marks the Line
Synchronization Word LWS of each, and the Clock Run
In CRI and Frame Sync Word FSW in line 625.
Pin 59 – Burst Data Output BDAT (Fig. 2–4)
This output supplies the recovered an decoded duobinary
data contained in a MAC signal. This signal may serve
as an input signal for the TPU 27xx Teletext Processor
or the DMA 2275, DMA 2285, DMA 2286 MAC Descrambler
processor or for other purposes.
Pin 60 – Burst Clock Output BCLK (Fig. 2–9)
This pin supplies the data clock signal required for the
serial data transfer of the Burst Data signal. The frequency
of this signal is equal MCLK or MCLK/2 controlled
by parameter Data Rate Select DRS via IM Bus.
Pin 61 – Ground GND
Pin 62 – Main Clock Input MCLK (Fig. 2–4)
By means of this input, the DMA 2271, DMA 2280 and
DMA 2281 receive the required main clock signal from
the MCU 2600 Clock Generator IC.
Pin 63 – Supply VSUP
Pin 64, 66, and 67 – Sound Bus Ident SBI (Fig. 2–9)
Data SBD and Clock SBC (Fig. 2–8)
These pins supply the Clock, Data and Ident signals to
the AMU 2481 Mixing Unit via the serial three–line
Sound Bus.
Pin 65 – Audio Clock Output ACLK (Fig. NO TAG)
This pin supplies the ACLK Audio Clock signal for the
AMU 2481.
Pin 68 – Column Address Select CASQ (Fig. 2–10)
This pin supplies the Column Address Select signal for
the external RAM.


Functional Description
The DMA 2271, DMA 2280 and DMA 2281 process the
digitized D2–MAC video signal supplied by the VCU
2133 or by the UVC 3130 in the various circuit parts
shown in Fig. 1–4. The resulting digital luminance and
chrominance signals are then reconverted to analog signals
in the VCU or HDAA. The resulting digital audio signals
are processed in the AMU 2481 Audio Mixer which
provides filtering of the medium–quality channels and allows
mixing of the four sound channels. The AMU’s digital
output signals are reconverted to analog in the ACP
2371 Audio Processor, which additionally carries out
functions like adjustment of volume, bass and treble,
loudness, etc. Remaining digital data as service and
channel information in packet 0 or line 625 can be handled
by software via the IM bus or by additional hardware
which uses the serial B–Data interface (B–Data, B–
Clock and B–Sync). Section 1.2. shows how the DMA
2271, DMA 2280 and DMA 2281 can be used together
with other circuits of INTERMETALLS’s DIGIT 2000 digital
TV system to realize a multistandard
NTSC/PAL/SECAM/C/D/D2–MAC color TV receiver.
To understand the signal processing in the DMA 2271,
DMA 2280, and DMA 2281 it may be useful to distinguish
three different function blocks, namely:
– Clock and Data Recovery
– Video Processing
– Sound/Data Processing
3.1. Clock and Data Recovery
3.1.1. The Code Converter
This circuit converts the digitized C/D/D2–MAC baseband
signal, delivered by the VCU 2133 in a parallel
Gray code, into a simple binary–coded signal. The function
of the circuit is controlled by the CCU 3000 via the
IM bus (see section 4.2.).
3.1.2. The Video Clamping Circuit and the AGC Circuit
The video clamping circuit measures the DC voltage level
of the clamp period and, by means of the pulse density
modulated signal from pin 48, sets the DC level of the
clamp period to a constant 5.5 V. The white and the black
levels in line 624 are measured for automatic gain control
(AGC pin 49) and the two values are fed to the IM
bus interface which organizes the data communication
with the CCU.
AGC (pin 49) = high if WL – BL < 224
AGC (pin 49) = high impedance if 224 3 WL – BL 3 240
AGC (pin 49) = low if WL – BL > 240
3.1.3. The Phase Comparator and the PLL Filter
The phase comparator derives the reference signal from
the slopes contained in the data burst of each line. Its
output signal, an 8–bit word which is passed through a
digital lowpass filter, is added to an 8–bit word, VCOA,
which is provided by the CCU for adjustment of the crystal
frequency. This digital PLL signal is output via pins 25
and 26 and routed to the MCU 2600 Clock Generator IC
thus closing the PLL, existing between DMA 2271, DMA
2280, and DMA 2281, VCU 2133 Video Codec and MCU
2600 Clock Generator IC. In this way, the main clock signal
FM of the system is in phase with the duobinary–
coded signal.
To adjust the crystal frequency, it is possible to render inoperative
the PLL by setting PLLO bit 4 in address 201
(Table 4–1). The VCO in the MCU is then free–running
and the center frequency can be aligned by varying the
data word VCOA (bits 0 to 7) in the IM bus address 14.
3.1.4. The Data Slicer and the Synchronization Circuit
The digitized C/D/D2–MAC baseband signal is filtered
by a 5 MHz lowpass filter before being routed to the data
slicer. The output of the slicer is connected to pin 59 (B–
Data). In phase with the continuous bit stream of 20.25
or 10.125 MBit/s, a clock signal (B–Clock), a synchronization
signal (B–Sync) and a signal for Teletext information
(TTSYNC) are available at pins 60, 58, and 57 (see
Fig. 2–15).
The vertical synchronization pulse, on–chip, is derived
from a 64–bit correlator which compares the data stream
at the output of the slicer with the fixed Frame Synchronization
Word (FSW). Whenever the correlation is equal
to or greater than 61 a frame reset pulse is generated.
Horizontal synchronization is derived by counting. In
phase with the video outputs (L0 to L7, C0 to C7), the
various synchronization and blanking signals are outputs
at pins 50 to 53 (Fig. 2–17, 2–18 and 2–18).
3.2. Video Processing
The DMA 2271, DMA 2280, and DMA 2281 process the
C/D/D2–MAC baseband signal, digitized by the VCU or
UVC at a sample frequency of 20.25 MHz. For time expansion,
the video samples of each line are stored in an
on–chip RAM and read to at the lower frequencies of
13.5 MHz for the luminance signal and 6.75 MHz for the
color difference signals.
3.2.1. The Luminance Store
Time expansion of the luminance signal is achieved by
digitizing the analog signal at a clock frequency of 20.25
MHz, storing the Bytes, and reading them at a frequency
of 13.5 MHz. For this, a fast RAM is provided on–chip.

3.2.2. The Luminance Interpolating Filter
An interpolation from 13.5 MHz to 20.25 MHz is performed
in order to overcome the need for a second system
clock of 13.5 MHz and to simplify the reconstruction
filters placed after the D/A conversion (RGB outputs of
the VCU). The interpolation filter has a linear phase and
can be switched to broad or narrow bandwidth by means
of the CCU via the IM bus (bits 10 and 11, address 201).
The different frequency responses are shown in Fig.
2–20 and in Table 2–1.
3.2.3. The Contrast Multiplier
After the luminance interpolating filter is a contrast multiplier.
The contrast setting is controlled by the CCU via
the IM bus (bits 10 to 15, address 200), depending on the
user’s instruction. From the contrast multiplier, the digital
luminance signal is fed back to the VCU 2133 in the
form of an 8–bit signal. In the VCU, this signal is converted
from digital to analog and fed to the RGB matrix.
The setting range of the contrast multiplier comprises 6
bits (64 steps). If the product at the multiplier’s output is
higher than the working range, the largest possible number
is output.
3.2.4. The Chrominance Store
The chrominance store contains the color information
for 3 lines. It is used for time expansion and line interpolation.
The input frequency is 20.25 MHz, the output frequency
6.75 MHz.
3.2.5. The Line Interpolating Filter
The color difference signals are transmitted within alternate
lines as U and V. A “1, 2, 1” post–filter required to
interpolate the color difference information is implemented.
The action of the filter is for even lines:
U = Un, V = Vn–1 + Vn +1
2
and for odd lines:
U = Un–1 + Un +1
2
, V = Vn
3.2.6. The Chrominance Interpolating Filter
After the line interpolating filter the 8–bit color difference
signals U and V are routed to the chroma interpolating
filter which has linear phase and can be switched to different
frequency responses via the IM bus (Fig.
NO TAG, Table 2–2) using bits 13 to 15 in address 201.
This filter is used for conversion of the sample rate from
6.75 MHz up to 10.125 MHz.
3.2.7. The Color Saturation Multiplier
The digital color difference signals U and V are routed to
a color saturation multiplier, whose setting is also controlled
by the CCU via the IM bus (address 23). The
range of the multiplier comprises 6 bits, with each color
difference signal being set independently.
The PAL matrix in the VCU requires a compensation factor
of 0.71. This means that the color saturation factor for
(B – Y) is equal to 0.71 the color saturation factor for
(R – Y). Both factors are calculated in the CCU.
3.2.8. The Color Multiplexer
The color difference signals are transferred back to the
VCU 2133 in multiplex via a 4–line bus. Demultiplexing
takes place in the VCU. The digital signals are then reconverted
to analog. Subsequently they are dematrixed
in the RGB matrix together with the Y signal, giving the
RGB signals which drive the output amplifiers of the
VCU 2133 Video Codec.
The color multiplexer can drive a 4–line bus with an effective
sample rate of 5.6025 MHz for each color difference
signal or an 8–line bus with a sample rate of 10.125
MHz. This function is controlled by the IM bus (Table
4–1), using bit 6 in address 201.
3.3. Sound/Data Processing
This section begins with a descrambler and de–interleaver.
The descrambler uses the same pseudo–random
binary sequence (PRBS) generator as is used for
the scrambling process. Its clock rate is 10.125 MHz or
20.25 MHz. The de–interleaver corrects the succession
of the transmitted packet bits which are interleaved in order
to minimize the effect of multiple bit errors.

3.3.1. The Golay and PT Byte Decoder
The data format has changed now from data burst format
(99 bits) to packet format (751 bits). The header of
each packet contains defined addresses for the different
sound and data services and four bits representing the
sound characteristics. The PT Byte of each packet distinguishes
between sound and data packets. After correction
of header and PT Byte with the Golay and PT
Byte decoder, this information is used for automatic configuration
of the DMA 2271, DMA 2280, and DMA 2281.
In addition, the Golay decoder is used for measuring the
bit error rate of the transmission channel. The bits in error
in each packet header are accumulated over one
frame (82 packets). The sum is stored in IM bus register
206 (Table 4–2) and can be read by the CCU which may
control different muting functions.
3.3.2. The Address Comparator
The DMA 2271, DMA 2280, and DMA 2281 D2–MAC
Decoders are able to treat different sound services automatically
by decoding the address field of the packet
header. The two continuity bits CI1 and CI0 are used to
link successive packets of the same service in case of
a 120 Byte sound coding service.
Among the different coding characteristics all combinations
are possible. The user can select up to four sound
channels simultaneously by programming the sound
services via the IM bus (address 203, 194, 195 and 196).
These addresses are compared with the address of
each transmitted sound packet. At correspondence, this
packet is selected and decoded.
3.3.3. The Sound Decoder
The sound decoding section converts all types of selected
sound packets into a sequence of 14–bit sound
samples. The medium–quality channels are up–
sampled to the 32 kHz sampling frequency of the high–
quality channels, i.e. every sample of a medium–quality
channel is put out twice, the second time as a zero sample.
The second part of the interpolation is performed in
the AMU 2481 Audio Mixer where two oversampling filters
are provided. The error correction section uses a
range check and/or Hamming decoder, depending on
the sound coding mode. The Hamming decoder is able
to correct one error per sample and to detect double errors.
The range check uses the highly protected scale
factor bits to check the MSBs of each sample. Its error
correction and detection abilities are shown in Table
3–2.
Erroneous samples, i.e. samples with uncorrectable errors,
are concealed by replacement with interpolated adjacent
samples. The storage capacity for buffering the
sound samples during processing and for obtaining a
smooth, regular output of sound samples is provided by
an external 64–K DRAM. To ensure the continuity of output
sound samples in case of packet loss or packet gain,
the silence information is used and blocks of samples
corresponding to “silence” are repeated or omitted.
3.3.4. The Sound Multiplex
After extension from 14 bits to 16 bits, the sound samples
of the four channels are loaded into a 64–bit shift
register and transferred to the AMU 2481 Audio Mixer
via a serial 3–lines S bus. Fig. 2–14 shows the S bus timing.

3.3.5. The FA Audio Clock
The audio clock FA for the AMU 2481 Audio Mixer and
the ACP 2371 Audio Processor is also supplied by the
DMA 2271, DMA 2280 and DMA 2281 which generate
this 18.432 MHz clock by means of the crystal connected
to pins 16 and 17 and supply it via pin 65. The frequency
of 18.432 MHz is an integer multiple of the sound
sampling frequency (32 kHz).
The FA audio clock output pin 65 can be switched over
to the normal main clock FM if a standard other than C/
D/D2–MAC is received. For this, bit ACS in address 204
of the IM bus is provided (Table 4–1).
The clock frequency FS for the serial S bus is also
derived from the audio clock FA (pin 65) by dividing by
eight (18.432 MHz: 4 = 4.608 MHz)
3.3.6. The Buffer for Packet 0
One packet address (000H) is reserved for service and
network identification data. A 720–bit (90 Byte) Buffer is
implemented on–chip especially for this, and is controlled
by the CCU via the IM bus (bits 8 and 9, address
204). The following conditions must be met to ensure
that a received packet is stored in this buffer:
Packet Address PA = 000H
Packet Type PT = F8H
Data Group Type TG = selected type in IM bus
register 204
Packet 0 Status P0 = 0 (see IM bus registers 204
and 206)
The packet 0 buffer can be read sequentially from a
16–bit IM bus register (address 210, Table 4–2). One
complete read cycle takes about 1.5 ms (IM bus frequency
= 1 MHz). It is possible to reset and to clear the
buffer via the IM bus in order to repeat the last–read
cycle or to receive the next zero packet. Additionally, the
last 16 bits of the zero packet are used for error checking.
This CRC check calculates the 16–bit syndrom vector
of the packet concerned and stores it in an IM bus
register. It can then be used by software for error detection.



The AMU 2481 Audio Mixer is a digital real–time signal
processor in NMOS technology, housed in a 24–pin Dil
plastic package or in a 44–pin PLCC package. It is designed
to perform digital processing of both TV audio information
and digital audio data supplied by the
DMA 2271 D2–MAC Decoder. The architecture of the
AMU 2481 combines two main blocks:
– I/O blocks
– DSP block
The I/O blocks are used to manage the input and output
of audio information. The DSP block consists of a mask–
programmable digital signal processor, whose software
can be controlled by a microprocessor (CCU) via the IM
bus. So parameters like coefficients can be modified
during performance. By means of the DSP software, audio
functions, such as deemphasis, oversampling mixing
and volume control are performed. Fig. 1–1 gives an
overview over the AMU’s functions.
1.1. Application of the AMU 2481
The AMU 2481 Audio Mixer is designed to interface with
INTERMETALL’s ADC 2311 E Audio A/D Converter,
DMA 2271 D2–MAC Decoder on the input side, and with
the APU 2471 or the ACP 2371 Audio Processors on the
output side. It can receive digital audio data in two different
formats:
Via the PDM inputs, the AMU 2481 is supplied with two
1–bit PDM data streams produced by the ADC 2311 E
Audio A/D Converter which receives analog audio information
either from the SCART interface (Euro connector),
which is used, e.g., for video recorder connection,
or from any terrestrial TV transmission. For this input format,
decimation filters are provided in the AMU 2481,
which convert each PDM stream into a 16–bit word at
a sampling rate of approximately 32 kHz.
Via the S bus interface the AMU 2481 receives serial
audio data, provided, e.g., by the DMA 2271 D2–MAC
Decoder.
Fig. 1–2 shows how the AMU 2481 can be used together
with the mentioned ICs of INTERMETALL to realize
multistandard audio processing with PAL and D2–MAC
signals. In the following descriptions data coming from
the ADC will be called “PDM data” and data coming from
the DMA will be called “S data”.

Digital Decimation Filters
The digital decimation filters are cascades of transversal
and recursive lowpass filters. They are required to convert
the two 1–bit PDM data streams by stepwise reduction
of bandwidth and word rate (sampling rate) into two
PCM data streams with 16 bit word length and a sampling
rate of approximately 32 kHz, which in the following
are called PCM data 1 and 2. They are temporarily
stored in the corresponding locations of the AMU’s data
RAM.
As the two PDM data streams at the input of the decimation
filters have no separate clock signal, the decimation
filters are equipped with a synchronization facility. This
feature also supplies the AMU software with the sampling
clock (approx. 32 kHz), which is called ”I/O Sync”
or IOSYNC. More details on data/clock timing can be
found in section 2.3.

Description of the S–Bus
The S–bus was designed to connect the digital sound
output of the DMA 2271 D2/MAC Decoder to audio–
processing ICs such as the AMU 2481 Audio Mixer or
the APU 2471 Audio Processor etc., and to connect
these ICs with each other. The S–bus is an unidirectional,
digital bus which transmits the sound information
in one direction only, so that it is not necessary to solve
priority problems on the bus.
The S–bus consists of the three lines S–Clock, S–Ident
and S–Data. The DMA 2271 generates the signals S–
Clock and S–Ident, which control the data transfer to and
between the various processors which follow the DMA
2271. For this, the S–Clock and S–Ident inputs of all
processors in the system are connected to the S–Clock
and S–Ident outputs of the DMA 2271. S–data output of
the DMA 2271 is connected to the S–Data input of the
next following AMU, the AMU’s S–Data output is connected
to the APU’s S–Data input and so on.
The sound information is transmitted in frames of 64 bits,
divided into four successive 16–bit samples. Each sample
represents one sound channel. The timing of a complete
transmission of four samples is shown in Fig. 2–1,
the times are specified in “Recommended Operating
Conditions”. The transmission starts with the LSB of the
first sample. The S–Clock signal is used to write the data
into the receiver’s input register. The S–Ident signal
marks the end of one frame of 64 bits and is used as
latch pulse for the input register. The repetition rate of
the S–Ident pulses is identical to the sampling rate of the
D2–MAC sound signal; thus it is possible to transfer four
sound channels simultaneously.
2.1.2.2. The S–Bus Interface
The S–bus interface of the AMU 2481 mainly consists of
an input and an output register, each 64–bit wide. The
timing to write or read bit by bit is supplied by the S–
Clock signal. In the case of an S–Ident pulse, the contents
of the input register are transferred to the data
RAM (see section 2.2.1.) and the contents of the output
register are written to the S–Data output.
The S–Ident is also used as the sampling rate reference
for the DSP software in the case of digital source mode.
In this mode the IOSYNC generated by the decimation
filters is locked to the S–Ident. This allows a mixed
mode: S–Data and PDM Data can be processed simultaneously.
In this case, however, there must be the same
audio sample rate of PDM data and S–bus data (see
2.3.). If this is not the case, the S–Ident line has to be disabled.
By means of coefficient k33 (see section 3.13.) the AMU
2481 can be switched to an S–bus slave mode (bit 4=0)
or to an S–bus master mode (bit 4 = 1). The slave mode
is required in an application as shown in Fig. 1–2 where
the DMA 2271 D2–MAC Decoder acts as master on the
S–bus, i.e. the DMA 2271 supplies the S–Clock and S–
Ident signals as well as the S–Data input signal.
To enable parallel cascading of AMUs without external
switches, (e.g. NICAM to SCART and D2MAC to TV) in
the 44–PLCC package, the SBUS signals S–Ident and
S–Clock, (and the Main Clock, see section 2.3.) can be
passed through the AMU 2481. The corresponding
open–drain outputs can be switched to high impedance,
which is the default status after power–on reset. To
switch them on or off (high imp.), use the same bit that
controls the SBUS data output:
k33 bit3 = 0 outputs = active
= 1 outputs = high impedance
2.1.3. IM Bus Interface and IM Bus
2.1.3.1. Description of the IM Bus
The INTERMETALL Bus (IM Bus for short) was designed
to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master whereas all controlled ICs are slaves.The IM
bus consists of three lines for the signals Ident (ID),
Clock (CL) and Data (D). The clock frequency range is
50 Hz to 170 kHz. Ident and clock are unidirectional from
the CCU to the slave ICs, Data is bidirectional. Bidirectionality
is achieved by using open–drain outputs with
On–resistances of 150 Ohm maximum. The 2.5 kOhm
pull–up resistor common to all outputs is incorporated in
the CCU.The timing of a complete IM bus transaction is
shown in Fig. 2–2 and in the “Recommended Operating
Conditions”. In the non–operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, then sets the CL signal to Low level and
switches the first bit on the Data line.Then eight address
bits are transmitted, beginning with the LSB. Data takeover
in the slave ICs occurs at the positive edge of the
clock signal. At the end of the address byte the ID signal
goes High, initiating the address comparison in the slave
circuits. In the addressed slave the IM bus interface
switches over to Data read or write, because these functions
are correlated to the address.
Also controlled by the address the CCU now transmits
eight or sixteen clock pulses, and accordingly one or two
Bytes of data are written into the addressed IC or read
out from it, beginning with the LSB. The completion of
the bus transaction is signalled by a short Low state
pulse of the ID signal. This initiates the storing of the
transferred data.
It is permissible to interrupt a bus transaction for up to 10
ms.

For future software compatibility, the CCU must write a
zero into all bits not used at present. When reading undefined
or unused bits, the CCU must adopt “don’t care”
behavior.
2.1.3.2. IM Bus Interface
To write coefficient value(s) into the AMU2481 registers
the following steps have to be taken:
1. addressing the AMU2481 (allows multiprocessor system)
2. writing of 8 bit data into the IM bus interface registers
After having completed step 1, step 2 can be performed
as often as the communication between AMU 2481 and
CCU is required, on the condition that the processor address
has not been changed by the CCU.
Comments to the steps mentioned above: The syntax of
step 1 is identical to that of step 2. The CCU transmits
an 8–bit address to the IM bus interface of the AMU
2481, addressing a certain register or C–RAM location
of the AMU. The IM bus interface has to check this address
and if necessary, to store it and the following 8 data
bits into special IM bus interface registers. Transfer of
the data bits to the corresponding C–RAM locations is
then performed by the AMU hardware at the sampling
rate. Transmission of one Byte (8 bits) takes 100 ms. A
spacing of 30 ms must be provided between the end of
one transmission and the start of the next one.
In the case of addressing the AMU 2481 (step 1 above),
the address transmitted first is 102 (= select register). If
the following 8–bit data is identical to 15, the AMU 2481
will accept further IM bus data. This kind of selective addressing
allows controlling of different AMU and APU
types (e.g. “selectword” of APU 2471 = 00, “selectword
of AMU 2481 VS = 14) in a multi–APU system without
using different address ranges. Each APU/AMU type will
have its own mask–programmed “selectword”.

Digital/Analog Converter (DAC) and Volume 2
Digital to analog conversion is performed by four special
conversion circuits. The channels 1 and 2 are assigned
to DAC 1, channels 3 and 4 to DAC 2. At any time, the
current level of the output signals depends on the value
of the reference currents, which are fed to pin 21 (for
DAC 1) and to pin 1 (for DAC 2). Fig. 2–3 gives application
diagrams for the DAC circuits. The RC network connected
to the outputs is required for suppressing the
clock from the D/A conversion (1 nF). To achieve an analog
deemphasis of 50 ms, the 1 nF capacitors must be
enlarged to the 10 nF. To improve the signal–to–noise
ratio of the AMU 2481 (especially for low volume settings)
an additional volume control facility (Vol 2) is provided
after the DAC 1 D/A converters. A digitally–adjusted
attenuator acts in 29 steps of 1 dB each.
Note:
There is an application restriction with these converters:
The clock rate of the AMU must meet the following clock
condition:
Clock rate = sampling rate n 16
n must be an integer value. In section 2.3. all clocks relevant
for the AMU application are listed. They fulfill that
condition.

DSP Block
The AMU 2481 contains a complete mask–programmable
digital signal processor with the blocks as described
in the following sections.
2.2.1. C–RAM, C–ROM and Data RAM
Coefficients and control parameters for digital processing
of audio data are either fixed or variable by means
of the CCU. The coefficient (C) memory is therefore divided
into two parts:
C–RAM, containing 32 locations of 8 bits each, which
can be loaded by the CCU via the IM bus interface. The
AMU software needs 32 variable parameters, and for
proper processing all locations must be loaded with the
corresponding values.
C–ROM, containing 28 locations of 8 bits each, which
are loaded with fixed values, required for the DSP software.
For the user there is no possibility to change coefficients
in the C–ROM. Input data and intermediate results
can be stored in the AMU’s Data RAM whose
locations have 16 bits each. This RAM is arranged in the
following way:
– 50 locations for intermediate results and output data
– 4 locations for S bus input channels
– 2 locations for 2 PDM channels from the decimation filters
2.2.2. Program ROM, Program Counter and Control
Block
The DSP software of the AMU 2481 is stored in the program
ROM. Its size is 256 14 bits, and its content cannot
be modified by the user because it is mask–programmed.
Program ROM is addressed by the program
counter (P.C.), which is a preset table counter.
Instruction decoding and coordinating of all time functions
is performed by the control block. Multiplexing of
the two busses, addressing the coefficient memory and
controlling the separator are also tasks of the control
block. By means of the separator, data are transferred
to the DACs.
2.2.3. Arithmetic Logic Unit (ALU)
The core of the DSP block is the ALU. Multiplication of
16 8 bit, addition using a 20–bit accumulator, and shift
operations are performed in the ALU. Accumulation is
done according to a saturation characteristic (see section
3.1.).
2.3. System Clock FM and PDM Sampling Rate
The clock at the AMU’s FM input is dependent on the
current TV standard. The AMU is mainly provided for the
German TV stereo system PAL and digital source standard
(e.g. D2–MAC). In all cases, the physical source of
the AMU’s system clock is the DMA 2271 D2–MAC Decoder.

Functions Solved by DSP Software
3.1. Representation of Numbers
The AMU 2481 has a two’s complement, fixed point
arithmetic with decimal point being left-hand and the
MSB being the sign bit. The word lengths are defined as
follows:
coefficients: 8 bits including sign bit
data at multiplier input: 16 bits including sign bit
intermediate results: 20 bits including sign bit
Table 3–1 shows as an example the range of the 8–bit
coefficients, resulting from the conditions mentioned
above. From the view of the CCU programmer this might
be the most interesting case. Three formats are used to
express the coefficient values: Integer decimal, integer
hexadecimal and normalized.
Coefficient values must be transferred from the CCU to
the AMU via the IM bus in binary format; therefore in
most tables of this data sheet the values will be presented
in HEX and additionally in the normalized format,
to make the digital signal processing background more
understandable. To save space the normalized values
will be rounded.
3.2. DC Offset Suppression (only for PDM–Data)
To avoid audible distortions caused by volume changes
the DC part of the signals coming from the decimation
filters has to be minimized. Therefore DC suppression
for both channels is performed by the following steps:
1. calculation of the DC levels in two separate measure
paths, i.e. down–sampling of both channels to about
1 kHz
2. lowpass filtering
3. subtracting the resulting DC signals from the original
channels ( = DC compensation)
Note: The feature DC offset suppression is not controllable
by the CCU, e.d. all coefficients are fixed and
stored in the AMU’s C–ROM.
3.3. 50 ms Digital Deemphasis (for PDM–Data Only).
A digital deemphasis is applied to the PDM inputs in order
to process preemphasized audio signals (e.g. FM
TV). So it is not necessary to realize the 50 ms deemphasis
by analog networks at the AMU’s outputs as
shown in Fig. 2–3 (or at the APU’s output with complete
systems, as shown in Fig. 1–2). In the case of processing
SCART signals or if an analog deemphasis at the
DAC outputs is preferred, the digital deemphasis can be
switched off (linear frequency response). Fig. 3–1
shows the 50 ms deemphasis frequency response.

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