PHILIPS 26CS3890/08R GOYA VT PRINTER CHASSIS K35 INTERNAL VIEW.

The PHILIPS 26CS3890/08R has a particularly complex version of the PHILIPS K35 CHASSIS.

First it's isolated from mains with an heavy transformer.

It has 4 or more power supply sections.

It has complex computerized digital circuitry to obtain the TELETEXT PRINTING FEATURE.

It's stereo even with only one channel HIFI sound system.

It's featuring SVM, called "BEAMBOOSTER"

The chassis is fitted with a mains isolation transformer as it is supplied with scart and din video/audio connection sockets.
The chassis is very complicated with an additional audio board together with all the remote control and teletext facilities.

The PHILIPS 26CS3890/08R with the CHASSIS K35 was using in this chassis the RC-5 infrared remote protocol widely used in after developed products for over 25 Years.

The RC-5 infrared remote protocol was developed by Philips in the late 1980s as a semi-proprietary consumer IR (infrared) remote control communication protocol for consumer electronics. However, it was also adopted by most European manufacturers, as well as many US manufacturers of specialty audio and video equipment.
The RC-5 infrared remote protocol was developed by Philips in the late 1980s as a semi-proprietary consumer IR (infrared) remote control communication protocol for consumer electronics. However, it was also adopted by most European manufacturers, as well as many US manufacturers of specialty audio and video equipment.The advantage of the RC-5 protocol is that (when properly followed) any CD handset (for example) may be used to control any brand of CD player using the RC-5 protocol.

Protocol Details

The basics of the protocol are well known. The handset contains a keypad and a transmitter integrated circuit (IC) driving an IR LED. The command data is a bi-phase encoded bitstream modulating a 36 kHz carrier. (Often the carrier used is 38 kHz or 40 kHz, apparently due to misinformation about the actual protocol.) The IR signal from the transmitter is detected by a specialized IC with an integral photo-diode, and is amplified, filtered, and demodulated so that the receiving device can act upon the received command. RC-5 only provides a one-way link, with information traveling from the handset to the receiving unit.
The command comprises 14 bits:

• A start bit, which is always logic 1 and allows the receiving IC to set the proper gain.
• A field bit, which denotes whether the command sent is in the lower field (logic 1 = 0 to 63 decimal) or the upper field (logic 0 = 64 to 127 decimal). The field bit was added later by Philips when it was realized that 64 commands per device were insufficient. Previously, the field bit was combined with the start bit. Many devices still use this original system.
• A control bit, which toggles with each button press. This allows the receiving device to distinguish between two successive button presses (such as "1", "1" for "11") as opposed to the user simply holding down the button and the repeating commands being interrupted by a person walking by, for example.
• A five-bit system address, that selects one of 32 possible systems.
• A six-bit command, that (in conjunction with the field bit) represents one of the 128 possible RC-5 commands.

The 36 kHz carrier frequency was chosen to render the system immune to interference from TV scan lines. Since the repetition of the 36 kHz carrier is 27.778 μs and the duty factor is 25%, the carrier pulse duration is 6.944 μs. Since the high half of each symbol (bit) of the RC-5 code word contains 32 carrier pulses, the symbol period is 64 x 27.778 μs = 1.778 ms, and the 14 symbols (bits) of a complete RC-5 code word takes 24.889 ms to transmit. The code word is repeated every 113.778 ms (4096 / 36 kHz) as long as a key remains pressed. (Again, please note that these timings are not strictly followed by all manufacturers, due to a lack of widespread distribution of accurate information on the RC-5 protocol.)

System and Command Codes

While the RC-5 protocol is well known and understood, what is not so well documented are the system number allocations and the actual RC-5 commands used for each system. The information provided below is the most complete and accurate information available at this time. It is from a printed document from Philips dated December 1992 that is unfortunately not available in electronic format (e.g., PDF), nor is an updated version available. This information is provided so that companies that wish to use the RC-5 protocol can use it properly, and avoid conflicts with other equipment that may or may not be using the correct system numbers and commands.

This code has an instruction set of 2048 different instructions and is divided into 32 address
of each 64 instructions. Every kind of equipment use his own address,
so this makes it possible to change the volume of the TV without change the volume of the hifi.
The transmitted code is a dataword wich consists of 14 bits and is defined as:


2 startbits for the automatic gain control in the infrared receiver.
1 toggle bit (change everytime when a new button is pressed on the ir transmitter)
5 address bits for the systemaddress
6 instructionbits for the pressed key.













The Philips RC5 IR transmission protocol uses Manchester encoding of the message bits. Each pulse burst (mark – RC transmitter ON) is 889us in length, at a carrier frequency of 36kHz (27.7us). Logical bits are transmitted as follows:

• Logical '0' – an 889us pulse burst followed by an 889us space, with a total transmit time of 1.778ms

• Logical '1' – an 889us space followed by an 889us pulse burst, with a total transmit time of 1.778ms

The pulse/pause ratio of the 36kHz carrier frequency is 1/3 or 1/4, which reduces power consumption.

When a key is pressed on the remote controller, the message frame transmitted consists of the following 14 bits, in order:

• two Start bits (S1 and S2), both logical '1'.

• a Toggle bit (T). This bit is inverted each time a key is released and pressed again.

• the 5-bit address for the receiving device

• the 6-bit command.

The address and command bits are each sent most significant bit first. Figure 1 illustrates the format of a Philips RC5 IR transmission frame, for an address of 05h (00101b) and a command of 35h (110101b).



Figure 1. Example message frame using the Philips RC5 IR transmission protocol.
From Figure 1 we can see that it takes:

• 5.334ms to transmit the Start and Toggle bits (S1, S2 and T). Notice that, as the first half-bit of S1 is a space, the receiver will only notice the real start of the message frame after 889us.

• 8.89ms to transmit the 5 bits for the address

• 10.668ms to transmit the 6 bits for the command

• 24.892ms to fully transmit the actual message frame.

The Toggle bit (T) is used by the receiver to distinguish weather the key has been pressed repeatedly, or weather it is being held depressed. As long as the key on the remote controller is kept depressed, the message frame will be repeated every 114ms. The Toggle bit will retain the same logic level during all of these repeated message frames. It is up to the receiver software to interpret this auto-repeat feature of the protocol.

PHILIPS 26CS3890/08R CHASSIS K35 TELEVISION-TELETEXT-VIDEOTEXT Printing apparatus

The main and unique feature of this CHASSIS is the printing apparatus for printing a picture /TEXT GRAPHIC which is formed by a plurality of full and half dots on the screen of a television receiver in response to a luminance signal supplied thereto, includes an integration circuit for integrating the transmitted signal and having a time constant which is selected so that the integrated transmitted signal of a saw-tooth waveform rises to a first level greater than a threshold level when the transmitted signal corresponds to a full dot of displayed information and rises to a second level less than the threshold level when the transmitted signal corresponds to half dot information; a latch circuit for latching the integrated transmitted signal only when the level thereof is greater than the threshold level in response to a latch signal supplied thereto, so as to produce an output signal corresponding only to that portion of the displayed picture formed of full dots; and a printer for printing the picture in response to the output signal.


1. Apparatus for printing a picture corresponding to a picture displayed by display means in response to a transmitted signal, said display means displaying said displayed picture as a plurality of full and half pictorial elements, said transmitted signal containing information indicating the presence of a half pictorial element, a full pictorial element, or the absence of either, and wherein said picture is printed in the form of full pictorial elements, said apparatus comprising:
integration means for integrating said transmitted signal and having a time constant;
the integrated transmitted signal having a first characteristic indicative of the presence of a half pictorial element in said transmitted signal and a second characteristic indicative of the presence of a full pictorial element in said transmitted signal;
means for generating a latch signal having a predetermined phase relation to said integrated transmitted signal;
latch means for latching said integrated transmitted signal in response to said latch signal supplied thereto so as to produce an output signal, said latch signal causing said latch means to latch said integrated transmitted signal at regular times determined by said time constant and said predetermined phase relation such that said latch means produces said output signal only when said integrated transmitted signal, at the time of latching, has said second characteristic, whereby said output signal corresponds to that portion only of the integrated transmitted signal indicative of the presence of a full pictorial element; and
printer means for printing said picture in response to said output signal in the form of full pictorial elements.
2. Apparatus according to claim 1; in which said integration means includes resistive means and capacitive means for determining the value of said time constant. 3. Apparatus according to claim 2; in which said integration means further includes discharge means connected to said capacitive means, said capacitive means charges at a rate determined by said time constant when the transmitted signal corresponds to one of a full and half pictorial element, and said capacitive means discharges through said discharge means when the transmitted signal corresponds to the absence of either a full or half pictorial element. 4. Apparatus according to claim 3; in which said capacitive means and said resistive means are connected in series between first and second reference potentials, said discharge means includes transistor means having a base and a collector-emitter path connected in parallel with said capacitive means, and said apparatus further includes inverting means for inverting said transmitted signal and supplying said inverted transmitted signal to the base of said said transistor means, wherein said integrated transmitted signal rises to a first level greater than a threshold level when the transmitted signal corresponds to a full pictorial element and rises to a second level less than said threshold level when the transmitted signal corresponds to a half pictorial element. 5. Apparatus according to claim 1; in which said latch means produces said output signal only when the level of said integrated transmitted signal is greater than a threshold level; the value of said time constant is selected so that said integrated transmitted signal rises to a first level greater than said threshold level during a first interval after the integrated transmittal signal begins to rise when the transmitted signal corresponds to a full pictorial element and rises to a second level less than said threshold level during a second interval shorter than said first interval after the integrated transmitted signal begins to rise when the transmitted signal corresponds to a half pictorial element, thereby defining a third interval between the endings of said second and first intervals; and the phase of said latch signal is selected so that the latter is supplied to said latch means during said third interval. 6. Apparatus according to claim 1; in which said latch means includes D-type flip-flop means having a D-input terminal supplied with said integrated transmitted signal, a latch input terminal supplied with said latch signal, and an output terminal at which said output signal is produced. 7. Apparatus according to claim 1; further including pulse generating means for producing said latch signal in response to a clock signal supplied thereto. 8. Apparatus according to claim 1; further including character generating means for producing said transmitted signal.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to printing devices and, more particularly, is directed to a printing device for producing a hard copy of a picture displayed on the screen of a television receiver.

2. Description of the Prior Art
Various systems, such as the "TELETEXT" and "VIEWDATA" systems, are known in which news, weather and other information are transmitted, for example, during the vertical blanking period of a television broadcast or through a telephone circuit, to a television receiver where such information is displayed. With these systems, each number, letter or other symbol is converted to a code signal and then transmitted to the receiving end of the system where the code signal is decoded to the original number, letter or other symbol and then displayed on the screen of the television receiver. For example, for the letter "A", a corresponding code signal "41" may be transmitted to a character generator at the receiving end which, in response thereto, generates a luminance signal corresponding to the letter "A" and supplies the same to the television receiver. Accordingly, the letter "A" is displayed on the screen of the television receiver.
With the above system, a printer can be connected to the television receiver for printing a hard copy of the picture, that is, the combination of numbers, letters or other symbols, which are displayed on the screen of the television receiver. It should be appreciated, however, that a printer cannot operate at the speed at which the luminance signal is supplied to the television receiver. Since the picture displayed on the screen of the television receiver is a still picture, that is, it remains on the screen long enough for the viewer to read the information, the luminance signal is sampled with a suitable sampling frequency to enable the printer to follow the luminance signal as the corresponding numbers, letters or other symbols are being displayed on the screen of the television receiver so as to print the sampled output thereof and thereby produce the desired hard copy.
Generally, the numbers, letters or other symbols displayed on the screen of the television receiver are formed from a plurality of pictoral elements, which will hereinafter be referred to as full or normal dots. In order to more clearly display the numbers, letters or other symbols on the screen, a plurality of half dots, having half the width of a normal or full dot, are added to the pictoral representation to provide a more rounded look to the numbers, letters or other symbols, thereby making the latter easier to see. However, various problems have arisen with the different control circuits used to control the printer. It is to be first noted that the printer is only adapted to print a full pictoral element on the hard copy in response to the sampled signal supplied thereto. Thus, with one known printer circuit, if a signal corresponding to a half dot of information displayed on the screen of the television receiver is sampled, the printer will print a full pictoral element on the hard copy. Accordingly, the numbers, letters and other symbols which are printed on the hard copy may become distorted.
In another proposed printer circuit, two separate sampling circuits and a logic circuit are provided to eliminate the sampled luminance signal corresponding to each half dot of information. However, because this circuit requires two sampling circuits and a logic circuit, the circuit is relatively complicated. Further, with this circuit, the sampled luminance signal corresponding to successive half dots of displayed information is interpreted by the logic circuit as corresponding to a full dot of information, so that the printer incorrectly prints a full pictoral element.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide a printing apparatus that avoids the above-described difficulties encountered with prior art.
More particularly, it is an object of this invention to provide a printing apparatus for printing a picture, which is formed by a plurality of full and half pictoral elements on the screen of a television receiver, as a hard copy without the half pictoral elements.
It is another object of this invention to provide a printing apparatus that is of a relatively simple construction.
In accordance with an object of this invention, apparatus is provided for printing a picture which is displayed by display means in response to a transmitted signal, the displayed picture being formed by a plurality of full and half pictoral elements, the apparatus including integration means for integrating the transmitted signal and having a time constant; latch means for latching the integrated transmitted signal in response to a latch signal supplied thereto so as to produce an output signal, the phase of the latch signal and the time constant of the integration means being selected so that the output signal corresponds only to that portion of the displayed picture formed of full pictoral elements; and printing means for printing the picture in response to the output signal.

The above, and other, objects, features and advantages of the present invention will become readily apparent from the following detailed description of an illustrative embodiment of the invention which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic perspective view of a printer with which the present invention can be utilized;
FIG. 2 is a circuit-wiring diagram of the thermal control elements for the printer of FIG. 1;
FIG. 3 is a schematic diagram of the dot arrangement on the screen of a television receiver;
FIG. 4 is a block diagram of a printing circuit according to the prior art;
FIG. 5 is a schematic diagram of a letter that is adapted to be displayed on the screen of FIG. 3 without rounding;
FIG. 6 is a schematic diagram of a letter that is adapted to be displayed on the screen of FIG. 3 with rounding;
FIG. 7A is a schematic diagram of the letter of FIG. 6, illustrating the points in the even field thereof at which the luminance signal is sampled by the prior art circuit of FIG. 4;
FIG. 7B is a time chart illustrating the sampling pulses used in the prior art circuit of FIG. 4;
FIG. 7C is a schematic diagram of the hard copy of the letter of FIG. 7A produced when the luminance signal is sampled during the even field thereof with the prior art circuit of FIG. 4;
FIG. 8 is a block diagram of another printing circuit according to the prior art;
FIGS. 9A-9G are waveform diagrams used for explaining the operation of the circuit of FIG. 8;
FIG. 10 is a circuit wiring-block diagram of a printing circuit according to one embodiment of the present invention; and
FIGS. 11A-11D are waveform diagrams used for explaining the operation of the circuit of FIG. 10.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Referring to the drawings in detail, and initially to FIGS. 1 and 2 thereof, there is shown a printer with which the present invention is adapted to be utilized. In particular, the printer includes a cylindrical platen 2 and a recording head 1 positioned longitudinally adjacent platen 2. Recording paper 3 is positioned between recording head 1 and platen 2 and is longitudinally advanced in the direction of arrow 4 in FIG. 1 during the printing operation. In the printer shown in FIGS. 1 and 2, recording head 1 is a thermal recording head which is comprised of a plurality of controllable heating resistors R ₁ -R ₂₅₂ (FIG. 2), and recording paper 3 is a thermal paper which is sensitive to the heat generated by the resistors of recording head 1.
The screen of the television receiver with which the present invention is also utilized is comprised of a plurality of horizontal and vertical rows, as shown in FIG. 3. For the purpose of illustrating the present invention, the screen of FIG. 3 is formed in a rectangular matrix with a plurality of pictoral elements, illustrated as being full or normal dots. In particular, each horizontal line on the screen includes 240 dots and each vertical column includes 252 dots, with each dot being selectively activated to display a combination of desired numbers, letters, or other symbols on the television screen. It is to be appreciated, however, that although dots have been utilized in the screen of FIG. 3, any other suitable configuration may be utilized. Also, although the television screen of FIG. 3 has been shown with 240 dots in each horizontal line and 252 dots in each vertical column, these numbers may also vary. However, consistent therewith, recording head 1 includes 252 resistors R ₁ -R ₂₅₂ , as previously stated, which are used as heating elements along the longitudinal direction of platen 2, corresponding to each vertical column of dots on the television screen of FIG. 3. Resistors R ₁ -R ₂₅₂ are arranged in nine sets of 28 resistors for easy control thereof.
A known printer circuit for controlling the operation of the printer is shown in FIG. 4. With this circuit, a luminance signal from a character generator is supplied to the television receiver, resulting in a still motion picture be displayed on the screen thereof by selective illumination of the dots thereon. Hereinafter, the term picture will refer to any combination of letters, numbers or any other pictoral representation. With this arrangement, one field of pictoral information is provided on the screen when a luminance signal necessary to selectively activate all of the dots on the screen has been supplied to the television receiver. As will hereinafter become apparent, for each pictoral representation displayed on the screen, at least 240 field intervals of the luminance signal are supplied to the television receiver.

The luminance signal is also supplied through an input terminal 11 to a sampling circuit 12 of the printer circuit of FIG. 4. During the first field interval, sampling circuit 12 sequentially samples the luminance signal corresponding to the first dot of information displayed on the screen of FIG. 3 for each of the 252 horizontal lines or rows. In other words, the luminance signal corresponding to the first column of dot information displayed on the screen of FIG. 3 is sampled by sampling circuit 12 during the first field interval. The sampled signal during the first field interval is stored in a memory 13A which is connected to sampling circuit 12 through a switch 17.

During the next or second field interval, in which the same or substantially the same luminance signal is supplied to the television receiver, sampling circuit 12 sequentially samples the luminance signal corresponding to the second dot of information displayed on the screen of FIG. 3 for each horizontal line or row. In other words, the luminance signal corresponding to the second column of dot information displayed on the screen of FIG. 3 is sampled by sampling circuit 12 during the second field interval. In this manner, sampling circuit 12 sequentially samples the luminance signal column by column until all 240 columns are sampled.
During the second field interval, the sampled contents of memory 13A are read out therefrom and supplied through a switch 18, a serial-to-parallel shift register 14, and a latch circuit 15 to recording head 1. It is to be appreciated that, in such case, switch 18 is changed over from the condition shown in FIG. 4. A driver circuit 16 is also connected to recording head 1 for selecting the respective set or sets of thermal resistors to be activated. In this manner, thermal resistors R ₁ -R ₂₅₂ of recording head 1 are controlled to print a hard copy of a picture corresponding the first column of displayed dot information. Further, during the second field interval, switch 17 is changed over from the condition shown in FIG. 4 so that the output of sampling circuit 12, corresponding to the second column of displayed dot information, is stored in a memory 13B. Then, during the third field interval, switches 17 and 18 are once again changed over to the condition shown in FIG. 4 so that new information is stored in memory 13A and the contents of memory 13B, corresponding to the second column of displayed information is printed by recording head 1. This procedure continues until the last column of displayed dot information is printed by recording head 1 so as to produce a hard copy of the picture displayed on the screen of FIG. 3.
Referring now to FIG. 5, there is shown a schematic diagram of the letter "A" displayed on the screen of FIG. 3 without a rounding operation being performed. In the diagram of FIG. 5, lines L ₁ -L ₁₄ illustrate the horizontal scan lines, with the odd scan lines L _2n +1 being formed during the odd field intervals and the even scan lines L _2n being formed during the even field intervals. It is to be appreciated that the letter "A" is shown in FIG. 5 as being formed of a plurality of boxes rather than dots merely for ease of illustration. Because the displayed letter "A" may be difficult to see by the viewer, the aforementioned character generator generally produces a luminance signal which results in a more detailed or rounded letter "A", as shown in FIG. 6, by utilizing both full and half dots, in which the width of each half dot is one-half that of a normal or full dot. In this manner, the letter "A" takes on a more rounded appearance and is easier to see by a viewer.
It should be appreciated, from a review of FIG. 6, that the luminance signal produced by the character generator during the odd field intervals is different from the luminance signal produced during the even field intervals, as a result of the rounding operation, unlike the case of FIG. 5 where no rounding occurs. Accordingly, sampling should only be performed during either the even field intervals or the odd field intervals. However, the printer is only adapted to print full or normal pictoral elements of information and is not adapted to print half pictoral elements, corresponding to the half dots of information displayed on the screen of FIG. 3. Thus, for example, if the luminance signal, corresponding to the x-marks in FIG. 7A, is sampled during an even field interval, at a sampling rate determined by the sampling pulses of FIG. 7B, the printer will print a hard copy, as shown in FIG. 7C. It should be appreciated that, because of the asymmetry between the pictures in the odd and even fields, distortion in the printed letter "A" results. More particularly, this distortion results because the printer of FIG. 1 prints a full pictoral element when the luminance signal corresponding to a displayed half dot is sampled or detedted. Further, such distortion is only changed and is not corrected by changing the phase of the sampling pulses or by sampling the luminance signal during the odd field intervals.
In order to overcome this deficiency, it has been proposed to provide circuitry to prevent the printing of a full pictoral element on the hard copy in response to the sampled luminance signal corresponding to eachhalf dot of displayed information. In particular, as shown in FIG. 8, a character generator 21 generates a luminance signal S _y (FIG. 9A) which is supplied to a television receiver 22 at which a picture formed of full and half dots is displayed. The shaded areas of the luminance signal S _y shown in FIG. 9A correspond to half dots of information. Luminance signal S _y is also supplied to sampling circuits 23A and 23B of the printer circuit. A sampling pulse generator 24, which is supplied with a clock pulse signal P _c , in response thereto, supplies pulses P _a (FIG. 9C) and P _b (FIG. 9D) to sampling circuits 23A and 23B, with the phase of pulses P _a and P _b being different from each other. It is to be appreciated, of course, that sampling circuits 23A and 23B correspond in structure and operation to sampling circuit 12 of FIG. 4. The outputs Q _a (FIG. 9E) and Q _b (FIG. 9F) of sampling circuits 23A and 23B are supplied to a logic circuit 25 which, in turn, supplies a modified luminance signal Q _y (FIG. 9G) having no half dot information to a printer 26 for producing the aforementioned hard copy. Since the luminance signal S _y is sampled at different times in sampling circuits 23A and 23B, if only one of the outputs Q _a and Q _b is produced, it is determined that the luminance signal contains a half dot of information. If both outputs Q _a and Q _b are produced, it is determined that the luminance signal includes a full dot of information. In this manner, logic circuit 25 eliminates from the modified luminance signal Q _y all half dots of information so that the luminance signal Q _y causes the letter "A", as shown in the schematic diagram of of FIG. 5, to be printed. Accordingly, a hard copy is obtained without the half dot information. However, it should be appreciated that the circuit of FIG. 8 is of a relatively complicated construction because of the use of two sampling circuits with two distinct sampling pulses and the use of the logic circuit. Further, if the luminance signal S _y is comprised of continuous half dots of information, logic circuit 25 determines that a full dot of information exists and causes the same to be printed on the hard copy as a full pictoral element.
Referring now to FIG. 10, there is shown a printer circuit according to one embodiment of the present invention, in which a character generator 41 supplies the luminance signal S _y (FIG. 11A) containing both full and half dot information to a television receiver 42 at which a picture formed of full and half dots is displayed. Luminance signal S _y is also supplied to an inverter 48 of the printer circuit which, in turn, supplies an inverted output to the base of an NPN transistor Q ₁ having its emittor connected to ground. A resistor R ₁ and a capacitor C ₁ are connected in series between a power supply terminal T ₁ supplied with a power supply voltage +V _cc , and ground, and the connection point between resistor R ₁ and capacitor C ₁ is connected to the collector of transistor Q ₁ . Transistor Q ₁ , resistor R ₁ and capacitor C ₁ thereby form an integration circuit 47. The connection point between resistor R ₁ and capacitor C ₁ constitutes the output of integration circuit 47, at which is produced an integrated saw-tooth signal S _s (FIG. 11B), and this latter signal is supplied to the D-input terminal of a latch circuit 49, which is preferably constituted by a D-type flip-flop circuit. As is apparent from FIG. 11B, saw-tooth signal S _s has a value which is less than a threshold voltage V _TH for half-dot information. The threshold voltage V _TH may, for example, be equal to one-half the power supply voltage +V _cc . The printer circuit according to this invention also includes a pulse generator 44 which is supplied with a clock signal P _c and which, in turn, produces a latch pulse P _l (FIG. 11C), which is synchronized with clock signal P _c and which is delayed by 270 degrees from the beginning of each clock period so as to occur during the latter half of each full dot information. Latch pulse P _l is supplied to a latch input L of latch circuit 49 for controlling the operation thereof.

In accordance with the above construction, when the level of the luminance signal S _y is at a high logic level condition, transistor Q ₁ is turned OFF, whereby capacitor C ₁ is charged through resistor R ₁ from power supply terminal T ₁ . On the other hand, when the level of the luminance signal S _y is at a low logic level condition, transistor Q ₁ is turned ON and capacitor C ₁ is rapidly discharged through the collector-emittor path of transistor Q ₁ . In this manner, signal S _s , having a saw-tooth wavefrom, as shown in FIG. 11B, is obtained in correspondance with luminance signal S _y . Signal S _s is then supplied to the D-input terminal of latch circuit 49. However, latch circuit 49 is constructed to latch and then transmit only those signals supplied thereto which have a level above the aforementioned threshold level V _TH . It should be appreciated from a review of FIG. 11B that the portion of signal S _s corresponding to half dot information is below the threshold voltage V _TH and is therefore not latched and transmitted by latch circuit 49, but that the portion of signal S _s corresponding to the last half of full dot information has a level above threshold voltage V _TH . Accordingly, because of the relationship of the threshold voltage V _TH of latch circuit 49 and the phase of latch signal P _l to signal S _s , output luminance signal Q _y from latch circuit 49 includes only full dot information. This luminance signal Q _y which is devoid of the half dot information is then supplied to a printer 46 whereby the displayed picture is printed as a hard copy. It should be appreciated that the present invention overcomes the problems previously discussed in regard to the prior art circuit of FIG. 8. Thus, in addition, to being of a relatively simple construction, the present invention prevents half dot signals from being interpreted as full dot signals.
It should be appreciated that the circuit of FIG. 10 may be modified by one of ordinary skill in the art within the scope of the present invention, as defined by the claims herein. In particular, although latch pulse P _l has been shown with a 270° phase relation with respect to each full dot of information, it is to be appreciated that latch pulse P _l may be positioned anywhere where within signal S _s corresponding to the last half (or last 180°) of each full dot of information when the threshold voltage V _TH is equal to one-half the power supply voltage +V _cc . In other words, it is only important that the latch pulse P _l activate latch circuit 49 when the level of signal S _s corresponding to full dot information is greater than the threshold voltage V _TH . Since the positioning of latch pulse P _l need not be precise, the construction of the present invention becomes even simpler. Further, the time constant of integration circuit 47, which is determined by resistor R ₁ and capacitor C 1 need only be selected so that the level of signal S _s is not greater than the threshold voltage V _TH during any half dot period of the signal S _y . This also results in a simpler construction of the circuit of FIG. 10.
Having described a specific preferred embodiment of the present invention with reference to the accompanying drawings, it is to be understood that the present invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.

PHILIPS 26CS3890/08R CHASSIS K35 Video signal reproducing apparatus with electron beam scanning velocity modulation / "BEAMBOOSTER":In a video signal reproducing apparatus having a cathode ray tube in which at least one electron beam is made to scan a screen in line-scanning and vertical directions while the intensity of the beam is modulated to establish the brightness of a video picture to be displayed on the screen, and in which bright picture portions are represented by respective high level portions of a video signal; a waveshaping circuit receives the video signal and acts thereon to provide a compensated video signal in which the width of each high level portion between the respective rising and falling edges is increased, the compensated video signal is employed to control the intensity of the electron beam, and the rising and falling edges of each high level portion of the compensated video signal are detected, as by a differentiating circuit or a delay line circuit, to provide respective output signals by which the scanning velocity of the beam in the line-scanning direction is modulated. The waveshaping circuit for providing the compensated video signal may be constituted by a delay line and an OR circuit having inputs to which the original video signal and the delayed video signal are applied, or by a differentiator receiving the original video signal and having its output applied to a polarity equalizer.

1. A video signal reproducing apparatus comprising
a source of a video signal representing at least the brightness of a video picture and in which bright picture portions are represented by video signal portions of high level defined between respective rising and falling edges;
waveshaping means receiving said video signal from said source for providing a corresponding compensated video signal in which the width of each of said high level signal portions between said respective rising and falling edges is increased, said wave shaping means including delay means receiving said video signal from said source for providing a delayed video signal, and OR gate means having inputs receiving said video signal from said source and said delayed video signal, respectively, and an output at which said compensated video signal appears;
a cathode ray tube having a screen, an electron gun including beam producing means directing an electron beam generally along the axis of the tube toward said screen for impingement on the latter and being controlled in response to said compensated video signal from said waveshaping means so that the intensity of the beam is modulated in accordance with said compensated video signal, and deflection means for causing said beam to scan said screen in line-scanning and vertical directions, respectively;
detecting means also receiving said compensated video signal from said waveshaping means and detecting said rising and falling edges of the high level signal portions of said compensated video signal for providing output signals in correspondence to the detected rising and falling edges; and
beam velocity modulation means for modulating the scanning velocity of said electron beam in said line-scanning direction in accordance with said output signals from said detecting means.
2. A video signal reproducing apparatus according to claim 1; in which said OR gate means includes first and second transistors having respective collector-emitter paths connected in parallel between an operating voltage source and said output of the OR gate means, said first and second transistors further having respective base electrodes constituting said inputs receiving said video signal from said source thereof and said delayed video signal, respectively. 3. A video signal reproducing apparatus according to claim 1; in which said detecting means includes means differentiating said compensated video signal so as to provide said output signals in correspondence to said detected rising and falling edges. 4. A video signal reproducing apparatus comprising
a source of a video signal representing at least the brightness of a video picture and in which bright picture portions are represented by video signal portions of high level defined between respective rising and falling edges;
waveshaping means receiving said video signal from said source for providing a corresponding compensated video signal in which the width of each of said high level signal portions between said respective rising and falling edges is increased, said waveshaping means including differentiating means for differentiating the video signal from said source of the latter, polarity equalizing means acting on the differentiated signal from said differentiating means for providing a differentiated signal of one polarity, and adder means adding the video signal from said source thereof and said differentiated signal of one polarity to provide said compensated video signal;
a cathode ray tube having a screen, an electron gun including beam producing means directing an electron beam generally along the axis of the tube toward said screen for impingement on the latter and being controlled in response to said compensated video signal from said waveshaping means so that the intensity of the beam is modulated in accordance with said compensated video signal, and deflection means for causing said beam to scan said screen in line-scanning and vertical directions, respectively;
detecting means also receiving said compensated video signal from said waveshaping means and detecting said rising and falling edges of the high level signal portions of said compensated video signal for providing output signals in correspondence to the detected rising and falling edges; and
beam velocity modulation means for modulating the scanning velocity of said electron beam in said line-scanning direction in accordance with said output signals from said detecting means.
5. A video signal reproducing apparatus according to cl

aim 4; in which said polarity equalizer includes a first diode connected in parallel with a series connection of an inventer and a second diode. 6. A video signal reproducing apparatus according to claim 4; in which said detecting means includes means differentiating said compensated video signal so as to provide said output signals in correspondence to said detected rising and falling edges. 7. A video signal reproducing apparatus comprising
a source of a video signal representing at least the brightness of a video picture and in which bright picture portions are represented by video signal portions of high level defined between respective rising and falling edges;
waveshaping means receiving said video signal from said source for providing a corresponding compensated video signal in which the width of each of said high level signal portions between said respective rising and falling edges is increased;
a cathode ray tube having a screen, an electron gun including beam producing means directing an electron beam generally along the axis of the tube toward said screen for impingement on the latter and being controlled in response to said compensated video signal from said waveshaping means so that the intensity of the beam is modulated in accordance with said compensated video signal, and deflection means for causing said beam to scan said screen in line-scanning and vertical directions, respectively;
detecting means also receiving said compensated video signal from said waveshaping means and detecting said rising and falling edges of the high level signal portions of said compensated video signal for providing output signals in correspondence to the detected rising and falling edges, said detecting means including means differentiating said compensated video signal so as to provide said output signals in correspondence to said detected rising and falling edges; and
beam velocity modulation means for modulating the scanning velocity of said electron beam in said line-scanning direction in accordance with said output signals from said detecting means.
8. A video signal reproducing apparatus comprising
a source of a video signal representing at least the brightness of a video picture and in which bright picture portions are represented by video signal portions of high level defined between respective rising and falling edges;
waveshaping means receiving said video signal from said source for providing a corresponding compensated video signal in which the width of each of said high level signal portions between said respective rising and falling edges is increased;
a cathode ray tube having a screen, an electron gun including beam producing means directing an electron beam generally along the axis of the tube toward said screen for impingement on the latter and being controlled in response to said compensated video signal from said waveshaping means so that the intensity of the beam is modulated in accordance with said compensated video signal, and deflection means for causing said beam to scan said screen in line-scanning and vertical directions, respectively;
detecting means also receiving said compensated video signal from said waveshaping means and detecting said rising and falling edges of high level signal portions of said compensated video signal for providing output signals in correspondence to the detected rising and falling edges; and
beam velocity modulation means for modulating the scanning velocity of said electron beam in said line-scanning direction in accordance with said output signals from said detecting means, said beam velocity modulation means including a tubular electrode on said axis of the tube for the passage of said electron beam axially through said tubular electrode between said beam producing means and said screen, said tubular electrode being in two parts which are axially separated along a vertical plane that is inclined relative to said axis of the tube, and means for applying said output signals from the detecting means across said two parts of the tubular electrode.
9. A video signal reproducing apparatus according to claim 8; in which said tubular electrode is included in electron lens means for focusing said beam at said screen, and said electron lens means further includes at least another tubular electrode arranged coaxially in respect to the first mentioned tubular electrode, with a relatively low potential being applied to said first tubular electrode and a relatively high potential being applied to said other electrode for producing an electrical field which effects said focusing of the beam.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to video signal reproducing apparatus, such as, television receivers, and more particularly is directed to providing such apparatus with improved arrangements for effecting electron beam scanning velocity modulation so as to significantly enhance the sharpness of the reproduced picture or image.
2. Description of the Prior Art
When the phosphor screen of a video signal reproducing apparatus, such as, the screen of the cathode ray tube in a television receiver, is scanned by an electron beam or beams so as to form a picture or image on the screen, the beam current varies with the luminance or brightness level of the input video signal. Therefore, each electron beam forms on the phosphor screen a beam spot whose size is larger at high brightness levels than at low brightness levels of the image so that sharpness of the reproduced picture is deteriorated, particularly at the demarcation between bright and dark portions on areas of the picture. Further, when a beam scanning the screen in the line-scanning direction moves across the demarcation or edge between dark and bright areas of the picture, for example, black and white areas, respectively, the frequency response of the receiver does not permit the beam intensity to change instantly from the low level characteristic of the black area to the high level characteristic of the white area. Therefore, the sharpness of the reproduced image is degraded at portions of the image where sudden changes in brightness occur in response to transient changes in the luminance or brightness of the video signal being reproduced. The increase in the beam current and in the beam spot size for bright portions of the reproduced picture or image and the inadequate frequency response of the television receiver to sudden changes in the brightness or luminance level of the incoming video signal are additive in respect to the degradation of the horizontal sharpness of the reproduced image or picture.
It has been proposed to compensate for the described degradation of the horizontal sharpness of the picture or image by employing the so-called "aperture correction or compensation technique," for example, as described in "Aperture Compensation for Television Camera," R. C. Dennison, RCA Review, 14,569 (1953). In accordance with such aperture correction or compensation technique, the intensity of the electron beam is first decreased and then increased at those portions of the picture image at which the brightness changes from a low level to a high level. Such modification or compensation of the electron beam intensity can be achieved by twice differentiating the original video signal so as to obtain a compensation signal which is added to the original video signal for obtaining a compensated video signal applied to the cathode of the cathode ray tube and having high level portions with relatively more steeply inclined rising and falling edges. However, with the foregoing aperture compensation technique, the peak luminance or brightness levels of the compensated video signal are increased and, as applied to the cathode of the cathode ray tube, result in beam currents that are increased relative to the maximum beam currents resulting from the original video signal so that the beam spot size is actually increased. By reason of the foregoing, the aperture compensation technique or method is insufficient for achieving really sharp definitions between light and dark areas of the reproduced picture or image, particularly in the case of relatively large screen areas, even though the described technique creates a visual edge effect which, to some extent, and particularly in the case of relatively small screens, registers psychologically as improved edge sharpness.
In order to avoid the above-described disadvantage of the aperture correction or compensation technique, it has been proposed to employ the so-called "beam velocity modulation method or technique" in which transient changes in the brightness level of the video signal are detected, and the scanning velocity of the electron beam in the line-scanning direction is modulated in accordance with the thus detected transient changes, for example, as described in detail in U.S. Pat. Nos. 2,227,630, 2,678,964, 3,752,916, 3,830,958 and 3,936,872, with the last two enumerated patents having a common assignee herewith.
More particularly, in the known beam velocity modulation technique or method, the original video signal representing brightness or luminance of a video picture and which incorporates "dullness" at abrupt changes in the luminance level due to the inadequate frequency response of the television receiver circuits to such abrupt changes in luminance level, is applied directly to the cathode or beam producing means of the cathode ray tube for modulating the intensity of the electron beam or beams, and such original video signal is also differentiated to obtain a modulation signal which is employed for effecting a supplemental horizontal deflection of the beam or beams in addition to the main or usual horizontal deflection thereof. The modulation or compensation signal may be supplied to the main deflection coil or yoke or to a supplemental deflection coil which is in addition to the main deflection coil with the result that the overall magnetic field acting on the beam or beams for effecting horizontal deflection thereof is modulated and corresponding modulation of the beam scanning velocity in the line-scanning direction is achieved. As is well known, the effect of the foregoing is to improve the sharpness of the image or picture in the horizontal direction. Since the original video signal is applied directly to the cathode or beam producing means of the cathode ray tube without increasing the level thereof at sharp changes in the brigheness level of the video signal, as in the aperture correction or compensation technique, the beam velocity modulation technique does not cause changes in the beam spot size so that sharpness of the image or picture in the horizontal direction is conspicuously improved.
However, it is a characteristic or inherent disadvantage of existing beam velocity modulation arrangements that the improved horizontal sharpness of the reproduced image or picture is achieved at the expense of a reduction in the width of the bright or white areas of the reproduced image or picture so that such bright or white areas are slimmer or more slender than would be the case if the depicted scene were accurately or precisely reproduced.
OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide a video signal reproducing apparatus with an improved arrangement for effecting beam scanning velocity modulation and thereby achieving enhanced sharpness of the reproduced image or picture, particularly at the demarcations between relatively dark and light picture areas, without reducing the widths of such light picture areas.
Another object is to provide an arrangement for effecting beam scanning velocity modulation, as aforesaid, which is relatively simple and is readily applicable to video signal reproducing apparatus, such as, television receivers.
In accordance with an aspect of this invention, in a video signal reproducing apparatus having a cathode ray tube in which at least one electron beam is made to scan a screen in line-scanning and vertical directions while the intensity of the beam is modulated to establish the brightness of a video picture to be displayed on the screen, and in which bright picture portions are represented by respective high level portions of an original video signal; a waveshaping circuit receives the original video signal and acts thereon to provide a compensated video signal in which the width of each high level portion between the respective rising and falling edges is increased, the compensated video signal is employed to control the intensity of the electron beam, and the rising and falling edges of each high level portion of the compensated video signal are detected to provide a respective output or modulation signal by which the scanning velocity of the beam in the line-scanning direction is modulated.
The above, and other objects, features and advantages of the invention, will be apparent in the following detailed description of illustrative embodiments thereof which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B are diagrammatic views representing reproduced video pictures including bright and dark areas;
FIGS. 2A-2D are waveform or graphic views to which reference will be made in explaining the aperture correction or compensation technique of the prior art;
FIGS. 3A-3E are waveform or graphic views to which reference will be made in explaining the beam velocity modulation technique of the prior art and the disadvantage inherent therein;
FIG. 4 is a schematic view illustrating a circuit according to an embodiment of the present invention for effecting beam velocity modulation in a video signal reproducing apparatus;
FIG. 5 is an axial sectional view of an electron gun in a cathode ray tube which is particularly suited for use with a beam velocity modulation arrangement according to this invention;
FIGS. 6A-6F are waveforms or graphic views to which reference will be made in explaining the operation of the circuit according to this invention as shown on FIG. 4;
FIG. 7 is a schematic view illustrating another embodiment of a portion of the circuit shown on FIG. 4 for effecting beam velocity modulation according to this invention;
FIGS. 8A-8D are waveforms or graphic views to which reference will be made in explaining the operation of the embodiment of this invention illustrated by FIG. 7;
FIG. 9 is a diagrammatic view illustrating a circuit that may be used for one of the components shown on FIG. 7; and
FIG. 10 is a wiring diagram illustrating another embodiment of a portion of the circuit shown on FIG. 4 for effecting beam velocity modulation in accordance with this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to the drawings in detail, and initially to FIG. 4 thereof, it will be seen that the present invention is related to a television receiver or other video signal reproducing apparatus 10 having a cathode ray tube 11 in which a beam producing means including a cathode 12 directs an electron beam B generally along the axis of the tube envelope toward a phosphor screen S on the faceplate of the tube. In the apparatus 10, the intensity of electron beam B, and hence the brightness of the beam spot produced at the location where the beam B impinges on screen S, is modulated in accordance with a video signal applied to cathode 12 and representing at least the brightness of a video picture to be reproduced on screen S. The cathode ray tube 11 is further shown to include the conventional deflection means or yoke 13 by which beam B is made to scan screen S in the line-scanning or horizontal and vertical directions, respectively. The simultaneous modulation of the beam intensity by the video signal applied to cathode 12 and the scanning of screen S by beam B in response to sweep signals applied to yoke 13 will result in the reproduction of an image or picture on screen S. The image or picture reproduced on screen S may be constituted by at least one white or bright picture portion, for example, in the form of a rectangle as shown at 14a on FIG. 1A, or in the form of a vertical line as indicated at 14b on FIG. 1B, and relatively darker picture portions. In any case, it will be understood that, in each line or horizontal interval of a video signal received by a television receiver and utilized in the cathode ray tube of the latter for reproducing a horizontal increment of an image or picture at a vertical position in the latter which is included in the bright or white area 14a or line 14b, the respective bright picture portion is represented by a corresponding high level video signal portion defined between rising and falling edges 15r and 15f, respectively (FIG. 2A). If the transmitted video signal S _T is to represent a white or bright shape or area surrounded by a black or very dark background with a sharp demarcation therebetween, the rising and falling edges 15r and 15f of the high level signal portion will be precipitous, that is, substantially vertical, as shown, so as to represent the desired high frequency change in luminance level. However, the usual television receiver circuit, for example, comprised of RF and IF amplifiers and a video detector, and by which the video signal to be used in the cathode ray tube is derived from the received television signal, has a frequency response that is inadequate to accommodate the mentioned high frequency components of the transmitted video signal S _T . Thus, the video signal S _O (FIG. 2B) which is available in the television receiver for controlling the intensity of the electron beam or beams in the cathode ray tube is relatively "dull" that is, it has decreased high frequency components, as represented by the illustrated sloping, rising and falling edges 16r and 16f of th

e high level signal portion. Such relatively dull video signal S _O is hereinafter referred to as the "original video signal," and such terminology is reasonable when considered from the point of view of the input side of the cathode ray tube. Further, the term "original video signal" has often been used in the prior art in the same sense that it is used herein.
The decrease in the high frequency components of the original video signal S _o as compared with the transmitted video signal S _T causes a decrease in the horizontal sharpness of the reproduced image or picture, that is, the sloping, rising and falling edges 16r and 16f (FIG. 2B) result in a gradual change from dark to bright and from bright to dark, respectively, rather than in the sudden changes in brightness represented by the transmitted signal S _T (FIG. 2A). Horizontal sharpness of the reproduced image or picture is furthermore decreased by the fact that, in the cathode ray tube, the electron beam current varies with the luminance or brightness level of the video signal applied to the cathode ray tube and, when the luminance level is high, for example, to represent a bright or white area of the picture, the beam spot size caused by impingement of the electron beam on the phosphor screen is enlarged to further decrease or deteriorate the sharpness of the reproduced picture.
In seeking to compensate for the above-described lack of sharpness of the reproduced picture by the known aperture correction or compensation technique, the original video signal S _O (FIG. 2B) is differentiated twice so as to obtain a compensation signal S _B (FIG. 2C) which is added to the original video signal S _O for providing a compensated video signal S _C (FIG. 2D). As shown, the compensated video signal S _C has rising and falling edges 17r and 17f which are more steeply inclined than the corresponding rising and falling edges 16r and 16f of the original video signal S _O . However, when the compensated video signal S _C is applied to the cathode of a cathode ray tube for controlling the intensity or beam current of the electron beam or beams therein, the sharpness of the reproduced picture is not conspicuously improved. The foregoing results from the fact that, by adding the compensation signal S _B to the original video signal S _O for obtaining the compensated video signal S _C applied to the cathode of the cathode ray tube, the maximum beam current corresponding to the peak luminance level of signal S _C is increased, as compared with the maximum beam current corresponding to the peak luminance level of original video signal S _O , with the result that the beam spot size resulting from compensated video signal S _C is enlarged. Such enlargement of the beam spot size causes a decrease in sharpness of the reproduced picture, as previously noted, and thus substantially defeats any increase in sharpness that might result from the relatively more steeply inclined rising and falling edges 17r and 17f of the compensated video signal S _C .
In the known beam velocity modulation technique for improving horizontal sharpness of the reproduced image or picture, the dull original video signal S _O (FIG. 3A) is applied, without alteration, to the cathode or beam producing means of the cathode ray tube for determining the intensity or beam current of the electron beam or beams in the cathode ray tube. The original video signal S _O is also subjected to differentiation to obtain a compensation signal S _A (FIG. 3B). The compensation signal S _A is applied to a supplemental deflection means which is in addition to the main deflection coils or yoke so that the horizontal deflection field for effecting scanning movement of each beam in the line-scanning direction is modified or compensated, as shown on FIG. 3C. As a result of such modified or compensated horizontal deflection field, the beam scanning velocity in the line-scanning direction, is modulated as shown on FIG. 3D. It will be appreciated that, during each period T _a on FIG. 3D, the beam scanning velocity is increased so that a decreased amount of light is emitted from the phosphor dots or areas on the screen that are impinged upon during each period T _a . On the other hand, during each period T _b , the beam velocity is decreased so that an increased amount of light is emitted from the phosphor dots or areas impinged upon by the electron beam during each period T _b . Therefore, the variation, in the horizontal direction across the screen, in the amount of emitted light, is substantially as indicated on FIG. 3E, from which it will be apparent that the sharpness of the reproduced image or picture in the horizontal direction is improved. Since the original video signal S _O is still applied to the cathode of the cathode ray tube for controlling the beam intensity, the beam spot size is not changed or increased by reason of the beam velocity modulation and, therefore, the improvement in sharpness in the horizontal direction is not adversely affected by increasing beam spot size, as in the aperture correction or compensation technique. However, the conventional beam velocity modulation technique still has the disadvantage that the width of each white or bright portion of the picture or image reproduced on the screen is less than that which would result from the original video signal S _o in the absence of the beam velocity modulation, as is apparent from the comparison of FIG. 3E with FIG. 3A.
Generally, in order to avoid the foregoing disadvantage of the previously known beam velocity modulation technique, the present invention employs a waveshaping circuit receiving the original video signal and providing a corresponding compensated video signal in which the width of each high level signal portion is increased relative to the corresponding width of the original video signal. The compensated video signal from the mentioned waveshaping circuit is applied to the cathode or beam producing means of the cathode ray tube for modulating the intensity of the electron beam or beams therein in accordance with the compensated video signal, while the rising and falling edges of the high level signal portions of the compensated video signal are detected to provide a corresponding output or modulating signal applied to the beam velocity modulation means for modulating the scanning velocity of the electron beam or beams in accordance with such output signal.
Referring in detail to FIG. 4, it will be seen that, in the video signal reproducing apparatus 10 according to this invention, as there shown, an antenna 18 receives a television signal which includes the transmitted video signal S _T (FIG. 2A) and applies the same to conventional video circuits indicated schematically at 19 and which include the usual RF and IF amplifiers and video detector for deriving the original video signal S _O (FIG. 6A) from the received television signal. As noted, the video circuits 19 of television receiver 10 are conventional so that no detailed explanation thereof will be included herein. The video signal from circuit 19 is supplied through a video amplifier 20 to a waveshaping circuit 21 which, in accordance with this invention, is operative to increase the width of each high level portion of the original video signal S _O from video amplifier 20.
The waveshaping circuit 21 is shown to include a pair of transistors 22 and 23 having their collectors connected together to an operating voltage source +V _cc , while the emitters of transistors 22 and 23 are connected together to one end of a resistor 24 having its other end connected to ground. The original video signal S _O (FIG. 6A) is applied to the base of transistor 22 from video amplifier 20 through a resistor 25, and the base of transistor 22 is further connected to ground through a resistor 26. The original video signal S _O from video amplifier 20 is further applied through a resistor 27 and a delay line 28 to the base of transistor 23 which is further connected to ground through a resistor 29. The resistors 27 and 29 provide impedance matching for the delay line 28, while the resistors 25 and 26 are provided for level adjusting purposes, that is, to ensure that the level of the original video signal S _O applied to the base of transistor 22 from video amplifier 20 will be equal to the level of the delayed video signal S _D (FIG. 6B) applied to the base of transistor 23 and which is delayed by the time τ in respect to the original video signal. Finally, the output of waveshaping circuit 21 is derived from a connection point between the emitters of transistors 22 and 23 and resistor 24.
It will be apparent that, during the period T _A (FIG. 6C), the level of original video signal S _O applied to the base of transistor 22 is higher than the level of the delayed video signal S _D applied to the base of transistor 23, so that transistor 22 is turned ON and transistor 23 is turned OFF. During the next period T _B , at which time both original video signal S _O and delayed video signal S _D are at the same level, transistors 22 and 23 are both turned ON. Finally, during the concluding period T _C , the level of delayed video signal S _D is higher than the level of original video signal S _O , so that transistor 22 is turned OFF and transistor 23 is turned ON. Thus, as is apparent on FIG. 6C, the level of the compensated video signal S _K obtained across resistor 24, that is, at the output of waveshaping circuit 21, is equal to the level of the input video signal S _O during the period T _A , is equal to the level of either the original video signal S _O or the delayed video signal S _D during the period T _B , and is equal to the level of the delayed video signal S _D during the period T _C . In other words, transistors 22 and 23 of waveshaping circuit 21 operate as an OR gate circuit in respect to the original video signal S _O and the delayed video signal S _D applied to the two inputs of such OR circuit defined by the base electrodes of the two transistors. Further, by comparing the compensated video signal S _K (FIG. 6C) with the original video signal S _O (FIG. 6A), it will be appreciated that the effect of waveshaping circuit 21 is to increase the width of each high level portion of the original or incomming video signal.
Referring again to FIG. 4, it will be seen that the compensated video signal S _K is applied through a video amplifier 30 to the cathode electrode 12 of cathode ray tube 11 for modulating the intensity of electron beam B therein. Simultaneously, the rising and falling edges of the high level signal portions of compensated video signal S _K are detected to provide a corresponding output or modulating signal by which the scanning velocity of the electron beam B in the line-scanning direction is modulated. More particularly, in the television receiver 10 of FIG. 4, the compensated video signal S _K from waveshaping circuit 21 is applied to a differentiation circuit 31 which acts as a detector for detecting the rising and falling edges of the compensated video signal and which provides a corresponding output signal in the form of a differentiated signal S _V (FIG. 6D). Such differentiated signal S _V is applied to a beam velocity mo

dulation means, for example, in the form of the supplemental deflection device 32 of FIG. 4, for modulating the scanning velocity of the electron beam B in the line-scanning direction in accordance with the differentiated signal S _V from differentiator 31. The supplemental deflection device 32 may be constituted, as shown, by two spaced apart plate-like electrodes 32a and 32b directed vertically in cathode ray tube 11 and arranged for the passage of electron beam B therebetween, with the differentiated signal S _V being applied across the plate-like electrodes 32a and 32b so as to produce a corresponding electrical field by which the scanning velocity of the beam, in the line-scanning direction, is modulated, for example, as shown on FIG. 6E.
Although the beam velocity modulation means is, in the embodiment of FIG. 4, constituted by a supplemental deflection device 32 in the form of a pair of plate-like electrodes 32a, 32b across which the output of differentiation circuit 31 is applied, the present invention is preferably employed in connection with a cathode ray tube of the type disclosed in detail by U.S. Pat. No. 3,936,872, and having an electron gun provided with a special focusing electrode to also function as the beam velocity modulating means, as shown on FIG. 5. More particularly, in the cathode ray tube 11A of FIG. 5, the neck portion 33 of the tube envelope is shown to contain an electron gun structure including a cathode 12a, a control electrode or grid 35, an acceleration electrode or grid 36, a first anode electrode 37, a focusing electrode 38 and a second electrode 39 all arranged successively in axial alignment along the central axis 40 of the cathode ray tube. The focusing electrode 38 is shown to be tubular and to be formed in two parts 38a and 38b which are axially separated along a vertical plane that is inclined relative to the axis 40 of the tube. For the operation of electron gun 34, appropriate static or bias voltages are applied to grids 35 and 36 and to electrodes 37, 38 and 39. Thus, for example, a voltage of zero to -400 V. may be applied to grid 35, a voltage of zero to 500 V may be applied to grid 36, a relatively high voltage or potential, for example, an anode voltage of 13 to 20 KV. may be applied to electrodes 37 and 39, and a relatively low voltage or potential of zero to only several KV. may be applied to parts 38a and 38b of electrode 38, with all of the foregoing voltages being upon the bias voltage applied to cathode 12a as a reference. With the foregoing voltage distribution, an electron lens field is established around the axis of electrode 38 by the electrodes 37, 38 and 39 to form a main focusing lens by which the electron beam is focused at the screen of the cathode ray tube. Furthermore, the differentiated or modulation signal S _V from differentiation circuit 31 of FIG. 4 is applied between parts 38a and 38b of electrode 38 in superposed relation to the static or bias voltage applied to electrode 38 for forming the focusing lens. It will be apparent that, by reason of the described diagonal separation between parts 38a and 38b of focusing lens electrode 38, the application of the differentiated signal or modulation signal S _V across electrode parts 38a and 38b results in a respective electric field which is operative to deflect the electron beam or beams in the horizontal or line-scanning direction. Thus, the beam velocity in the line-scanning direction is modulated accordingly.
Whether the velocity modulation signal S _V is applied to the plates 32a and 32b of supplemental deflection device 32, or across the parts 38a and 38b of focusing electrode 38, it will be seen that, in accordance with this invention, such velocity modulation signal S _V (FIG. 6D) for effecting beam velocity modulation in the line-scanning direction is derived from the compensated video signal S _K (FIG. 6C) in which the width of each bright or white signal portion is enlarged as compared with the width thereof in the original video signal S _O (FIG. 6A). Therefore, the intensity of light emission is changed or varied in the horizontal direction across the screen in the manner represented by FIG. 6F, from which it is apparent that the sharpness of the reproduced image or picture in the horizontal direction is substantially improved. Furthermore, from a comparison of FIG. 6F with FIG. 6A, it will be apparent that, by a proper selection of the delay time τ of delay line 28, the width of the white or bright portion of the reproduced image or picture is not substantially decreased and may be made to accurately correspond to the width of corresponding high level portion of the original video signal. Therefore, the previously described disadvantage of the known technique for effecting beam velocity modulation has been avoided by the present invention.
Referring now to FIG. 7, it will be seen that, in accordance with another embodiment of this invention, a waveshaping circuit 21' which can be substituted for the waveshaping circuit 21 in the apparatus 10 of FIG. 4, includes a differentiation circuit 41, a polarity equalizer 42 and an adding circuit 43. The original video signal S _O (FIG. 8A) from video amplifier 20 on FIG. 4 is applied directly to one input of adding circuit 43 and also to differentiation circuit 41 which provides a corresponding differentiated signal S _A (FIG. 8B). The differentiated signal S _A from circuit 41 is applied to polarity equalizer 42 in which the negative polarity portion of the differentiated signal S _A , which corresponds to the falling edge of the original video signal S _O , is inverted so as to have a positive polarity. The resulting polarity equalized signal S _E (FIG. 8C) is applied to another input of adder circuit 43 so as to be added in the latter to the original video signal S _O and thereby obtain the compensated video signal S _K (FIG. 8D). Such compensated video signal S _K shown on FIG. 8D corresponds generally to the compensated video signal S _K previously described with reference to FIG. 6C, and is similarly applicable to amplifier 30 and differentiation circuit 31 of FIG. 4. It will be apparent that the compensated video signal S _K (FIG. 8D) obtained from waveshaping circuit 21' also has the width of its high level signal portions enlarged relative to the widths of such signal portions in the original video signal S _O . Therefore, when the compensated video signal S _K from waveshaping circuit 21' is applied through amplifier 30 to cathode 12 of cathode ray tube 11 and also to differentiation circuit 31 to form therefrom the beam velocity modulation signal S _V applied to the supplemental deflection device 32, the resulting beam velocity modulation is performed in the same manner as described above with reference to FIG. 4 so as to obtain improved horizontal sharpness of the resulting reproduced picture or image without narrowing of the bright or white areas of such image or picture.
As shown on FIG. 9, the polarity equalizer 42 employed in the waveshaping circuit 21' of FIG. 7 may simply consist of a first diode 44 connected in parallel with a series connection of an inverter 45 and a second diode 46. The diodes 44 and 46 both have the same polarity so that the positive polarity portion of the differentiated signal S _A passes through diode 44, while the negative polarity portion of signal S _A , after being inverted by inverter 45, passes through diode 46.
In the embodiment of the invention described above with reference to FIG. 4, the differentiation circuit 31 is employed for detecting the rising and falling edges of the high level signal portions of the compensated video signal S _K and for providing output signals or beam velocity modulation signals in correspondence to the detected rising and falling edges. However, reference to FIG. 10 will show that a circuit 31' of a type disclosed in detail in U.S. Pat. No. 3,936,872, may be employed in place of differentiation circuit 31 for providing the desired beam velocity modulating signal. More particularly, circuit 31' is known to contain a single delay line 47 having input and output ends 47a and 47b, with the compensated video signal S _K being applied to input end 47a by way of a transistor 48 of collector-common configuration which acts to amplify the signal without altering the phase thereof. More specifically, as shown, the compensated video signal S _K is applied to the base electrode of transistor 48 which has its collector connected to ground, while the emitter of transistor 48 is connected through a resistor 49 to an operating voltage source +V _cc , and through a resistor 50 to the input end 47a of delay line 47. Further, as shown, the output end 47b of delay line 47 is connected through a bleeder resistor 51 to ground, and is also connected to a transistor 52 of base-common configuration which acts as an impedance converter. More specifically, transistor 52 is shown to have its emitter connected to the output end 47b of delay line 47 while its base electrode is connected to ground through a capacitor 53 and also connected between biasing resistors 54 and 55 which are connected in series between operating voltage source +V _cc and ground. Finally, a resistor 56 is connected between the operating voltage source and the collector of transistor 52, and output terminals 57 and 58 are respectively connected to the input end 47a of delay line 47 and to the collector of transistor 52.
In circuit 31', bleeder resistor 51 is dimensioned to provide a relatively small current flow therethrough, while the input impedance, that is, the base-emitter impedance of transistor 52 is very small in respect to the impedance of resistor 51. Therefore, in response

to a transient or sharp change in the compensated video signal transmitted along delay line 47, the output end 47b of the latter is shorted to ground so as to cause a negative reflected wave to travel back along delay line 47 to its input end 47a. As a result of the foregoing, the resistor 56 detects the short circuit current at the output end of delay line 47, and more precisely at the collector of transistor 52, so as to provide a corresponding voltage or signal S _K1 at output terminal 58 which corresponds to the compensated video signal S _K once delayed by the delay line 47. Further, the reflected wave returning to the input end of delay line 47 in response to a transient change in the compensated video signal S _K results in a signal S _K2 that corresponds to the signal S _K twice delayed by the delay line 47. Therefore, in response to a transient change in the signal S _K , there is obtained at output terminal 57 a signal S _V1 equal to the difference between compensated video signal S _K and the twice delayed signal S _K2 . When using the circuit 31 of FIG. 10 in place of the differentiation circuit 31 in the apparatus of FIG. 4, the output signal S _K1 is applied to the cathode 12 of the cathode ray tube 11 for controlling the intensity of the electron beam, while the output signal S _V1 is applied from circuit 31' to supplemental deflecting device 32 for effecting the beam scanning velocity modulation.
In the above described embodiments of the invention, the signal S _V or S _V1 for controlling the beam scanning velocity modulation has been applied across the plates 32a and 32b of the supplemental deflection device 32 or across the parts 38a and 38b of the focusing lens electrode 38. However, it will be understood that, in all of the described embodiments of the invention, the signal S _V or S _V1 from circuits 31 or 31', respectively, can be superimposed on the horizontal sweep or deflection signal and applied with the latter to the horizontal deflection coil of the main deflection yoke 13 so as to again modulate the beam scanning velocity in the line scanning direction.
Further, in FIGS. 4 and 5 of the drawings, the invention has been illustrated as applied to a monochrome television receiver for modulating the beam scanning velocity of a single electron beam in the cathode ray tube 11 or 11A. However, it will be understood that the invention is similarly applicable to a color television receiver in which the luminance component of the color television signal is the video signal that is compensated in circuit 21 or 21' and then detected in circuit 31 or 31'.
In any event, it will be apparent that, in a television receiver or other video signal reproducing apparatus according to this invention, the sharpness of the reproduced image or picture is improved without a decrease in the width of the relatively bright or white areas of the reproduced picture.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the invention, as defined in the appended claims.

PHILIPS 26CS3890/08R CHASSIS K35 / PHILIPS Display device using scan velocity modulation / BEAMBOOSTER FOR 30AX CRT TUBE SYSTEM:To improve pictures to be displayed on a display screen of a display device, it is known to use scan velocity modulation. In scan velocity modulation the (horizontal) deflection rate of the electron beam(s) is modulated with the luminance component of the video signal. As a result of scan velocity modulation, the information of the video signal will no longer be displayed at the correct position on the display screen. By using the modulation signal applied to the scan velocity modulator also for modulating the (read) clock rate of the video signal from the memory, it can be ensured that the video signal and the (modulated) deflection signal are always in synchronism with each other.


1. A display device for displaying a video signal on a display screen of a display tube comprising at least one control electrode and deflection coils for deflecting at least one electron beam current, said display device further having an input for receiving the video signal, means for determining a derivative of a luminance component of the video signal, a scan velocity modulator for modulating the deflection rate of the electron beam current in the display tube in dependence upon the determined derivative, a position error correction circuit for correcting the video signal in dependence upon the derivative of the luminance component of the video signal, and means for applying the corrected video signal to the control electrode of the display tube, characterized in that the position error correction circuit comprises a frequency-modulatable clock (16) which is coupled to the means for determining the derivative of the luminance component of the video signal, said frequency-modulatable clock thereby generating a read clock signal; and a memory into which said video signal is written, said memory having a read clock signal input to which said read clock signal is applied, whereby the video signal stored in said memory is read at a frequency-modulated clock rate in dependence on said derivative of the luminance component. 2. A display device as claimed in claim 1, characterized in that the means for determining the derivative of the luminance component of the video signal comprise a clock signal generator, a further memory and a differentiator, the luminance Component of the video signal being written into said further memory under the control of said clock signal generator, and the luminance component stored in said further memory being applied to the differentiator. 3. A display device as claimed in claim 2, characterized in that the output of the differentiator is coupled to the scan velocity modulator for supplying a modulation signal. 4. A display device as claimed in claim 2, characterized in that the memory includes a write clock signal input coupled to the output of said clock signal generator so that the video signal is written into said memory at a fixed write clock rate u

nder control of the clock generator. 5. A display device as claimed in claim 1, characterized in that the means for applying the corrected video signal comprises a display tube control circuit for receiving the modulated video signal read from the memory and for applying the video signal suitable for display to the control electrode(s) of the display tube. 6. A display device as claimed in claim 1, characterized in that the display device further comprises a beam current modulator coupled to an output of said means for determining a derivative for modulating the electron beam current in dependence upon the determined derivative of the luminance component in the video signal. 7. A display device as claimed in claim 6, characterized in that the beam current modulator has an output coupled to the means for applying the corrected video signal to the control electrode of the display tube for adapting the video signal in the applying means in dependence upon the output signal of the beam current modulator. 8. A display device as claimed in claim 1, characterized in that the display device also comprises an aperture correction circuit for correcting the luminance component of the video signal in dependence upon the derivative of the luminance component, the display device comprising a comparator for comparing the luminance component with a reference value and for aperture-correcting said component in dependence upon the output signal of the comparator.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a display device for displaying a video signal on a display screen of a display tube comprising at least one control electrode and deflection coils for deflecting at least one electron beam current, said display device further having an input for receiving the video signal, means for determining a derivative of a luminance component of the video signal, a scan velocity modulator for modulating the deflection rate of the electron beam current in the display tube in dependence upon the determined derivative, a position error correction circuit for correcting the video signal in dependence upon the derivative of the luminance component of the video signal, and means for applying the corrected video signal to the control electrode of the display tube.
2. Description of the Related Art
A display device of this type is known from U.S. Pat. No. 4,183,064. In this known display device, the position error is corrected by enlarging the portion of a display line having a higher luminance with respect to a portion having a smaller luminance and by subsequently applying scan velocity modulation (so as to obtain an improved definition) at which the dark/light transition is delayed and the light/dark transition is brought forward. As a result, the picture to be displayed is displayed with the original picture contents (the same quantity of light and dark portions as in the original video signal). In this solution, a second error (enlarging the light portions) is deliberately introduced to correct the first error (reducing the light portions as a result of scan velocity modulation). This is not an ideal solution because the two errors must compensate each other in this case. Correcting a non-linear error by means of a linear system is not very well possible. The drawback is that the position error cannot be satisfactorily corrected in this way. At a less sharp transition from light to dark (or conversely), the second error will be too large so that it will overcompensate the first error, whereas with a very sharp transition, the second error is too small so that the first error is not fully compensated. A further drawback is that it is not easy to enlarge the portions of the video signal having a higher luminance/brightness. Moreover, by enlarging the light portion, the beam current is increased so that the definition is adversely influenced due to spot growth.
To give pictures a better (impression of) sharpness, manufacturers focus on improvements of the display tube, inter alia by providing an improved phosphor layer and by improving the electron gun/guns. Moreover, scan velocity modulation of the electron beam deflection is used in a display tube (as is described, for example in the above-mentioned U.S. Patent). In this method the scan velocity (deflection rate) is adapted to the picture contents, notably to brightness variations. In scan velocity modulation, the derivative of the luminance component of the video signal is determined. Generally, the second derivative of the luminance component is used, which second derivative is applied to a voltage amplifier, an output of which applies a voltage to, for example, a scan velocity modulation coil. If a voltage-controlled current source is used instead of the voltage amplifier, the first derivative of the luminance component is taken. Actually, the scan velocity modulation coil is then the second differentiator. The scan velocity modulation is proportional to the second derivative of the voltage across the coil. By using scan velocity modulation, a position error is produced on the display screen (the video information rate is no longer synchronous with the scan velocity) at which a dark/light transition of the video signal is shifted to the right and a light/dark transition of the video signal is shifted to the left on the display screen. Consequently, portions of the video signal having a higher brightness/luminance are reduced with respect to portions of the video signal having a smaller light intensity. For example, when a plurality of successive squares (for example, a chessboard) is displayed, this effect can be clearly observed: larger (darker) and smaller (lighter) squares instead of squares all having the same size.
SUMMARY OF THE INVENTION
It is, inter alia an object of the invention to eliminate the above-mentioned drawbacks. To this end, the display device according to the invention is characterized in that the position error correction circuit comprises a frequency-modulatable clock which is coupled to the means for determining the derivative of the luminance component of the video signal for frequency-modulating the read clock rate of the video signal stored in a memory.
By modulating (varying) the clock rate at which the video information is written or read, the position error caused by scan velocity modulation can be corrected. The video signal is applied to the display tube at the same information rate as the scan velocity. Here, a (position) error which would arise due to scan velocity modulation is thus corrected instead of making two errors which hopefully counteract each other and are equally large as described in said U.S. patent.
Literature describes all kinds of examples in which higher derivatives or combinations of different derivatives for correcting the position error are used instead of the first and second derivatives of the video signal for use in scan velocity modulation. However, this results in a full correction of the position error at most for given slopes of transitions from light to dark and vice versa, whereas the picture will only degrade in the case of other slopes. Moreover, this renders the scan velocity modulation circuit much more complicated and hence more expensive. The display device according to the invention provides a solution which is completely different. This solution is that it is not attempted to correct the position error by means of the scan velocity modulation method (or by introducing a second error) but by modulating the clock with which the video information and the deflection is maintained synchronous at all times, thus principally precluding a position error.
The clock modulator is controlled by the same signal or by a corresponding signal with which the scan velocity modulator is controlled.
An embodiment of a display device according to the invention is characterized in that the display device further comprises a beam current modulator for modulating the electron beam current in dependence upon the determined derivative of the video signal.

By using beam current modulation, brightness modulations occurring as undershoots and overshoots which may be produced by scan velocity modulation can be prevented or in any case reduced. This provides the possibility of using scan velocity modulation at a larger amplitude without this being a hindrance to the user of the display device, while a better picture sharpness is obtained. A larger amplitude of the scan velocity modulation results in a larger position error, which position error can be simply corrected again by means of the clock modulation.
A further embodiment of a display device according to the invention is characterized in that the display device also comprises an aperture correction circuit for correcting the luminance component of the video signal. By combining the scan velocity modulation with an aperture correction, a picture which is even sharper is obtained. At small or less steep jumps in the beam currents, the scan velocity modulation does not yield considerable improvements of the picture sharpness, whereas the opposite is true for aperture correction. By combining scan velocity modulation with an aperture correction, the sharpness of the picture can also be improved at these beam currents.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 shows a first embodiment of a display device according to the invention;
FIG. 2 shows an example of luminance variation of a video signal after scan velocity modulation;
FIG. 3 shows a second embodiment of a display device according to the invention;
FIG. 4 shows an example of beam current variation in the case of aperture correction; and
FIG. 5 shows an example of a display device according to the invention in which scan velocity modulation is combined with aperture correction.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows an embodiment of a display device W having inputs 1, 2 and 3 which receive a luminance component Y and chrominance components U and V, respectively, of a video signal. An input 4 of the display device receives a synchronizing signal sync. The luminance component Y of the video signal is applied to a memory 6 in which the luminance component is stored under the control of a clock signal generated in a clock generator 8. The memory is also used for an adapted delay until the relevant signals are satisfactorily timed. The clock generator 8 will generally be controlled by the synchronizing signal sync. The second derivative of the luminance component stored in the memory 6 is determined by a differentiator 10. Instead of a differentiator, one or two delay elements (for example, combined with the memory) may alternatively be used for determining the second derivative. As is known, the second derivative of the luminance component Y is necessary for generating scan velocity modulation. This second derivative is applied to a scan velocity modulator 12 which controls (for example) a modulation coil Lsvm for generating the scan velocity modulation of electron beam currents deflected in a display tube 14 for displaying the video signal on a display screen 15. As is common practice, the display tube is further provided with a line deflection coil Lx and a field deflection coil Ly. These coils are controlled in known manner by line and field deflection circuits (not shown).
The second derivative is also applied to a modulatable clock 16. The clock 16 may be coupled to, for example the clock generator 8. The luminance component Y of the video signal is also applied to a second memory 18. The chrominance components (U, V) of the video signal are applied to a third memory 20 and a fourth memory 22, respectively. All the memories 18, 20 and 22 are controlled by the clock generator 8 for writing the components Y, U and V of the video signal into the memories (for example, under the control of the synchronizing signal) and for reading the components of the video signal from the memories under the control of the modulatable clock 16. The respective components of the video signals are therefore read in a modulated form from the respective memories. By modulating the modulatable clock 16 with the second derivative of the luminance component of the video signal, the clock signal undergoes the same variation as the electron beam in the display tube 14. The information rate can be modulated by modulating the clock. The video signal undergoes the same variation as the deflection of the electron beam current/currents in the display tube by reading the components Y, U and V of the video signal from the memories 18, 20 and 22 under the control of this modulated clock signal. Consequently, the deflection signals (which determine the position on the display screen) and the video signal are always synchronous so that, in principle, there will be no position error. The modulatable clock 16 and the memories 18, 20 and 22 form part of a position error correction circuit 34 which corrects the position error on the screen (at transitions between portions having a lower and a higher luminance), which error is caused by scan velocity modulation. Subsequently, the three components of the video signal are applied to a display tube control circuit 24. YUV signals are converted into RGB signals in the display tube control circuit, which RGB signals are applied to the (three respective) control electrode(s) (C), for example, three electron guns of the display tube 14. If desired, a transition in luminance may be further intensified in the display tube control circuit by rendering, for example, a less sharp transition even sharper (at a constant beam current the luminance is inversely proportional to the scan velocity).
As is known, a dark/light transition results in undershoots and overshoots in the displayed video signal when applying scan velocity mod

ulation. This is understood to mean that at a dark/light transition, the luminance is decreased during a first part of the transition (lower than before the transition) and is increased during a last part of the transition (higher than after the transition). FIG. 2 shows this effect, with the position on the display screen being plotted on the horizontal axis and the luminance of the video signal being plotted on the vertical axis. FIG. 2 also shows, in broken lines, the luminance transition without scan velocity modulation. Due to this undershoot and overshoot, the impression of sharpness of the displayed video signal is intensified. However, a too large undershoot and/or overshoot is observed by the user as troublesome reflections and thereby detracts from the improved sharpness. The undershoots and overshoots are eliminated or at least reduced in luminance by using beam current modulation at a luminance transition of the video signal at which the beam current is increased during the first part of the transition and is decreased during the second part of the transition. This provides the possibility of using scan velocity modulation at a larger amplitude without producing effects which are troublesome to the user. This results in an even sharper display of the picture and also in a larger position error (which can, however, be simply corrected by means of clock modulation). An additional advantage of beam current modulation is that the beam current on the display screen is reduced during the second half of a rising edge (dark/light transition). This reduces the spot on the display screen so that the sharpness will further increase.
The embodiment of FIG. 1 shows a beam current modulator 26 in broken lines, which beam current modulator, similarly as the scan velocity modulator 12 and the modulatable clock 16, modulates the beam current under the control of the second derivative of the luminance component of the video signal. The beam current modulator applies a modulation signal to the display tube control circuit 24, which circuit corrects the R, G and B signals (or the Y component) with reference to this modulation signal and applies the corrected signals to the control electrodes C of the display tube 14. As described above, the amplitude of the scan velocity modulation can be increased without negative effects by using the beam current modulator. However, this results in a larger position error, but since the (read) clocks of the Y, U and V components of the video signal are modulated, this larger error is also corrected.
FIG. 3 shows a second embodiment of a display device. Elements denoted by the same reference numerals as in FIG. 1 have the same function. In this embodiment inputs 1, 2 and 3 of the display device receive R, G and B signals (from, for example a scart input). For the scan velocity modulation, it is necessary to determine the variation (derivative) of the luminance component of the video signal. In contrast to the embodiment shown in FIG. 1, the luminance component is now not directly available. To obtain the luminance component, the R, G and B signals are applied to a converter circuit 28 for determining the luminance component Y. The converter circuit is controlled by the clock generator 8. This luminance component is subsequently applied to the memory 6 whereafter the second derivative is determined in the differentiator 10. The R, G and B signals are also applied to the memories 18, 20 and 22, respectively (similarly as in FIG. 1). Now again these signals are written under the control of the clock generator 8 and read under the control of the modulatable clock 16 which, similarly as in FIG. 1, again receives a signal which is a measure of the second derivative. The display tube control circuit 24' need not perform the conversion YUV➝RGB in this case, because the R, G and B signals are applied thereto. This display device W may also be provided with a beam current modulator 26 which applies a modulation signal for the beam current to the display tube control circuit.
As described with reference to FIGS. 1, 2 and 3, the sharpness of a picture to be displayed can be improved by combining scan velocity modulation and clock modulation, and possibly beam current modulation. However, scan velocity modulation has a poor result at low mean beam currents and at small luminance transitions. Another way of improving the sharpness at small transitions in the luminance of the video signal of a picture to be displayed is the aperture correction (or spot size correction). At a large beam current the spot size is also (too) large. Edges (having a low intensity) of the aperture (spot) cannot be prevented from being incident on adjacent pixels. The blur which is then produced can be corrected in the video signal. If, due to the size of the spot, the number of phosphors luminescing on the display screen is larger than was intended, these adjacent phosphors are not excited by the correct beam current. This means that a given part of the information will land on adjacent phosphors. One manner of correcting this is to reduce the video signal for a given pixel by a suitably chosen fraction of the video signal which is associated with the adjacent pixels. These video signals can be obtained from the continuous video signal by means of delay lines. It is also possible to perform this operation on a digitized video signal. A correction signal Icor is derived from the original beam current I by means of, for example, a single or a double delay. This correction signal is then subtracted from the original beam current, which yields the aperture-corrected beam current Iapc. This is shown in FIG. 4 for a dark/light transition. As is apparent from this Figure, the beam current has an undershoot and an overshoot upon aperture correction. This is the reason why aperture correction does not yield any improvement at a high mean beam current and/or large transients, whereas a larger beam current (overshoot) produces such a spot growth that the improvement of the aperture (spot) is completely eliminated. However, there is an essential improvement at a low mean beam current.
FIG. 5 shows an embodiment of a display device W according to the invention in which scan velocity modulation is combined with aperture correction in such a way that the aperture correction prevails at a low mean beam current and the scan velocity modulation prevails at a high mean beam current. Elements having the same function as in FIG. 1 and/or 3 have the same reference numerals. The display device may also be provided with a beam current modulator 26. In this embodiment the luminance component Y of the video signal is not only applied to the memories 6 and 18 but also to a comparison circuit 28. In this comparison circuit, the luminance component Y is compared with a reference value Yref. If the luminance component Y is smaller than the reference value, the comparison circuit will supply a control signal under whose control switches S 1, $2, $3 and $4 are put from the position shown in FIG. 5 to the position not shown. In the shown position of the switches, the display device operates in conformity with the embodiment as shown in FIG. 1. In the position not shown the output of the differentiator 10 is coupled to an aperture correction circuit 30 via the switch S1. A second input of the aperture correction circuit receives, via the switch S3, the luminance component Y as stored in and read from the memory 18 (under the control of the clock generator 8, switch S2 in the position not shown). The aperture correction circuit computes a corrected luminance component, which corrected component is applied to the display tube control circuit 24 via the switch S4. The display tube control circuit 24 converts, inter alia, the incoming (corrected) luminance component Y and the chrominance components U and V into the R, G, B signals to be applied to the display tube 14. The aperture correction circuit 30 may subtract, for example, the second derivative of the luminance component from the luminance component so as to obtain a corrected luminance component. It is alternatively possible for the aperture correction circuit 30 to compute a corrected luminance component in a more complex manner. When the switches S1, S2, S3 and S4 are in the position shown in FIG. 5, the output of the differentiator 10 is connected to the input of the scan velocity modulator 12. In dependence upon the second derivative of the luminance component, this scan velocity modulator applies a control signal to the modulation coil Lsvm for generating the scan velocity modulation. The output of the differentiator 10 is also connected to the modulatable clock 16 which, as described with reference to FIGS. 1 and 3, supplies a modulated clock signal. This modulated c

lock signal is applied via the switch S2 to the memories 18, 20 and 22 for reading the components Y, U and V of the video signal in a modulated form. The output of the memory 18 is connected to one of the inputs of the display tube control circuit 24 via the switch S3. In this state, the aperture correction circuit 30 cannot apply an output signal to the display tube control circuit because the switch S4 is open. It will be evident that the corrections of the luminance component of the video signal by means of the aperture correction circuit 30 and the scan velocity modulator 12 may even better blend with each other, for example, by superimposing the two corrections. This can be realized, for example, by superimposing the two circuits with a weighting factor dependent on the video signal instead of by switching between the two circuits, so that the two areas will easily blend with each other.
The embodiments of a display device according to the invention are described with reference to color display tubes. It will be evident that the invention may also be used in a display device having a monochrome display screen or in (computer) monitors. In embodiments of digital television, the delay elements required for computing the derivatives can be easily realized by means of modulatable clock signals, etc.

PHILIPS 26CS3890/08R CHASSIS K35 CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.

1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.

Description:

The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.

Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply voltage device.

In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.

It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.

The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.

As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.

Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.

In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:

FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.

FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.

FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.

FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.

In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.

The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V _i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V _o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V _o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V ₀ . In fact, it is readily evident that output voltage V _o is proportional to the ratio δ :

V _o = V _i ^. δ

Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V ₀ . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V _o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V _o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).

However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V _o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.

In addition this facilitates smoothing of voltage V _o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V _o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.

It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.

In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.

A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.

In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V _o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.

It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i _C which flows in the collector of transistor 16 and of the drive voltage v ₁₄ across the terminals of secondary winding 14. During the flyback period (0, t ₁ ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v ₁₄ must then be absolutely negative. During the scan period (t ₁ , t ₄ ) a sawtooth current i _C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t ₃ when current i _C becomes zero lies, as is known, before the middle of the scan period. At the end t ₄ of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t _s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v ₁₄ is positive must end at the latest at the instant (t ₄ - t _s ) located after the commencement (t = 0) of the previous flyback.

The time δ T may be initiated at any instant t ₂ which is located between the end t ₁ of the flyback period and the instant t ₃ when collector current i _C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t ₂ , but collector current i _C is not influenced thereby, at least not when the supply voltage (= V _o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i _C of FIG. 2a represents the current flowing through the said efficiency diode.

After the instant t ₃ voltage v ₁₄ must be positive. In other words, the minimum duration of the period T when voltage v ₁₄ must be positive is (t ₄ - t _s ) - t ₃ whilst the maximum duration thereof is (t ₄ - t _s ) - t ₁ . In a television system employing 625 lines per raster the line period t ₄ is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t ₃ would be located approximately 26 μus after the instant t ₁ , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t _s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V _i has a peak-to-peak value of 40 V and V _i is nominally 270 V, then the lowest occurring V _i is:

0.85 × 270 V - 20 V = 210 V and the highest occurring V _i is

1.1 × 270 V + 20 V = 320 V. For an output voltage V _o of 135 V the ratio must thus vary between

δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.

A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V _i - V _o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V _o is maintained constant at nominal mains voltage V _o = δ V _inom . However, if as a result of an increase or a decrease of the mains voltage V _i increases or decreases proportionally therewith, i.e., V _i = V _i nom + Δ V, the positive portion of V ₁₄ becomes equal to n(V _i nom - V _o +Δ V) = n [(1 -δ)V _i nom +ΔV] = n(0.5 V _inom +ΔV) if δ = 0.5 for V _i = V _i nom. Relatively, this is a variation which is twice as great. For example, if V _i nom = 270 V and V _o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V _i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.

This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i _b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i _b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V _i = V _i nom +Δ V, then ##SPC1## because V _i nom = 2 V _o . Thus this variation is equal to that of the mains voltage and is not twice as great.

During switching off, t ₂ , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.

The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.

FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V _i - V _o = 0.5 V _i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V _i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.

Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.

In this connection it is to be noted that it is possible to obtain an output voltage V _o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V _i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.

The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.

If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V _o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V _o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.

The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V _o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V _i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.

Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V _o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.

Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.

As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.

A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V _o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.

Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.

The 50 Hz ripple voltage which is superimposed on the rectified input voltage V _i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V _i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.

PHILIPS 26CS3890/08R CHASSIS K35 PHILIPS TRD 3 (Tuning Remote Digital) Search type tuning system Chassis K35:Dics-Digital Tuning System For TV Receivers" by N.V. Philips' Gloeilampenfabrieken, Netherlands, 2/1977

A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past thosechannels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning systemfor a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control)detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.

Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuningsystems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.

Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptablereception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.

A)- A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A first programmable frequency divider controlled by a reversible counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator, after passing through another programmable frequency divider, also is applied. The phase comparator output is a tuning voltage used to control the tuning of the local oscillator. A logic circuit is coupled to sense predetermined relationships of signals from a picture carrier detector, a sound carrier detector, an AFT discriminator circuit, and the presence of vertical synchronization signal components for changing the count in the reversible binary counter to adjust the first programmable frequency divider to compensate for channel frequency offsets which may occur in excess of the pull-in range of the AFT discriminator circuit. To permit operation of the

receiver as a signal seek receiver, a pair of signal seek pushbuttons for the "up" and for the "down" direction, respectively, are provided. Operation of either of these pushbuttons functions in conjunction with further logic circuitry and in conjunction with timing circuitry to automatically step tune the receiver channel-by-channel in the selected direction until a channel with a signal present is sensed by the first logic circuit, whereupon the signal seek circuit operation is disabled until one or the other of the signal seek pushbuttons is reactivated.
1. A frequency synthesizer signal seek tuning system for a tuner of a television receiver capable of receiving a composite television signal, said system including in combination:

reference oscillator means providing a reference signal at a predetermined frequency;

local oscillator means in the tuner providing a variable output frequency in response to the application of a control signal thereto;

a programmable frequency divider having an input coupled to said reference oscillator means for producing an output signal having a frequency which is a programmable fraction of the frequency of the signal applied to the input thereto from saidreference oscillator means;

means coupled to the output of said programmable frequency divider and the output of said local oscillator means for developing a control signal and applying such control signal to said local oscillator means for controlling the frequency ofoperation thereof;

channel selection means coupled to said programmable frequency divider for establishing a predetermined initial programmable fraction therein each time a new channel is selected by said channel selection means;

control means coupled to the output of the tuner of the television receiver and further coupled to said programmable frequency divider for controlling said frequency divider to change the programmable fraction thereof in response to predeterminedconditions of the signals from the tuner; and

signal seek tuning means coupled to said channel selection means and said control means for causing said channel selection means to select a new channel in response to said predetermined conditions of the tuner signals persisting for a predetermined time period.

2. The combination according to claim 1, wherein the composite television signal has at least carrier signal components and synchronizing signal components and further including carrier sensing means coupled to receive at least the carriersignal components of the composite signal from the tuner and providing an output voltage indicative of the tuning of said receiver to a carrier component of said composite signal; and synchronizing signal component sensing means coupled to receive atleast said synchronizing signal components of the composite signal for providing a first predetermined output with synchronizing signal components sensed thereby; wherein said control means is coupled to the outputs of said carrier sensing means andsaid synchronizing signal components sensing means and further coupled to said programmable frequency divider means for changing the programmable fraction thereof in response to first predetermined conditions of signals at the outputs of said carriersensing means and said synchronizing signal components sensing means and the operation of said signal seek tuning means being terminated in response to second predetermined conditions of signals at the outputs of said carrier sensing means and saidsynchronizing signal components sensing means.

3. The combination according to claim 1, further including first and second switches in said signal seek tuning means for initiating a signal seek operation in the "up" and "down" directions, respectively, operation of one of said first andsecond switches causing said channel selection means to select the next channel in the selected direction and establishing said predetermined initial programmable fraction in said programmable frequency divider in response thereto.

4. The combination according to claim 3, wherein said control means terminates operation of said signal seek means in response to detection of second predetermined conditions of the signals from the tuner.

5. The combination according to claim 1, wherein said predetermined conditions of the tuner signals comprise first and second predetermined conditions, respectively; said programmable frequency divider has its input coupled to the output ofsaid reference oscillator means; and wherein said control means includes reversible digital counter means coupled to said programmable frequency divider, and logic circuit means coupled to the output of the tuner for causing said counter means to countin one direction when said first predetermined conditions exist and to count in the opposite direction when said second predetermined conditions exist.

6. The combination according to claim 5, further including additional means coupled to said counter means and coupled to said logic circuit means for inhibiting operation of said signal seek tuning means and for preventing a change in the countof said counter means when third predetermined signal conditions exist in the tuner output.

7. The combination according to claim 6, further including a second programmable frequency divider coupled to the output of said local oscillator means and producing an output signal having a frequency which is a programmable fraction of thefrequency of the signal applied to the input thereto from said local oscillator means; and wherein said channel selection means is further coupled to said second programmable frequency divider for controlling said second programmable frequency dividerto establish the programmable fraction thereof each time a new channel is selected by said channel selection means.

B)- A tuning system for a television receiver includes a local oscillator which is controlled first by a phase lock loop arrangement and then by an AFT discriminator arrangement for tuning the receiver to non-standard as well as standard frequency carriers. The phase lock loop arrangement includes a programmable divider for dividing the local oscillator frequency by a programmable factor corresponding to the presently selected channel. When the local oscillator is being controlled by the AFT discriminator arrangement, the count accumulated by the programmable divider during a reference interval determines how far the local oscillator frequency has drifted from its nominal value. If a predetermined frequency offset has been exceeded, control is returned to phase lock loop control and the programmable factor is incrementally changed.

1. In a system for tuning a television receiver to the various channels a viewer may select, apparatus comprising:

local oscillator means for generating a local oscillator signal;

counter means for generating a frequency divided signal by counting a predetermined number of periods of said local oscillator signal, said predetermined number being proportional to the frequency of said local oscillator signal;

means for generating a reference frequency signal;

phase control means for generating a control signal representing the phase and frequency deviation between said frequency divided signal and said reference frequency signal;

mode switching means for selectively coupling said control signal to said local oscillator means; said mode switching means initially coupling said control signal to said local oscillator means;

said local oscillator means changing the frequency of said local oscillator signal in response to said control signal until said frequency divided signal and said reference frequency signal to be in a predetermined phase and frequency relation;

said counter means accumulating a nominal number of counts during a predetermined portion of said frequency divided signal when said frequency divided signal and said reference signal are in said predetermined phase and frequency relationship;

means for generating a lock signal when said frequency divided signal and said reference frequency signal are in said predetermined phase and frequency relationship;

said mode switching means decoupling said control signal from said local oscillator means in response to said lock signal;

means for generating a count signal when said control signal is decoupled from said local oscillator means, said count signal having a duration with a predetermined time relationship to said reference frequency signal;

means responsive to said count signal for disabling said counter means from counting when said control signal is decoupled from said local oscillator means except during the duration of said count signal; and

means for generating an offset signal representing the deviation between the count accumulated by said counter means during a time interval corresponding to said predetermined portion of said frequency divided signal when said control signal isdecoupled from said local oscillator means and said nominal number of counts, said offset signal being coupled to said mode switching means to control the coupling of said control signal to said local oscillator means.

2. The apparatus recited in claim 1 wherein said means for generating said offset signal includes:

memory means for generating an output signal having a first amplitude when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;

means for resetting said memory means prior to the occurrence of said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillator means;

means for setting said memory means if the count accumulated by said counter during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillatormeans is less than said nominal number of counts by a first predetermined deviation; and

means for resetting said memory means if the count accumulated by said counter means during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said localoscillator means is greater than said nominal number of counts by a second predetermined deviation.

3. The apparatus recited in claim 1 wherein said counter means derives said frequency divided signal by counting a first number of periods during a first portion of said frequency divided signal and by counting a second number of periods duringa second portion of said frequency divided signal.

4. The apparatus recited in claim 3 wherein the various channels a viewer may select are partitioned into frequency bands, said first number is related to the channel selected by a viewer and said second number is related to the frequency bandin which the selected channel resides.

5. The apparatus recited in claim 4 wherein said predetermined portion is at least a part of said second portion.

6. The apparatus recited in claim 5 wherein said counter includes:

variable modulus frequency divider means for selectively dividing the frequency of said local oscillator signal by a first factor or a second factor, said first factor being related to the frequency spacing between channels in at least one ofsaid bands;

decade counter means for counting periods of the output signal of said variable modulus frequency divider;

channel number comparator means for generating a channel match signal when the number of periods counted by said decade counter means eq

uals said first number, said decade counter means being reset in response to said channel match signal;

first factor stop comparator means for generating a first factor stop signal when the number of periods counted by said decade counter means equals a third number, said third number being also related to the band in which the selected channelresides but less than said second number, said variable modulus divider means being caused to divide by said second factor in response to said first factor stop signal; and

added count comparator means for generating an added count match signal when the number of periods counted by said decade counter means equals said second number, said decade counter means being reset in response to said added count match signal,said variable modulus divider means being caused to divide by said first factor in response to said added count match signal.

7. The apparatus recited in claim 6 wherein said nominal number of counts equals said second number.

8. The apparatus recited in claim 7 wherein said means for generating said offset signal includes means for resetting at least said decade counter means and for causing said variable modulus divider to divide by said first factor in response tothe initiation of said count signal.

9. The apparatus recited in claim 7 wherein said means for generating said offset signal includes:

memory means for generating an output signal when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;

means for resetting said memory means prior to the occurrence of said first factor stop signal during the duration of said count signal when said control signal is decoupled from said local oscillator;

means for inhibiting the generation of said added count signal when said control signal is decoupled from said local oscillator;

means for setting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is less than said second number by a first predetermineddeviation; and

means for resetting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is greater than said second number by a secondpredetermined deviation.

10. The apparatus recited in claim 9 wherein said means for generating said offset signal includes means for repetitively generating said offset signal.

11. The apparatus recited in claim 1 wherein said means for disabling said counter means includes input switching means for selectively decoupling said local oscillator signal from said counter means when said control signal is decoupled fromsaid local oscillator means except in response to said count signal; and

said counter means includes means for generating an illegal signal when an illegal channel has been selected;

said input switching means also decoupling said local oscillator signal from said counter means in response to said illegal signal.

12. The apparatus recited in claim 11 wherein:

said means for generating said illegal signal includes band selection means for generating a band traversed signal whenever the count accumulated by said counter corresponds to the boundary of a band and means for generating a band signalrepresenting the band in which the selected channel resides in accordance with which of said band traversed signals have been generated during said first portion of said frequency divided signal, said means for generating a band signal generating saidillegal signal when a band signal is not generated.

13. The apparatus recited in claim 11 wherein said means for generating said reference frequency also includes means for deriving a signal having a predetermined frequency; and said input means includes means for coupling said signal having apredetermined frequency to said counter means in response to said illegal signal.
Description: The present invention pertains to television tuning systems including a phase locked loop frequency synthesizerand particularly pertains to frequency counters which may be utilized in such systems.

In concurrently filed U.S. patent application Ser. No. 70,849, and now U.S. Pat. No. 4,031,549 by Henderson et al., assigned to the same assignee as the present invention, there is described a tuning device system for a television receiverwhich includes a phase locked loop for tuning a local oscilator to the nominal local oscillator frequencies required to tune the receiver to RF carriers at standard broadcast frequencies allocated to the various channels a viewer may select. The tuningsystem also includes an automatic fine tuning (AFT) frequency discriminator for tuning the local oscillator to minimize any deviation between the frequency of an actual picture carrier and the nominal picture carrier frequency. If the receiver iscoupled to a television distribution system which provides RF carriers having nonstandard frequencies arbitrarily near respective ones of the standard broadcast frequencies, when the phase locked loop has achieved lock at a nominal frequency, a modecontrol unit selectively couples the discriminator and a frequency drift control circuit to the local oscillator. If the frequency of the local oscillator drifts more than a predetermined offset from the frequency synthesized under phase locked loopcontrol because no carrier has been detected by the discriminator, discriminator and drift control are terminated so that the receiver will not be tuned to an undesired carrier such as, for example, the lower adjacent channel sound carrier, and phaselocked loop control is reinitiated to synthesize a local oscillator signal having a frequency incremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. After the phase locked loop is locked at anincremented frequency, discriminator control is again initiated. If, during this cycle of discriminator control, the local oscillator again drifts more than the predetermined offset from the incremented local oscillator frequency because no carrier isdetected by the discriminator, phase locked loop control is again reinitiated to synthesize a local oscillator signal having a frequency decremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. Ifduring any discriminator control cycle the local oscillator has not drifted further than the predetermined offset because the discriminator has tuned the local oscillator to a carrier within the predetermined offset, phase locked loop control is notreinitiated and the tuning sequence is complete.

In order to reduce the complexity, and therefore the cost, of an implementation of such a tuning system, it is desirable that individual potions of the system be capable of performing more than one function. For example, in copending UnitedStates Patent Application Ser. No. 663,097 filed for R. M. Rast on Feb. 27, 1976, and now U.S. Pat. No. 4,009,439 and assigned to the same assignee as the present invention, which is hereby incorporated by reference, there is described a frequencydivider for a television tuning phase locked loop tuning system. For each channel a viewer selects, the divider divides the frequency of the local oscillator signal by a number proportional to the nominal local oscillator frequency by forming a signalincluding first and second portions having durations respectively equal to first and second numbers of periods of the local oscillator signal. The first number is related to the selected channel number. The second number is related to the frequencyband in which the selected channel resides. To generate signals including in which band the selected channel resides for use in the phase locked loop itself and in the local oscillator to control its frequency range, a band selection unit is included asan integral part of the divider.

In accordance with the present invention, a programmable counter which may be used, for example, in a phase locked loop portion of a tuning system of the type decribed in the concurrently filed Henderson et al. application referenced above todivide the frequency of the local oscillator by a number proportional to the nominal local oscillator frequency for a selected channel is arranged so that it may also serve to generate a signal indicating whether or not the frequency of the localoscillator has drifted beyond a predetermined frequency offset after phase locked loop control of the local oscillator has been terminated. When the local oscillator is under phase locked loop control, the programmable counter accumulates a nominalnumber of counts during a predetermined portion of its output signal. Means are provided for generating a count signal after phase locked loop control of the local oscillator has been terminated. The count signal has a duration with a predeterminedtime relationship to a reference signal to which the local oscillator signal is locked when the local oscillator is under phase locked loop control. The counter is disabled from counting when the local oscillator is not under phase locked loop controlexcept during the duration of the count signal. Offset detection means, in response to the count signal, generates an offset signal representing the deviation between the count accumulated during a time interval corresponding to the predeterminedportion after phase locked loop control of the local oscillator has been terminated to determine how far the frequency of the local oscillator has drifted from the frequency synthesized under phase locked loop control.





C)- A tuning system for a televisio

n receiver includes a phase locked loop (PLL) configuration and an automatic fine tuning (AFT) configuration which are selectively enabled to operate to tune the receiver to nonstandard as well as standard frequency RF carriers which may be provided by cable and master antenna systems. After the selection of a new channel, the operations of the PLL and AFT configurations are sequentially enabled by a mode control apparatus. During the operation of the AFT configuration, an offset detector determines when the frequency of the local oscillator signal is caused to be more than a predetermined offset from its value established during the previous operation of the PLL configuration. In response, the mode control unit reestablishes the operation of the PLL configuration. Channel selection apparatus causes a new channel to be selected after a predetermined number of alternate operating cycles of the two configurations.

1. Apparatus for selectively tuning a receiver to any one of a plurality of RF carriers associated with respective channels, comprising:
local oscillator means for generating a local oscillator signal;
mixer means for combining a selected one of said RF carriers with said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value;
phase locked loop (PLL) means for selectively controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal;
programmable fac

tor control means for determining programmable factor in accordance with the channel selected and for generating a CHANGE signal when a new channel is selected;
lock means for generating a LOCK signal when said local oscillator signal has a frequency substantially equal to said programmed frequency;
automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value;
offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means;
mode control means for enabling the operation of said PLL means in response to said CHANGE signal, for enabling the operation of said AFT means in response to said LOCK signal and for again enabling the operation of said PLL means in response to said OFFSET signal; and
channel selection means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated a predetermined number of times.
2. The apparatus recited in claim 1 wherein:
said predetermined number of times is equal to one.
3. The apparatus recited in claim 1 wherein:
said programmable factor control means is coupled to counter means for counting the number of times said OFFSET signal is generated to change said programmable factor by an increment less than the difference between programmable factors associated with respective adjacent channels when said OFFSET signal is generated a second predetermined number of times less than said first mentioned predetermined number of times; and
said channel selection means is also coupled to said counter means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated said first mentioned predetermined number of times.
4. The apparatus recited in claim 3 wherein:
said programmable factor control means increases said programmable factor by said increment in response to a first generation of said OFFSET signal and decreases said programmable factor by said increment in response to a second generation of said OFFSET signal and changes said programmable factor to the value associated with the next channel in response to a third generation of said OFFSET signal.
5. The apparatus recited in claim 4 wherein:
said programmable factor control means includes inhibiting means for inhibiting said programmable factor control means from changing said programmable factor to the value in response to said OFFSET signal after a predetermined time longer than the time required to tune said receiver to a selected channel.

Description:

BACKGROUND OF THE PRESENT INVENTION
The present invention relates to search type tuning systems.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past those channels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning system for a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control) detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuning systems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.
Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptable reception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
SUMMARY OF THE PRESENT INVENTION
The present invention is an improvement to the type of electronic tuning system which includes first tuning means for tuning a tuner to standard frequencies associated with respective channels, second tuning means for tuning the tuner to reduce deviations between the frequency of an IF carrier generated by the tuner and its desired or nominal value that may arise due to, e.g., offsets in the frequencies of received RF carriers, and mode switching means for selectively applying the first and second tuning control signals to the tuner. In this type of electronic tuning system, the operation of the first tuning means is enabled after a new channel is selected

and the operation of the second tuning means is enabled after the first tuning means has completed its operation. During the operation of the second tuning means, an offset detector determines when the frequency of a local oscillator signal generated by the tuner becomes offset from value established during the operation of the first tuning means and causes the operation of the first tuning means to again be enabled.
In accordance with the present invention, search means are provided in the above described type of electronic tuning system for causing a new channel to be selected if no RF carrier is tuned by the end of a predetermined number of operating cycles of the second tuning means.

PHILIPS 26CS3890/08R CHASSIS K35 Channel selector having a plurality of tuning systems:A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.

1. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-state switching circuit.


2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.

3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.

4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.

5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.


6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.


7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.

8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.

9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.

Description:

BACKGROUND OF THE INVENTION
This invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.

PHILIPS SAB1018
The SAB1018 is a 950MHz frequency divider 256:1 with high input sensitivity preferred for use in HF divider applications for synthesizer tuning systems

In the figure above the latter indicates an infrared remote control transmitter, comprising a keyboard and known coding and transmitting circuits (e.g. the integrated circuit SAB 3021 of the firm Philips); the other indicates an infrared receiving circuit comprising an amplifier and a decoder (e.g. integrated circuit SAB 3042 of the firm Philips); the outputs D (data output) and C (clock output) are coupled to a known control unit , which controls the tuning and the analogic controls of the television receiver (e.g. comprising the integrated circuits SAB 1018, SAB 3034 and the microprocessor 8048 of the firm Philips), and to a teletext signals decoder circuit 4, of known type (including for instance the integrated circuits SAB 5020, SAB 5030, SAB 5040 and SAB 5050 of the firm Philips).

 

 

 

 

 

 

 

 

 

 

 

 

 

PHILIPS  26CS3890/08R GOYA VT PRINTER CHASSIS K35    Television receiver including a teletext decoder :
 
 PREMISE:
 
 In any normal television system, the transmission of the wide band video signals which are to produce the actual picture elements on the screen of the receiver is interrupted between the scannning periods for line and field synchronization purposes. Consequently, there are periods during which no video signals are being transmitted. It is now possible to use these periods for the transmission of data which is not necessarily concerned with the video transmission itself.

Basically, data representable by standard symbols such as alpha-numeric symbols can be transmitted via a restricted channel provided that the rate of transmission is restricted. It is now possible to use periods as aforesaid especially the line times of the field blanking intervals (i.e. the times of the individual lines occurring between fields which correspond with the times occupied by video signals on active picture lines), for the transmission of pages of data. Typically, using 8-bit digital signals representing alpha-numeric characters (7 bits of data plus 1 bit for protection) at a bit rate of 2.5M bit per second, 50 pages of data each consisting of 22 strips of 40 characters can be transmitted repeatedly in a total cycle time of 90 seconds using only a single line of the field blanking period per field of the 625 lines system as operated in the United Kingdom.

Data transmission as described above is already commercially available in the United Kingdom under the name "Teletext", and transmitters and receivers are described in more detail in our U.K. Pat. Nos. 1,486,771; 1,486,772; 1,486,773 and 1,486,774.

Existing teletext displays consist of 40 characters per row and 24 rows per page. The U.K. teletext transmission standard specifies a data rate of 6.9375 Mbits per second (which has proven to be at the upper reasonable limit of transmission rate for system I, B/G system) so as just to achieve transmission of a complete row of text on one video line of the field blanking time.

The advantage of conveying one row of text on one video line is to achieve maximum economy in requirements for transmission of addressing information needed to correctly position the text information on the displayed page. Since whole rows of text are transmitted on each line, only a row number need be transmitted with each data line of text. Row zero which acts as the page demarcation signal requires additional page numbering information and also incorporates various display and interpretation codes appropriate to the particular page. In order to facilitate parallel magazine working every row of text also incorporates a 3-bit magazine number, being the most significant digit of the page number.

The above structure incorporating as it does one text row on every data line thus results in a very efficient utilization of the transmission facility. However, the existing Teletext transmissions do have limitations in so far as they are less satisfactory when in a "graphics" mode as compared with an "alpha-numeric" mode.


 In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.
 
 
 
  1. A receiver for television signal s including a teletext decoder circuit for decoding teletext signals constituted by character codes which are transmitted in the television signal, and comprising:

a video input circuit receiving the television signal and converting it into a serial data flow;

an acquisition circuit for receiving the serial data flow supplied by the video input circuit and selecting that part therefrom which corresponds to the teletext page described by the viewer;

a character generator comprising:

a memory medium addressed by the character codes which together represent the teletext page desired by the user and which in response to each character code successively supply m2 series of m1 simultaneously occurring character picture element codes each indicating wether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;

a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;

a converter circuit receiving each series of m1 simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m1 character picture element codes of a series one after the other and at the display clock pulse rate;

a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed;

characterized in that

the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulse to function as display clock pulses;

the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.


2. A character generator for use in a receiver teletext claim 1, comprising:

a memory medium which is addressable by character codes and successively applies m2 series of m1 simultaneously occurring character picture element codes in response to a character code applied as an address thereto, each character picture element code indicating whether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;

a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;

a converter circuit receiving each series of m1 simultaneously occurring character picture element codes and the display clock pulses for supplying the m1 character picture element codes of the series one after the other at the display clock pulse rate;

a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed; characterized in that

the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulses to function as display clock pulses;

the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.


Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.

2. Description of the Prior Art

As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.

Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.

A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.

For the purpose of display each character is considered as a matrix of m1 ×m2 picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m1 qμsec, each line has a length of 40 m1 μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m1 =6 have been chosen.

The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m1 ×m2 memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m1 memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m1 substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m1 character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).

The frequency fd at which the display clock pulses occur directly determines the length of a picture element and hence the character width. In the above-mentioned case in which m1 =6 and in which a character width of 1 μsec is chosen, this means that fd =6 MHz. A change in the rate of the display clock pulses involves a change in the length of a line of the page to be displayed (now 40 μsec). In practice a small deviation of, for example, not more than 5% appears to be acceptable. For generating the display clock pulses the generator circuit receives reference clock pulses. In the decoder circuit described in Reference 1 these reference clock pulses are also supplied at a rate of 6 MHz, more specifically by an oscillator specially provided for this purpose.

OBJECT AND SUMMARY OF THE INVENTION

A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.

According to the invention,

the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m1 clockpulses to function as display clock pulses;

the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.

The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m1 picture elements, m1 reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.

REFERENCES

1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.

2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.

3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.

4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;

FIG. 2 shows different matrices of picture elements constituting a character;

FIG. 3 shows diagrammatically the general structure of a character generator;

FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and

FIG. 5 shows some time diagrams to explain its operation;

FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and

FIG. 7 shows some time diagrams to explain its operation;

FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.

EXPLANATION OF THE INVENTION

General structure of a TV receiver

FIG. 1 shows diagrammatically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2 receiving a television signal modulated on a high-frequency carrier, which signal is processed in a plurality of processing circuits. More particularly, it is applied to a tuning circuit 23 (tuner or channel selector). This circuit receives a band selection voltage VB in order to enable the receiver to be tuned to a frequency within one of the frequency bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning voltage VT with which the receiver is tuned to the desired frequency within the selected frequency band.

This tuning circuit 3 supplies an oscillator signal having a frequency of fOSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.

The signal CVBS thus obtained is also applied to a colour decoder circuit 5. this circuit supplies the three primary colour signals R', G' and B' which in their turn are applied via an amplifier circuit 6 to a display device 7 in the form of a display tube for the display of broadcasts on a display screen 8. In the colour decoder circuit 5 colour saturation, contrast and brightness are influenced by means of control signals ANL. The circuit also receives an additional set of primary colour signals R, G and B and a switching signal BLK (blanking) with which the primary colour signals R', G' and B' can be replaced by the signals R, G and B of the additional set of primary colour signals. A Philips IC of the TDA 356X family described in Reference 3 can be used for this circuit 5.

The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency fo from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.

The Philips IC SAA 5030 may be used as video input circuits 91, the Philips IC SAA 5040 may be used as teletext acquisition and control circuit, a 1K8 RAM may be used as page memory, a modified version of the Philips IC SAA 5050 may be used as character generator 94 and a modified version of the Philips IC SAA 5020 may be used as control circuit 95, the obvious modification being a result of the fact that this IC is originally intended to receive reference clock pulses at a rate of 6 MHz for which 13.5 MHz has now been taken.

The acquisition and control circuit 92 is also connected to a bus system 11. A control circuit 12 in the form of a microcomputer, an interface circuit 13 and a non-volatile memory medium 14 are also connected to this system. The interface circuit 13 supplies the said band selection voltage VB, the tuning voltage VT and the control signals ANL for controlling the analog functions of contrast, brightness and colour saturation. It receives an oscillator signal at the frequency f'OSC which is derived by means of a frequency divider 15, a dividing factor of which is 256, from the oscillator signal at the frequency fOSC which is supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 13 combined constitute a frequency synthesis circuit. The Philips IC SAB 3035 known under the name of CITAC (Computer Interface for Tuning and Analog Control) and described in Reference 4 can be used as interface circuit 13. A specimen from the MAB 84XX family, manufactured by Philips, can be used as a microcomputer.

The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage VB and a given tuning voltage VT so that the receiver is tuned to the desired transmitter.

For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.

The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receives operating instructions and activates, via the bus system 11, one of the circuits connected thereto. It is to be noted that an operating instruction may be a single instruction, that is to say, it is complete after depressing only one key. It may also be multiple, that is to say, it is not complete until two or more keys have been depressed. This situation occurs, for example, when the receiver is operating in the teletext mode. Operation of figure keys then only yields a complete operating instruction when, for example, three figure keys have been depressed. As is known, such a combination results in the page number of the desired teletext page.

The character generator

As already stated, a character is a matrix comprising m2 rows of m1 picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m1 =6 and m2 =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.

FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m1 ×m2 memory elements each comprising a character picture element code. Each m1 ×m2 character picture element code corresponds to a picture element of the character and defines, as already stated, whether the relevation picture element must be displayed in the so-called foreground colour or in the so-called background colour. Such a character picture element code has the logic value "0" or "1". A "0" means that the corresponding picture element must be displayed in the background colour (for example, white). The "1" means that the corresponding picture element must be displayed in the foreground colour (for example, black or blue). At C in FIG. 2 there is indicated, the contents of the sub-memory for the character shown at B in FIG. 2.

The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.

The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.

The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f0. In the character generator described in Reference 2, page 391, f0 is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.

When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f0 is not a rational multiple of 6 MHz, for example, if f0 =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.

FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec.

An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding network 9442 each time supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse in a group of fourteen reference clock pulses. More particularly the display clock pulse, which is obtained each time in response to the first reference clock pulse of a group, is applied to the output line 9443, whilst the other display clock pulses are applied to the output line 9444. Thus, the pulse series shown at B and C in FIG. 5 occur at these output lines 9443 and 9444, respectively.

The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.

This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register elements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422.

Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.

The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.

The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.

As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner.

In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6 by ensuring that two consecutive picture elements partly overlap each other. This is realized in the converter circuit shown in FIG. 4 by means of a rounding circuit 9427 which receives the character picture element codes occurring at the output of the shift register circuit 9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D flip-flop 9427(2). The T input of this flip-flop receives the clock pulses shown at E in FIG. 5, which pulses are derived from the reference clock pulses TR by means of a delay circuit 9427(3). This circuit has a delay time t0 for which a value in the time diagram indicated at E in FIG. 5 is chosen which corresponds to half a clock pulse period of the reference cock pulses. The character picture element codes supplied by the shift register circuit 9420 are now applied directly and via the D flip-flop 9427(2) to the OR gate which thereby supplies the six character picture element codes CH(.) in the time intervals as indicated at F in FIG. 5. The result of this measure for the display of the character with the letter A is shown at F in FIG. 2.

The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providing it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 have the same reference numerals. The converter circuit 942 shown in FIG. 8 differs from the circuit shown in FIG. 6 in that the said rounding circuit denoted by the reference numeral 9428 is incorporated between the pulse widening circuit 9426 and the AND gate circuits 9424(.). More particularly this rounding circuit is a pluriform version of the rounding circuit 9427 shown in FIG. 4 and is constituted by six D flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the respective control signals S(1) to S(6) directly and via the D flip-flops. The T inputs of these D flip-flops again receive the version of the reference clock pulses delayed over half a reference clock pulse period by means of the delay circuit 94210. This rounding circuit thus supplies the control signals S'(.) shown in FIG. 7.

 Other References:
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5030 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.

AFIPS Conference Proceedings, May 1981, by Rocchetti, "Vision II: A Dynamic Raster-Scandisplay", pp. 671-676.
Computer Design, vol. 18, No. 10, Oct. 1979, by Hughes, "Videotex and Teletext Systems", pp. 10-23.
NHK Laboratories Note, No. 249, Mar. 1980, by Fujiwara, "A Versatile Editing Equipment for Japanese Teletext", pp. 1-9.
ANT Abstract of New Technology, NTN 77/0255, 1977 (May), by McDonough, "Automatic Digitizing System".
The SERT Journal, vol. 11, Oct. 1977, by Insam et al., "An Integrated Teletext and Viewdata Receiver", pp. 210-213.
Wireless World, Nov. 1978 by Hinton, "Character Rounding for the Wireless World Teletext Decoder", pp. 49-53.
Inspec, GEC Journal of Science and Technology, vol. 41, No. 4, 1974, by Biggs et al., "Broadcast Data in Television", pp. 117-124.
Texas Instruments, Application Report B183, by Norris et al., "The TIFAX XM II Teletext Decoder", pp. 1-20.
IEEE Transactions on Consumer Electronics, vol. CE-26, No. 3, Aug. 1980, (New York, U.S.), pp. 605-614, by Bown et al., "Comparative Terminal Realizations with Alpha-Geometric Coding".
Consumer Electronics, vol. CE-22, No. 3, Aug. 1976 by Norris et al., "Teletext Data Decoding-The LSI Approach", pp. 247-252.

Inventors:
Van Gestel, Henricus (Eindhoven, NL)  Philips Corporation (New York, NY)

Brockhurst, David M. (Winchester, GB)
Vivian, Roy H. (Andover, GB)
Dyer, Martyn R. (Romsey, GB) Independent, Broadcasting Authority (London, GB2)
Day, Stephen (Winchester, GB)