Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.


Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....
Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !
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©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of
Engineer Frank Sharp. NOTHING HERE IS FOR SALE !

Sunday, December 25, 2011

PHILIPS 26CP2402/08R VELASQUEZ CHASSIS K12Z INTERNAL VIEW.























This version of the PHILIPS K12z is introducing the TRD 2 RC5 TUNING SYSTEM (TUNING REMOTE DIGITAL) WHICH allows direct selection of channel frequency on front keyboard or even via remote through a help of a Ucontroller which sends command to the TRD Units system.
The system is developed on one big board carrying all functions except timer and frontend sections.

Furthermore it has a programmable realtime digital clock which allows to start the tellye at a prefixed time on a prefixed program and prefixed day of the week with even separated and dedicated Ucontroller for timer and displays.


FURTHERMORE The PHILIPS CHASSIS K12z WAS the first PHILIPS monocarrier type chassis with isolated from mains circuits. Previous K12 was direct mains supply type.

The PHILIPS chassis K12z is using the 30AX system crt tube family instead of the 20 AX originally used.

The chassis is a pretty unique type because it was introducing improvements and technology philosophy kindly singular and unique in it's fashion.





From signal processing to Video Matrixing to power supply technology and many further aspects this chassis was a reference to understand PHILIPS development flexibility.

This chassis has known many further versioning and enhancements even in more sophisticated and complex types with different CRT TUBE like the 30AX FAMILY.

Modularity is the main concept of construction but some Units like the E/W and FRAME UNIT gave problems in the insertion slot which often was burning the contacts producing several faults.

The solution was simple: A complete hardening with soldering and reworking of the enpoints of the Units contacts was a definitive solution for long time. But when the damage was more extended the only solution was to direct wire all contacts from Unit to chassis !


Line Deflection + EHT, Line synchronized Supply, EW Correction + Supply, Frame Deflection, Signal Section Parts.


PHILIPS 26CP2402/08R CHASSIS K12Z CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:

Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:

A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.






1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.

Description:

The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.

Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit emp
loys a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.

In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.




It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.

The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.


As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.

Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.

In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:


FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.

FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.

FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.

FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.

In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.

The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :

V o = V i . δ

Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V 0 . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).

However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.

In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.

It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.

In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.

A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.

In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.

It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that
switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.

The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.

After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:

0.85 × 270 V - 20 V = 210 V and the highest occurring V i is

1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between

δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.

A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.

This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.

During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.

The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.

FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.

Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.

In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.

The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.

If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.

The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.

Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.

Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.

As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.

A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.

Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.

The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.


PHILIPS 26CP2402/08R CHASSIS K12Z PHILIPS TRD 2 (Tuning Remote Digital) Search type tuning system Chassis K12z:Dics-Digital Tuning System For TV Receivers" by N.V. Philips' Gloeilampenfabrieken, Netherlands, 2/1977


A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past thosechannels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning systemfor a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control)detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.

Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuningsystems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.

Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptablereception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.

A)- A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A first programmable frequency divider controlled by a reversible counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator, after passing through another programmable frequency divider, also is applied. The phase comparator output is a tuning voltage used to control the tuning of the local oscillator. A logic circuit is coupled to sense predetermined relationships of signals from a picture carrier detector, a sound carrier detector, an AFT discriminator circuit, and the presence of vertical synchronization signal components for changing the count in the reversible binary counter to adjust the first programmable frequency divider to compensate for channel frequency offsets which may occur in excess of the pull-in range of the AFT discriminator circuit. To permit operation of the
receiver as a signal seek receiver, a pair of signal seek pushbuttons for the "up" and for the "down" direction, respectively, are provided. Operation of either of these pushbuttons functions in conjunction with further logic circuitry and in conjunction with timing circuitry to automatically step tune the receiver channel-by-channel in the selected direction until a channel with a signal present is sensed by the first logic circuit, whereupon the signal seek circuit operation is disabled until one or the other of the signal seek pushbuttons is reactivated.
1. A frequency synthesizer signal seek tuning system for a tuner of a television receiver capable of receiving a composite television signal, said system including in combination:

reference oscillator means providing a reference signal at a predetermined frequency;

local oscillator means in the tuner providing a variable output frequency in response to the application of a control signal thereto;

a programmable frequency divider having an input coupled to said reference oscillator means for producing an output signal having a frequency which is a programmable fraction of the frequency of the signal applied to the input thereto from saidreference oscillator means;

means coupled to the output of said programmable frequency divider and the output of said local oscillator means for developing a control signal and applying such control signal to said local oscillator means for controlling the frequency ofoperation thereof;

channel selection means coupled to said programmable frequency divider for establishing a predetermined initial programmable fraction therein each time a new channel is selected by said channel selection means;

control means coupled to the output of the tuner of the television receiver and further coupled to said programmable frequency divider for controlling said frequency divider to change the programmable fraction thereof in response to predeterminedconditions of the signals from the tuner; and

signal seek tuning means coupled to said channel selection means and said control means for causing said channel selection means to select a new channel in response to said predetermined conditions of the tuner signals persisting for a predetermined time period.

2. The combination according to claim 1, wherein the composite television signal has at least carrier signal components and synchronizing signal components and further including carrier sensing means coupled to receive at least the carriersignal components of the composite signal from the tuner and providing an output voltage indicative of the tuning of said receiver to a carrier component of said composite signal; and synchronizing signal component sensing means coupled to receive atleast said synchronizing signal components of the composite signal for providing a first predetermined output with synchronizing signal components sensed thereby; wherein said control means is coupled to the outputs of said carrier sensing means andsaid synchronizing signal components sensing means and further coupled to said programmable frequency divider means for changing the programmable fraction thereof in response to first predetermined conditions of signals at the outputs of said carriersensing means and said synchronizing signal components sensing means and the operation of said signal seek tuning means being terminated in response to second predetermined conditions of signals at the outputs of said carrier sensing means and saidsynchronizing signal components sensing means.

3. The combination according to claim 1, further including first and second switches in said signal seek tuning means for initiating a signal seek operation in the "up" and "down" directions, respectively, operation of one of said first andsecond switches causing said channel selection means to select the next channel in the selected direction and establishing said predetermined initial programmable fraction in said programmable frequency divider in response thereto.

4. The combination according to claim 3, wherein said control means terminates operation of said signal seek means in response to detection of second predetermined conditions of the signals from the tuner.

5. The combination according to claim 1, wherein said predetermined conditions of the tuner signals comprise first and second predetermined conditions, respectively; said programmable frequency divider has its input coupled to the output ofsaid reference oscillator means; and wherein said control means includes reversible digital counter means coupled to said programmable frequency divider, and logic circuit means coupled to the output of the tuner for causing said counter means to countin one direction when said first predetermined conditions exist and to count in the opposite direction when said second predetermined conditions exist.

6. The combination according to claim 5, further including additional means coupled to said counter means and coupled to said logic circuit means for inhibiting operation of said signal seek tuning means and for preventing a change in the countof said counter means when third predetermined signal conditions exist in the tuner output.

7. The combination according to claim 6, further including a second programmable frequency divider coupled to the output of said local oscillator means and producing an output signal having a frequency which is a programmable fraction of thefrequency of the signal applied to the input thereto from said local oscillator means; and wherein said channel selection means is further coupled to said second programmable frequency divider for controlling said second programmable frequency dividerto establish the programmable fraction thereof each time a new channel is selected by said channel selection means.

B)- A tuning system for a television receiver includes a local oscillator which is controlled first by a phase lock loop arrangement and then by an AFT discriminator arrangement for tuning the receiver to non-standard as well as standard frequency carriers. The phase lock loop arrangement includes a programmable divider for dividing the local oscillator frequency by a programmable factor corresponding to the presently selected channel. When the local oscillator is being controlled by the AFT discriminator arrangement, the count accumulated by the programmable divider during a reference interval determines how far the local oscillator frequency has drifted from its nominal value. If a predetermined frequency offset has been exceeded, control is returned to phase lock loop control and the programmable factor is incrementally changed.

1. In a system for tuning a television receiver to the various channels a viewer may select, apparatus comprising:

local oscillator means for generating a local oscillator signal;

counter means for generating a frequency divided signal by counting a predetermined number of periods of said local oscillator signal, said predetermined number being proportional to the frequency of said local oscillator signal;

means for generating a reference frequency signal;

phase control means for generating a control signal representing the phase and frequency deviation between said frequency divided signal and said reference frequency signal;

mode switching means for selectively coupling said control signal to said local oscillator means; said mode switching means initially coupling said control signal to said local oscillator means;

said local oscillator means changing the frequency of said local oscillator signal in response to said control signal until said frequency divided signal and said reference frequency signal to be in a predetermined phase and frequency relation;

said counter means accumulating a nominal number of counts during a predetermined portion of said frequency divided signal when said frequency divided signal and said reference signal are in said predetermined phase and frequency relationship;

means for generating a lock signal when said frequency divided signal and said reference frequency signal are in said predetermined phase and frequency relationship;

said mode switching means decoupling said control signal from said local oscillator means in response to said lock signal;

means for generating a count signal when said control signal is decoupled from said local oscillator means, said count signal having a duration with a predetermined time relationship to said reference frequency signal;

means responsive to said count signal for disabling said counter means from counting when said control signal is decoupled from said local oscillator means except during the duration of said count signal; and

means for generating an offset signal representing the deviation between the count accumulated by said counter means during a time interval corresponding to said predetermined portion of said frequency divided signal when said control signal isdecoupled from said local oscillator means and said nominal number of counts, said offset signal being coupled to said mode switching means to control the coupling of said control signal to said local oscillator means.

2. The apparatus recited in claim 1 wherein said means for generating said offset signal includes:

memory means for generating an output signal having a first amplitude when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;

means for resetting said memory means prior to the occurrence of said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillator means;

means for setting said memory means if the count accumulated by said counter during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillatormeans is less than said nominal number of counts by a first predetermined deviation; and

means for resetting said memory means if the count accumulated by said counter means during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said localoscillator means is greater than said nominal number of counts by a second predetermined deviation.

3. The apparatus recited in claim 1 wherein said counter means derives said frequency divided signal by counting a first number of periods during a first portion of said frequency divided signal and by counting a second number of periods duringa second portion of said frequency divided signal.

4. The apparatus recited in claim 3 wherein the various channels a viewer may select are partitioned into frequency bands, said first number is related to the channel selected by a viewer and said second number is related to the frequency bandin which the selected channel resides.

5. The apparatus recited in claim 4 wherein said predetermined portion is at least a part of said second portion.

6. The apparatus recited in claim 5 wherein said counter includes:

variable modulus frequency divider means for selectively dividing the frequency of said local oscillator signal by a first factor or a second factor, said first factor being related to the frequency spacing between channels in at least one ofsaid bands;

decade counter means for counting periods of the output signal of said variable modulus frequency divider;

channel number comparator means for generating a channel match signal when the number of periods counted by said decade counter means equals said first number, said decade counter means being reset in response to said channel match signal;

first factor stop comparator means for generating a first factor stop signal when the number of periods counted by said decade counter means equals a third number, said third number being also related to the band in which the selected channelresides but less than said second number, said variable modulus divider means being caused to divide by said second factor in response to said first factor stop signal; and

added count comparator means for generating an added count match signal when the number of periods counted by said decade counter means equals said second number, said decade counter means being reset in response to said added count match signal,said variable modulus divider means being caused to divide by said first factor in response to said added count match signal.

7. The apparatus recited in claim 6 wherein said nominal number of counts equals said second number.

8. The apparatus recited in claim 7 wherein said means for generating said offset signal includes means for resetting at least said decade counter means and for causing said variable modulus divider to divide by said first factor in response tothe initiation of said count signal.

9. The apparatus recited in claim 7 wherein said means for generating said offset signal includes:

memory means for generating an output signal when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;

means for resetting said memory means prior to the occurrence of said first factor stop signal during the duration of said count signal when said control signal is decoupled from said local oscillator;

means for inhibiting the generation of said added count signal when said control signal is decoupled from said local oscillator;

means for setting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is less than said second number by a first predetermineddeviation; and

means for resetting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is greater than said second number by a secondpredetermined deviation.

10. The apparatus recited in claim 9 wherein said means for generating said offset signal includes means for repetitively generating said offset signal.

11. The apparatus recited in claim 1 wherein said means for disabling said counter means includes input switching means for selectively decoupling said local oscillator signal from said counter means when said control signal is decoupled fromsaid local oscillator means except in response to said count signal; and

said counter means includes means for generating an illegal signal when an illegal channel has been selected;

said input switching means also decoupling said local oscillator signal from said counter means in response to said illegal signal.

12. The apparatus recited in claim 11 wherein:

said means for generating said illegal signal includes band selection means for generating a band traversed signal whenever the count accumulated by said counter corresponds to the boundary of a band and means for generating a band signalrepresenting the band in which the selected channel resides in accordance with which of said band traversed signals have been generated during said first portion of said frequency divided signal, said means for generating a band signal generating saidillegal signal when a band signal is not generated.

13. The apparatus recited in claim 11 wherein said means for generating said reference frequency also includes means for deriving a signal having a predetermined frequency; and said input means includes means for coupling said signal having apredetermined frequency to said counter means in response to said illegal signal.
Description: The present invention pertains to television tuning systems including a phase locked loop frequency synthesizerand particularly pertains to frequency counters which may be utilized in such systems.

In concurrently filed U.S. patent application Ser. No. 70,849, and now U.S. Pat. No. 4,031,549 by Henderson et al., assigned to the same assignee as the present invention, there is described a tuning device system for a television receiverwhich includes a phase locked loop for tuning a local oscilator to the nominal local oscillator frequencies required to tune the receiver to RF carriers at standard broadcast frequencies allocated to the various channels a viewer may select. The tuningsystem also includes an automatic fine tuning (AFT) frequency discriminator for tuning the local oscillator to minimize any deviation between the frequency of an actual picture carrier and the nominal picture carrier frequency. If the receiver iscoupled to a television distribution system which provides RF carriers having nonstandard frequencies arbitrarily near respective ones of the standard broadcast frequencies, when the phase locked loop has achieved lock at a nominal frequency, a modecontrol unit selectively couples the discriminator and a frequency drift control circuit to the local oscillator. If the frequency of the local oscillator drifts more than a predetermined offset from the frequency synthesized under phase locked loopcontrol because no carrier has been detected by the discriminator, discriminator and drift control are terminated so that the receiver will not be tuned to an undesired carrier such as, for example, the lower adjacent channel sound carrier, and phaselocked loop control is reinitiated to synthesize a local oscillator signal having a frequency incremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. After the phase locked loop is locked at anincremented frequency, discriminator control is again initiated. If, during this cycle of discriminator control, the local oscillator again drifts more than the predetermined offset from the incremented local oscillator frequency because no carrier isdetected by the discriminator, phase locked loop control is again reinitiated to synthesize a local oscillator signal having a frequency decremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. Ifduring any discriminator control cycle the local oscillator has not drifted further than the predetermined offset because the discriminator has tuned the local oscillator to a carrier within the predetermined offset, phase locked loop control is notreinitiated and the tuning sequence is complete.

In order to reduce the complexity, and therefore the cost, of an implementation of such a tuning system, it is desirable that individual potions of the system be capable of performing more than one function. For example, in copending UnitedStates Patent Application Ser. No. 663,097 filed for R. M. Rast on Feb. 27, 1976, and now U.S. Pat. No. 4,009,439 and assigned to the same assignee as the present invention, which is hereby incorporated by reference, there is described a frequencydivider for a television tuning phase locked loop tuning system. For each channel a viewer selects, the divider divides the frequency of the local oscillator signal by a number proportional to the nominal local oscillator frequency by forming a signalincluding first and second portions having durations respectively equal to first and second numbers of periods of the local oscillator signal. The first number is related to the selected channel number. The second number is related to the frequencyband in which the selected channel resides. To generate signals including in which band the selected channel resides for use in the phase locked loop itself and in the local oscillator to control its frequency range, a band selection unit is included asan integral part of the divider.

In accordance with the present invention, a programmable counter which may be used, for example, in a phase locked loop portion of a tuning system of the type decribed in the concurrently filed Henderson et al. application referenced above todivide the frequency of the local oscillator by a number proportional to the nominal local oscillator frequency for a selected channel is arranged so that it may also serve to generate a signal indicating whether or not the frequency of the localoscillator has drifted beyond a predetermined frequency offset after phase locked loop control of the local oscillator has been terminated. When the local oscillator is under phase locked loop control, the programmable counter accumulates a nominalnumber of counts during a predetermined portion of its output signal. Means are provided for generating a count signal after phase locked loop control of the local oscillator has been terminated. The count signal has a duration with a predeterminedtime relationship to a reference signal to which the local oscillator signal is locked when the local oscillator is under phase locked loop control. The counter is disabled from counting when the local oscillator is not under phase locked loop controlexcept during the duration of the count signal. Offset detection means, in response to the count signal, generates an offset signal representing the deviation between the count accumulated during a time interval corresponding to the predeterminedportion after phase locked loop control of the local oscillator has been terminated to determine how far the frequency of the local oscillator has drifted from the frequency synthesized under phase locked loop control.



C)- A tuning system for a television receiver includes a phase locked loop (PLL) configuration and an automatic fine tuning (AFT) configuration which are selectively enabled to operate to tune the receiver to nonstandard as well as standard frequency RF carriers which may be provided by cable and master antenna systems. After the selection of a new channel, the operations of the PLL and AFT configurations are sequentially enabled by a mode control apparatus. During the operation of the AFT configuration, an offset detector determines when the frequency of the local oscillator signal is caused to be more than a predetermined offset from its value established during the previous operation of the PLL configuration. In response, the mode control unit reestablishes the operation of the PLL configuration. Channel selection apparatus causes a new channel to be selected after a predetermined number of alternate operating cycles of the two configurations.

1. Apparatus for selectively tuning a receiver to any one of a plurality of RF carriers associated with respective channels, comprising:
local oscillator means for generating a local oscillator signal;
mixer means for combining a selected one of said RF carriers with said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value;
phase locked loop (PLL) means for selectively controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal;
programmable fac
tor control means for determining programmable factor in accordance with the channel selected and for generating a CHANGE signal when a new channel is selected;
lock means for generating a LOCK signal when said local oscillator signal has a frequency substantially equal to said programmed frequency;
automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value;
offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means;
mode control means for enabling the operation of said PLL means in response to said CHANGE signal, for enabling the operation of said AFT means in response to said LOCK signal and for again enabling the operation of said PLL means in response to said OFFSET signal; and
channel selection means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated a predetermined number of times.
2. The apparatus recited in claim 1 wherein:
said predetermined number of times is equal to one.
3. The apparatus recited in claim 1 wherein:
said programmable factor control means is coupled to counter means for counting the number of times said OFFSET signal is generated to change said programmable factor by an increment less than the difference between programmable factors associated with respective adjacent channels when said OFFSET signal is generated a second predetermined number of times less than said first mentioned predetermined number of times; and
said channel selection means is also coupled to said counter means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated said first mentioned predetermined number of times.
4. The apparatus recited in claim 3 wherein:
said programmable factor control means increases said programmable factor by said increment in response to a first generation of said OFFSET signal and decreases said programmable factor by said increment in response to a second generation of said OFFSET signal and changes said programmable factor to the value associated with the next channel in response to a third generation of said OFFSET signal.
5. The apparatus recited in claim 4 wherein:
said programmable factor control means includes inhibiting means for inhibiting said programmable factor control means from changing said programmable factor to the value in response to said OFFSET signal after a predetermined time longer than the time required to tune said receiver to a selected channel.
Description:
BACKGROUND OF THE PRESENT INVENTION
The present invention relates to search type tuning systems.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past those channels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning system for a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control) detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuning systems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.
Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptable reception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
SUMMARY OF THE PRESENT INVENTION
The present invention is an improvement to the type of electronic tuning system which includes first tuning means for tuning a tuner to standard frequencies associated with respective channels, second tuning means for tuning the tuner to reduce deviations between the frequency of an IF carrier generated by the tuner and its desired or nominal value that may arise due to, e.g., offsets in the frequencies of received RF carriers, and mode switching means for selectively applying the first and second tuning control signals to the tuner. In this type of electronic tuning system, the operation of the first tuning means is enabled after a new channel is selected and the operation of the second tuning means is enabled after the first tuning means has completed its operation. During the operation of the second tuning means, an offset detector determines when the frequency of a local oscillator signal generated by the tuner becomes offset from value established during the operation of the first tuning means and causes the operation of the first tuning means to again be enabled.
In accordance with the present invention, search means are provided in the above described type of electronic tuning system for causing a new channel to be selected if no RF carrier is tuned by the end of a predetermined number of operating cycles of the second tuning means.



PHILIPS 26CP2402/08R CHASSIS K12Z Programmable timer television receiver controllers:

Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, AM or PM, the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment, an external controller is disclosed which can be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.


1. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address for application to said memory means means for generating said write-addresses;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and
control means for controlling the reception of a television receiver according to said data read from said memory means.
2. The controller of claim 1 wherein said memory means is a semiconductor memory. 3. The controller of claim 1 wherein said storing means includes a means for generating said write-addresses which is responsive to the position of at least one first switch and a means for generating said data corresponding to channel selections which is responsive to the position of at least one second switch. 4. The controller of claim 1 wherein said controller means controls the reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 5. A programmable television controller comprising: random-access memory means for storing data;
data means for selectively generating data corresponding to a television channel;
write-address means selectively generating a write-address corresponding to a future time for application to said memory means;
program means for selectively storing said data in said memory means at said write-address;
read-address means for generating said read-addresses responsive to real time;
memory read means for applying said read-addresses to said memory means for reading out said data stored in said memory means; and
control means for controlling the reception of a television receiver according to said data read from said memory means.
6. The controller of claim 5 wherein said memory means is a semiconductor memory. 7. The controller of claim 5 wherein said data means comprises at least one switch. 8. The controller of claim 5 wherein said write-address means comprises at least one switch. 9. The controller of claim 5 wherein said program means comprises:
means for normally coupling said read-address means to said memory;
means for normally placing said memory in a read mode;
switching means for momentarily decoupling the read-address means from said memory means, coupling said write-address means to said memory means, and switching said memory means from said read mode to a write mode.
10. The controller of claim 5 wherein said read-addresses are binary coded signals which increment on one-half hour intervals. 11. The controller of claim 5 wherein said control means controls said reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 12. The controller of claim 5 wherein said control means controls the reception of said television receiver by limiting the reception to a channel other than the channel corresponding to said data received from said memory means if said data is present. 13. The controller of claim 5 wherein said control means includes a pretuner means having at least one input for coupling to a television receiver antenna and a pretuner output for coupling to an input on a television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal. 14. The controller of claim 13 wherein said control means further includes a disable means for disabling said control means thereby preventing reception of any channel when a power source powering said controller is interrupted, said disable means continuing to disable said controller until said disable means is reset. 15. The controller of claim 13 wherein said controller is installed within a controller housing, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller. 16. The controller of claim 13 wherein said pretuner output is for coupling to an antenna input on the television receiver and the frequency of said fixed frequency signal corresponds to a predetermined television signal. 17. The controller of claim 13 wherein said pretuner output is for coupling to an input of an intermediate frequency amplifier stage in the television receiver and the frequency of said fixed frequency signal corresponds to the intermediate frequency amplifier stage frequency of operation. 18. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address means for generating said write-addresses for application to said memory means;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and,
control means for controlling the reception of a television receiver according to said data read from said memory means, said control means including a pretuner means having at least one input for coupling to a television receiver antenna and pretuner output for coupling to an input on the television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal;
a controller housing for housing said controller, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of automatic controllers, and more particularly, to programmable controllers for use with television receivers and like equipment.
2. Prior Art
Many systems have been proposed for the automatic control of television receivers, that is, automatic channel selection for particular times of the day based upon programming information entered into the controller at some previous time. Most of these systems, however, are in substantial part mechanical systems which are not particularly easy to program, thereby being relatively expensive to manufacture and difficult to use. Accordingly, such systems have not enjoyed significant commercial use on conventional receivers.
Simple programmable television receiver controllers would provide a number of advantages over conventional channel selectors, and even over remote controlled channel selectors for a number of reasons. There may be programs of particular merit or interest which a viewer does not want to miss. However, the viewer's attention may inadvertently be drawn to another channel at the time, thereby failing to change channels to the more desirable program at the appropriate time. Also at the present time, a number of programs and movies being shown on T.V. are directed toward an adult audience, which programs may be undesirable or outright unsuitable for viewing by children, a situation which may only be expected to increase in the future. In addition, more andmore homes have at least one television receiver controllable at least a substantial amount of the time by children, whereby with conventional channel selectors the "viewers discretion" cannot be exercised by a parent. Accordingly, aprogrammable controller could be programmed periodically, such as once a week, so that those programs of highest merit or viewer interest, will be automatically selected and/or predetermined unobjectionable programs will be selected at times when objectionable programming is being televised on other channels. As an alternative, of course, objectionable programming itself could be programmed for the purposes of locking out such programs from the viewer's selections, e.g., eliminating such programming from the channel selections accessible from the manual channel selector.
U.S. Pat. Nos. 3,215,798 and 3,388,308 disclose automatic television programming systems of the mechanical or electromechanical type, whereby a rotary device mechanically tied to a time clock is programmed to provide some physical movement indicative of the channel to be selected at that time. Devices of the same general type involving some form of motor driven switching unit are also disclosed in U.S. Pat. Nos. 2,755,424, 3,496438, and 3,569,839. In all of these patents the mechanical complexity of the system disclosed is believed to preclude the widespread adoption thereof on receivers intended for consumer use. Further, most of these systems are operative on a number of switching signals equal to the number of selections desired, though some coding to somewhat reduce the complexity of such systems is known, such as that in U.S. Pat. No. 3,496,438. Also, obviously timing mechanisms or the electromechanical type for various other applications are also known, that disclosed in U.S. Pat. No. 3,603,961 being but one example of such devices.
BRIEF SUMMARY OF THE INVENTION
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, A.M. or P.M., the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment an external controller is disclosed which may be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.



PHILIPS 26CP2402/08R CHASSIS K12Z AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION



1. In a color television apparatus, a circuit for varying color display characteristics in accordance with variations in ambient light comprising: 2. In a color picture display system having a display device comprising: 3. The display system of claim 2 with kinescope means having a first set of electrodes and a second set of electrodes, 4. The display system of claim 2 with said light sensing means being responsive to the intensity of the ambient light and said parameter varying in accordance with the intensity of ambient light. 5. The display system of claim 4 with said modifying means increasing the gain of said luminance amplifying means at a greater rate than the gain of said chroma amplifying means as said ambient light intensity is increased. 6. A color television apparatus comprising: 7. In a color television receiver: 8. The receiver of claim 7 with said modifying means comprising a light dependent resistor means, 9. The receiver of claim 8 with second impedance means coupling said light dependent resistor means to said luminance gain means to control the gain of said luminance gain means. 10. The receiver of claim 9 with said second impedance means comprising a parallel combination of capacitance and resistance. 11. The receiver of claim 7 with said modifying means varying the gain of the luminance gain means at a greater rate than the gain of the chroma gain means as ambient light is varied. 12. The receiver of claim 7 with said modifying means being responsive to the intensity of ambient light and said parameter being varied as the intensity of the ambient light is varied. 13. The receiver of claim 7 with said modifying means attenuating the gain of said luminance amplifying means approximately fifty percent more than the gain of said chroma amplifying means, when the attenuation is measured in decibels, as said ambient light intensity is decreased. 14. In a color television receiver:
Description:
BACKGROUND OF THE INVENTION

The present invention relates generally to a television receiver control system and more particularly to a control system for maintaining proper balance between room lighting conditions and the level of picture tube excitation in a color television receiver. More especially the present invention functions to increase contrast, intensity and chroma signal strength when the room lighting level increases to diminish these parameters when the level of room lighting decreases.

Conventional television receivers, of course, have manually operable controls by means of which a viewer may set the level of contrast, intensity, and chroma signal strength to what he feels to be an optimum level for given room lighting conditions. Under changed room lighting conditions, the viewer will obtain the optimum viewing situation by changing these manual controls to a new preferred level.

It is also known in the prior art to automate this process for a black and white television receiver, for example, as taught in the U.S. Pat. No. 3,165,582 to Korda, issued Jan. 12, 1965, and the French patent 1,223,058 issued in June of 1960.

It is accordingly an object of the present invention to provide an automatic color saturation control for a color television receiver by providing separate, predetermined gains for the luminance and chroma for a given change in ambient light. In the disclosed preferred embodiment, the luminance signal is attenuated 3.3 dB and the chroma signal is attenuated 2.1 dB for a change in ambient light from 100 footcandles to 0.1 footcandles, measured at the display face.

SUMMARY OF THE INVENTION

The foregoing as well as numerous other objects and advantages of the present invention are achieved by providing a light sensitive element in a television receiver exposed to ambient light in the vicinity of the receiver for separately controlling brightness, contrast and chroma signal strength of the displayed picture in accordance with the level of ambient light. The circuit of a preferred embodiment of the present invention, in response to an increase of ambient light level, functions to increase the gain of the luminance amplifier in a relatively greater ratio than the increase in the gain of the chrominance amplifier whereas when the ambient light level decreases the respective gains of these two amplifiers are decreased, again, with the change in the luminance signal being in a greater proportion than the change in the chroma signal strength signal. By using the teaching of this invention, other gain relationships between the luminance components and chroma signal, for a given change in ambient light, may be automatically attained to achieve a desired result of luminance and color saturation.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned and other objects, features and advantages of the present invention will become more apparent from the following detailed description thereof when considered in conjunction with the drawings wherein:

FIG. 1 is a partial block diagram of a color television receiver employing the present invention;

FIG. 2 is a detailed schematic diagram of those portions of FIG. 1 embodying the present invention;

FIG. 3 illustrates chroma gain control characteristic curves for the circuit of FIG. 2; and

FIG. 4 is a graph showing changes in luminance and chroma signal strength according to changes in ambient light.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Considering first FIG. 1 which illustrates generally in block diagram form a color television receiver embodying the present invention, this receiver is seen to comprise a tuner and radio frequency amplifier 11 for detecting and amplifying incoming signals received on the antenna 13 and supplying those signals through an appropriate heterodyning process to an intermediate frequency amplifier 15. After detection in the detector 17, the luminance signals are passed through a delay 19 which compensates for the delays experienced by the chroma signal strength signals and then to the luminance amplifier 21, which, of course, corresponds to the video amplifier of a black and white receiver, to then be supplied to the cathode ray tube 23. The luminance or video amplifier may also be provided with gain control circuitry 25. An appropriate band pass amplifier 27 may be employed to separate out the chroma signal strength signals which are demodulated by the demodulator 29 in well known fashion to provide the three color difference signals to grids in the color cathode ray tube 23. While the present invention will be described with respect to such color difference signals, it is equally applicable to direct RGB color separation systems. An ambient light level detector 31 such as a light dependent resistor of the cadmium sulphide variety is physically located on the front of the television receiver in such a position as to be exposed to the light levels in the vicinity of the receiver so that its resistance varies inversely in accordance with variations in the ambient light levels around the receiver. These resistance variations are then employed to control the gain of the luminance amplifier 21 by way of gain control 25 and to control the gain of the chroma signal strength amplifier circuitry.

The entire color demodulation process is only generally depicted in the block diagram of FIG. 1 and is illustrated as a closed loop burst gain controlled chroma amplifier system with auxiliary chroma gain control introduced by way of the detector 33 from the ambient light level detector 31. A burst gain controlled chroma amplifier circuit is somewhat analogous to a black and white keyed AGC circuit and functions to set the gain level of the amplifier 27 in accordance with the color sync burst rather than the chroma signal level associated with a particular picture. While the present invention is being described with respect to this preferred type of gain control, it would, of course, be possible, in television circuits employing DC gain controls for chroma and/or contrast, to connect the ambient light tracking means to these direct current control circuits. The gain controlled chroma band pass amplifier, of course, supplies an output to a burst amplifier 35 which in turn drives an automatic phase control system 37 for synchronizing the 3.58 megacycle oscillator 39 the output of which is used in the color demodulation process.

Considering now FIG. 2 which illustrates schematically in detail those portions of the receiver of FIG. 1 necessary for a complete understanding of the present invention, the light dependent resistor 41 is mounted near the front of the television receiver in such a position as to adequately receive the ambient lighting conditions in the vicinity of the receiver. The resistance of this device is inversely proportional to the intensity of light incident thereon. If the room ambient light experiences an increase in level, the resistance of light dependent resistor 41 will decrease which decrease in turn lowers the voltage at the base of transistor 43 which in turn lowers the voltage at the emitter due to increased conduction through that transistor. This in turn increases the gain of the chroma amplifier transistor stage 45. More precisely the lowering the voltage at the emitter of transistor 43 raises a threshold in the automatic chroma control detector 33 so that the chroma signal strength signal, and hence the color saturation level, to the picture tube is increased. In the absence of a chroma signal with its synchronizing burst, the gain of the chroma amplifier is set at a maximum by the voltage divider comprising resistors 47 and 49. At this time there is no output from the automatic chroma control detector to the base of transistor 51 and that transistor is non-conducting.

When a color signal is received, the detector provides an output signal proportional to the color sync burst level which turns on the transistor 51 to control the gain of the chroma amplifier stage 45 so as to maintain the desired output level. The turn on level of transistor 51 represents a fairly well defined knee in the chroma gain control characteristic curves illustrated in FIG. 3. Operation beyond the knee or threshold of such a curve operates to maintain a nearly constant chroma output level while operation below the knee of the curve and its extension as the almost vertical dotted line represents the open loop characteristic wherein there is no automatic gain control to the chroma amplifier. Since transistor 51 is non-conducting below the knee of this curve, gain control is delayed until the output signal reaches this threshold point. Since variations in the potential at the emitter of transistor 43 cause corresponding variations in the potential at the base of transistor 51, it is clear that a variation in the resistance of the light dependent resistor 41 will, for example, cause the gain control characteristic curve to shift from that depicted by curve A to that depicted by curve B and that for a given burst level input as represented by the vertical dotted line, two different levels of chroma output which, in turn, cause two different levels of color saturation will be achieved by a change in the light intensity incident on the resistor 41.

To better understand the operation of detector 33, assume that the burst voltage induced across the top half of the secondary of transformer 34 is in phase with the 3.58 megacycle reference signal and that the burst voltage induced across the bottom half of the secondary of transformer 34 is 180° out of phase with this reference signal. Assuming further that the diodes 36 and 38 have equal characteristics, that the resistors 40 and 42 are equal, that the capacitors 44 and 46 are equal, and that the two portions of the secondary winding on transformer 34 are equal when no burst is being received, diodes 36 and 38 will conduct equally but during opposite portions of a cycle. Diode 36 conducts during negative excursions of the reference signal whereas diode 38 conducts during positive portions of that reference wave form. Thus during the negative portions of the reference wave form diode 36 conducts to charge capacitor 44 so that its right hand plate is negative and its left hand plate is positive. During the positive excursions, diode 38 conducts to charge capacitor 46 with its right hand plate positive and its left hand plate negative. Under this assumed no burst input condition the net charge on these capacitors yields a voltage on line 48 which is zero. If noise is introduced into the system, it will be of equal amplitude but opposite phase across the two diodes and both diodes will be affected to an equal extent resulting in no change in the voltage on line 48. When during a color telecast a burst signal is present, we may assume that the burst voltage induced across the two portions of the secondary of transformer 34 are of equal amplitude to the 3.58 megacycle reference signal. With this situation the diode 36 will not conduct since the burst voltage is equal in phase and amplitude to the reference signal and its anode and cathode remain at the same potential. The diode 38
will, however, conduct readily since the burst and reference signals have an additive rather than a cancelling effect on it resulting in the diode 38 conducting twice as much as in the previous no burst example and resulting in the capacitor 46 charging to about twice its previous voltage which voltage is presented on line 48 as a control signal.

Suppose now that the burst signal amplitude is reduced to one half that of the foregoing example. With this new assumption the phase relationships remain as before but now diode 36 will conduct about one half its previous amount while diode 38 conducts about one and one half times its previous amount resulting in a voltage on line 48 which is about one half the previous voltage.

The voltage on line 48 which is approximately proportional to the burst voltage is applied to the base of transistor 51 which biases the base of the chroma amplifier transistor 45 thereby controlling the gain of that chroma amplifier stage.

A variation in threshold can be achieved by altering the conduction points of the diodes 36 and 38. This is accomplished by applying a bias voltage to the junction of these two diodes to alter their respective points of conduction thereby changing the output voltage on line 48. For example, if a positive 2-volt direct current bias is applied to the junction of the two diodes, under a no burst input condition, diode 38 will conduct sooner and turn off later than with no bias applied, while diode 36 will turn on later and off sooner than under the no bias condition. This results in a control voltage on line 48 under the no burst condition. In other words, a bias voltage applied to the junction of the two diodes acts as an additional bias on the chroma amplifier stage thereby affecting its gain.

The control of brightness (intensity) and contrast is achieved in the present invention by a second light dependent resistor 53 which is optically coupled to a light emitting diode 55. LIght emitting diode 55 and light dependent resistor 53 are encapsulated in a light impervious housing illustrated by the dotted line 57. As the room ambient light changes, the change in the resistance of light dependent resistor 41 causes a change in the current through light emitting diode 55. Variations in the current through the light emitting diode cause corresponding variations in the light emitted thereby which in turn cause variations in the resistance of the light dependent resistor 53. The luminance or video amplifier is here illustrated as a three transistor amplifier with the output of the first amplifier stage being across resistor 59. A diminution in the resistance of light dependent resistor 53 causes a lowering of this output impedance and thus a diminution in the gain of the luminance amplifier. In other words, if the light intensity in the room increases, the resistance of resistor 41 will decrease causing a decrease in the current through light emitting diode 55 and, therefore, a decrease in its light output level and this decreased light will cause an increase in the resistance of light dependent resistor 53 thus increasing the effective output load resistor for the transistor 61 thus increasing the gain of the video amplifier as desired.

Variable resistor 63 being effectively in series with the light dependent resistor 41 may be varied to compensate for differences in specific light dependent resistors so as to establish a desired level of picture brightness, contrast and color saturation for a given level of ambient light. Variable resistance 65 which is in parallel with the light dependent resistor 41 may be varied so as to effectively change the range of variation in brightness, contrast and color saturation for a specific range of variations in the ambient light conditions. The entire automatic control circuit of the present invention may be bypassed by closing the defeat switch 67.

Looking now at FIGS. 2 and 4, the relative attenuation of the chroma channel and luminance channel will become apparent. Looking first at FIG. 4, the abscissa is the measure of ambient illumination in foot candles on a log scale, and the ordinate is the measure of attenuation of signal amplitude in dB. At 100 footcandles there is 0 dB attenuation of luminance and chroma signals and as the ambient illumination decreases to 0.1 foot candles, it is seen that the chroma signal line 72 is down 2.1 dB while the luminance signal line 72 is down 3.3 dB. This ratio has been found to be a highly satisfactory ratio giving a very pleasing picture at all ambient light levels between 0.1 footcandles and 100 footcandles of ambient light.

The manner in which this variation in luminance attenuation is achieved may be seen by looking at FIG. 2. As mentioned, the chroma channel signal is varied by the conduction level of transistor 43. As light dependent resistor 41 changes in resistance, the conduction level of transistor 43 will also change with the degree of change being determined by divider resistances 75 and 76. Further the luminance channel gain is determined by resistor 77 since it is this resistor which will control the signal level of light emitting diode 55 which in turn will control the gain to luminance transistor 61. It is these resistors which determine the relative amount of attenuation of gain in the chroma and luminance channels as the ambient light is changed. In this embodiment, resistance 75 is 5.6 k ohms, resistance 76 is 4.3 k ohms, resistance 77 is 3.9 k ohms, resistance 78 is 7.5 k ohms, the voltage applied to the upper terminal of resistance 78 is 35 volts, resistance 63 is 500 ohms, resistance 65 is 25 k ohms, resistance 69 is 4.7 k ohms, capacitance 71 is 47 microfarads, resistance 59 is 1 k ohm, resistance 59a is 6.8 k ohms, resistance 62a is 1 k ohms, resistance 64a is 100 ohms, resistance 64b is 6.8 k ohms. Light dependent resistor 41 is a Clariex CL-11360, photocoupler unit 57 is Magnavox Part Number 701482. Transistors 43, 61, 62, and 64 are 2N3962, 2N4916, MPSA20 and 25C685A, respectively. This invention has been incorporated in a Magnavox Company T979 color television chassis.

The effective load resistance for the transistor 61 under direct current conditions is the parallel combination of the resistor 59 and the series pair of resistors 53 and 69 whereas due to the presence of capacitor 71 this effective load resistance under alternating current conditions is the parallel combination of resistors 59 and 53. Thus the ratio of AC to DC gain for this video amplifier stage may be selected by proper selection of these parameters so as to maintain the black level of the picture essentially constant.

Thus while the present invention has been described with respect to a specific embodiment, numerous modifications will suggest themselves to those of ordinary skill in the art. Since the luminance and chroma gains are individually controlled for a given change in ambient light, the gain ratios between the luminance and chroma channels may be selected as desired to achieve a desired effect for a given change in ambient light. Also, while the present invention has been described in the environment of a television receiver, the invention could equally well be used in television monitors as well as many other types of display devices. Accordingly the scope of the present invention is to be measured only by that of the appended claims.



PHILIPS 26CP2402/08R CHASSIS K12Z AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION Gain control arrangement useful in a television signal processing system
In a color television receiver, first and second amplifiers are respectively included in the luminance and chrominance channels to permit control of contrast and saturation. The amplifiers have gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. A first potentiometer is coupled between a source of fixed voltage equal to the extrapolated cut off voltage of the first amplifier and a gain controlling voltage source. The gain controlling voltage may be produced by a circuit including an element responsive to ambient light. The wiper of the first potentiometer is coupled to the first amplifier to couple a voltage developed at a predetermined point of the first potentiometer to the first amplifier to control its gain. A second potentiometer is coupled between a source of voltage equal to the extrapolated cut off voltage of the second amplifier and the gain controlling voltage source to receive a portion of the gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the first and second amplifiers. The wiper of the second potentiometer is coupled to the second amplifier to couple a voltage developed at a predetermined point of the second potentiometer to the second amplifier to control its gain. In this manner, the contrast of the receiver may be varied over a relatively wide range while saturation is maintained substantially constant.


1. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut-off at predetermined voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer means coupled between a fixed voltage substantially equal to the extrapolated cut-off voltage of said second amplifier and to said gain controlling voltage source to recieve a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut-off voltages of said first and second amplifiers; and
means for coupling a voltage developed at a predetermined point on said potentiometer means to said second amplifier to control its gain.
2. The apparatus recited in claim 1 wherein said means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut-off voltage of said first amplifier and said gain controlling voltage source. 3. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain control voltage characteristics including linear portions extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first variable gain amplifying means for amplifying a first signal in response to a first DC control signal, said first amplifying means having a first gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to VO ;
second variable gain amplifying means for amplifying a second signal in response to a second DC control signal, said second amplifying means having a second gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to AVO, where A is a number greater than 0;
a first source of fixed voltage substantially equal to VO ;
a second source of fixed voltage substantially equal to AVO ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first means for deriving said first control voltage including means for providing the difference between said third control voltage v and said fixed voltage VO and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage VO to said DC control voltage v; and
second means for deriving said second control voltage including means for providing the difference between a portion Av of said third control voltage v and said fixed voltage AVO and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AVO to said DC control voltage v.
5. The apparatus recited in claim 4 wherein A is equal to 1. 6. The apparatus recited in claim 4 wherein said first amplifying means is included in a luminance channel of a televeision signal processing system and said second amplifying means is included in a chrominance channel of said television signal processing system. 7. The apparatus recited in claim 6 wherein means for developing said third control voltage includes means responsive to ambient light. 8. The apparatus recited in claim 4 wherein said first means includes first voltage divider means coupled between said fixed voltage VO and said third DC control voltage v; and wherein said second means includes second voltage divider means coupled between said fixed voltage AVO and said portion Av. 9. The apparatus recited in claim 8 wherein said first voltage divider means includes a first potentiometer, said first potentiometer having a wiper coupled to said first amplifying means; and wherein said second voltage divider means includes a second potentiometer, said second potentiometer having a wiper coupled to said amplifying means. 10. The apparatus recited in claim 4 wherein said second gain versus DC control voltage characteristic includes a region between said voltage AVO and a voltage VB where the gain is greater than 0, said voltage VB being substantially equal to the voltage at which said second amplifying means has a gain substantially equal to 0; and wherein said second source of fixed voltage includes means for coupling said voltage VB to said second amplifying means. 11. The apparatus recited in claim 10 wherein said second source of said voltage AVO includes a third source of fixed voltage VB ; potentiometer means coupled between said third source of fixed voltage VB and said means for developing said third DC control voltage; and means coupled to said potentiometer means for developing said voltage AVO at a point along said potentiometer means; said potentiometer means including a wiper coupled to said second amplifier means, said wiper being adjustable to couple a DC voltage VFB and said third control voltage to said second amplifying means.
Description:
The present invention pertains to gain controlling apparatus and particularly to apparatus for controlling the gains of amplifiers included in the luminance and chrominance channels of a television signal processing system.
Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be reproduced under conditions of high ambient light as well as under conditions of low ambient light. Apparatus is known for automatically controlling the contrast and brightness properties of a television receiver in response to ambient light to provide a pleasing image over a range of ambient light conditions. Such apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit Arrangements For Automatically Adjusting The Brightness And The Contrast In A Television Receiver," issued to H. Heijligers on Mar. 27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic Readjustment Of The Background Brightness And The Contrast In A Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with the present invention, apparatus is provided which may be utilized in a color television receiver to control contrast over a relatively wide range while maintaining constant saturation. The apparatus includes first and second amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. Means couple a gain controlling voltage source to the first amplifier to control its gain. Potentiometer means are coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of the second amplifier and the source of gain controlling voltage to receive a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the amplifiers. A voltage developed at a predetermined point along the potentiometer means is coupled to the second amplifier to control its gain.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now to FIG. 1, the general arrangement of a color television receiver employing the present invention includes a video signal processing unit 112 responsive to radio frequency (RF) television signals for generating, by means of suitable intermediate frequency (IF) circuits (not shown) and detection circuits (not shown), a composite video signal comprising chrominance, luminance, sound and synchronizing signals. The output of signal processing unit 112 is coupled to chrominance channel 114, luminance channel 116, a channel 118 for processing the synchronizing signals and a channel (not shown) for processing sound signals.
Chrominance processing channel 114 includes chrominance processing unit 120 which serves to remove chrominance signals from the composite video signal and otherwise process chrominance signals. Chrominance signal processing unit 120 may include, for example, automatic color control (ACC) circuits for adjusting the amplitude of the chrominance channels in response to amplitude variations of a reference signals, such as a color burst signal, included in the commposite video signal. Chrominance signal processing circuits of the type described in the U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control System," issued to L.A. Harwood, on June 19, 1973 and assigned to the same assignee as the present invention are suitable for use as chrominance processing unit 120.
The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
Channel 118 includes a sync separator 134 which separates horizontal and vertical synchronizing pulses from the composite video signal. The synchronizing pulses are coupled to horizontal deflection circuit 136 and vertical deflection circuit 138. Horizontal deflection circuit 136 and vertical deflection circuit 138 are coupled to kinescope 128 and to a high voltage unit 140 to control the generation and deflection of one or more electron beams generated by kinescope 128 in the conventional manner. Deflection circuits 136 and 138 also generate horizontal and vertical blanking signals which are coupled to luminance signal processing unit 132 to inhibit its operation during the horizontal and vertical retrace intervals.
Gain control unit 142 is coupled to luminance amplifier 130 and to chrominance amplifier 122 to control their gains. Gain control unit 142 includes a PNP transistor 152 arranged as an emitter-follower amplifier. The collector of transistor 152 is coupled to ground while its emitter is coupled through a series connection of a potentiometer 156 and fixed resistor 154 to a source of positive supply voltage VO. The wiper of potentiometer 156 is coupled to luminance amplifier 130. The series connection of a potentiometer 158 and a variable resistor 159 is coupled between the source of positive supply voltage VO and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
In operation, gain control circuit 142 maintains the ratio of the gain of chrominance amplifier 122 to the gain of amplifier 130 constant in order to maintain constant saturation while providing for contrast adjustment either manually by means of potentiometer 146 or automatically by means of LDR 148. If the gain of luminance were adjusted to control the contrast of an image without a corresponding change in the gain of chrominance amplifier 122, the amplitudes of luminance signals -Y and color difference signals R-Y, B-Y and G-Y would not, in general, be in the correct ratio when combined by divider 126 to provide the desired color.
When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
Referring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO.
From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With reference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122.
In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
Referring to FIG. 3 there are shown gain versus DC control voltage characteristics of chrominance and luminance amplifiers which do not have the same extrapolated linear cut off control voltage. The gain versus control voltage characteristic gL ' of the luminance amplifier has a reverse S-shape characteristic including a linear portion 312. Extrapolated linear portion 312 of gL ' intersects the GAIN axis at a gain GL ' and intersects the CONTROL VOLTAGE axis at a voltage VO '. The gain versus control voltage characteristic gC ' of the chrominance amplifier has a reverse S-shape characteristic having a linear portion 314. Extrapolated linear portion 314 of gC ' intersects the GAIN axis at a gain GC ' and intersects the CONTROL VOLTAGE axis at a voltage AVO ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of gL ' is ##EQU6## where vL ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of gC ' is ##EQU7## where vC ' is the DC control voltage coupled to the chrominance amplifier.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]
where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitter-follower, via terminal 512. The collector of transistor 514 is coupled to bias supply 546. The emitter of transistor 514 is coupled to ground through the series connection of resistor 516, a diode connected transistor 518 and resistor 520.
The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, there is shown an amplifier suitable for use as chroma amplifier 120 of FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S. patent application Ser. No. 530,405 entitled "Controllable Gain Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.
The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a se
ries resistor 652. A signal by-pass circuit comprising a series resonant combination 654 of inductance and capacitance is coupled from the anode of diode 634 to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz to provide a low impedance path to ground for color subcarrier signals.
Bias voltages and currents are supplied to the amplifier arrangement by bias supply 610, illustrated as a series connection of batterys. A voltage B+ is coupled to the collector of transistor 646. A lower bias voltage is coupled to the load circuits of transistors 632 and 633. The bases of transistors 632 and 633 are coupled in common to a still lower bias voltage. The bases of transistors 624 and 625 are coupled to a still lower bias voltage via substantially equal in value resistors 658 and 659. A resistor 694 is coupled from the common junction of resistors 658 and 659 to ground.
In operation, a quiescent operating current is provided through resistor 630. In the absence of an input signal at terminal 603, this current will divide substantially equally between the similarly biased transistors 624 and 625. If the DC control voltage at terminal 602 is near ground potential, transistor 646 will be effectively cut off and no current will flow in resistor 652 and diodes 634 and 635. In that case, neglecting the normally small difference betweeen collector and emitter currents of NPN transistors, the collector currents of transistors 624 and 625 will flow, respectively, in transistors 632 and 633. The transistors 632 and 633 are operated in common base mode and form cascode signal amplifiers with respective transistors 624 and 625. With the DC control voltage near ground potential, one-half of the quiescent current from resistor 630 flows in each of the load circuits and maximum gain for chrominance signals supplied from terminal 603 is provided.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It is noted that although the characteristics shown in FIGS. 2 and 3 were reversed S-shaped characteristics, the characteristics could have other shapes including linear portions. For example, the characteristics could be substantially linear. Furthermore, with reference to FIG. 3, although gC ' was shown as having a linear portion that had a cut off control voltage lower than the cut off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL '. In addition, the gain control units and associate amplifiers could be arranged to utilize voltages opposite in polarity to those shown. These and other modifications are intended to be within the scope of the invention.











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“Advanced Voltage Mode Pulse Width Modulator,” UNITRODE Corp., UCC15701/2, UCC25701/2, UCC35701/2, Jan. 2000, pp. 1-10.
“Advance Information: High Voltage Switching Regulator,” MC33362, MOTOROLA Inc., Motorola Analog IC Device Data, Rev 2, 1996, pp. 1-12.


 


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