PANASONIC TX-28LD1C CHASSIS EURO 2-S VIEW

This is one of the PANASONIC DIGITAL CHASSIS versions Implementing DIGITAL SIGNAL PROCESSING and basing it on the ITT DIGIVISION DIGIT3000 family chipset.

It's a successor of EURO 2 L and a full successor of the PANASONIC EURO 1 DIGITAL CHASSIS which can be seen HERE 


It's developed on a Single PCB with one Vertical unit which is a Input selector for A/V and contains the MSP3400 Digital Sound Processor.













Power Supply is Based on the well known TDA4601

TDA4601 Operation.

* The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600
device, the TDA4601 however has improved switching, better protection and cooler running.

The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type,
which operates on the same basic principle as a line output stage. It is turned on and off by a
square wave drive pulse, when switched on energy is stored in the chopper transformer
primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic
flux collapses, causing a large back emf to be produced. At the secondary side of the chopper
transformer this is rectified and smoothed for H.T. supply purposes.
The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz
according to load) allows the use of relatively small H.T. smoothing capacitors making
smoothing easier. Also should the chopper device go short circuit there is no H.T. output.


In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage
is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5
requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby
switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v
and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing
circuit.

PIN DESCRIPTIONS
Pin 1 This is a 4v reference produced within the I.C.
Pin 2 This pin detects the exact point at which energy stored in the chopper transformer
collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the
chopper transistor. It also opens the switch at pin 4 allowing the external capacitor
C813 to charge from its external feed resistor R810.
Pin 3 H.T. control/feedback via photo coupler D830.
The voltage at this pin controls the on time of the chopper transistor and hence the
output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a
proportion of the +4v reference at pin 1, offset by conduction of the photo coupler
D830 which acts like a variable resistor. An increase in the conduction of transistor
D830 and therefor a reduction of its resistance will cause a corresponding reduction
of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter
on time for the chopper transistor and therefor a lowering of the output voltage and
vice versa, oscillation frequency also varies according to load, the higher the load the
lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip
flop is triggered causing the chopper drive mark space ratio to extend to 244 (off
time) to 1 (on time), the chip is now in over volts trip condition.
Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is
produced by a time constant network R810 and C813. C813 charges when the
chopper is on and is discharged when the chopper is off, by an internal switch
strapping pin 4 to the internal +2v reference, see Fig 2.
The amplitude of the ramp is proportional to chopper drive. In an overload
condition it reaches 4v amplitude at which point chopper drive is reduced to a
mark-space ratio of 13 to 1, the chip is then in over current trip.

The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the
power supply simply squegs quietly. Pin 4 is protected by internal protection
components which limit the maximum voltage at this pin to 6.5v.
Should a fault occur in either of the time constant components, then the chopper
transistor will probably be destroyed.
Pin 5 This pin can be used for remote control on/off switching of the power supply, it is
normally held at about +7v and will cause the chip to enter standby mode if it falls
below 2v.
Pin 6 Ground.
Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to
switch off the chopper.
Pin 8 Chopper base current output drive pin.
Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running,
Current consumption of the I.C. is typically 135mA. The voltage at this pin must
reach 6.7v in order for the chip to start-up.

Frame Deflection Output with TDA8175

Audio Out with LA4290

MAIN CPU CCU3000




Single-Chip Video Processor VDP 3108





1. Introduction
The entire video processing and controlling for a color
TV has been developed on a single chip in 0.8m CMOS
technology. Modular design and submicron technology
allow the economic integration of features in all classes
of TV sets.
Open architecture is the key word to the new DSP generation.
Flexible standard building blocks have been defined
that offer continuity and transparency of the entire
system.


























Single-Chip Video Processor
1. Introduction
The entire video processing and controlling for a color
TV has been developed on a single chip in 0.8m CMOS
technology. Modular design and submicron technology
allow the economic integration of features in all classes
of TV sets.
Open architecture is the key word to the new DSP generation.
Flexible standard building blocks have been defined
that offer continuity and transparency of the entire
system.
One IC contains the entire video and deflection processing
and builds the heart of a modern color TV. Its performance
and complexity allow the user to standardize
his product development. Hardware and software applications
can profit from the modularity as well as manufacturing,
system support or maintenance. The main
features are:
– low cost, high performance
– all digital video processing
– multi-standard color decoder PAL/NTSC/SECAM
– 3 composite, 1 S–VHS input
– integrated high-quality AD/DA converters
– sync and deflection processing
– luminance and chrominance features, e.g.
peaking, color transient improvement
– programmable RGB matrix
– various digital interfaces
– embedded RISC controller (80 MIPS)
– one crystal, few external components
– single power supply 5 V
– 0.8m CMOS Technology
– 68-pin PLCC or 64-pin Shrink DIL Package
1.1. System Architecture
Two main modules have been defined:
Video Processor and
Display Processor.
They are designed as silicon building blocks. Their partitioning
permits a variety of IC configurations with the aim
to satisfy the particular requirements of different applications.
Both, analog and digital interfaces, support
state of the art TV receivers as well as other environments.
Fig. 1–1 shows the block diagram of the singlechip
Video Processor which consists of both modules.


2. Functional Description


2.1. Analog Front End
This block provides the analog interfaces to all video inputs
and mainly carries out analog-to digital conversion
for the following digital video processing. A block diagram
is given in figure 2–1.
Most of the functional blocks in the front end are digitally
controlled (clamping, AGC and clock-DCO). The control
loops are closed by the Fast Processor (‘FP’) embedded
in the decoder.



2.1.1. Input Selector
Up to four analog inputs can be connected. Three inputs
are for input of composite video or S–VHS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S–VHS carrier–chrominance signal.
This input is internally biased and has a fixed gain amplifier.


2.1.2. Clamping
The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling capacitors
and is generated by digitally controlled current
sources. The clamping level is the back porch of the video
signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.


2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in 64
logarithmic steps to the optimal range of the ADC .
The gain of the video input stage including the ADC is
213 steps/V for all three standards (PAL/NTSC/SECAM/
Y/C), with the AGC set to 0 dB.



2.1.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit resolution.
An integrated bandgap circuit generates the required
reference voltages for the converters.
The two ADCs are of a 2-stage subranging type.

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