SAMBERS (HANTAREX) SOUND 22 CHASSIS CTV200 110° INTERNAL VIEW.

Teletext Unit
SAA5020 (PHILIPS)
SAA5053 (PHILIPS)
SAA5042 (PHILIPS)
SAA5030 (PHILIPS)

Luminance+ Chrominance TDA3562A (PHILIPS)
PAL/NTSC ONE-CHIP DECODER
DESCRIPTION


The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.


.CHROMINANCE SIGNALPROCESSOR

.LUMINANCE SIGNAL PROCESSING WITH
CLAMPING

.HORIZONTAL AND VERTICAL BLANKING
.LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS
.LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS
.AUTOMATIC CUT-OFF CONTROL
.NTSC HUE CONTROL

TDA2579 (synchronization) (PHILIPS).GENERAL DESCRIPTION

The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth.


FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
Standard TV-norm
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 <>
In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height
is achieved.
Video tape recorders in feature mode
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.

The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated
via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at
count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by
adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of
the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage
a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).
The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value
of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends.
The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is
discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and
ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current
source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a
typical voltage of » 7.5 volts. The recommended operating current range is 10 to 75 mA. The resistance at pin R4 should
be 100 to 770 kW. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired
value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current
measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback
voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and
AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.
The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a
fully DC coupled feedback circuit is possible.
Vertical guard
The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level
on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output
signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard
levels specified refer to the zener diode reference voltage source level.
Driver output
The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately
170 W. The output pin is also connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins 5,6,7,8 and 18)
The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of
the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level value
is stored in the capacitor at pin 6. The slicing level value can be chosen by the value of the external resistor between
pins 6 and 7.


Black level detector
A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with
a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC
conditions at input pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and
ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced
and separation of the vertical sync pulse is improved.
Noise level detector
An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a
built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at
the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated.
A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below
19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated
by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the
“acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant.
When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync
pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.






IF DEM + AMPL with TDA3541

DESCRIPTION
The TDA3541;Q are integrated IF
amplifier and demodulator circuits for colour or black/white
television receivers, the TDA8340;Q is for application with
n-p-n tuners and the TDA8341;Q for p-n-p tuners.

The TDA8340;Q and TDA8341;Q are pin-compatible
successors with improved performance to types
TDA2540/2541;Q and TDA3540/3541;Q.
Features
· Full range gain-controlled wide-band IF amplifier
· Linear synchronous demodulator with excellent
intermodulation performance
· White spot inverter
· Wide-band video amplifier with noise protection
· AFC circuit with AFC on/off switching and
sample-and-hold function
· Low impedance AFC output
· AGC circuit with noise gating
· Tuner AGC output for n-p-n tuners (TDA8340) or p-n-p
tuners (TDA8341)
· External video switch for switching-off the video output
· Reduced sensitivity for high sound carriers
· Integrated filter to limit second harmonic IF signals
· Wide supply voltage range
· Requires few external components


------------------------------

Television receiver including a teletext decoder circuit :

In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.

1. A receiver for television signal s including a teletext decoder circuit for decoding teletext signals constituted by character codes which are transmitted in the television signal, and comprising:
a video input circuit receiving the television signal and converting it into a serial data flow;
an acquisition circuit for receiving the serial data flow supplied by the video input circuit and selecting that part therefrom which corresponds to the teletext page described by the viewer;
a character generator comprising:
a memory medium addressed by the character codes which together represent the teletext page desired by the user and which in response to each character code successively supply m₂ series of m₁ simultaneously occurring character picture element codes each indicating wether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m₁ simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m₁ character picture element codes of a series one after the other and at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed;
characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m₁ clock pulse to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m₁ character picture element codes.
2. A character generator for use in a receiver teletext claim 1, comprising:
a memory medium which is addressable by character codes and successively applies m₂ series of m₁ simultaneously occurring character picture element codes in response to a character code applied as an address thereto, each character picture element code indicating whether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m₁ simultaneously occurring character picture element codes and the display clock pulses for supplying the m₁ character picture element codes of the series one after the other at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed; characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m₁ clock pulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m₁ character picture element codes.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.
2. Description of the Prior Art
As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.
Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.
A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.
For the purpose of display each character is considered as a matrix of m ₁ ×m ₂ picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m ₁ qμsec, each line has a length of 40 m ₁ μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m ₁ =6 have been chosen.
The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m ₁ ×m ₂ memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m ₁ memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m ₁ substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m ₁ character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).
The frequency f _d at which the display clock pulses occur directly determines the length of a picture element and hence the character width. In the above-mentioned case in which m ₁ =6 and in which a character width of 1 μsec is chosen, this means that f _d =6 MHz. A change in the rate of the display clock pulses involves a change in the length of a line of the page to be displayed (now 40 μsec). In practice a small deviation of, for example, not more than 5% appears to be acceptable. For generating the display clock pulses the generator circuit receives reference clock pulses. In the decoder circuit described in Reference 1 these reference clock pulses are also supplied at a rate of 6 MHz, more specifically by an oscillator specially provided for this purpose.
OBJECT AND SUMMARY OF THE INVENTION
A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.
According to the invention,
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m ₁ clockpulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m ₁ character picture element codes.
The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m ₁ picture elements, m ₁ reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m ₁ character picture element codes.
REFERENCES
1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.
3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.
4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;
FIG. 2 shows different matrices of picture elements constituting a character;
FIG. 3 shows diagrammatically the general structure of a character generator;
FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 5 shows some time diagrams to explain its operation;
FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 7 shows some time diagrams to explain its operation;
FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.
EXPLANATION OF THE INVENTION
General structure of a TV receiver
FIG. 1 shows diagrammatically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2 receiving a television signal modulated on a high-frequency carrier, which signal is processed in a plurality of processing circuits. More particularly, it is applied to a tuning circuit 23 (tuner or channel selector). This circuit receives a band selection voltage V _B in order to enable the receiver to be tuned to a frequency within one of the frequency bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning voltage V _T with which the receiver is tuned to the desired frequency within the selected frequency band.
This tuning circuit 3 supplies an oscillator signal having a frequency of f _OSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.
The signal CVBS thus obtained is also applied to a colour decoder circuit 5. this circuit supplies the three primary colour signals R', G' and B' which in their turn are applied via an amplifier circuit 6 to a display device 7 in the form of a display tube for the display of broadcasts on a display screen 8. In the colour decoder circuit 5 colour saturation, contrast and brightness are influenced by means of control signals ANL. The circuit also receives an additional set of primary colour signals R, G and B and a switching signal BLK (blanking) with which the primary colour signals R', G' and B' can be replaced by the signals R, G and B of the additional set of primary colour signals. A Philips IC of the TDA 356X family described in Reference 3 can be used for this circuit 5.
The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency f _o from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.
The Philips IC SAA 5030 may be used as video input circuits 91, the Philips IC SAA 5040 may be used as teletext acquisition and control circuit, a 1K8 RAM may be used as page memory, a modified version of the Philips IC SAA 5050 may be used as character generator 94 and a modified version of the Philips IC SAA 5020 may be used as control circuit 95, the obvious modification being a result of the fact that this IC is originally intended to receive reference clock pulses at a rate of 6 MHz for which 13.5 MHz has now been taken.
The acquisition and control circuit 92 is also connected to a bus system 11. A control circuit 12 in the form of a microcomputer, an interface circuit 13 and a non-volatile memory medium 14 are also connected to this system. The interface circuit 13 supplies the said band selection voltage V _B , the tuning voltage V _T and the control signals ANL for controlling the analog functions of contrast, brightness and colour saturation. It receives an oscillator signal at the frequency f' _OSC which is derived by means of a frequency divider 15, a dividing factor of which is 256, from the oscillator signal at the frequency f _OSC which is supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 13 combined constitute a frequency synthesis circuit. The Philips IC SAB 3035 known under the name of CITAC (Computer Interface for Tuning and Analog Control) and described in Reference 4 can be used as interface circuit 13. A specimen from the MAB 84XX family, manufactured by Philips, can be used as a microcomputer.
The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage V _B and a given tuning voltage V _T so that the receiver is tuned to the desired transmitter.
For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.
The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receives operating instructions and activates, via the bus system 11, one of the circuits connected thereto. It is to be noted that an operating instruction may be a single instruction, that is to say, it is complete after depressing only one key. It may also be multiple, that is to say, it is not complete until two or more keys have been depressed. This situation occurs, for example, when the receiver is operating in the teletext mode. Operation of figure keys then only yields a complete operating instruction when, for example, three figure keys have been depressed. As is known, such a combination results in the page number of the desired teletext page.
The character generator
As already stated, a character is a matrix comprising m ₂ rows of m ₁ picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m ₁ =6 and m ₂ =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.
FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m ₁ ×m ₂ memory elements each comprising a character picture element code. Each m ₁ ×m ₂ character picture element code corresponds to a picture element of the character and defines, as already stated, whether the relevation picture element must be displayed in the so-called foreground colour or in the so-called background colour. Such a character picture element code has the logic value "0" or "1". A "0" means that the corresponding picture element must be displayed in the background colour (for example, white). The "1" means that the corresponding picture element must be displayed in the foreground colour (for example, black or blue). At C in FIG. 2 there is indicated, the contents of the sub-memory for the character shown at B in FIG. 2.
The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.
The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.
The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f ₀ . In the character generator described in Reference 2, page 391, f ₀ is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.
When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f ₀ is not a rational multiple of 6 MHz, for example, if f ₀ =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.
FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec.
An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding network 9442 each time supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse in a group of fourteen reference clock pulses. More particularly the display clock pulse, which is obtained each time in response to the first reference clock pulse of a group, is applied to the output line 9443, whilst the other display clock pulses are applied to the output line 9444. Thus, the pulse series shown at B and C in FIG. 5 occur at these output lines 9443 and 9444, respectively.
The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.
This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register elements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422.
Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.
The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.
The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.
As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner.
In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6 by ensuring that two consecutive picture elements partly overlap each other. This is realized in the converter circuit shown in FIG. 4 by means of a rounding circuit 9427 which receives the character picture element codes occurring at the output of the shift register circuit 9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D flip-flop 9427(2). The T input of this flip-flop receives the clock pulses shown at E in FIG. 5, which pulses are derived from the reference clock pulses TR by means of a delay circuit 9427(3). This circuit has a delay time t ₀ for which a value in the time diagram indicated at E in FIG. 5 is chosen which corresponds to half a clock pulse period of the reference cock pulses. The character picture element codes supplied by the shift register circuit 9420 are now applied directly and via the D flip-flop 9427(2) to the OR gate which thereby supplies the six character picture element codes CH(.) in the time intervals as indicated at F in FIG. 5. The result of this measure for the display of the character with the letter A is shown at F in FIG. 2.
The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providing it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 have the same reference numerals. The converter circuit 942 shown in FIG. 8 differs from the circuit shown in FIG. 6 in that the said rounding circuit denoted by the reference numeral 9428 is incorporated between the pulse widening circuit 9426 and the AND gate circuits 9424(.). More particularly this rounding circuit is a pluriform version of the rounding circuit 9427 shown in FIG. 4 and is constituted by six D flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the respective control signals S(1) to S(6) directly and via the D flip-flops. The T inputs of these D flip-flops again receive the version of the reference clock pulses delayed over half a reference clock pulse period by means of the delay circuit 94210. This rounding circuit thus supplies the control signals S'(.) shown in FIG. 7.

Other References:

Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5030 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.



Teletext / Videotext Error correction circuit using character probability :

An error correction circuit in a television receiver for receiving, for example, Teletext information, Viewdata information or information of comparable systems. The codes representing symbol information received by the receiver are classified into one out of two or more classes in dependence on the frequency of their occurrence, this classification being an indication of the extent to which it is probable that a received code is correctly received.
In FIG. 1, a picture text television receiver has a receiving section, audio and video amplifiers 4 and 9 and a picture tube 10, 11. A text decoder 21 receives symbol information which is stored in a store 25 for display. An error detector circuit 40 including a comparison circuit 43 and two parity circuits 41 and 42, and checks for parity between newly received and already stored symbol information. A reliability circuit 60 is also included.

1. An error correction circuit for a receiving device for receiving digitally transmitted symbol information, the transmission of this information being repeated one or more times, the receiving device having a decoding circuit for decoding the received information, an information store coupled to said decoding circuit for storing the information, a circuit for generating synchronizing signals and a video converter circuit coupled to said information store and said generating circuit for converting information and synchronizing signals into a composite video signal for application to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of video lines greater than one, the error correction circuit being coupled to said decoding circuit and said information store and including means coupled between said decoding circuit and said information store for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, a write-switch having one input coupled to said decoding circuit and an output coupled to said information store, and a write-setting circuit, coupled to another input of said write-switch, which determines whether the newly received information is written or not written into the information store, said write-setting circit having an input coupled to said checking means whereby the results of said checking are a factor in the setting of said write-switch by said write-setting circuit, characterized in that the error correction circuit further comprises a classification circuit coupled to the output of said decoding circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, the input of the classification circuit being coupled to another input of the write-setting circuit. 2. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the write-setting circuit includes a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to the information store for accessing the additional storage elements, for determining, from the additional storage element corresponding with the symbol address position of newly received symbol information, a new reliability bit, an output of the reliability circuit being coupled back to the information store for writing this new reliability bit into the corresponding additional storage element when the reliability bit for this symbol address changes its value. 3. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the checking means comprises a comparison circuit for bit-wise comparing a newly received and decoded symbol with a symbol read from an address of the information store, this address corresponding with the symbol location, a comparison output of the comparison circuit being coupled to a further input of the reliability circuit. 4. An error correction circuit for a receiving device as claimed in any one of the preceding claims, characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store. 5. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the reliability circuit comprises a reliability flipflop and a reliability read circuit for this flipflop, an output of which also constitutes the output of the reliability circuit. 6. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the error correction circuit comprises a second classification circuit, coupled between said other classification circuit and said write-setting circuit and having inputs coupled to said information store, for classifying a symbol read from the information store. 7. An error correction circuit for a receiving device as claimed in claim 1 characterized in that the information store comprises, for each symbol address in the information store, at least one further storage element for storing the classification associated with the symbol for that symbol address.

Description:

BACKGROUND OF THE INVENTION
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking.
Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity.
For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 ⁸ ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European languages, in so far they are written in latin characters, have all sorts of "extra" characters, for example Umlaut letters, accent letters, etc. When all these extra characters are totalled, including Icelandic, Maltese and Turkish, then it appears that a total of approximately 220 symbols is required, namely the 128 known symbols plus further symbols for these "extra" characters.
Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds.
As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the symbols for one text line of 40 characters in one video line, whereas on the other hand the average transmission rate decreases if more video lines are needed for the information transmission. This solution is generally considered to be unacceptable, also because the compatibility with existing receivers would be fully lost.
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.

SUMMARY OF THE INVENTION
It is the object of the invention to provide an error correction circuit of the type referred to for a receiving device for Teletext and comparable systems, which offers such a solution for the problem outlined above that also for an 8-bit code without a parity bit substantially all errors, if any, can be corrected in the second transmission cycle which is received.
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A _x will never be received as another A-symbol A _y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839.
For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be considered to be somewhat suspect. This also applies to each B-symbol recorded in the first cycle, which may lead to a further improvement when a decision is taken.
Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
When the transmitter successively transmits an A-symbol for a certain symbol and location and symbols ABA are successively received, then the A-symbol may be recorded as being "non-suspect" after the first cycle, indicated by an R (reliable) hereinafter. An R' after the second (A), the brackets indicating that the information is retained (not written into the information store) indicates the assumed non-reliability of this retained (A)-symbol, and an A and an R in the third cycle indicates the reliability of the correctly received A-symbol. The A-symbol in the information store is now again assumed to be reliable for this symbol sequence.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used.
As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.

 It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:

TABLE I

______________________________________

Modified Class Symbol (n+1) Parity symbol (n+1) Parity

______________________________________

A xxxxxxx 1 1 xxxxxxx 1 1 A xxxxxxx 0 1 xxxxxxx 1 0 B xxxxxxx 1 0 xxxxxxx 0 1 B xxxxxxx 0 0 xxxxxxx 0 0

______________________________________

In this case only one 8-bit parity circuit is needed.
It is of course alternatively possible to realize the second classification circuit virtually by using the first classification circuit twice on a time-sharing basis, first as the first and then as the second classification circuit. This requires some additional control logic and some additional time, so that the provision of a second classification circuit will be preferred, especially in the case where a simple parity check is performed.
The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A receiving section 1 having an aerial input 2 comprises the high-frequency receiving section, the intermediate-frequency amplifier section, the detection and the synchronizing circuits of the receiver. An audio output 3 is coupled to one or more loudspeakers 5 via an audio amplifier 4. Via control switches 7 and 8 a video output 6 is coupled for normal television reception to a video amplifier 9 for a picture tube 10 comprising the picture screen 11. Via a control switch 13 a synchronizing output 12 is coupled during normal television reception to a time-base circuit 14 which supplies the deflection voltages for the picture tube 10 via an output 15.
However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.
The decision whether the content of the buffer register 23 must be transferred or not transferred to the storage register 24 is taken by an error correction circuit, which would, in the known Teletext system, consist of a parity check circuit.
The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having two inputs and an output. An input 45-i of each of the write switches is always connected to a corresponding output 46-i of the buffer register 23, these outputs also being connected respectively to inputs 47-1 to 47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7 inclusive, of the comparison circuit 43.
The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK _R =CLK, obtained from the clock signal generator 29. J _R =R/WR _G +(R/W)'EP (I) K _R =R/WR _G +(R/W)'EB (II)
in which R _G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2.
Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S _x in consecutive cycles 0 to 7, inclusive, indicated as S _x ,0 to S _x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S ₀ to S _x -1, inclusive, and S _x +1 to S ₉₅₉ , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R _G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R _G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R _G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.

TABLE II

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Decision Read Write SR EP EB R G 23➝24 Written S R K R

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1 0 0 0 1 0 0 x 2 1 0 0 1 1 1 x 3 1 1 0 1 1 1 x 5 1 1 1 0 1 x 1 6 1 0 1 0 0 x 0 7 0 0 1 0 0 x 0 (4) 1 0 0 1 0 0 x

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The states, indicated by an x, of J _R and K _R are irrelevant for the position of the flipflop. The equations I and II have been chosen thus that the required values "0" and "1" for J _R and K _R are produced.
FIG. 2 shows the states and EP, EB and R in the line sections 112, 113 and 105, respectively, by means of an example which shows an unprobable burst of received errors, such that each one of the decisions occurs at least once.
When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R _G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R _G remains "0" because J _R =0, K _R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R _G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.
In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1" at the output "odd parity".
This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R _G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:

TABLE III

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Read Write Written Decision EP R G 23-24 R G

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1A 1 0 1 1 2A 1 1 1 1 3A 0 0 1 0 4A 0 1 0 0

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Again this embodiment can be easily realized by one normally skilled in the art, using what has been described herein.
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.