THE GRUNDIG CHASSIS CUC5860 IS a SEMI MODULAR TYPE:
- 29304-469.71 TELETEXT UNIT
- 29304-324.65 VIDEO CHROMA RGB UNIT (FARBE UND RGB)
- 29304-449.84 STEREO SOUND AND IF AND SYNCHRO UNIT
- 29304-587.74 FRAME DEFLECTION AND E/W CORRECTION UNIT (ABLENKUNG)
- 29504-104.511 POWER SOUND AMPLIFIER
CHASSIS GRUNDIG CUC5860 UNITS VIEWING AND CIRCUITS DESCRIPTIONS:
TDA8146 EAST/WEST CORRECTION FOR RECTANGULAR TV-TUBES:
The TDA8146 is a monolithic integrated circuit in a
14 pin dual-in-line plastic package.
The TDA8146 is designed for use in the east-west
pin-cushion correction by driving a diode modulator
in TV and monitor applications.
Since the parabola current generator is programmable
the device can operate with different CRTs.
.LOW POWER DISSIPATION
.PULSE WIDTH MODULATOR FOR SWITCH MODE OPERATION
.OUTPUT SINK CURRENT UP TO 800mA
.OUTPUT SOURCE CURRENT UP TO 100mA
.PARASITIC PARABOLA SUPPRESSION DURING VERTICAL FLYBACK
.VERTICAL CURRENT SENSE INPUTS GROUND COMPATIBLE
.PROGRAMMABLE PARABOLA CURRENT GENERATOR FOR DIFFERENT TV-TUBES .EXTERNAL KEYSTONE ADJUSTMENT
TDA8170 TV VERTICAL DEFLECTION OUTPUT CIRCUIT:
The TDA8170 is a monolithic integrated circuit in
HEPTAWATTTM package. It is a high efficiency
power booster for direct driving of verticalwindings
of TV yokes. It is intended for use in Colour and B
&Wtelevision receivers as well as in monitorsand
The functions incorporated are :
TDA 4480-C Multi standard quasi parallel-sound processor for TV-sets
High signal sensitivity
Simple filter configuration and few external
Processing of two carrier stereo signals
Low intercarrier distortions
Alignment free AM demodulator for the standard L
VCO controlled mixer stage converts intercarrier
frequencies of different standards into a preferred
Optimum tuning characteristic
The integrated circuit allows the high quality processing of sound carrier for different TV standards. The circuit requires
separate vision and audio carrier inputs. It delivers the output audio signal for mono, two channels or stereo applications.
Audio carrier signal (simple or double carrier, FM and AM) is applied via three stage AGC controlled broad band amplifier
which delivers regulated output signal for two mixing stages. One mixer works for AM-demodulation and AGC-function
whereas the second mixer produces the sound intercarrier IF-frequencies (5.5/5.74 MHz).
Vision carrier signal for the intercarrier generation is delivered from the demodulator tank of the video IF circuit (TDA
4439, TDA 4453). It is then matched via a limiter stage to the FM intercarrier mixer. FM-sound-IF-carrier reaches the
quadrature demodulator via the selection circuit and the following limiter amplifier. The final audio signal is supplied
to the low ohmic output (Pin 7,14) with low pass filter character.
There is a switchable converter for different audio standards (4.5, 6.00 and 6.5 MHZ), which mixes the sound 1P-signal
properly e.g. at 5.5 MHz. The VC0 (Pin 10) must be controlled across the sound output (Pin 7) which includes
Sound signal at the AM-modulation is introduced via standard switch in the first sound channel, whereas the intercarrier,
converter section and both FM demodulators are switched off. In case of sound IF converter operation, the second sound
channel and the AM-section are switched off. The standard mode is controlled by a tristate signal on Pin 6.
TDA2579 Horizontal/vertical synchronization circuit
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth.
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 <>
In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height
Video tape recorders in feature mode
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.
The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated
via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at
count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by
adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of
the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage
a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).
The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value
of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends.
The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is
discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and
ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current
source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a
typical voltage of » 7.5 volts. The recommended operating current range is 10 to 75 mA. The resistance at pin R4 should
be 100 to 770 kW. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired
value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current
measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback
voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and
AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.
The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a
fully DC coupled feedback circuit is possible.
The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level
on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output
signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard
levels specified refer to the zener diode reference voltage source level.
The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately
170 W. The output pin is also connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins 5,6,7,8 and 18)
The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of
the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level value
is stored in the capacitor at pin 6. The slicing level value can be chosen by the value of the external resistor between
pins 6 and 7.
Black level detector
A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with
a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC
conditions at input pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and
ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced
and separation of the vertical sync pulse is improved.
Noise level detector
An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a
built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at
the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated.
A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below
19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated
by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the
“acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant.
When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync
pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.
TDA 5931-4 Video IF Amplifier and Demodulator with Full-SCART Bipolar IC
l Multistandard video IF
l Interference suppression circuitry
l Mean/peak value control
l Area of application: TV set with Full-SCART
Video IF for all European standards for positive and negative modulation. The video section
contains a Full-SCART interface. An output for the demodulated video signal (pin 9) allows the
insertion of a sound trap into the signal path to the input or the SCART switch and the SCART output
buffer amplifier (pin 7). The analog setting function (delayed AGC threshold) is controlled via a
potentiometer, all other switch functions are controlled via open-collector transistors.
The component includes a four-stage, capacitively coupled, symmetrically designed and controlled
amplifier, a limiter with selection, and a mixer for quasi-synchronous demodulation of positive and
negative modulated IF signals. In addition a video output amplifier and noise suppression circuitry
are included. This output is used for generating the AGC voltage. The AGC for both modulation
types has been realized as integral AGC with noise free peak and mean value detector (only for
positive modulation). For SCART applications this output is switched a video source switch with two
inputs (for the demodulator signal or SCART socket) and two outputs (SCART- and TV output). The
demodulator output (pin 9) provides a video signal output level 3 dB higher than the level required
for the operation of the TV set or to drive the SCART connector. Therefore it is possible to insert a
sound trap in between this output and the input of the SCART switch (pin 7). The insertion loss of
the sound trap has to attenuate the signal level at pin 9 by a factor 2/3 or 3 dB (AC and DC) to avoid
distortions in the SCART switch.
The delayed tuner AGC is generated by a threshold amplifier driven by the control voltage. The
amplifier response can be controlled by means of an external potentiometer. (The increase of the
tuner AGC voltage shall create a higher tuner gain = positive control).
At a video carrier input level of V1/18 = 4 mVrms, fPC = 38.9 MHz and a superimposed AGC voltage
of V16 = 1.5 V the tank circuit is aligned that way, that at the positive video output the demodulated
video signal 6 Vpp is at its maximum.
As a modulation every sufficient video test pattern can be used. Then the superimposed AGCcontrol
voltage at pin 16 is reduced until the video signal has an amplitude of approx. 2 Vpp. The
video signal is then fine tuned for its maximum.
The adjustment is not critical due to the wide maximum.
The adjustment can also be performed regarding intercarrier signal to noise ratio, differential gain or
TDA4650 Multistandard colour decoder, with negative colour difference output signals
Identifies and demodulates PAL,
SECAM, NTSC 3.58 and NTSC 4.43
chrominance signals with:
– automatic standard identification
by sequential inquiry
– secure SECAM identification at
50 Hz only, with PAL priority
– four switched outputs for
chrominance filter selection and
– external service switch for
· PAL / NTSC demodulation
– H (burst) and V blanking
– PAL switch (disabled for NTSC)
– NTSC phase shift (disabled for
– PLL-controlled reference
– two reference oscillator crystals
on separate pins with automatic
– quadrature demodulator with
· SECAM demodulation
– quadrature-demodulator with a
single external reference tuned
– alternate line blanking, H and V
· Gain controlled chrominance
· ACC demodulation controlled by
· Internal colour-difference signal
output filters to remove the residual
The TDA4650 is a monolitic
integrated multistandard colour
decoder for PAL, SECAM and NTSC
(3.58 and 4.43 MHz) with negative
colour difference output signals. The
colour-difference output signals are
fed to the TDA4660/TDA4661,
Switched capacitor delay line.
Notes to the characteristics
1. For the SECAM standard, amplitude and H/2 ripple content of the CD signals (R-Y) and (B-Y) depend on the
characteristics of the external tuned circuit at pins 7 to 10. The resonant frequency of the external tuned circuit must
be adjusted such that the demodulated fo voltage level is zero in the -(B-Y) output channel at pin 3.
Now it is possible to adjust the quality of the external circuit such that the demodulated fo voltage level is zero in the
-(R-Y) output channel at pin 1. If necessary, the fo voltage level in the -(B-Y) output channel must be readjusted to
zero by the coil of the tuned circuit.
The external capacitors at the pins 2 and 4 (220 pF each) are matched to the internal resistances of the de-emphasis
network such that every alternate scanned line is blanked.
2. The fo frequencies of the 8.8 MHz crystal at pin 21, and the 7.2 MHz crystal at pin 19, can be adjusted when the
voltage at pin 17 is less than 0.5 V (burst OFF), thus providing double subcarrier frequencies of the chrominance
3. The inquiry sequence for the standard is: PAL - SECAM - NTSC (3.58 MHz) - NTSC (4.43 MHz).
PAL has priority with respect to SECAM, etc.
4. The super sandcastle pulse is compared with three internal threshold levels which are proportional to VP.
TDA4665 Baseband delay line
· Two comb filters, using the switched-capacitor
technique, for one line delay time (64 ms)
· Adjustment-free application
· No crosstalk between SECAM colour carriers (diaphoty)
· Handles negative or positive colour-difference input
· Clamping of AC-coupled input signals (±(R-Y) and
· VCO without external components
· 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 ms line)
· Sample-and-hold circuits and low-pass filters to
suppress the 3 MHz clock signal
· Addition of delayed and non-delayed output signals
· Output buffer amplifiers
· Comb filtering functions for NTSC colour-difference
signals to suppress cross-colour.
The TDA4665 is an integrated baseband delay line circuit
with one line delay. It is suitable for decoders with
colour-difference signal outputs ±(R-Y) and ±(B-Y).
TDA4565 Colour transient improvement circuit
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
· Two Y output signals; one of 180 ns less delay.
TDA3505 Video control combination circuit with automatic cut-off control
The TDA3505 and TDA3506 are monolithic integrated circuits which perform video control functions in a PAL/SECAM
decoder. The TDA3505 is for negative colour difference signals -(R-Y), -(B-Y) and the TDA3506 is for positive colour
difference signals +(R-Y), +(B-Y).
The required input signals are: luminance and colour difference (negative or positive) and a 3-level sandcastle pulse for
control purposes. Linear RGB signals can be inserted from an external source. RGB output signals are available for
driving the video output stages. The circuits provide automatic cut-off control of the picture tube.
· Capacitive coupling of the colour difference and
luminance input signals with black level clamping in the
· Linear saturation control acting on the colour difference
· (G-Y) and RGB matrix
· Linear transmission of inserted signals
· Equal black levels for inserted and matrixed signals
· 3 identical channels for the RGB signals
· Linear contrast and brightness controls, operating on
both the inserted and matrixed RGB signals
· Peak beam current limiting input
· Clamping, horizontal and vertical blanking of the three
input signals controlled by a 3-level sandcastle pulse
· 3 DC gain controls for the RGB output signals (white
· Emitter-follower outputs for driving the RGB output
· Input for automatic cut-off control with compensation for
leakage current of the picture tube
1. < 110 mA after warm-up.
2. Values are proportional to the supply voltage.
3. When V11-24 < 0,4 V during clamping time - the black levels of the inserted RGB signals are clamped on the black
levels of the internal RGB signals.
When V11-24 > 0,9 V during clamping time - the black levels of the inserted RGB signals are clamped on an internal
DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the
4. When pins 21, 22 and 23 are not connected, an internal bias voltage of 5,5 V is supplied.
5. Automatic cut-off control measurement occurs in the following lines after start of the vertical blanking pulse:
line 20: measurement of leakage current (R + G + B)
line 21: measurement of red cut-off current
line 22: measurement of green cut-off current
line 23: measurement of blue cut-off current
6. Black level of the measured channel is nominal; the other two channels are blanked to ultra-black.
7. All three channels blanked to ultra-black.
The cut-off control cycle occurs when the vertical blanking part of the sandcastle pulse contains more than 3 line
The internal blanking continues until the end of the last measured line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses, otherwise another control cycle begins.
8. The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate
the various pulses.
9. Blanked to ultra-black (-25%).
10. Pulse duration ³ 3,5 ms.
GRUNDIG M70-590/9 TOP MONOLITH CHASSIS CUC5860 Television receiver comprising a teletext videeotext decoding circuit and a page number memory:
A television receiver which is suitable for displaying teletext pages comprises a control system including a microcomputer. The microcomputer is coupled to a volatile memory which comprises a plurality of page number registers. A page number can be temporarily stored in each of these registers. With the aid of a keyboard the user makes known which page numbers he wants to have stored in the different registers and the stored page numbers represent a first series of pages. One single read key (RCL) is provided for the display of such a page. Each time this key is depressed once, a different page belonging to the first series appears on the picture screen. The sequence in which the pages appear is the same as the sequence in which the user has keyed-in the relevant page numbers. This sequence can be interrupted by the occurrence of a preselected operating instruction in response to which a number of teletext pages not associated with said first series can be displayed on the picture screen. Thereafter, the display of the teletext pages of the first series can be continued.
1. A television receiver comprising:
a control system for generating in response to external manipulations control instructions including teletext page numbers of teletext pages to be displayed on said television receiver;
a teletext-decoder circuit having a page number input for receiving from said control system page numbers of teletext pages to be displayed and having a picture output applying the picture signal of the teletext page to be displayed;
a picture screen coupled to display the picture signal from the picture signal output of the teletext decoder circuit, said picture screen displaying a teletext page which is identified by an associated page number;
page number storage means for storing a plurality of page number; and
a programmable control circuit coupled to the page number storage means and to the control system for receiving the control instructions, and to said page number input of the teletext decoder circuit to apply teletext page numbers thereto, the control circuit being programmed for carrying out the steps of:
storing in the page number storage means a first series of preselected teletext page numbers selected by a user in the order in which the corresponding teletext pages are desired for display;
successively applying the teletext page numbers of said first series to the teletext-decoder in response to successive occurrences of a selected first control instruction for successively displaying the teletext pages corresponding to the teletext page numbers successively applied to the teletext-decoder;
interrupting the successive application of teletext page numbers of said first series to the teletext-decoder in response to the occurrence of a selected further control instruction;
storing intermediate teletext page numbers in the order in which the corresponding teletext pages are desired for display;
successively applying the intermediate teletext page number to the teletext-decoder in response to successive further occurrences of the selected control instruction; and
continuing the successive application of the remainder teletext page numbers of said first series to the teletext decoder after all the intermediate teletext page numbers have been applied thereto.
2. A television receiver as claimed in claim 1, in which the storage means comprises N registers, each register storing a teletext page number, whereby registers storing teletext page numbers selected by the user are defined to be occupied registers and whereby the remaining registers are defined to be non-occupied registers, the control circuit is further programmed for:
making a register non-occupied in response to each occurrence of the selected first control instruction,
generating a sequence of further page numbers S+1, S+2, S+3, . . . in which S represents the last teletext page number of the first sequence; and
storing the teletext page numbers S+1, S+2, . . . S+(N-M) in the respective non-occupied registers, where M is the actual number of occupied register.
(1) Field of the Invention
The invention relates to a television receiver of a type comprising a teletext decoding circuit and a storage means (page number memory) in which the page numbers associated with a plurality of teletext pages can be stored.
(2) Description of the Prior Art
Such a television receiver has several operating modes, more specifically a program-mode and a teletext mode. In the program mode the video signal transmitted by a transmitter is applied through a video channel to a picture screen for displaying the television program. In the teletext mode said video signal is applied through a teletext decoder circuit to the picture screen for displaying the teletext associated with the program. The television itself can be partly or wholly suppressed.
The operating mode is determined by the viewer, (user). To enable the viewer to inform the receiver about his wishes, the receiver includes a control system comprising external components which can be manipulated by the viewer. More specifically, this control system has a control panel with control keys, each having a specific control function. This function is indicated by a sign applied on, over or under the relevant control key. Thus, there are for example a volume control key, a luminance key, a teletext key, a mixed-mode key, a program key and a plurality fo figure keys etc. These last-mentioned keys are characterized in that the associated signs are numerals. If the receiver is in the program mode, the viewer can inform the receiver with the aid of the figure keys which program or channel is wanted. After the teletext or the mixed-mode key has been operated the set is in the teletext mode with a partly or wholly suppressed television program and the viewer keys-in the page number of the desired teletext page, using the same above mentioned keys.
Operation (or manupulating) of one or more of the keys on the control panel generally results in the generation of a control instruction by the control system. Such control instruction may include the page numbers of a desired teletext page. All these instructions are received by a control circuit which interprets these instructions and gives instructions to the different circuits to be controlled, including the teletext decoder circuit. More specifically, the teletext decoder receives a page number in response to which the required teletext page is captured, stored in a page memory and thereafther displayed on the picture screen by a character generator.
As is known a teletext index page is first displayed on the picture screen after a teletext key or the mixed-mode key has been operated. By selecting a desired page from this index and keying-in the associated page number with the aid of the numeric keys this teletext page is captured by the teletext decoder circuit and displayed thereafter.
If thereafter the display is required of a page associated with a different subject, the index page must usually again be consulted to find the page number of the relevant page. It should be borne in mind that each time the page number of a desired page is keyed-in it takes a certain period of time before the relevant page is displayed on the screen. It is therefore justified to state that such a television receiver is far from user-friendly. To improve this, it is proposed on page 527 of reference 1 to provide the receiver with a storage means which is coupled to the control circuit and in which a plurality of page numbers can be stored. This storage means will be referred to as the page number memory hereinafter.
By operating the control circuit, the user can store a first series of page numbers in a sequence in which he wants them to be displayed, in the page number memory. To enable the display in the desired sequence of these preselected teletext pages, the control panel has a key which will be called the read key hereinafter. Each time this key is operated, the control circuit receives an accurately defined operating instruction and a subsequent page number of the first series is read from the page number memory and applied to the teletext decoder circuit. In this way the teletext pages of the first series are sequentially displayed on the picture screen.
Thus, for this television receiver it is possible to select all those pages from an index page the viewer is interested in. The page corresponding numbers can be stored in the page number memory in the sequence in which the display of these pages is desired. Thereafter, they can be caused to appear in the desired sequence, one after the other, by pushing the read key once for every page.
It should be noted, that, after the read key has been operated, it also takes a certain time before the new page appears on the picture screen. However, by constructing the teletext decoder circuit in the way described in reference 1 or 2, a new page can be displayed immediately after pushing the read key. It is possible to couple to the teletext decoder circuit detailed in said reference a page memory having a capacity that no less than four pages can be stored therein simultaneously. All this is then organised such that this page memory contains the page actually displayed on the picture screen and also the three pages of the first series.
It should also be noted that the page number memory may be constituted by a non-volatile memory, so that the same series of teletext pages are permanently available. It is alternatively possible to use a volatile memory for this purpose, optionally in combination with a non-volatile page number memory.
SUMMARY OF THE INVENTION
The invention has for its object to further improve the convenience of use of a television receiver of the type defined in the foregoing, having a volatile page number memory. According to the invention, the control circuit performs the following additional steps:
interrupting the sequential display of the teletext pages of the series for the benefit of the sequential display of a number of further teletext pages which do not belong to the first series, whose associated page numbers are generated by means of the control system; and,
continuing the display of the teletext pages of the first series in response to a further operation of the read key, after all the further teletext pages have been displayed on the screen.
The properties of the television receiver thus obtained will no doubt be appreciated when the following is considered. The contents of the first series of pages whose page numbers are stored in the page number memory are not known previously. When those pages are displayed, it may happen that a given page is itself an index page (denoted sub-index page in the sequel) or that it contains a reference to pages in which additional information on the same subject is contained. The viewer can now select from such sub-index page a further series of pages, generate the associated page numbers with the aid of the control system and insert the display of these pages between the sub-index page and the subsequent page of the first series. If the control circuit were not implemented in such a way that the above-defined steps can be performed, then these further pages could not be displayed until all the pages of this first series have been displayed on the picture screen.
1. Enhanced UK teletext moves towards still pictures; J. P.Chambers: IEEE Transactions on Consumer Electronics, Vol. Ce-26, Aug. 1980, pages 527-532.
2. Computer controlled teletext; J. R.Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
3. Bipolar IC's for video equipment; Philips Data Handbook Integrated Circuits Part 2, Jan. 1983.
4. IC's for digital systems in radio, audio and video equipment; Philips Data Handbook Integrated Circuits, Part 3, Sept. 1982.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 shows the general structure of a television receiver comprising a teletext decoder circuit and
FIGS. 2 to 10 shows diagrams to explain the operation of this television receiver.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
General Structures of the Television Receiver
FIG. 1 shows schematically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2, which receives a video signal modulated on a high-frequency carrier and processed in a plurality of processing circuits. More specifically, the video signal is applied to a tuning circuit 3 (tuner or channel selector) This tuning circuit receives a band selection voltage V B to enable tuning of the receiver to a frequency within one of the frequency bands VHF1, VHF2, UHF etc. In addition, the tuning circuit receives a tuning voltage V T for tuning the receiver to the desired frequency within the selected frequency band.
This tuning circuit 3 produces an oscillator signal having frequency f OSC and also an intermediate-frequency signal IF. The last-mentioned signal is applied to an intermediate-frequency amplifying and demodulating circuit 4 which produces a base band composite video signal CVBS. For this circuit 4 reference could be made to Philips IC TDA 2540, described in Reference 3.
The signal CVBS thus obtained is further applied to a colour decoder circuit 5, which produces the three primary colour signals R, G and B, which are applied by an amplifier circuit 6 to a picture tube 7 for displaying television programs on the picture screen 8. In the colour decoding circuit 5 colour saturation, contrast and luminance are influenced by means of control signals. In addition, the colour decoder circuit receives an additional set of primary colour signals R', G' and B', and also a switching signal BLK (Blanking) with which the primary colour signals R, G and B can be suppressed. For this circuit 5 a Philips integrated circuit of the group TDA 356 X, which is also described in Reference 3, can be used.
The video signal CVBS is also applied to a teletext decoder circuit 9, which comprises a video input processor 9 (1) receiving the video signal CVBS, separates the teletext data therefrom and applies the latter through a data line TTD to a circuit 9 (2) which will be called the computer controlled teletext decoder (abbreviated to CCT-decoder). This CCT-decoder also receives a clock signal from the video input processor 9 (1) through a clock line TTC. The decoder is further coupled to a memory 9 (3) in which one or more teletext pages can be stored and which is therefore called the page memory. This CCT-decoder produces the three previously-mentioned primary signals R', G', B' and also the switching signal BLK. The video input processor 9 (1) may be constituted by the Philips IC SAA 5230, the CCT-decoder 9 (2) by the Philips IC SAA 5240 and the page memory by a 1K8 to 8K8 RAM. For an detailed description of the structure and operation of a teletext decoder circuit reference is made, for the sake of brevity, to Reference 2.
The CCT-decoder 9 (2) is further connected to a bus system 10, to which also a control circuit 11, in the form of a microcomputer, an interface circuit 12, a non-volatile storage means 13 and a volatile storage means 14 are connected. The interface circuit 12 produces the band selection voltage V B , the tuning voltage V T and also the control signals for controlling the analog functions contrast, luminance, colour saturation. It receives an oscillator signal having frequency f' OSC which by means of a frequency divider 15 whose dividing factor is 256, is derived from the oscillator signal having frequency f OSC supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 12 together form a frequency synthesizing circuit. The Philips IC SAB 3035, which is known by the name CITAC (Computer Interface for Tuning and Analog Control) and is described in Reference 4 may be used as the interface circuit.
The storage means is, for example, used to store the tuning data of a plurality of preselected transmitters, or programs. If under the control of the microcomputer 11 such a tuning datum is applied to the interface circuit 12, then it produces a given band selection voltage V B and given tuning voltage V T , in response to which the receiver is tuned to the desired transmitter.
For the microcomputer the microcomputer of the Philips MAB 84XX family can be used. Although it may be assumed that the structure of a microcomputer is generally known, it should here be briefly remarked that it comprises a program memory (usually a ROM) in which the manufacturer stores a plurality of control programs, and also a working memory.
The volatile storage means 14 is used as a page number memory. It comprises a number of N page number-registers having the register numbers R(1), R(2), . . . R(p), . . . R(N), respectively, wherein N=10. This volatile storage means 14 which is shown in the drawing as a separate memory, is preferably constituted by a portion of the working memory of the microcomputer 11.
To operate this television receiver a control system is provided which in the embodiment shown is in the form of a remote control system and is constituted by a hand set 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt"-input) of the microcomputer. The receiver may be the Philips IC TDB 2033 described in Reference 4 and then has for its object to receive infrared signals transmitted by the hand set 16.
The handset 16 comprises a control panel 16 (1) which, in addition to a number of numeric keys indicated by the numerals 0 to 9, has the following keys; a saturation key SAT, a brightness key BRI, a volume control key VOL, a teletext key TXT, a mixed-mode key MIX, a program key PR, a storage key ENT and a read key RCL. The keys of this control panel are coupled to a transmitter circuit 16 (2) for which the Philips IC SAA 3004 which is described in detail in Reference 4, may, for example, be used. If a key is depressed, then the transmitter circuit 16 (2) generates a code which is specific for that key and which transmitted on a infrared carrier to the local receiver 17, is demodulated there and thereafter applied to the microcomputer 11. Thus, the microcomputer receives control instructions and through the bus system 10 energizes one of the circuits coupled thereto. It should be noted that a control instruction may be single, that is to say that it is complete after only one single key has been operated. It may alternatively be a multiple instruction, that is to say that it is not complete until two or more keys have been operated. This situation occurs, for example, when the receiver is in the teletext mode. In that case operating the numeric keys does not produce a complete operating instruction until, for example, three numeric keys have been depressed. Such an operating instruction, consisting of for example three figures is called a page number.
Operation of the Television Receiver
The operation of the television receiver shown in FIG. 1 is wholly determined by the various control programs stored in the internal program memory of the microcomputer. A control program which is always stored in such a receiver, is the switch-on program SWON which is symbolically shown in FIG. 2. Although this program is generally known, it should be noted for the sake of completeness that this program immediately applies a predetermined tuning datum present in the strorage means 13 to the circuit 12 after the receiver has been switched on, in response to which the receiver is tuned to the relevant transmitter. This may either be a predetermined transmitter, or it may be the transmitter the receiver was tuned to at the moment it was switched off.
After the switch-on program has been performed, the initiation program INT which is symbolically indicated in FIG. 3 is started. During this program the content of the first page number-register R (1) is made equal to a fixed page number; for example 100 (one hundred). This page number 100 is also applied to the CCT-decoder 9 (2) which decodes this page, stores it in the page memory 9 and displays it on the picture screen 8 after the teletext key TXT or the mixed-mode key MIX has been operated. To determine whether a key has been depressed, the so-called background program BGR, which is shown symbolically in FIG. 4 is started.
After the teletext key or the mixed-mode key has been operated a teletext program is started which is given the reference numeral 50 in FIG. 5. This program includes a step 51 in which the value 2 is assigned to a vector p. Thereafter, in a step 52 it is checked whether a page number is received. If so, then a storage program 53 is passed through or, if negative, a read program 54. After such a program has ended, it is checked in step 53 whether a new page number is received.
The storage program 53 includes a step 531 in which the page number received is stored in the register R(p). Thereafter, in a step 532 it is checked whether the storage key (enter key) ENT has been operated. If not, then this storage program has ended and the content of the register R(p) can be overwritten by a different page number. If the enter key has been operated, the vector p is first incremented by one in a step 533. Acting thus, the registers R(1) to R(N) can be loaded with page numbers of a first series of teletext pages. These pages can now be sequentially displayed on the picture screen by means of the read program and by operating the read key RCL. More specifically, the read program 54 has a step 541 in which it is checked whether the read key has been operated. If no, the read program has ended, if yes the contents of the registers are shifted in a step 542 to registers of the next lower number, that is to say the content of register R(2) is shifted to R(1), the content of register R(3) is shifted to R(2) etc. Thereafter the vector p is decremented by one unit in a step 543. So now vector p indicates the empty register having the lowest number. If now a new page number were received and the storage key ENT were depressed, then this new page number would be stored in the register R(p-1). Before the associated teletext page can be displayed, the read key RCL must then first be depressed p-2 times. Prestoring the page numbers of the desired teletext pages and the fact that only one key (namely the read key) must be operated to effect the display of these pages, makes this television receiver very user-friendly. However, the fact that a new page number cannot result in the immediate display of the associated page when not all the page number registers are empty (so that the vector p=1) is experienced as annoying. To increase the convenience and ease of use of this television receiver the storage program is provided, as is shown in FIG. 6, with an auxiliary read program 534 consisting of one step 5341 in which it is checked if after reception of a page number the read key RCL has been operated without the storage key ENT having been depressed. If this is indeed the case, then in a step 5342 the content of register R(p) is transferred to register R(1) and thus the relevant page is pulled-in and displayed as soon as the opportunity arises.
With the program shown in FIG. 6 a subsequent, new page number can be applied after the preceding new page number has been transferred from register R(p) to register R(1). A storage and read program with which the successive display of the teletext pages of the first series can be interrupted to enable the storage of a second series of pages in a sequence the user wants them to be displayed and the sequential display of the pages of this second series in response to the pushing of the read key RCL, followed by the display of the original (first) series of pages, is illustrated in FIG. 7. This program differs from the program shown in FIG. 5 in that now the read program 54, has, instead of the program step 543 a program step 543' in which the vector p is made equal to two after each operation of the read key RCL and the register contents have been shifted one register in step 542, this vector becomes equal to two.
The storage program 53 further comprises a step 535 in which the contents of the register R(p) to R(N-1) are shifted to registers of a next higher number.
If, after the read key RCL has been depressed and the read program has been performed a new page number is applied to the microcomputer, then in step 535 the content of the second register R(2) is shifted to the third register R(3), the content of the third register R(3) is shifted to the fourth register R(4) etc. Thereafter the new page number is stored in the second register R(2) in step 531. If thereafter the storage key ENT is operated, then the vector becomes equal to 3. A new page number is then stored in the third register R(3), whilst the original content of the third, fourth, fifth, sixth etc. registers are shifted to the fourth, fifth, sixth, seventh etc. registers, respectively. So acting thus a second series of Q-1 page numbers can be stored in the registers R(2) to R(Q) each time the read key RCL is operated, the page numbers originally contained in these registers being shifted to registers of Q-1 higher numbers. When the read key is now operated, these Q-1 page numbers of the second series are first applied to the teletext decoding circuit and only thereafter the display of the original (first) series is continued.
The program shown in FIG. 6, which provides the possibility of storing a new page number directly in the first register, and thus to display the associated page on the display screen at the first opportunity can advantageously be combined with the program shown in FIG. 7. For the sake of completeness, FIG. 8 shows a program comprising both the program steps shown in FIG. 6 and those shown in FIG. 7. To have this program proceed adequately, the steps 5343, 5344 are additionally present which, in view of the foregoing need no further explanation.
The teletext programs shown in FIGS. 5, 6, 7 and 8 are structured such that storing a series of new page numbers requires the operation of the storage key ENT after a new page number has been applied. It is however, alternatively possible to structure the teletext program such that the storage key must be operated before a new page number is applied. Such a teletext program is shown for the sake of completeness in FIG. 9. It comprises a step 51' in which the vector p is given the value one. To enable, a decision which the program shown in FIG. 6, also now the immediate storage of any random page number in the register R (1), this program has a step 60 in which it is checked whether a page number is applied. If yes, this page number is immediately stored in the first register R(1) in step 61, whereafter early display of the relevant page can follow. If no page number is coming forward, then it is checked in step 62 whether the storage key ENT has been operated. If not, the read program 54 is effected or else the storage program 63.
The read program again includes the steps 541 and 542. It now also has a step 543" in which the vector p is again made equal to one. The storage program 63 has a step 631 in which the actual value of the vector is incremented by one. Thereafter, in a step 632, the arrival of a new page number is awaited, whereafter in step 633 the contents of the registers R(p) to R(N-1), respectively are shifted to the registers R(p+1) to R(N). Finally, in step 634 the latest page number is stored in the register R(p).
The teletext programs mentioned in the following have the property that those page number registers R(.) in which no page numbers selected by the user are stored remain empty. This implies that when the user repeatedly depresses the read key he may be confronted by the situation that all registers are empty. To prevent this situation from occurring, these registers may be filled automatically with page numbers for which there are two adequate possibilities. Firstly, they might be the page numbers of preferred pages which had previously been stored already by the user in a non-volatile memory, for example, the memory 13 in FIG. 1. Secondly, they might be the page numbers S+1, S+2, . . . etc., S being the last page number of the first series. To accomplish that the page number registers are filled thus with page numbers, the teletext program might be of a structure as shown in FIG. 10. This program corresponds to a considerable extent to the program shown in FIG. 8, but differs therefrom in several respects. Step 52 is followed by a step 70 in which a page number and also a user flag flg.(-) are stored in the registers R(2) to R(N) (see FIG. 1). More specifically, the page number in the register R(i) then becomes one higher than the page number in the preceding register R(i-1), so that at the end of this step 70 the page number registers R(1) to R(n) contain the respective page numbers 100, 101, 102, 103, . . . 100+(N-1). The associated user flags are all zero.
If at a given value of the vector p a new pagenumber, for example S, is applied, then in step 71 it is first checked whether the user flag (flg(p) in the register R(p) is equal to one. If not this implies that the register R(p) is not filled with a page number explicitly stipulated by the user. In step 721 this newly applied page number S is then stored in this register R(p). At the same time the associated user flag flg (p) becomes 1 to indicate that this page number has been selected by the user. Thereafter a step 722 is performed which corresponds to step 70. More specifically, the page number S+1 is then stored in the register R(p+1), the page number S+2 in the register R(p+2) whilst the associated user flags flg(p+11), flg(p+2), etc. all become equal to zero, signifying that these page numbers were not explicitly stated by the user.
If upon performing of step 71 it appears that the user flag flg(p) in the register R(p) is indeed equal to one, then in step 535 the contents of the registers R(p) to R(N-1) are shifted to the respective register R(p+1) to R(N), so that in step 531' the latest page number can be stored in the register R(p), the associated user flag flg(p) then simultaneously becoming equal to one.
This teletext program further differs from the program shown in FIG. 8 in that the auxiliary read program 534 has a further step 5345 and the read program 54 has a further step 544 identical thereto. In these steps, each time after the last page number register R(n) has become empty because of the shift operation effected in the preceding step, a page number which is one higher than the page number stored in the last-but-one register R(N-1) is stored in this register R(N). At the same time the associated user flag flg (N) becomes equal to zero.
It should be noted that in the embodiment shown in FIG. 1 the control circuit is predominantly constituted by the microcomputer 11. In practice it has however been found advantageous to arrange between the microcomputer 11 and the CCT-decoder 9(2) a second micro computer which only controls this CCT-decoder 9(2) and for that purpose comprises one of the teletext programs described in the foregoing.