GRUNDIG SUPER COLOR 4230 CHASSIS 29301-374.06 UNITS VIEW.

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Frame oscillator Unit: 29301 - 009.02

- Synchronization Unit + Line oscillator:29301 - 008.02 (TBA920C)

- Sound Unit:29301- 004.02

- Luminance amplifier:29301 - 005.01

- Color difference amplifier:29301 - 006.01

- Luminance + Chrominance Signal processing:29301 - 024.01 (TDA2510 + TDA2521)

- Tuning control / drive :29301 -056.11

- Line supply stabiliser with magnetic transductor:29301 - 035.01

















TBA920 line oscillator combination

DESCRIPTION
The line oscillator combination TBA920 is a monolithic
integrated circuit intended for the horizontal deflection of the black and white
and colour TV sets
picture tube.

FEATURES:
SYNC-PULSE SEPARATION
OPTIONAL NOISE INVERSION
GENERATION OF A LINE FREQUENCY VOL-
TAGE BY MEANS OF AN OSCILLATOR
PHASE COMPARISON BETWEEN SYNC-
PULSE AND THE OSCILLATOR WAVEFORM
PHASE COMPARISON BETWEEN THE OS-
CILLATOR WAVEFORM AND THE MIDDLE OF
THE LINE FLY-BACK PULSE
AUTOMATIC SWITCHING OF THE VARIABLE
TRANSCONDUCTANCE AND THE VARIABLE
TIME CONSTANT TO ACHIEVE NOISE SUP-
PRESSION AND, BY SWITCHING OFF, POS-
SIBILITY OF TAPE-VIDEO-REGISTERED RE-
PRODUCTION
SHAPING AND AMPLIFICATION OF THE OS-
CILLATOR WAVEFORM TO OBTAIN PULSES
FOR THE CONTROL OF DRIVING STAGES IN
HORIZONTAL, DEFLECTION CIRCUITS
USING EITHER TRANSISTORS OR THYRISTORS.


TDA2521 synchronous demodulator for PAL

GENERAL DESCRIPTION
The TDA2521 is a monolithic integrated circuit designed as a synchronous demodulator for PAL color television receivers. It includes an 8.8 MHz oscillator and divider, to generate two 4.4 MHz reference signals, and provides color difference output.
The TDA2521 is intended to interface directly with the TDA251O with a minimum of external components and is constructed on a single silicon chip using the Fairchild Planar
epitaxial process.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage 14 V
Internal Power Dissipation 600 mW ORDER INFQRMATIQN
Operating Temperature Range —2O°C to +6O°C TYPE PART NO.
Storage Temperature Range —55°C to +125°C 2521 TDA2521
Pin Temperature iSo|dering 10 si 260°C

Planar is a patented Fairchild process

















TDA2510 CHROMINANCE COMBINATION

GENERAL DESCRIPTION —
The TDA2510 is a monolithic integrated circuit designed for the function of a color television receiver. It Is designed to Interface directly with the TDA2521, using a minimum number of external components.
TDA251O is constructed on a single silicon chip using the Fairchild Planar‘ epitaxial process.

ABSOLUTE MAXIMUM RATINGS

supply Voltage 15 V
Collector voltage of chroma output transistor (pin 7) 20 V
(PD I 100 mW max)
Collector current of chroma output transistor (pin 7) 20 mA
Collector current of color killer output transistor (pin 11) 10 mA
Power dissipation 500 mW
Operating temperature range —25°C 10 +6O°
Storage temperature range *55°C to +12!-3°C

GRUNDIG SUPER COLOR 4230  CHASSIS  29301-374.06 VIDEO Amplifier suitable for use as a color CRT TUBE / kinescope driver:

A color kinescope matrix amplifier has a first input coupled through a capacitor to a source of color difference signals. Another input is coupled to a source of luminance signals. The matrix amplifier includes a cascode output stage direct current coupled to a cathode of a kinescope. A portion of a direct voltage developed at the cascode output amplifier is coupled to one input of a comparator circuit. The other input of the comparator circuit is coupled to a temperature compensated direct voltage reference source. The comparator is rendered operative during horizontal retrace intervals to provide a current to either charge or discharge the input capacitor in accordance with the difference between the voltage at the output of the cascode output amplifier and the reference voltage to compensate for voltage variations at the output of the cascode amplifier due to power supply variations and the like. To compensate for droop caused by the discharge of the input capacitor during the scanning interval, one input of a differential amplifier is included between the input capacitor and the input of the cascode output stage. Negative signal feedback is provided from the output stage to the other input of the differential amplifier via a capacitor arranged to be charged during the horizontal retrace interval. The two capacitors discharge at substantially the same rates during the scanning interval. By virtue of the common mode operation of the differential amplifier droop effects are minimized.


1. In a television receiver including an image reproducing device, a source of chrominance signa

ls, a source of luminance signals and a source of horizontal blanking pulses, said horizontal blanking pulses occurring during the time interval during which said image reproducing device is horizontally retraced, the apparatus comprising:
amplifying means for combining said chrominance signals and said luminance signals, said amplifying means including first and second input terminals and an output terminal, said output terminal being direct current coupled to said image reproducing device, said second input terminal being direct current coupled to said source of said luminance signals;
first capacitive means for coupling said chrominance signals to said first input terminal;
comparator means having first and second input terminals for comparing voltages applied thereto, said comparator means being normally inoperative;
a relatively low level stabilized reference voltage source coupled to said first input terminal of said comparator means;
means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal;
means for selectively rendering said comparator operative in response to said horizontal blanking pulses; and
current converting means coupled to said comparator and to said first capacitive means for charging and discharging said capacitive means to a direct voltage level in relation to the difference in voltage between said first and second input terminals of said comparator means so as to counteract the changes of the voltage developed at said output terminal.
2. The apparatus recited in claim 1 wherein said amplifying means includes:
a differential amplifier having first and second input terminals and an output terminal, said first input terminal being coupled to sai

d first input terminal of said amplifying means, said output terminal of said differential amplifier being coupled to said output terminal of said amplifying means;
second capacitive means coupled to said second input terminal of said differential amplifier; and
means for selectively charging said second capacitive means during said horizontal retrace interval, said first and second capacitive means being selected to have substantially equal discharging rates during the time intervals between said horizontal retrace intervals.
3. The apparatus recited in claim 2 wherein said second capacitive means is coupled between said output terminal of said amplifying means and said second input terminal of said differential amplifier. 4. The apparatus recited in claim 3 wherein said amplifying means includes a cascode amplifier coupled between the output of said differential amplifier and said output terminal of said amplifying means. 5. The apparatus recited in claim 3 wherein said amplifying means includes first and second transistors, the emitter of said first transistor being direct current coupled to the collector of said second transistor, the base of said first transistor being coupled to said first input terminal of said amplifying means, the base of said second transistor being coupled to said second input terminal of said amplifying means, the emitter of said first transist

or being coupled to said first input terminal of said differential amplifier. 6. The apparatus recited in claim 3 wherein said means for selectively charging said second capacitive means includes means for clamping the second input terminal of said differential amplifier to a predetermined voltage during said horizontal retrace interval. 7. The apparatus recited in claim 3 wherein means are provided for adjusting the portion of the voltage developed at said output terminal of said amplifying means which is coupled to said second capacitive means. 8. The apparatus recited in claim 1 wherein said means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal of said amplifying means includes means for adjusting the voltage coupled to said second input terminal of said comparator means. 9. The apparatus recited in claim 1 wherein said comparator means includes:
a differential amplifier having two input terminals and two output terminals, one of said input terminals being coupled to said reference voltage source, the other of said input terminals being coupled to said output terminal of said amplifier means; and
a current mirror circuit having an input and an output, one of said output terminals of said differential amplifier being coupled to said input terminal of said current mirror circuit, the other of said output terminals of said differential amplifier being coupled to the output of said current mirror circuit and to said first capacitor means.
10. The apparatus recited in claim 1 wherein said voltage reference source is temperature compensated. 11. In a television receiver including a color kinescope leaving a plurality of electron beam forming apparatus, a source of luminance signals, a source of a plurality of color difference signals, and a source of horizontal blanking pulses, said horizontal blanking pulses corresponding to the time interval during which said electron beams are horizontally retraced, the apparatus comprising:
a plurality of amplifiers, each of said amplifiers including
amplifying means for com

bining one of said plurality of color difference signals with said luminance signals, said amplifying means including first and second input terminals and an output terminal, said output terminal being direct current coupled to a respective one of said plurality of electron beam forming apparatus, said second input terminal being direct current coupled to said source of said luminance signals, capacitive means for coupling said one of said plurality of color difference signals to said first input terminal,
comparator means having first and second input terminals for comparing voltages applied thereto, said comparator means being normally inoperative,
means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal,
means for selectively rendering said comparator operative in response to said horizontal blanking pulses, and
current converting means coupled to said comparator and to said capacitive means for charging and discharging said capacitive means to a direct voltage level in relation to the difference in voltage between said first and second input terminals of said comparator means so as to counteract the changes of the voltage developed at said output terminal; and a relatively low level stabilized reference
voltage source coupled to said first input terminals of each of said plurality of comparator means.

Description:

The present invention is directed to the field of amplifiers and is particularly directed to the field of amplifier arrangements utilized to drive color image reproducing devices such as kinescopes.
The electron guns of a color kinescope are typically driven by separate amplifier stages. Variations of the operating conditions of an amplifier stage, such as variations of the stage's supply voltage, tend to produce variations in the brightness of a reproduced image. Furthermore, because each of the stages tends to operate at different power dissipation levels the operating conditions of the stages vary with respect to each other and hence color imbalances may occur.
Athou

gh supply voltage regulators and high level clamping circuits have been employed in conjunction with kinescope amplifier stages to inhibit the aformentioned problems, it is desirable to provide kinescope driver amplifier arrangements which maintain their operating point stability with variations in operating conditions such as power supply variations without the need of supply voltage regulators or high level clamping circuits.
Furthermore, it is desirable, because of the trend toward miniaturization in electronic art, that at least a portion of the kinescope amplifier driver should be able to be constructed in integrated circuit form.
It is also desirable to provide kinescope driver amplifier arrangements which include independent controls for adjusting the DC level and the AC amplitude of the signals coupled to the kinescope. This is particularly desirable where "precision-in-line" kinescopes or the like, in which the electron guns have common control electrodes, are employed since, in these types of kinescopes, it is difficult to independently adjust the operating conditions associated with the respective guns because of the commonality of control electrodes.
Furthermore, it is desirable that a kinescope driver amplifier which is to be utilized with a precision-in-line type of kinescope provide a relatively wide bandwidth without the requirement of high frequency peaking coils. Peaking coils tend to be bulky. In addition, undesirable voltages may be developed across a peaking coil due to the large magnetic fields which may be produced by the yokes associated with a precision-in-line kinescope. These undesirable voltages may produce disconcerting brightness and/or hue changes.
In accordance with the present invention, one input terminal of amplifying means is coupled to a source of chrominance signals through capacitive means. A second input of the amplifying means is direct current coupled to a source of luminance signals. The output terminal of the amplifying means is direct current coupled to a color image reproducing device such as a precision-in-line kinescope of the like. The amplifying means includes means for combining the luminance and chrominance signals to provide the image reproducing device with color signals. The amplifying means also includes comparator means for comparing the voltage developed at the output terminal to a reference voltage to generate a current to control the charging of the capacitive means in a manner so as to counter-act the changes of the voltage developed at the output due, for example, to changes in the power supply voltage. The comparator means is arranged to be normally inoperative and is selectively rendered operative during the horizontal retrace interval.
In accordance with another aspect of the present invention, the amplifying means includes a differential amplifier having first and second input terminals and an output terminal. The output terminal of the differential amplifier is coupled to the output terminal of the amplifying means. The first input terminal of the differential amplifier is coupled to the input terminal of the amplifying means. The second input terminal of the differential amplifying means is coupled to a second capacitive means. Means are provided for selectively charging the second capacitive means during the horizontal retrace interval. The first and second capacitive means are selected to have substantially equal discharging rates so as to compensate for any decrease in the DC content (i.e., droop) at the output terminal of the amplifying means during the scanning interval.
In accordance

with still another feature of the present invention, the second capacitive means is coupled to the output terminal of the amplifying means in a manner so as to allow adjustment of the AC gain of the amplifying means. The DC conditions of the output of the amplifying means may be controlled by controlling the portion of the voltage developed at the output terminal coupled to the comparator means.
The present invention may best be understood by reference to the following detailed description and accompanying drawing which shows, partially in block diagram form and partially in schematic form, the general arrangement of a color television receiver employing a kinescope driver amplifier arrangement constructed in accordance with the present invention .
The color television receiver includes a video signal processing unit 141 responsive to radio frequency (RF) signals, received by an antenna, for receiving in a known manner, a composite video signal comprising chrominance, luminance, sound and synchronizing signal components.
The output of video processing unit 141 is coupled to a chrominance channel 142 including a chrominance processing unit 143 and a color demodulator 144. Chrominance processing unit 143 separates chrominance signals from the composite video signal. Color demodulator 144 derives signals of the appropriate polarity representing, for example, R-Y, G-Y and B-Y color difference signal information from the chrominance signals. The TAA630 integrated circuit or similar circuit is suitable for use as color demodulator 144.
The output of video processing unit 141 is also coupled to a luminance channel 145 including a luminance processing unit 146 which amplifies and processes luminance components of the composite signal to form an output signal of the appropriate polarity representing luminance, Y, information. A brightness control unit 147 to control the DC content of luminance signal Y and a contrast control unit 148 to control the amplitude of luminance signal Y are coupled to processing unit 146.
The composite video signal is also coupled to a sync separator 149 which, in turn, is coupled to a horizontal deflection unit 151 and a vertical deflection unit 152. Horizontal deflection unit 151 is also coupled to a high voltage unit 154 which generates operating voltages for kinescope 153. Outputs from horizontal deflection unit 151 and vertical deflection unit 152 are coupled to luminance pr
ocessing unit 146 to inhibit or blank luminance signal Y during the horizontal and vertical retrace intervals. Similarly, an output from horizontal deflection unit 151 may be coupled to chroma processing unit 143 or color demodulator 144 to inhibit the color difference signals during the horizontal retrace interval. Furthermore, first and second signals including positive going pulses, the pulses of each signal being coincident with the horizontal retrace or blanking interval, are coupled to matrix unit 100 to control its operation, as will appear below, via conductors 159 and 167, respectively.

The R-Y output signal and luminance signal Y are coupled to a matrix unit 100 where they are combined to form a color signal representing red (R) information. Similarly, the B-Y and G-Y color difference signals are respectively coupled to matrix-driver units 150 and 157, similar to the combination of matrix unit 100 and kinescope driver 199, where they are matrixed with luminance signal Y to produce color signals representing blue (B) and green (G) information. Since the matrix units for the various color difference signals are similar, only matrix unit 100 will be described in detail.
Matrix unit 100, enclosed within dotted line 160, is suitable for construction as an integrated circuit. The R-Y color difference signal is coupled through a capacitor 110 to the base of an NPN transistor 101 which is a

rranged as a common collector amplifier for color difference signals. Transistor 101, NPN transistor 102, resistors 178 and 184 form a summing circuit 161 for the color difference signal and luminance signal Y, the latter being direct current coupled to the base of transistor 102. The combined output of circuit 161, taken at the collector of transistor 102, is coupled to the base of an NPN transistor 105. Transistor 105 and an NPN transistor 106 form a differential amplifier 162 to which bias current is supplied from a current source including a suitably biased transistor 182. The output of differential amplifier 162, taken at the collector of transistor 105, is coupled through a level shifter, shown as the series connection of a zener diode 163, and a diode 165 to a kinescope 199. Bias current is provided for zener diode 163 and diode 165 through a resistor 183, which serves as the load resistor of transistor 105, and resistors 176 and 177.
Kinescope driver 199 comprises a cascode amplifier 164 including NPN transistors 120 and 119. The output of matrix unit 100 is coupled to the base of transistor 119 while a positive supply voltage (e.g. +12 volts) is coupled to the base of transistor 120. The output of kinescope driver 199, taken at the collector of transistor 120 is direct current coupled through a resistor 179 to the red (R) cathode of kinescope 153. The collector of transistor 120 is coupled to a source of supply voltage B+ through a load resistor 165. Supply voltage B+ is a relatively high voltage, typically, in the order of 200 to 300 vdc.
The collector of transistor 120 is also coupled to a series combination of a resistor 166 and a black level setting potentiometer 167, the latter being returned to ground. A direct voltage proportional to that at the collector of transistor 120 is developed at the wiper arm of potentiometer 167 and is coupled to one input of a voltage comparator circuit 168. Comparator 168 comprises NPN transistors 103 and 104 coupled as a differential amplifier. A second input of comparator 168, at the base of transistor 103, is coupled to a temperature compensated voltage reference (TCVR) unit 169. Voltage reference unit 169, which may, for example, be similar to that employed in the CA3085 integrated circuit manufactured by RCA Corporation, supplies a regulated reference voltage of approximately 1.6 vdc.
Voltage reference unit 169 is also coupled to the matrix portions of units 150 and 157 via conductor 155 so that a common reference voltage is coupled to the respective comparators of units 100, 150 and 157. It is noted that matrix unit 100 and the matrix portions of units 150 and 153 may be constructed as a single integrated circuit.
A current source including an NPN transistor 170 is coupled to the jointly connected emitters of transistors 103 and 104. The first horizontal blanking pulse signal generated by horizontal deflection unit 151 is coupled to the base of transistor 170 via conductor 159.
The output of differential amplifier 168 provided at the collector of NPN transistor 103 is converted to a bidirectional current by means of a current mirror circuit 180 comprising a diode-connected PNP transistor 172 and a PNP transistor 173. The collector of transistor 173 is coupled to the collector of transistor 104 and to the base of transistor 101.
The junction of resistors 166 and 167 is coupled to a signal feedback circuit comprising a series connection of a potentiometer 174 and a resistor 175. Feedback voltage developed at the wiper arm of potentiometer 174 is coupled through a capacitor 120 to the base of transistor 106 (i.e., one input of differential amplifier 162). The base of transistor 106 is returned to ground through resistor 181 and the collector-emitter junction of a transistor 108. The base of transistor 108 is coupled to horizontal deflection unit 151 to receive the first horizontal blanking pulse signal via conductor 159. An NPN transistor 107, the emitter of which is coupled to the base of transistor 106, is arranged together with resistor 181 and the collector-emitter junction of transistor 108 as an emitter follower. The base of transistor 107 is coupled to horizontal deflection unit 151 to receive the second horizontal blanking pulse signal via conductor 167. It is noted that this signal may also be generated within the IC device.
Kinescope 153 may be a precision-in-line kinescope such as the RCA type 15VADTCO1. As is described in U.S. Pat. No. 3,817,397, issued May 21, 1974, there is no provision for separate adjustment of red, green and blue gun screen and grid potentials and only the cathodes of the three guns of such a kinescope are available for separate adjustment of the cut off point of the guns. As will become apparent in the following description, matrix unit 100 and kinescope driver 199 are particularly suited to a kinescope of the precision-in-line type but it should be appreciated that they may be utilized for other types of kinescopes such as delta-gun, shadow mask or other slotted mask types.
In operation, the signal supplied to the base of transistor 107 during the scanning interval by horizontal deflection unit 151 is of sufficiently low amplitude (e.g., less than +4vdc) in relationship to the voltage at its emitter (controlled by the charge on capacitor 120 as will be explained) that it is non-conductive. Because of relatively low voltage applied to the bases of transistors 108 and 170 during the scanning interval, transistors 108, 170, 103 and 104 are also non-conductive and do not affect the operation of matrix circuit 100 during the scanning interval.
The signal -(R-Y), representing red color difference information, and the signal Y, representing luminance information, are coupled to amplifier 161 where they are combined in the emitter circuit of transistor 101 to form a signal -R, representing red information. The signal -R is further amplified and inverted twice by differential amplifier 162 and cascode amplifier 164 for application to kinescope 153.
It is noted that resistors 183, 176 and 177 should be selected so that zener diode 163 is biased well into its reverse breakdown region to inhibit noise.
The portion of the output signal of cascode amplifier 164 developed at the wiper arm of potentiometer 174, is capacitively fed back to one input of differential amplifier 162. This negative feedback arrangement, in conjunction with the use of cascode amplifier 199, provides for a relatively wide bandwidth, thereby eliminating the need for peaking coils or the like to improve high frequency response. The AC gain (or drive) of the matrix unit-kinescope driver arrangement may be adjusted by adjustment of the wiper arm of potentiometer 174 (normally a service or factory adjustment).
During the horizontal retrace interval, a relatively high voltage (e.g., approximately +6 vdc plus the base to emitter voltage of transistor 107 when transistor 107 is rendered conductive) is applied to the base of transistor 107 from horizontal deflection unit 151. Horizontal deflection unit 151 also applies a relatively high voltage to the bases of transistors 108 and 170. As a result transistors 107, 108, 170, 103 and 104 are rendered conductive and the base of transistor 106 is clamped to a voltage substantially equal to the voltage at the base of transistor 107 less the base emitter voltage of transistor 107 (e.g., +6 vdc). The voltage to which the base of transistor 106 is clamped is sufficiently lower than that at the base of transistor 105 so that transistor 106 will be rendered non-conductive and transistor 105 will be rendered fully conductive. Under these conditions, the voltage developed at the collector of transistor 120 will rise toward B+ to a voltage determined by t
he conduction of transistors 119 and 120 and the voltage division action of resistors 165, 166 and the impedance of potentiometer 167 in parallel combination with the series combination of potentiometer 174 and resistor 175.

While the base of transistor 106 is clamped to the voltage applied to the base of transistor 107 less the voltage developed between the base and emitter of transistor 107, the AC feedback provided by capacitor 120 is effectively disconnected and capacitor 120 is provided with a charging path including resistor 166 and a portion of potentiometer 174 by which it is rapidly charged to a voltage determined by the voltage at the emitter of transistor 107 and DC voltage developed at the collector of transistor 120.
The voltage developed at the wiper arm of potentiometer 167 is coupled to the base of transistor 104 and, during each horizontal retrace interval, is compared to the voltage developed at the base of transistor 103 by TCVR 169. A difference in voltage is converted by virtue of the current mirror configuration of transistors 172 and 173 into an error current at the junction of the collectors of transistors 104 and 173. The error current acts, depending on the relative levels at the bases of transistors 103 and 104, to charge or discharge capacitor 110.
Potentiometer 167 initially is adjusted to provide a voltage at the collector of transistor 120 sufficient to cut off the red gun of kinescope 153 when a black image signal is present. Therefore, it is desirable to select the values of resistors 165 and 166 and potentiometer 167 to ensure that the full range of black level control at the red cathode of kinescope 153 is available.
Matrix circuit 100 is arranged so that capacitor 110 will be charged or discharged in a manner to compensate for any change in B+. For example, if B+ decreases, the voltage developed at the base of transistor 104 will decrease relative to the stable reference voltage developed at the base of transistor 103. Therefore, the collector current of transistor 103 and the substantially equal currents flowing through the emitter-collector circuits of transistors 172 and 173 will increase, causing capacitor 110 to be charged. As a result, the voltage at the base of transistor 101 will increase, the voltage at the bas

e of transistor 105 will increase, the voltage at the collector of transistor 105 will decrease and the voltage at the collector of transistor 120 will increase.
It is noted that transistor 173 and transistor 104 operate in what may be termed a push-pull fashion in that the change in current flowing between the emitter and collector of transistor 173 is inversely related to the change in current flowing between the collector and the emitter of transistor 104. Thus, if the current flowing through the emitter-collector of transistor 104 increases, the current through the collector-emitter of transistor 173 decreases, so that capacitor 110 is discharged by the excess of current flowing through transistor 104 rather than being charged by current from transistor 173.
Thus, the feedback arrangement including TCVR 169 of matrix unit 100 adjusts the charge on capacitor 110 to compensate for, and therefore substantially eliminate, the effect on the direct voltage applied to the kinescope cathodes of variations in B+. Furthermore, it is noted that variations in other portions of the matrix amplifier driver arrangement (such as variations caused by temperature or component tolerance changes) affecting the DC conditions at the collector of transistor 120 will be compensated for by the arrangement in a similar manner.
The charge stored on capacitor 110 during the horizontal retrace interval serves to control the bias on cascode amplifier 164 during the succeeding scanning interval. It is noted that the charge on capacitor 110 is not affected by the color difference signals or luminance signals during the horizontal retrace interval, since these signals are arranged to be constant during the horizontal retrace interval.
After the horizontal retrace interval, transistors 103, 104, 170, 172, 173, 107 and 108 are rendered nonconductive (as previously described) and capacitors 110 and 120 begin to discharge. While capacitor 110 controls the bias voltage at the base of transistor 105, capacitor 120 controls the bias voltage at the base of transistor 106. Capacitors 110 and 120 and their associated discharging circuitry preferably are selected so that capacitors 110 and 120 discharge at substantially equal rates. The similar changes in voltage are applied to opposite sides of differential amplifier 162. The common mode rejection characteristics of differential amplifier 162 will prevent the discharging of capacitor 110 to be reflected in the DC conditions at the collector of transistor 120. This "droop" compensation feature provided by capacitor 120 in junction with differential amplifier 162 is desirable, since in its absence, capacitor 110 would have to be a relatively large value to prevent droop. This is especially undesirable if it is desired to construct matrix unit 100 as an integrated circuit because large currents, not compatible with integrated circuit technology, would be required to charge and discharge capacitor 110.

Typical values for the arrangement are shown on the accompanying drawing.
It should be noted that although the present invention has been described in terms of a particular configuration shown in the diagram, modifications may be made which are contemplated to be within the scope of the invention. For instance, cascode driver 199 may be placed with other driver stages well known in the art. Furthermore, the current mirror configuration comprising transistors 172 and 173 may be modified in accordance with other known current mirror configurations.

GRUNDIG SUPER COLOR 4230  CHASSIS  29301-374.06 memory-saving all channel digital tuning system:

A tuning system for a television receiver includes fine tune memories and tuning information memories, the latter having reference channel nominal tuning information for each of the various frequency bands, first increment tuning information for each frequency band and second increment tuning information for each channel. The first increment information represents the initial slope of the tuning characteristic and the second increment information represents the slope of the slope of the tuning characteristic for each channel. Accumulator means add the reference channel and first and second increment informations to derive nominal tuning information for any selected channel. Control logic including counters and latches control the operation of the accumulator means and memories. The accumulator means and fine tune counters are interrogated by counter-driven comparators which develop pulse-width modulated signals corresponding to the tuning information therein. A tuning voltage generator develops the final tuning voltage from the pulse-width modulated signals. Increment tuning information representative of the slope of the tuning characteristic at each channel is derived and used to equalize any auxiliary tuning source. The reference channel information is combined with appropriate numbers of first tuning increments and second tuning increments for deriving nominal tuning information for the selected channel.

1. A television tuning system including:
a voltage controlled tuner having a nonlinear tuning voltage-versus-frequency characteristic;
memory means storing reference tuning information, first increment tuning information related to the slope of said characteristic at a base channel and second increment tuning information related to the slope of the slope of said characteristic at each channel;
tuning voltage means generating a tuning voltage for said tuner;
channel address means accessing said memory means and reading out the corresponding tuning informations; and
accumulator means coupled between said memory means and said tuning voltage means for generating nominal tuning information for the selected channel from said reference tuning information, said first increment tuning information and said second increment tuning information.
2. A television tuning system as set forth in claim 1 wherein said reference tuning information comprises nominal tuning information for a reference channel, said first increment tuning information represents the change in nominal tuning information between said reference channel and the next adjacent channel and said second increment tuning information represents the change in said first increment tuning information between adjacent channels;
said accumulator means algebraically adding second increments of tuning information to said first increment of tuning information and to said reference tuning information to derive the nominal tuning information for the selected channel.
3. A television tuning system as set forth in claim 2 wherein the reference channel tuning information is for a channel at one extremity of the frequency band and the first increment tuning information is for an adjacent channel. 4. A television tuning system as set forth in claim 3 wherein the reference channel tuning information and the first increment tuning information correspond to a pseudo channel 6 MHz below the lowest numbered channel in said band, and wherein said accumulator means add second increment tuning information to the pseudo channel tuning informations to derive the nominal tuning information for the selected channel. 5. A television tuning system as set forth in claim 3 further including a source of secondary tuning information;
said accumulator means adding said first and said second increment tuning information to derive a last increment of tuning information;
means proportioning said secondary tuning information by said last increment of tuning information; and
means combining said derived nominal tuning information for the selected channel with the proportioned secondary tuning information.
6. The method of operating a television tuning system including a tuner having a nonlinear tuning voltage-versus-frequency characteristic and a channel-number-accessible memory for storing tuning information, comprising the steps of:
storing in said memory reference tuning information, first increment tuning information related to the slope of said characteristic at a base channel and second increment tuning information related to the slope of the slope of said characteristic at successive channel positions;
reading out the reference and first increment tuning informations and the second increments of tuning informations for a selected channel;
computing the nominal tuning information for the selected channel from the read-out tuning informations; and
producing a tuning voltage therefrom for said tuner.

7. The method of claim 6 wherein said reference tuning information comprises nominal tuning information for a pseudo channel, said first increment tuning information is representative of the change in nominal tuning information between said pseudo tuning information and said base channel and said second increment tuning information is representative of the change in first increment tuning information between successive channels;
said computing step including the step of:
algebraically summing second increment tuning information with said first increment tuning information and the reference channel tuning information to derive nominal tuning information for the selected channel.
8. The method of claim 7 wherein the pseudo channel is located below the lowest numbered channel in the band and wherein said summing step includes the further step of:
adding the second increment tuning informations of successive higher channels to the first increment tuning information and the nominal tuning information of said pseudo channel.
9. The method of claim 8 further including the steps of:
proportioning a source of secondary tuning information with the summation of the first increment tuning information and the second increment tuning informations corresponding to the selected channel; and
combining the derived nominal tuning information for the selected channel with the proportioned secondary tuning information for producing the tuning voltage for said tuner.
10. The method of operating a television tuning system including a tuner having a nonlinear tuning voltage-versus-frequency characteristic and a channel-number-accessible memory for storing tuning information comprising the steps of:
storing in said memory
(a) nominal tuning information and first increment tuning information for a pseudo channel;
(b) second increment tuning information for each channel corresponding to the change in first increment tuning information between successive channels including the pseudo channel, said pseudo channel corresponding to a frequency 6 MHz below the lowest numbered channel in the frequency band;
interrogating said memory for a desired channel to read out the pseudo channel tuning informations and one or more of said second increment informations;
computing the nominal tuning voltage information for said desired channel from said pseudo channel information and said second increment information; and
producing a tuning voltage therefrom for said tuner.
11. The method of claim 10 further including accumulating means having arithmetic logic units and storage registers, and further comprising the steps of:
transferring to one of said storage registers said first increment tuning information and to another of said storage registers said reference tuning information; and
operating said arithmetic logic units to combine said first increment and said reference tuning informations with successive second increment tuning informations.
12. The method of claim 11 further including a channel number counter and a channel number latch, said method further comprising the steps of:
latching the desired channel number in the latch;
resetting the channel number counter and clearing the registers;
operating the channel number counter to count up to the number in the latch; and
interrogating said memory to read the appropriate tuning informations into the registers as the counter is stepped.
13. The method of claim 12 further including a viewer operated channel Up/Dn switch for controlling the counter and means displaying the channel number in the latch to the viewer, and further including the steps of:
automatically replacing the number in the latch with the new channel number in the counter at a given repetition rate in response to operation of the Up/Dn switch; and
repeating said interrogating and computing steps for each new channel number, said latter steps taking significantly less time to perform than the period of said given repetition rate.
14. A television tuning system including a voltage-controlled tuner having a nonlinear voltage-versus-frequency characteristic and a memory having a plurality of accessible locations storing nominal tuning information for a reference channel, first increment tuning information representative of changes in nominal tuning information between said reference channel and the next adjacent channel and second increment tuning information representative of changes in first increment tuning information between successive pairs of adjacent channels;
a channel number counter for accessing said different memory locations in accordance with channel numbers;
a

ccumulator means coupled to said memory for developing nominal tuning information for a selected channel by combining said nominal tuning information for said reference channel and first increment information with second increment tuning informations between said reference channel and said selected channel; and
a tuning voltage generator coupled to said accumulator means for generating a tuning voltage for said tuner from said developed nominal tuning information.
15. A television tuning system as set forth in claim 14 wherein said reference channel is a pseudo channel selected at a point on said characteristic 6 MHz below the frequency corresponding to the lowest numbered channel in the band. 16. A television tuning system as set forth in claim 15 further including control logic means comprising a channel number latch;
a high speed clock;
state counter means driven by said clock for resetting said channel number counter after a channel number change has been stored in said latch and for operating said channel number counter until its count matches the number in said latch; and
comparator means disabling said state counter means when the channel number counter counts to the number in said latch.
17. A television tuning system as set forth in claim 16 wherein said accumulator means include arithmetic logic units and storage registers;
said arithmetic logic units either substituting information in said registers or adding information to previous information therein under control of said state counter means.
18. A television tuning system as set forth in claim 17 including means displaying the channel number in the latch and a viewer-operable Up/Dn switch for producing a channel change initiate signal for said control logic means;
said initiate signal comprising a pulse train of predetermined periodicity and changing the count in said channel number counter;
said state counter means being activated by said initiate signal for latching the new channel number, resetting said channel counter, driving said channel counter from its reset count to the count stored in the latch and disabling itself when the number in the channel counter matches the number in the latch.
19. A television tuning system as set forth in claim 18 wherein said state counter means cycles once for each count change in the channel counter, the maximum cycle time of the state counter means being less than the predetermined periodicity of said pulse train. 20. An all-channel television tuning system including a voltage controlled tuner having a nonlinear voltage-versus-frequency characteristic and a memory having a plurality of locations each accessible by a distinct channel number, said channels being numbered consecutively but lying in more than one distinct frequency band;
one or more of said locations in each distinct frequency band storing nominal tuning information for a reference channel in its associated band and first increment tuning information representative of changes in nominal tuning information between the associated reference channel and the next adjacent channel;
others of said locations in each band storing second increment tuning informations representative of changes in first increment tuning information between successive pairs of adjacent channels in each band;
a channel number counter;
accumulator means coupled to said memory for developing nominal tuning information for any selected channel by combining the nominal tuning information and first increment tuning information for its associated reference channel with second increment tuning information between the associated reference channel and the selected channel;
a tuning voltage generator coupled to the said accumulator means for generating a tuning voltage for said tuner from said developed nominal tuning information;
band decoder means determining the proper frequency band for each channel number; and
memory location translation means for allocating blocks of memory locations to said different frequency bands.

21. An all-channel television tuning system as set forth in claim 20 wherein said channel number counter generates a BCD tens digit and a BCD units digit corresponding to the respective digits of the selected channel number, said units digits being coupled directly to said memory and said tens digit being routed through said memory location translation means along with the output of said band decoder means. 22. An all-channel television tuning system as set forth in claim 21 wherein said reference channels comprise pseudo channels selected to be 6 MHz below the lowest channels in each band.

Description:

CROSS REFERENCE TO RELATED PATENT APPLICATION
This application is related to, but not dependent upon, the invention and apparatus disclosed in copending application Ser. No. 791,897 filed Apr. 28, 1977 and application Ser. No. 807,627 filed June 17, 1977, both in the name of Akio Tanaka and assigned to Zenith Radio Corporation.
FIELD OF THE INVENTION
This invention relates generally to digital tuning systems and in particular to all-electronic television receiver digital tuning systems having a memory for storing tuning information.
BACKGROUND OF THE INVENTION AND PRIOR ART
Varactor diode tuners have contributed to the simplification of tuning systems in general, and television receiver tuning systems in particular. In such tuners, which are often referred to as electronic tuners, the varactor diodes exhibit capacitance variations with changes in bias voltage and serve as the variable reactances in-otherwise-conventional tuned circuits. Such tuning systems are easy to tune, free from RF signal carrying contacts and afford the designer great versatility in receiver styling. As pointed out in the related applications, their most serious drawbacks are the limited range of diode capacitance change and the nonlinear relationship between frequency and bias voltage.
The invention in the first-mentioned related application (Ser. No. 791,897)--now U.S. Pat. No. 4,142,157--provides an attractive solution to these problems and the problems associated with implementation of the Federal Communications Commission so-called "equal tuning" rule for VHF and UHF television channels. In brief, that system produces a separate "slope factor" which is related to the slope of the tuning voltage-versus-frequency characteristic for proportioning the "fine" tuning voltage such that equal frequency excursions are experienced for equal tuning information increments. The result is a truly "equalized" tuning system. The slope factors are stored in appropriate channel-number-addressable memories as are the nominal (coarse) tuning informations and fine tuning informations. For each channel selection a nominal tuning voltage information, a fine tuning voltage information and a slope factor are produced. The fine tuning information is multiplied by the slope factor and combined with the nominal tuning information for conversion to the final tuning voltage.
The invention in the second-mentioned copending application Ser. No. 807,627 is concerned with memory utilization in digital tuning systems and the savings in memory which may be achieved by proper utilization of the slope factor. The structure of that invention accomplishes significant memory reduction by storing initial value tuning information for a pseudo channel in each frequency band and separate tuning increment information, representing the tuning voltage changes required to successively tune from one channel to the next, beginning with the pseudo channel. (These increments are the difference equation analog of the slope factors defined in the application Ser. No. 791,897--now U.S. Pat. No. 4,142,157--). Upon occurrence of a channel change, an arithmetic computation is performed in which the initial value information and successive increment informations are added. The initial value tuning information is selected at a point 6 MHz below the lowest numbered channel in the band which point is then referred to as the pseudo channel number. Thus, in the low VHF band, for instance, rather than storing complete information words corresponding to the nominal tuning information for channels 2-4, the nominal tuning information for pseudo channel 1 is stored along with the slope factors or increments required to go from pseudo channel 1 to real channel 2, from channel 2 to channel 3, and from channel 3 to channel 4. Suitable logic and apparatus are provided for summing the pseudo channel information and successive increments for obtaining the nominal tuning information corresponding to the selected channel number.
Since the last increment represents the slope factor of the tuning curve at the selected channel, and since this slope information is separately available, it is readily usable for equalization of any auxiliary tuning voltage source to provide true equalized tuning for the system. In the offset fine tuning system disclosed, one-half of the fine tune information, after equalization, is added to the derived nominal tuning information to produce the final tuning information for the selected channel.
There is no art known to the inventor which is relevant to the invention described and claimed; that is a system which "computes" a tuning voltage by algebraic summation of nominal tuning information for a reference channel and increment tuning information representative of tuning differences between channels.
The present invention represents a further improvement in memory utilization over that obtainable in the system of the Ser. No. 807,627 application. In essence, only the differences in increment tuning information from channel to channel are stored in the memory. Effectively these difference increments result from taking the "slope of the slope" of the tuning characteristic at each channel tuning position, and may be conveniently referred to as a second derivative system. Thus rather than storing a tuning information increment equivalent to a one volt tuning change for example, only the tuning increment change for that channel, which may amount to only a tenth of a volt, is stored and thus a substantial further savings in memory is obtainable. The nominal tuning information for the selected channel is derived by summing the nominal tuning information for the pseudo channel and first increment tuning information in that band with the appropriate number of successive second increment tuning informations. The first and second increment tuning informations are added to produce a last tuning increment for the selected channel, which is the slope factor, and which may be conveniently used to produce equalized tuning as disclosed in the Ser. No. 791,897 application.
OBJECTS OF THE INVENTION
The principal object of this invention is to provide a novel television tuning system.
Another object of this invention is to provide a television tuning system requiring less memory.
SUMMARY OF THE INVENTION
In accordance with the invention a television receiver includes a voltage controlled tuner having a nonlinear tuning voltage-versus-frequency characteristic, tuning voltage means for generating a tuning voltage for the tuner and memory means storing reference tuning information, first increment tuning information related to the slope of the characteristic at a base channel and second increment tuning information related to the slope of the slope of the tuning characteristic at each channel position. The memory means supply the tuning informations to accumulator means which generate therefrom the nominal tuning information and slope factor for the selected channel.