PHILIPS 22CS1263 CANALETTO CHASSIS K30 UNITS VIEW.

Detailed view Modules (units)

Mains rectifier 8222 280 2097.3

Supply control With TDA2581q (PHILIPS) 8222 280 2089.6

IF DEM Unit with TDA2540q (PHILIPS) 3122 128 80281 8222 280 2109.4

Synch with TDA2571AQ (PHILIPS) 8222 280 2105.4

Lum + Chrom with TDA 2525Q AND TDA2560/3Q + Delay Line DL 700. 8222 280 2093.3

RGB OUTPUT 8222 280 2101.4

SOUND With TBA120AS 8222 280 2082.6

TBA120T (Siemens) SIF (S



PHILIPS 20C939 Chassis KT30 detailed view.

Supply + line + EHT Stages

Focus + G2 + E/W Correction - FRAME Deflection.

Signal Stages (Chroma + Luma + Sound + RGB + Synch + IF + RF Tuner)


Line deflection output transistor (BU208A)




TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).

The left positioned board contains all search tuning functions and it's based on a complex ASIC Ic called SONG IC which is followed by a vertical little unit in the near of it which contains the two SONG II ICS which also are the tuning memory supplyied by a NiCd battery.

The board contains even additional complex funcions realized via discrete components such analog functions - stby startup via remote - automatic search.

TDA2581 CONTROL CIRCUIT FOR SMPS
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed

-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.

BU208(A)

Silicon NPN
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.

DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.

APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.

ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C


The TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.

APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.

Video signal processing circuit for a color television receiver  PHILIPS TDA3560: In a video signal processing circuit for a color television receiver, a brightness setting, which is operative for external color signals as well as for internal color signals and which does not produce a color shift, can be obtained by combining with the luminance signal (Y) a level shift signal (H) the amplitude of which is adjustable by the brightness setting and by employing in each color channel two clamping circuits, the first one of which clamps a first reference level (RL₁) in the external color signal (ER, EG, EB) onto a combination of the level shift signal and the internal color signal (R, G, B) and the second clamping circuit clamps a second reference leve (RL₂) which occurs in the sum signal of the internal and the external color signal when the level shift signal has zero value, onto the cutoff level of the relevant electron gun of a picture display tube.
1. A video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals and for external color signals, comprising respective matrix circuits for combining the respective color difference signals with the luminance signal to form respective color signals, respective first clamping circuits for clamping the respective external color signals onto the respective color signals, respective combining circuits for combining the respective clamped external color signals with the respective color signals, respective second clamping circuits for clamping the outputs of the respective combining circuits onto a predetermined level, and a brightness setting circuit, characterized in that the first clamping circuits act on a first reference level in said respective external color signals occurring in a first group of periods and the second clamping circuits act on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal, which is combined with the luminance signal prior to processing the color difference signals, with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.

2. A video signal processing circuit as claimed in claim 1, characterized in that the respective first and second clamping circuits are operative alternately and every other line flyback period.

Description:

BACKGROUND OF THE INVENTION
The invention relates to a video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals, and for external color signals, comprising a matrix circuit for combining a color difference signal with the luminance signal to form a color signal, a first clamping circuit for clamping an external color signal onto the corresponding color signal, a combining circuit for combining a clamped external color signal with the corresponding color signal, a second clamping circuit acting on an output signal of the combining circuit and a brightness setting circuit.
A video signal processing circuit of the type defined above is described in Philip Data Handbook for Integrated Circuits, Part 2, May, 1980 as IC TDA3560. The brightness setting, which is common for internal and external video signals, is obtained by means of a common direct current level setting of the second clamping circuits. The settings of the three electron guns of a picture display tube coupled to the outputs of the video signal processing circuit are changed to an equal extent by this direct current level setting as a result whereof, due to the mutual differences in the efficiency of the phosphors of the picture display tube, a color shift may occur at a brightness adjustment. It is an object of the invention to prevent this.
SUMMARY OF THE INVENTION
According to the invention, a video signal processing circuit of the type defined in the preamble is therefore characterized in that the first clamping circuit acts on a first reference level occurring in a first group of periods and the second clamping circuit acts on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
Owing to the measure in accordance with the invention, the common setting of the brightness for internal video signals is maintained and a color shift is prevented from occurring at a brightness setting.
DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be further described by way of example with reference to the accompanying drawings.
In the drawings:
FIG. 1 illustrates, by means of a block schematic circuit diagram, a video signal processing circuit in accordance with the invention; and
FIG. 2 shows some waveforms such as they may occur in the circuit shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1, an external red color signal ER' is applied to an input 1, a red color difference signal (R-Y) to an input 3, an external green color signal EG' to an input 5, a luminance signal Y to an input 7, a green color difference signal (G-Y) to an input 9, an external blue color signal EB' to an input 11, a blue color difference signal (B-Y) to an input 13 and a synchronizing signal S to an input 15.
The luminance signal at the input 7 is shown in FIG. 2 as a waveform 207. In the line flyback periods this luminance signal has a black level Z which, for simplicity, is assumed to occur in all cases during the whole line flyback period but which may, of course, alternatively occur during only a portion of that line flyback period.
The luminance signal Y is applied to an input 17 of a combining circuit 19. To a further input 21 thereof, a level shift signal H is applied which, via an amplitude setting circuit 23, is obtained from an output 25 of a pulse generator 27, to an input 29 of which the synchronizing signal S is applied.
The level shift signal H is shown in FIG. 2 as a waveform 221 which in this case has a zero amplitude every other line flyback period and at other times an amplitude which depends on the setting of the amplitude setting circuit 23.
The respective color difference signals (R-Y), (G-Y) and (B-Y) at the respective inputs 3, 9 and 13, are applied to inputs 31, 33 and 35, respectively, of matrix circuits 37, 39 and 41, respectively, to respective inputs 43, 45 and 47 of which the combination Y+H of the luminance signal (Y) and the level shift signal (H) is applied, and from respective outputs 49, 51 and 53, the red (R) and green (G) and blue (B) color signals are obtained. FIG. 2 shows the red color signal of said color signals as a waveform 249.
The respective external color signals ER', EG' and EB' at the respective inputs 1, 5 and 11 are applied to respective inputs 61, 63 and 65 of respective combining circuits 67, 69 and 71 via respective capacitors 55, 57 and 59. Further inputs 73, 75 and 77, respectively, of the combining circuits 67, 69 and 71, respectively, are connected to the outputs 49, 51 and 53, respectively, of the matrix circuits 37, 39 and 41, respectively, and receive the red, green and blue color signals, respectively.
Arranged between the inputs 61 and 73, 63 and 75, and 65 and 77, respectively, there are first clamping circuits 79, 81 and 83, respectively, which, under the control of a pulse signal K₁ coming from an output 84 of the pulse generator 27, clamps a first reference level RL₁ in the respective external color signals ER', EG' and EB' onto the respective color signals R, G and B, as a result of which the respective clamped external color signals ER, EG and EB at the respective inputs 61, 63 and 65 of the combining circuits 67, 69 and 71 are produced, the signal level ER at the input 61 of the combining circuit 67 being shown in FIG. 2 as the waveform 261. The pulse signal K1 is shown in FIG. 2 as the waveform 284.
At respective outputs 85, 87 and 89 of the combining circuits 67, 69 and 71, respectively, there are now produced signals which are the sums of the respective clamped external color signals ER, EG and EB and the respective color signals R, G and B. Via respective capacitors 91, 93 and 95, said sum signals (ER+R), (EG+G) and (EB+B), respectively, are applied to respective inputs 97, 99 and 100 of respective video output amplifiers 102, 104 and 106, respective outputs 108, 110 and 112 of which being connected to respective cathodes of a picture display tube 114.
Second clamping circuits 116, 118 and 120, respectively, which are rendered operative by a pulse signal K2 coming from an output 122 of the pulse generator 27 and whereby a second reference level RL2 in the signals at the respective inputs 97, 99 and 100 is adjusted to a fixed potential, zero potential here, are connected to the respective inputs 97, 99 and 100 of the respective video output amplifiers 102, 104 and 106. This is shown in FIG. 2 by means of the waveform 297 for the signal (ER+R) at the input 97 of the video output amplifier 102. For the sake of clearness, the luminance signal (Y) and the red color difference signal (R-Y) are assumed to have zero values.
The picture display tube 114 has a deflection circuit 124 which is controlled by signals coming from outputs 126 and 128, respectively, of the pulse generator 27.
On the basis of FIG. 2, it will now be demonstrated that the brightness of the color signals as well as of the external color signals is adjustable by means of the amplitude setting circuit 23, more specifically in such a ratio, occurring at the picture display tube 114, that no color shift is produced.
If a luminance signal Y and a color difference signal (R-Y) are produced and the external color signal ER' has zero value, the signal at the output 49 of the matrix circuit 37 has the waveform 249 and likewise the signal at the input 97 of the video output amplifier 108, as during the occurrence of the signal K2 (waveform 222), the second clamping circuit 116 has adjusted the second reference level RL₂ to zero, which corresponds to the cutoff level of the relevant cathode of the picture display tube 114. Outside the periods in which signal is clamped to the second reference level RL₂, the black level, shown in the waveform 249 by means of a dashed line, of the color signal at the input 97 of the video amplifier is determined by the amplitude of the level shift signal H, which, in response to the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube, are applied in the relevant signal paths to the cathodes of the picture display tube 114 to said cathodes in such an amplitude ratio that no color shift can be produced.
If there is an external color signal but no luminance and color difference signals (Y=O, R-Y=O, G-Y=O, B-Y=O), then a signal is produced at the input 97 of the video output amplifier 102 which has the waveform 297 and which, during the occurrence of the second reference level RL₂, is clamped onto zero by the second clamping circuit 116 by means of the clamping pulses K2 and which consequently corresponds to the cutoff level of the relevant cathode of the picture display tube 114. During the occurrence of the first reference level RL₁ in the signal ER', the first clamping circuit 79 clamps the signal ER (waveform 261) at the input 61 of the combining circit 61 onto the output signal of the matrix circuit 37 during the occurrence of the clamping pulses K1 (waveform 284). Now this output signal has the waveform 221, as R-Y and Y have zero values. From the waveform 297, it now appears that the signal ER+R, which in this case is equal to ER+H, has, outside the periods in which the second reference level RL₂ occurs in the waveform 297, a black level which is indicated by means of a dashed line and is determined by the amplitude of the level shift signal H. Also now this amplitude is applied in the proper ratio to the cathodes of the picture display tube 114 by the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube 114, so that no color shift can be produced.
It will be obvious that it is not imperative that the clamping pulses K1 and K2 be produced alternately and every other line flyback period. If so desired, the clamping pulses K1 may, for example, occur in a number of line trace periods of the field trace which are located outside the visible picture plane, and the clamping pulses K2 may occur in the line flyback periods. The clamping pulses K2 must be produced in the period in which the level shift signal causes the second reference level RL₂ and the clamping pulses K1 outside said periods and in the periods the first level reference level RL₁ occurs.
In the above-described embodiment the clamping circuits are provided in the form of short-circuiting switches which are arranged subsequent to capacitors which have for their function to block direct current signals. It will be obvious, that, if so desired, clamping circuits in the form of control circuits may alternatively be used and that in that event, if so desired, blocking the direct current component by a capacitor may be omitted.
If so desired, instead of an adder circuit 19, an insertion circuit may be employed by means of which, in the appropriate periods of the luminance signal, when the signal K2 is produced the reference level Z then present, is replaced by a new level which is influencable by the brightness setting .

You can see the complexity of the tellye even only from the wiring around it.