TELEFUNKEN PALCOLOR HIFI 292 PIP "MILLENNIUM" CHASSIS 618 A-2 PIP (ICC5341) THOMSON ICC5 Color television standard identification circuit:
A PAL-NTSC color television standard identification circuit, comprising a first demodulation circuit (7) for a reference component and a second demodulation circuit (11) for a possible color identification component of a color synchronizing signal, can perform a reliable identification by means of a digital decoding circuit (81) for the output signals of the demodulation circuits if the second demodulation circuit (11) is adapted (41, 45, 49) to demodulate along an axis slightly differing from the axis of the color identification component (FIG. 1).
1. A color television standard identification circuit for distinguishing at least a PAL and an NTSC color television signal, said identification circuit comprising a first demodulation circuit for demodulating a reference component (R) of a color synchronizing signal occurring in both PAL and NTSC, a second demodulation circuit for demodulating a color identification component of the color synchronizing signal occurring only in PAL, and a decoding circuit having an input coupled to respective outputs of said first and second demodulation circuits for determining whether the color synchronizing signal is a PAL or an NTSC color synchronizing signal, wherein said identification circuit further comprises a sign determination circuit coupled between the outputs of said first and second demodulation circuits and the input of said decoding circuit, said sign determination circuit comprising a comparison circuit having a comparison level, at which the level of an output signal of said comparison circuit changes, which is substantially equal to a reference level of said first and second demodulation circuits, and a sampling circuit having a input coupled to an output of said comparison circuit, an input of said sign determination circuit being coupled to an input of said comparison circuit and an output of said sign determination circuit being coupled to an output of said sampling circuit, wherein said second demodulation circuit is arranged to demodulate the color synchronizing signal at an axis slightly differing from the axis of the color identification component, whereby said sign determination circuit may accurately determine the correct sign of the output signal from said second demodulation circuit during demodulation of an NTSC color synchronizing signal by said second demodulation circuit. . 2. A color television standard identification circuit as claimed in claim 1, wherein said first demodulation circuit comprises a first synchronous demodulator having an input and an output coupled, respectively, to an input and the output of said first demodulation circuit; and said second demodulation circuit comprises a second synchronous demodulator having an input coupled to an input of said second demodulation circuit, and an adder circuit having a first input coupled to the output of said first synchronous demodulator and a second input coupled to an output of said second synchronous demodulator, an output of said adder circuit being coupled to the output of said second demodulation circuit, and wherein said identification circuit further comprises an oscillator for supplying reference signals to reference signal inputs of said first and second synchronous demodulators, said oscillator having a control input coupled to the output of said second synchronous demodulator thereby forming a phase-locked loop for controlling the phase of said oscillator. 3. A color television standard identification circuit as claimed in claim 1 or 2, wherein a change-over switch is coupled between the input of said sign determination circuit and the outputs of said first and second demodulation circuits, respectively, said change-over switch having a switching signal input coupled to an output of said decoding circuit.
A color television standard identification circuit of the type described above is known from IEEE Transactions on Consumer Electronics, Vol. CE 31, No. 3, August 1985, pp. 147-155. The greater part of this circuit is incorporated in an integrated circuit to which two capacitors performing a memory function in the decoding circuit must be connected.
It is an object of the invention to obviate as much as possible the use of capacitors to be connected externally.
According to the invention, a color television standard identification circuit of the type described in the opening paragraph is therefore characterized in that a sign determination circuit is arranged between an output of the demodulation circuits and an input of the decoding circuit, said sign determination circuit comprising a comparison circuit whose sign reversal level is substantially equal to the rest level of the demodulation circuits and further comprising a sampling circuit, the second demodulation circuit being adapted to demodulate the color synchronizing signal at an axis slightly differing from the axis of the color identification component in such a way that the sign determination circuit cannot determine an incorrect sign during demodulation of an NTSC color synchronizing signal.
It is to be noted that the use of a sign determination circuit with a comparison circuit and a sampling circuit for obtaining a decoding circuit no longer requiring capacitors is known from French Patent Application FR-A 2,575,353 for identifying a color difference signal associated with a given line period in a SECAM receiver.
It has been found that it is insufficient to incorporate a sign determination circuit, for example, after the demodulation circuits of a color television standard identification circuit.
To obtain a reliable standard identification, it is necessary that the second demodulation circuit supplies a signal from which the sign determination circuit can obtain such a signal that the decoding circuit can make a distinction between noise and the presence of an NTSC color synchronizing signal.
If the second demodulation circuit had a demodulation axis which would completely coincide with the phase of the PAL color identification component, it would supply an output signal which would be equal to the rest level of the second demodulation circuit in the case of demodulation of an NTSC color synchronizing signal. With a slight internal shift of its comparison level, its own noise could then cause the sign determination circuit to supply a signal which would not correspond to the sign desired for the rest level of the second demodulation circuit. This is prevented by slightly modifying the demodulation axis of the second demodulation circuit.
The invention will now be described in greater detail, by way of example, with reference to the accompanying drawing in which
FIG. 1 is a block diagram of a color television standard identification circuit according to the invention,
FIG. 2 is a phasor diagram of the demodulation of the components of a PAL color synchronizing signal by means of a circuit according to FIG. 1, and
FIG. 3 is a phasor diagram of the demodulation of the components of an NTSC color synchronizing signal by means of a circuit according to FIG. 1.
In FIG. 1 a chrominance signal is applied to an input 1, from which signal a gating circuit 3 selects the color synchronizing signal and passes it on to an input 5 of a first demodulation circuit 7 and to an input 9 of a second demodulation circuit 11.
The first demodulation circuit 7 is a first synchronous demodulator which receives a reference signal at a reference signal input 13 from an output 15 of a 90° phase-shifting network 17, which reference signal has a phase which is 90° shifted with respect to the phase of a reference signal occurring at an input 19 thereof and originating from an output 21 of an oscillator 23.
The input 9 of the second demodulation circuit 11 is also an input of a second synchronous demodulator 25, a reference signal input 27 of which is connected to the output 21 of the oscillator 23 and an output 29 of which applies, via a low-pass filter 31, a control signal to a control signal input 33 of the oscillator 23.
The oscillator 23, the second synchronous demodulator 25 and the low-pass filter 31 constitute a phase-locked loop controlling the phase of the reference signal at the reference signal input 27 of the second synchronous demodulator 25 in such a way that it differs ninety degrees from that of the reference component of the color synchronizing signal. As a result, the demodulated color identification component of the color synchronizing signal occurs at the output 29 of the second synchronous demodulator 25 in the case of synchronous demodulation of a PAL color synchronizing signal, whilst the phase-locked loop will control said output 29 substantially at its rest level in the case of synchronous demodulation of an NTSC color synchronizing signal.
The demodulation axis of the second synchronous demodulator 25 is the ninety-degree axis in FIGS. 2 and 3, and the demodulation axis of the first synchronous demodulator 7 is the zero axis. The reference component of the color synchronizing signal is denoted by R in the two Figures and has a phase of one hundred and eighty degrees. The PAL color synchronizing signal is denoted by B and B' in FIG. 2, dependent on the line period in which it occurs.
In FIG. 1 an output 35 of the first synchronous demodulator 7 applies the demodulated reference component R of the color synchronizing signal, which has a negative polarity, to an input 37 of a change-over switch 39 and via an attenuator 41 to an input 43 of an adder circuit 45, an output 47 of which is also the output of the second demodulation circuit 11.
The output 29 of the second synchronous demodulator 25 applies the demodulated color identification component via a further attenuator 49 to a further input 51 of the adder circuit 45. The output 47 of the second demodulation circuit 11 now applies a demodulated color synchronizing signal to a further input 53 of the change-over switch 39, which signal is demodulated in accordance with an axis which is denoted by D in FIGS. 2 and 3 and which differs slightly from the ninety-degree axis. This difference is determined by the ratio of the attenuations of the attenuators 41 and 49.
FIGS. 2 and 3 show that in the case of PAL a slightly asymmetrical demodulation of the color identification component is effected with an amplitude A in the one line period and an amplitude A' in the next period, whilst in the case of NTSC a small negative amplitude C is demodulated by the second demodulation circuit 11.
In FIG. 1 an output 55 of the change-over switch 39 is connected to an input 57 of a sign determination circuit 59 via a low-pass filter 56 having an integration time of approximately half a microsecond. The input 57 is also an input of a comparison circuit 61, a reference level input 63 of which receives the rest level of the first and the second demodulation circuits 7, 11, which is symbolically indicated by a connection between this input 63 and a rest level output 65, 67 of the first and the second synchronous demodulator 7, 25, respectively.
An output 69 of the comparison circuit 61 is connected to a D input 71 of a D flip-flop 73 operating as a sampling circuit, a clock signal input 75 of which receives a pulse each time at the end of the occurrence of a color synchronizing signal. As a result, a logic value of one is obtained at an output 77 of the D flip-flop 73, which output is also the output of the sign determination circuit 59, if the signal at the input 57 of the sign determination circuit 59 was positive with respect to the reference level at the reference level input 63 of the comparison circuit 61, and a logic value of zero if the signal at the input 57 was negative with respect to this reference level.
The output 77 of the sign determination circuit 59 applies this logic one or logic zero signal to an input 79 of a decoding circuit 81 which supplies at an output 83 a switching signal of half the line frequency and the correct phase for switching the demodulation axis of a (R-Y) demodulator when a PAL signal is received, at an output combination 85 a signal combination which can bring a color television receiver comprising the color identification circuit to a PAL or NTSC receiving state, and at an output 87 a switching signal which can cause the change-over switch 39 to successively take up its two positions in a given receiving state of the receiver and which to this end is applied to a switching signal input 89 of the change-over switch 39.
The decoding circuit 81 compares the pattern of logic levels at its input 79 with a pattern to be expected in a given receiving state and a given state of the change-over switch 39, and with reference to the number of differences per period of time, for example, per field period it determines whether the receiving state of the receiver is the desired state, or whether no color information is received. This is effected by means of a counter which may be in the form of, for example a pseudo-random counter in order to obtain a small number of components.
The demodulation axis D, which is different from ninety degrees, of the second demodulation circuit 11 can now give a clear distinction between the pattern of logic levels occurring at the output 77 of the sign determination circuit due to a noise signal or due to an NTSC color synchronizing signal which occurs at the input 9 of the second demodulation circuit 11 when the change-over switch 39 is in the state not shown.
In the presence of an NTSC color synchronizing signal the negative amplitude C of the demodulated color synchronizing signal will cause the input 57 to be negative during the occurrence of the signal with respect to the rest level at the rest level input 63 so that the output 77 of the sign determination circuit always remains logic zero. In the presence of a noise signal, thus in the absence of a color synchronizing signal, the output 77 will, at an average, assume a logic zero level approximately as frequently as a logic one level.
If the demodulation axis of the second demodulation circuit 11 had been at ninety degrees, no distinction could be made because the own noise of the comparison circuit 61 could then cause the same logic signal pattern at the input 79 of the decoding circuit 81 in the presence of a noise signal as well as in the presence of an NTSC color synchronizing signal at the input 9 of the second demodulation circuit 11.
As can be seen in FIG. 2, a small difference from ninety degrees will cause a small asymmetry in a demodulated color identification component, which does not, however, introduce any change in the logic signal pattern at the input 79 of the decoding circuit 81.
If desired, the circuit may be extended by a section for identification of a SECAM color television signal, for example, by applying a frequency-demodulated SECAM color synchronizing signal to a third input of the change-over switch 39.
Capacitors are no longer required for the identification function, because this identification is now carried out in a digital signal processing section.
Instead of combining the output signals of the first and the second synchronous demodulator by means of the adder circuit 45, a third synchronous demodulator whose reference signal would have the desired phase D could be used in the second demodulation circuit 11.
The first and the second synchronous demodulators 7, 25 may also be used as color difference signal demodulators if the gating circuit 3 is omitted and if the demodulated color synchronizing signals are obtained from the output signals of the synchronous demodulators by means of gating circuits.
If desired, a sign determination circuit may be incorporated after each demodulation circuit and the change-over switch 39 may be omitted if the decoding circuit 81 is adapted to simultaneously process the output signals of the sign determination circuits.
Instead of using attenuators 41 and 49, the demodulators 7 and 25 may be formed in such a manner, for example, by choosing a certain ratio of currents supplied by current sources of multipliers in the form of synchronous demodulators, that the adder circuit 45 receives the correct amplitude ratio in the non-shown state of the change-over switch 39.
TDA4556 Multistandard decoder
The TDA4555 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
· Gain controlled chrominance amplifier for PAL, SECAM
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
· Two identification circuits for PAL/SECAM (H/2) and
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.
TELEFUNKEN PALCOLOR HIFI 292 PIP "MILLENNIUM" CHASSIS 618 A-2 PIP (ICC5341) U4647 - TEA5040 (TELEFUNKEN) WIDE BAND VIDEO PROCESSOR
The U4647 - TEA5040S is a serial bus-controlled videoprocessing
device which integrates a complex architecture
fulfilling multiple functions.
.DIGITAL CONTROL OF BRIGHTNESS,
SATURATION AND CONTRAST ON TV SIGNALS
AND R, G, B INTERNAL OR EXTERNAL
SOURCES .BUS DRIVE OF SWITCHING FUNCTIONS .DEMATRIXING OF R, G, B SIGNALS FROM
Y, R-Y, B-Y, TV MODE INPUTS .MATRIXING OF R, G, B SOURCES INTO
Y, R-Y, B-Y SIGNALS .AUTOMATIC DRIVE AND CUT-OFF CONTROLS
BY DIGITAL PROCESSING DURING
FRAME RETRACE .PEAK ANDAVERAGE BEAM CURRENT LIMITATION
.ON-CHIP SWITCHING FOR R, G, B INPUT
SELECTION .ON-CHIP INSERTION OF INTERNAL OR EXTERNAL
R, G, B SOURCES
An automatic contrast control circuit in a color television receiver for stabilizing the average DC level of the luminance information at a desired level and preventing focus blooming. The control circuitry, which is suitable for fabrication as a monolithic integrated circuit, contemplates the provision of a gain-controlled luminance amplifier stage for driving an image reproducer with luminance information having a stabilized black level. An average detector coupled to the amplifier stage output develops a control signal representative of the average DC level of the luminance information and applies it to the amplifier stage, varying its gain inversely with changes in the average luminance level. A peak limiter circuit is also provided for modifying the control signal to reduce the amplifier stage's gain whenever an AC brightness component comprising the luminance information exceeds a defined threshold level, regardless of the average DC level of the luminance information.
1. In a television receiver having a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer, said luminance signals including black level reference information, an automatic contrast control circuit comprising in combination:
2. An automatic contrast control circuit in accordance with claim 1, wherein adjustable level shifting means are interposed between said amplifier stage and said average detector means, said adjustable level shifting means providing a contrast control for manually varying the average DC level of said luminance signals.
3. An automatic contrast control circuit in accordance with claim 1, wherein said average detector means includes a capacitor having an output terminal coupled to said amplifier stage and a second terminal coupled to a plane of reference potential, said capacitor being charged by luminance signals from said amplifier stage and developing control signals representative of the average DC level of said luminance signals.
4. An automatic contrast control circuit in accordance with claim 3, wherein said control signals with respect to a plane of reference potential are equal to the potential at which black level is stabilized minus the potential drop between black level and the average DC level of said luminance information, said control signal increasing with respect to said plane of reference potential responsive to decreasing average DC levels of said luminance signals and decreasing responsive to increasing average DC levels.
5. An automatic contrast control circuit in accordance with claim 3, wherein said peak detector means includes a semi-conductor arrangement for providing said capacitor with a low impedance discharge path whenever said brightness components exceed a predetermined threshold level, the impedance of said discharge path being dependent on the amplitude of said brightness components and the discharge interval of said semiconductor arrangement being the time period during which said brightness components exceed said threshold level, said semiconductor arrangement further decreasing said control signals with respect to said plane of reference potential irrespective of the average DC level of said luminance signals.
6. An automatic contrast control circuit in accordance with claim 5, wherein said semiconductor arrangement comprises first and second transistors, said luminance signals from said amplifier stage being coupled to the input base electrode of said first transistor, said first transistor further having an emitter electrode coupled to said capacitor output terminal and a collector electrode coupled to the base electrode of said second transistor, said second transistor having a collector electrode coupled to said capacitor output terminal and an emitter electrode coupled to said plane of reference potential, said semiconductor arrangement being conductive to provide said capacitor with a low impedance discharge path whenever said brightness components exceed the base-emitter junction breakdown voltage of said first transistor.
7. An automatic contrast control circuit in accordance with claim 6, wherein said gain-controlled luminance amplifier stage includes a pair of transistors arranged in a differential amplifier configuration, the gain of which is dependent on the bias applied to the base electrodes of said transistors.
8. An automatic contrast control circuit in accordance with claim 7, wherein inverter means invert and couple said control signals to said base electrodes in said amplifier stage, the inverted control signals increasing the gain of said amplifier stage whenever the average DC level of said luminance signals decreases and decreasing the gain of said amplifier stage whenever the average DC level of said luminance information increases or whenever said brightness components exceed said threshold level.
9. An automatic contrast control circuit in accordance with claim 3, wherein said beam current limiter means provide a low impedance discharge path for said capacitor whenever the beam current exceeds a predetermined level.
10. An automatic contrast control system in accordance with claim 9, wherein said beam current limiter means monitors pulses from a voltage multiplier high-voltage system, said pulses being proportional to the beam current generated during the previous horizontal scan line.
11. An automatic contrast control circuit in accordance with claim 10, wherein said beam current limiter means comprises a transistor having a base electrode coupled to said voltage multiplier high-voltage system, an emitter electrode coupled to a plane of reference potential and a collector electrode coupled to said capacitor, said transistor providing a low impedance discharge path whenever said pulses exceed the base-emitter junction breakdown voltage of said transistor.
This invention relates in general to control circuitry for color television receivers and more particularly to an automatic contrast control circuit incorporated in the luminance processing channel. In accordance therewith, a variable DC control signal is derived from the luminance signal information as a function of the average luminance level. The DC control signal is applied to a gain-controlled amplifier stage in the luminance channel, varying its gain and thereby insuring that excessive beam currents will not be generated due to high average luminance levels. Conversely, the circuit is effective to increase the gain of the amplifier stage when under-modulated signals are received thereby providing the desired contrast level. When the white content of the instantaneous received signal exceeds a predetermined level, however, the DC control signal is modified to reflect the excessive white content even though the average luminance level may be low. Accordingly, the amplifier stage's gain is reduced to prevent defocusing.
In color television receivers, the various elemental areas of differing brightness levels, or shades, in the televised image correspond to the amplitude levels of the instantaneous brightness components of the luminance signals which, together with the chrominance signal, reproduce the transmitted picture information on the image display tube. The intensity of the electron beams developed in the receiver's image display tube are varied, for the most part, according to the detected amplitude levels of the instantaneous luminance signals. Accordingly, progressively higher amplitude levels generate higher intensity electron beams and, consequently, progressively lighter shades. In addition, suitable viewer-adjustable controls are customarily provided in the television receiver whereby a particularized contrast and brightness setting may be selected according to viewer preference.
It is desirable that the level of the luminance signal component corresponding to black in the televised image be maintained at the cut-off of the image reproducer. But even in those instances where there is a measure of DC coupling, the DC components of the luminance signal coupled from the video detector to the luminance channel may be degraded or otherwise restricted due to the nature of the processing circuitry as well as to other factors. Moreover, the luminance processing channel itself may well permit a degradation or undesirable shift in the desired DC characteristics. The result is that the DC level in the processed luminance signal is not properly maintained, such that, upon application to the image display tube, the black level is shifted to some undesirable reference. This leads to less than faithful half-tone reproduction on the screen of the image display tube. Gray tones can be lost simply because they are beyond the cut-off of the display tube. In other instances, blacks may appear as grays on the image display tube screen.
Thus, it is desirable to make provision for the maintenance of black level in the televised image at some stabilized reference. Various systems are of course known in the art for accomplishing this objective and take various forms and configurations. For example, an arrangement commonly known as a DC restorer circuit which includes a clamping device may be employed. However, when the black level is effectively stabilized at the image reproducer's cut-off bias point, the average level of the luminance signal information may reach the point where excessive average beam currents capable of severely damaging the image reproducer are generated. In addition, the high voltage power supply during instances of high beam current may be incapable of delivering the required beam current. Such overloading reduces the power supply output voltage and results in undesirable "focus blooming." That is, there will be a loss of brightness, reduction of horizontal widths and severe defocusing of the reproduced image. The problem in this regard has been further compounded by the "new generation" high-brightness cathode-ray tubes which require higher beam currents in order to illuminate the tube to its fullest capability during high-modulation (white) scenes. In view of the added demands on the high voltage power supply and the danger of damaging the image display tube, some method for effectively limiting the beam current is required.
Accordingly, automatic contrast control systems have been developed which reduce the gain of the luminance amplifier stage to prevent the generation of excessive beam currents or increase the gain when under-modulated signals are received. Most of these prior art automatic contrast control systems, however, measure only the average level of the luminance signals to derive the control signal utilized to vary the gain of the luminance amplifier. Consequently, when all or a major portion of the luminance signal's white content is of a high amplitude level and is concentrated on a very small portion of the image reproducer's screen, the control signal derived from the average luminance level is low, permitting the luminance amplifier stage to operate at nearly maximum gain. By concentrating the high-amplitude white content into a small area of the screen, the image display tube is likely to be overdriven during that period of time and "focus blooming" will result. Some automatic contrast systems, on the other hand, derive a control signal based on the peak amplitudes of the instantaneous luminance signals without regard to the average luminance level. Thus, while preventing blooming on high-amplitude white content, such systems are susceptible to luminance signals which have a dangerously high average level, but do not have any peak white signal content of a level where the system would take corrective action.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the present invention to provide a color television receiver having black level stabilization with a new and improved automatic contrast control circuit which effectively overcomes the aforenoted disadvantages and deficiencies of prior circuits.
A further object of the invention is to provide an improved automatic contrast control circuit which develops control signals effectively varying the gain of a luminance amplifier stage to maintain an optimum contrast, while preventing the generation of excessive beam currents in the cathode-ray tube.
A more particular object of the invention is to provide an improved automatic contrast control circuit for continuously monitoring the average (DC) level of the luminance signal information and providing a control signal representative thereof to vary the gain of a luminance amplifier stage while remaining sensitive to the amplitude levels of brightness components exceeding a threshold level and modifying the control signal in accordance therewith.
Another object of the invention is to provide an improved automatic contrast control circuit which increases the gain of a luminance amplifier stage during reception of undermodulated luminance signals.
A further object of the present invention is to provide an automatic contrast control circuit of the foregoing type for deriving a variable DC control potential from applied luminance signals which, upon application to the luminance channel, adjusts the gain of a luminance amplifier stage in accordance with the varying luminance signal requirements.
Still another object of the invention is to provide a luminance processing channel including automatic contrast control circuitry which may be fabricated as a monolithic integrated circuit to provide an output luminance signal having stabilized black level and optimum contrast without producing excessive beam currents.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved automatic contrast control circuit is provided for varying the gain of an amplifier stage in the luminance processing channel of a color television receiver whenever the average DC level of the input luminance information varies from a desired level, or whenever the peak amplitudes of the AC brightness components of the luminance information exceed a predetermined threshhold level. In a preferred embodiment, the automatic contrast control circuit includes a gain-controlled luminance amplifier stage in a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer. The amplified luminance signals found at the output of the amplifier stage have a stabilized black level. There are also provided detector means coupled to the amplifier output for developing control signals that are representative of the average DC level of the instantaneous luminance signals. The control signals are then applied to the gain-controlled amplifier stage to vary its gain inversely with changes in the average luminance level. Finally, peak limiter means are coupled between the amplifier output and the detector means to modify the control signals whenever the instantaneous luminance signals exceed a threshhold level. The modified control signals are similarly utilized to effect inverse gain variations in the gain-controlled amplifier stage regardless of the average level of the luminance signals.
This integrated circuit incorporates the following
- a synchro and two video inputs
- a fixed video output
- a switchable video output
- normal Y, R-Y, B-Y TV mode inputs
- double set of R, G, B inputs
- brightness, contrast and saturation controls as
wellon aR,G, B picture ason a normalTVpicture
- digital control inputs by means of serial bus
- peak beam current limitation
- average beam current limitation
- automaticdrive and cut-off controls
Block Diagram Description
A 3 lines bus (clock, data, enable) delivered by the
microcontroller of the TV-set enters the videoprocessor
integrated circuit (pins 13-14-15). A control
system acts in such a way that only a 9-bit word is
taken intoaccount by the videoprocessor.Six of the
bits carry the data, the remaining three carry the
address of the subsystem.
A demultiplexer directs the data towards latches
which drive the appropriate control. More detailed
information about serial bus operation is given in
the following chapter.
The video switch has three inputs :
- an internal video input (pin 39),
- an external video input (pin 37),
- a synchro input (pin 41),
and two outputs :
- an internal video output (pin 40),
- a switchable video output (pin 42)
The 1Vpp composite video signal applied to the
internal video input is multiplied by two and then
appears as a 2Vpp low impedance composite
video signal at the output. This signal is used to
deliver a 1Vpp/75W composite video signal to the
The switchable video output canbe any of the three
inputs.When the Int/Ext one active bit word is high
(address number 5), the internal video input is
selected. If not, either a regeneratedsynchro pulse
or the external video signal is directed towards this
output depending on the level of the Sync/Async
one active bit word (address number 4). As this
output is to be connected to the synchro integrated
circuit, RGB information derived from an external
source via the Peri-TV plug canbedisplayed on the
screen, the synchronization of the TV-set being
then made with an external video signal.
When RGB information is derived from a source
integrated in the TV-set, a teletext decoder for
example, the synchronization can be made either
on the internal video input (in case of synchronous
data) or on the synchro input (in case of asynchronous
R, G, B Inputs
There are two sets of R, G, B inputs : one is to be
connected to the peri-TV plug (Ext R, G, B), the
second one to receive the information derived from
the TV-set itself (Int R, G, B).
In order to have a saturation control on a picture
coming from the R, G, B inputs too, it is necessary
to getR-Y, B-Y and Y signals from R, G, B information
: this is performed on the first matrix that
receives the three 0.9Vp (100% white) R, G, B
signals and delivers the corresponding Y, R-Y, B-Y
signals. These ones are multiplied by 1.4 in order
to make the R-Y and B-Y signals compatible with
the R-Y and B-Y TV mode inputs. The desired R,
G, B inputs are selected by means of 3 switches
controlled by the two fast blanking signal inputs. A
high level on FB external pin selects the external
RGB sources. The three selected inputs are
clamped in order to give the required DC level at
the output of this firstmatrix. Thethree not selected
inputs are clamped on a fixed DC level.
Y, R-Y, B-Y Inputs
The 2Vpp composite video signal appearing at the
switchable output of the video switch (pin 42) is
driven through the subcarrier trap and the luminance
delay line with a 6 dB attenuation to the Y
input (1Vpp ; pin 12). In order to make this 1Vpp
(synchro to white) Y signal compatible with the
1Vpp (black to white) Y signal delivered by the first
matrix, it is necessary to multiply it by a coefficient
The four brightness, contrastand saturationcontrol
functions are direct digitally controlled without using
The contrast control of the Y channel is obtained
by means of a digital potentiometer which is an
attenuator including several switchable cells directly
controlled by a 5 active bit word (address
number 1). The brightness control is also made by
a digital potentiometer (5 active bit word, address
number 0). Since a + 3dB contrast capability is
required, the Y signal value could be up to 0.7Vpp
nominal. For both functions, the control characteristics
In each R-Y and B-Y channel, a six-cell digital
attenuator is directly controlled by a 6 active bit
word (address number 6 and 7). The tracking
needed to keep the saturation constant when
changing the contrast has to be done externally by
the microcontroller. Furthermore, colour can be
disabledby blankingR-Y andB-Ysignals using one
active bit word (address number 2) to drive the
one-chip colour ON/OFF switch.
Second Matrix, Clamp, Peak Clipping, Blanking
The second matrix receives the Y, R-Y and B-Y
signals and delivers the corresponding R, G, B
signals. As it is required to have the capability of +
6dB saturation, an internal gain of 2 is applied on
both R-Y and B-Y signals.
A low clipping level is included in order to ensure a
correct blanking during the line and frame retraces.
Ahigh clipping level ensures thepeakbeamcurrent
limitation. These limitations are correct only if the
DC bias of the three R, G, B signals are precise
enough. Therefore a clamp has been added in
each channel in order to compensate for the inaccuracy
of the matrix.
Sandcastle Detector And Counter
The three level supersandcastle is used in the
circuit to deliver the burst pulse (CLP), the horizontal
pulse (HP), and the composite vertical and
horizontal blanking pulse (BLI). This last one is
regenerated in the counter which delivers a new
composite pulse (BL) in which the vertical part lasts
23 lines when the vertical part of the supersandcastle
lasts more than 11 lines.
The TEA5040S cannot work properly if this minimum
duration of 11 lines is not ensured.
The counterdelivers different pulses neededcircuit
and especially the line pulses 17 to 23 used in the
automatic drive and cut-off control system.
Automatic Drive And Cut-off Control System
Cut-off and drive adjustments are no longer required
with this integrated circuit as it has a sample
and hold feedback loop incorporating the final
stages of the TV-set. This system works in a sequentialmode.
For this purpose, special pulses are
inserted in G, R and B channels. During the lines
17, 18 and 19, a ”drive pulse” is inserted respectively
in the green, red and blue channels. The line
20 is blanked on the three channels. During the
lines 21, 22 and 23, a ”quasi cut-off pulse” is
inserted respectively in the green, red and blue
The resulting signal is then applied to the input of
a voltage controlled amplifier. In the final stages of
the TV-set, the current flowing in each green, red
and blue cathode is measured and sent to the
videoprocessorby a current source.
The three currents are added together in a resistor
matrix which can be programmed to set the ratio
between the three currents in order to get the
appropriate colour temperature. The output of the
matrix forms a high impedance voltage source
which is connectedto the integratedcircuit (pin 34).
Same measurement range between drive and cutoff
is achieved by internally grounding an external
low impedance resistor during lines 17, 18 and 19.
This is due to the fact that the drive currents are
about one hundred times higher than the cut-off
and leakage currents.
Each voltage appearing sequentially on the wire
pin 34 is then a function of specific cathode current
- When a current due to a drive pulse occurs, the
voltage appearing on the pin 34 is compared
within the IC with an internal reference, and the
result of the comparison charges or discharges
an external appropriate drive capacitor which
stores the value during the frame. This voltage is
applied to a voltage controlled amplifier and the
system works in such a waythat the pulse current
drive derived from the cathode is kept constant.
- During the line 20, the three guns of the picture
tube are blanked. The leakagecurrent flowing out
of the final stages is transformed into a voltage which is stored by an external leakage capacitor
to be used later as a reference for the cut-off
- When a current due to a cut-off pulse occurs, the
voltage appearing on the pin 34 is compared
within the ICto the voltagepresenton the leakage
memory. Anappropriate externalcapacitor is then
charged or discharged in such a way that the
difference between each measured current and
the leakage current is kept constant, and thus the
quasi cut-off current is kept constant.
AverageBeam Current Limitation
The total current of the three guns is integrated by
means of an internal resistor and an external capacitor
(pin 36) and thencompared with a programmable
voltage reference(pin 38). When 70% of the
maximum permitted beam current is reached, the
drive gain begins to be reduced ; to do so, the
amplitude of the inserted pulse is increased.
In order to keep enough contrast, the maximum
drive reduction is limited to 6dB. If it is not sufficient,
the brightness is suppressed.
SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL
This is a bi-directional 3-wire (ENABLE, CLOCK,
DATA) serial bus. The DATA line transmission is
bi-directional whereas ENABLE and CLOCK lines
are only microprocessor controlled. The ENABLE
and CLOCK lines are only driven by the microcomputer.
Colour transient improvement
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
· Two Y output signals; one of 180 ns less delay.
TDA8421 Hi-fi stereo audio processor;,I2C bus
The TDA8421 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel (CH1) and a headphone
channel (CH2), digital controlled via the I2C bus, for application in hi-fi audio and television sound.
· Input selector
· Mode selector
· Loudspeaker channel (CH1); with volume control, balance control and mute
· Headphone channel (CH2); with volume control, balance control and mute
· Pseudo stereo and spatial function
· Bass and treble control
· Electrostatic discharge protection diodes
The input to channel 1 (CH1) and channel 2 (CH2) is determined by the input selector. The selection is made from the
following AF input signals:
· IN1 L (pin 26); IN1 R (pin 28) or
· IN2 L (pin 1); IN2 R (pin 3)
Where IN1 is an internal input signal and IN2 an external input signal.
For each channel (CH1 and CH2) there is a mode selector which selects between stereo, sound A and sound B in the
event of bilingual transmission. Both mode selectors can be controlled independently.
Headphone channel (CH2)
Volume control and balance
The stages for volume control for CH2 consist of two parts
for left and right. In each part the gain can be adjusted
between 0 and -62 dB in steps of 2 dB. An additional step
allows an attenuation of ³ 90 dB. Both parts can be
controlled independently over the whole range, which
allows the balance to be varied by controlling the volume
of left and right.
Loudspeaker channel (CH1)
Volume control and balance
The loudspeaker channel (CH1) also consists of two parts
for volume control (left and right). In each part the gain
can be adjusted between + 16 dB and -62 dB in steps of
2 dB. An additional step allows an attenuation of ³ 90 dB.
Both parts can be controlled independently over the
whole range, which allows the balance to be varied by
controlling the volume of left and right.
Stereo/pseudo stereo/spatial stereo mode
It is possible to select three modes. Stereo, pseudo or
spatial stereo. The pseudo stereo mode receives mono
transmissions and the stereo and spatial stereo mode
receives stereo transmissions.
The bass control stage can be switched from an
emphasis of 15 dB to an attenuation of 12 dB for low
frequencies in steps of 3 dB.
The treble control stage can be switched from + 12 dB to
-12 dB in steps of 3 dB.
Bias and power supply
The TDA8421 includes a bias and power supply stage,
which generates a voltage of 1¤2 VCC with a low output
impedance and injector currents for the logic part.
The on-chip power-on reset circuit sets the mute bit to
active, which mutes both the loudspeaker channel (CH1)
and the headphone channel (CH2). The muting can be
switched by transmission of the mute bit.
I2C bus receiver and data handling
The TDA8421 is controlled via the 2-wire I2C bus by a
microcomputer. The two wires (SDA - serial data, SCL -
serial clock) carry information between the devices
connected to the bus. Both SDA and SCL are bidirectional
lines, connected to a positive supply voltage via a pull up
When the bus is free both lines are HIGH. The data on the
SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW.
The set up and hold times are specified in
A HIGH-to-LOW transition of the SDA line while SCL is
HIGH is defined as a start condition. A LOW-to-HIGH
transition of the SDA line while SCL is HIGH is defined as
a stop condition. The bus receiver will be reset by the
reception of a start condition. The bus is considered to be
busy after the start condition. The bus is considered to be
free again after a stop condition.
TEA5115 5 CHANNELS VIDEO SWITCH
EACH CHANNEL EXCEPT FAST BLANKING
HAS 6dB GAIN .R, G, B AND VIDEO SIGNALS ARE CLAMPED
TO HAVE NO OUTPUT DIFFERENTIAL
VOLTAGEWHEN SWITCHING .ALL INPUT LEVELSCOMPATIBLE WITH NFC
92250AND EN 50049NORMS .30MHzBAND WIDTH FOR R, G, B SIGNALS .INTERNAL 6.7V SHUNT REGULATOR FOR :
- LOW IMPEDANCE LOADS,
- POWER DISSIPATIONLIMITATION .INDEPENDANT VIDEO OR SYNCHRONIZING
SIGNAL SELECTION .SIMULTANEOUSSWITCHING OFR, G, BAND
FB SIGNALS BY FB1 INPUT (internal)
VCU 2133 Video Codec UNIT
High-speed coder/decoder IC for analog-to-digital and di-
gital-to-analog conversion of the video signal in digital TV
receivers based on the DIGIT 2000 concept. The VCU 2133
is a VLSI circuit in Cl technology, housed in a 40-pin Dil
plastic package. One single silicon chip combines the fol-
lowing functions and circuit details (Fig. 1):
- two input video amplifiers
- one A/D converter for the composite video signal
- the noise inverter
- one D/A converter for the luminance signal
- two D/A converters for the color difference signals
- one RGB matrix for converting the color difference sig-
nals and the luminance signal into RGB signals
- three RGB output amplifiers
- programmable auxiliary circuits for blanking, brightness
adjustment and picture tube alignment
- additional clamped RGB inputs for text and other analog
- programmable beam current limiting
1. Functional Description
The VCU 2133 Video Codec is intended for converting the
analog composite video signal from the video demodulator
into a digital signal. The latter is further processed
in the VPU 2203 Video Processor and in the DPU 2553 De-
flection Processor. After processing in the VPU 2203 (color
demodulation, PAL compensation, etc.), the VPU‘s digital
output signals (luminance and color difference) are recon-
verted into analog signals in the VCU 2133. From these an-
alog signals are derived the RGB signals by means of the
RGB matrix, and, after amplification in the integrated RGB
amplifiers, the RGB signals drive the RGB output amplifiers
of the color T\/ set.
For TV receivers using the NTSC standard the VPU 2203
may be replaced by the CVPU 2233 Comb Filter Video Pro-
cessor which is pin-compatible with the VPU 2203, but of-
fers better video performance. In the case of SECAM, the
SPU 2220 SECAM Chroma Processor must be connected
in parallel to the VPU 2203 for chroma processing, while
the luma processing remains inthe VPU 2203.
In a more sophisticated CTV receiver according to the Dl-
GIT 2000 concept, after the VPU Video Processor may be
placed the DTI 2223 Digital Transient Improvement Proces-
sor which serves for sharpening color transients on the
screen. The output signals of the DTI are fed to the VCU’s
luma and chroma inputs. To achieve the desired transient
improvement, the R-Y and B-Y D/A converters of the VCU
must be stopped for a certain time which is done by the
hold pulse supplied by the DTI and fed to the Reset pin 23
of the VCU. The pulse detector following this pin seperates
the (capacitively-coupled) hold pulse from the reset signal.
In addition, the VCU 2133 carries out the functions:
- brightness adjustment
- automatic CRT spot-cutoff control (black level)
- white balance control and beam current limiting
Further, the VCU 2133 offers direct inputs for text or other
analog RGB signals including adjustment of brightness and
contrast for these signals.
The RGB matrix and RGB amplifier circuits integrated in
the VCU 2133 are analog. The CRT spot-cutoff control is
carried out via the RGB amplifiers’ bias, and the white bal-
ance control is accomplished by varying the gain of these
amplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHz
clock signal supplied by the MCU 2632 Clock Generator IC.
1.1. The A/D Converter with Input Amplifiers and Bit
The video signal is input to the VCU 2133 via pins 35 and 37
which are intended for normal TV video signal (pin 35) and
for VCR or SCART video signal (pin 37) respectively. The
video amplifier whose action is required, is activated by the
CCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-
ware. The amplification of both video amplifiers is doubled
during the undelayed horizontal blanking pulse (at pin 36)
in order to obtain a higher digital resolution of the color
synchronization signal (burst). At D 2-MAC reception, the
doubled gain is switched off by means of bit p = 1 (Fig. 8).
The A/D converter is of the flash type, a circuit of 2" com-
parators connected in parallel. This means that the number
of comparators must be doubled if one additional bit is
needed. Thus it is important to have as few bits as possi-
ble. For a slowly varying video signal, 8 bits are required.
order to achieve an 8-bit picture resolution using a 7-bit
converter, a trick is used: during every other line the refer-
ence voltage of the A/D converter is changed by an
amount corresponding to one half of the least significant
bit. ln this procedure, a grey value located between two 7-
bit steps is converted to the next lower value during one
line and to the next higher value during the next line. The
two grey values on the screen are averaged by the viewer’s
eye, thus producing the impression of grey values with
8-bit resolution. Synchronously to the changing reference
voltage of the A/D converter, to the output signal of the Y
D/A converter is added a half-bit step every second line.
The bit enlargement just described must be switched off in
the case of using the D2-MAC standard (q = 1 and r = 1
in Fig. 8). ln the case of using the comb filter CVPU instead
of the VPU, the half-bit adding in the Y D/A converter must
be switched off (r = 1 in Fig. 8).
The A/D converter’s sampling frequency is 17.7 MHZ for
PAL and 14.3 MHz for NTSC, the clock being supplied by
the MCU 2632 Clock Generator IC which is common to all
circuits for the digital T\/ system. The converter’s resolu-
tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded to
eliminate spikes and glitches resulting from different com-
parator speeds or from the coder itself. The output is fed to
the VPU 2203 and to the DPU 2553 in parallel form.
1.2. The Noise Inverter
The digitized composite video signal passes the noise in-
verter circuit before it is put out to the VPU 2203 and to the
DPU 2553. The noise inverter serves for suppressing bright
spots on the screen which can be generated by noise
pulses, p. ex. produced by ignition sparks of cars etc. The
function of the noise inverter can be seen in Fig. 2. The
maximum white level corresponds with step 126 of the A/D
converter’s output signal (that means a voltage of 7 V at
pin 35). lf, due to an unwanted pulse on the composite
video signal, the voltage reaches 7.5 V (what means step
127 in digital) or more, the signal level is reduced by such
an amount, that a medium grey is obtained on the screen
(about 40 lFiE). The noise inverter circuit can be switched
off by software (address 16 in the VPU 2203, see there).
1.3. The Luminance D/A Converter (Y)
After having been processed in the VPU 2203 (color de-
modulation, PAL compensation, etc.), the different parts of
the digitized video signal are fed back to the VCU 2133 for
further processing to drive the RGB output amplifiers. The
luminance signal (Y) is routed from the VPU’s contrast mul-
tiplier to the Y D/A converter in the VCU 2133 in the form of
a parallel 8-bit signal with a resolution of 1/2 LSB of 9
This bit range provides a sufficient signal range for contrast
as well as positive and negative overshoot caused by the
peaking filter (see Fig. 3 and Data Sheet VPU 2203).
The luminance D/A converter is designed as an R-2R lad-
der network. lt is clocked with the 17.7 or the 14.3 MHz
clock signal applied to pin 22. The cutoff frequency of the
luminance signal is determined by the clock frequency.
1.4. The D/A Converters for the Color Difference Signals
R-Y and B-Y
ln order to save output pins at the VPU 2203 and input pins
at the VCU 2133 as well as connection lines, the two digital
color difference signals R-Y and B-Y are transferred in time
multiplex operation. This is possible because these signals’
bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3
The two 8-bit D/A converters R-Y and B-Y are also built as
R-2R ladder networks. They are clocked with ‘A clock fre-
quency, but the clock for the multiplex data transfer is 17.7
or 14.3 MHz. Four times 4 bits are transferred sequentially,
giving a total of 16 bits. A sync signal coordinates the
plex operations in both the VCU 2133 and the VPU 2203.
Thus, only four lines are needed for 16 bits. Fig. 4 shows
the timing diagram of the data transfer described.
ln a CTV receiver with digital transient improvement (DTI
2223), the R-Y and B-Y D/A converters are stopped by the
hold pulse supplied by the DTI, and their output signal is
kept constant for the duration of the hold pulse. Thereafter,
the output signal jumps to the new value, as described in
the DTl’s data sheet.
Timing diagram of the multiplex data transfer of the chroma
channel between VPU 2203, VCU 2133 and SPU 2220
a) main clock signal QSM
b) valid data out of the VCU 2133’s video A/D converter.
AIAD is the delay time of this converter, about 40 ns.
c) valid data out of the VPU 2203.
d) MUX data transfer of the chroma signals from VPU 2203
to VCU 2133, upper line: sync pulse from pin 27 VPU to
pin 21 VCU during sync time in vertical blanking time,
see Fig. 8; lower line: valid data from pins 27 to 30
(VPU) to pins 18 to 21 (VCU)
1.5. The RGB Matrix and the RGB Output Amplifiers
ln the RGB matrix, the signals Y, R-Y and B-Y are dema-
trixed, the reduction coefficients of 0.88 and 0.49 being tak-
en into account. In addition, the matrix is supplied with a
signal produced by an 8-bit D/A converter for setting the
brightness of the picture. The brightness adjustment range
corresponds to 1/2 of the luminance signal range (see Fig.
3). It can be covered in 255 steps. The brightness is set by
commands fed from the CCU 2030, CCU 2050 or CCU 2070
Central Control Unit to the VPU 2203 via the IM bus.
There are available four different matrices: standard PAL,
matrix 2, 3 and 4, the latter for foreign markets. 'The re-
quired matrix must be mask-programmed during produc-
tion. The matrices are shown in Table 1, based on the for-
R = r1~(R-Y)+ l'2~(B-Y) +Y
G = Q1-(Ft-Y)+ Q2 - (B-Y) +Y
B = b1-(Ft-Y)+ bg - (B-Y) +Y
The three RGB output amplifiers are impedance converters
having a low output impedance, an output voltage swing of
6 V (p-p), thereof 3 V for the video part and 3 V for bright-
ness and dark signal. The output current is 4 mA. Fig. 5
shows the recommended video output stage configuration.
For the purpose of white-balance control, the amplification
factor of each output amplifier can be varied stepwise in
127 steps (7 bits) by a factor of 1 to 2. Further, the CRT
spot-cutoff control is accomplished via these amplifiers’ bi-
as by adding the output signal of an 8-bit D/A converter to
the intelligence signal. The amplitude of the output signal
corresponds to one half of the luminance range. The eight
bits make it possible to adjust the dark voltage in 0.5 %
steps. By means of this circuit, the factory-set values for
the dark currents can be maintained and aging of the pic-
ture tube compensated.
1.6. The Beam Current and Peak Beam Current Limiter
The principle of this circuitry may be explained by means of
Fig. 6. Both facilities are carried out via pin 34 of the VCU
2133. For beam current limiting and peak beam current li-
miting, contrast and brightness are reduced by reducing
the reference voltages for the D/A converters Y, Ft-Y and
B-Y. At a voltage of more than +4 V at pin 34, contrast and
brightness are not affected. In the range of +4 V to +3 V,
the contrast is continuously reduced. At +3 V, the original
contrast is reduced to a programmable level, which is set
by the bits of address 16 of the VPU as shown in Table 2. A
further decrease of the voltage merely reduces brightness,
the contrast remains unchanged. At 2 V, the brightness is
reduced to zero. At voltages lower than 2 V, the output
goes to ultra black. This is provided for security purposes.
The beam current limiting is sensed at the ground end of
the EHT circuit, where the average value of the beam cur-
rent produces a certain voltage drop across a resistor in-
serted between EHT circuit and ground. The peak beam
current limiting can be provided additionally to avoid
“blooming” of white spots or letters on the screen. For
this, a fast peak current limitation is needed which is
sensed by three sensing transistors inserted between the
RGB amplifiers and the cathodes of the picture tube. One
of these three transistors is shown in Fig. 6. The sum of the
picture tube’s three cathode currents produces a voltage
drop across resistor R1. If this voltage exceeds that gen-
erated by the divider R2, B3 plus the base emitter voltage
of T2, this transistor will be turned on and the voltage at
34 of the VCU 2133 sharply reduced. Time constants for
both beam current limiting and peak beam current limiting
can be set by the capacitors C1 and C2.
1.7. The Blanking Circuit
The blanking circuit coordinates blanking during vertical
and horizontal flyback. During the latter, the VCU 2133's
output amplifiers are switched to “ultra black”. Such
switching is different during vertical flyback, however, be-
cause at this time the measurements for picture tube align-
ment are Carried out. During vertical flyback, only the ca-
thode to be measured is switched to “black” during mea-
suring time, the other two are at ultra black so that only the
dark current of one cathode is measured at the same time.
For measuring the leakage current, all three cathodes are
switched to ultra black.
The sequence described is controlled by three code bits
contained in a train of 72 bits which is transferred from the
VPU 2203 to the VCU 2133 during each vertical blanking in-
terval. This transfer starts with the vertical blanking pulse.
During the transfer all three cathodes of the picture tube
are biased to ultra black. In the same manner, the white-
balance control is done.
The blanking circuit is controlled by two pulse combina-
tions supplied by the DPU 2553 Deflection Processor
(“sandcastle pulses"). Pin 39 of the VCU 2133 receives the
combined vertical blanking and delayed horizontal blanking
pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of the
VCU gets the combined undelayed horizontal blanking and
color key pulse from pin 19 of the DPU (Fig. 7 a). The two
outputs of the DPU are tristate-controlled, supplying the
output levels max. 0.4 V (low), min. 4.0 V (high), or high-im-
pedance, whereby the signal level in the high-impedance
mode is determined by the VCU’s input configuration, a
voltage divider of 3.6 KS! and 5 KQ between the +5 V sup-
ply and ground, to 2_8 V. The VCU’s input amplifier has two
thresholds of 2.0 V and 3.4 V for detecting the three levels
of the combined pulses. ln this way, two times two pulses
are transferred via only two lines.
1.8. The Circuitry for Picture Tube Alignment
During vertical flyback, a number of measurements are tak-
en and data is exchanged between the VCU 2133, the VPU
2203 and the CCU 2030 or CCU 2050. These measure-
ments deal with picture tube alignment, as white level and
dark current adjustment, and with the photo current sup-
plied by a photo resistor (Fig. 5) which serves for adapting
Data sequence during the transfer of test results from the
VPU 2203 to the VCU 2133. Nine Bytes are transferred, in
each case the LSB first. These 9 Bytes, 8 bits each, coin-
cide with the 72 pulses of 4.4 MHz that are transferred dur-
ing vertical flyback from pin 27 of the VPU 2203 to pin 21 of
the VCU 2133 (see Fig. 9).
l and mi beam current limiter range
l<: noise inverter on/off
n: video input switching bit
S: SECAM chroma sync bit; S = 1 means that the chroma
demultiplexer is synchronized every line. The switch-over
time from C0 to demux counter begins with the end of the
undelayed horizontal blanking pulse and remains valid for a
time of 12 Q M clock periods.
the contrast of the picture to the light in the room where
the TV set is operated. The circuitry for transferring the
ture tube alignment data, the sensed beam currents and
the photo current is clocked in compliance with the VPU
2203 by the vertical blanking pulse and the color key pulse.
To carry out the measurements, a quadruple cycle is pro-
vided (see Table 3). The timing of the data transfer during
the vertical flyback is shown in Fig. 9, and Fig. 8 shows the
data sequence during that data transfer.
Ft, G, B: code bits
p=1; no doubled gain in the input amplifier during horizon-
tal blanking (see section 1.1.)
q=1: no changing of the A/D converter’s reference vol-
tage during every other line (see section 1.1.)
r=1: when operating with the DMA D2-MAC decoder or
the CVPU comb filter video processor, the adding of
a step of ‘/2 LSB to the output signal of the Y D/A
converter is switched off (see section 1.1.).
s=1; the blankirig pulse in the analog video output signal
at pins 26 to 28 is switched off, as is required in
1.9. The Additional RGB Inputs
The three additional analog RGB inputs are provided for
inputting text or other analog RGB signals. They are con-
nected to fast voltage-to-current converters whose output
current can be altered in 64 steps (6 bits) for contrast set-
ting between 100 % and 30 %. The three inputs are
clamped to a DC black level which corresponds to the level
of 31 steps in the luminance channel, by means of the color
key pulse. So, the same brightness level is achieved for
normal and for external RGB signals. The output currents
ofthe converters are then fed to the three RGB output am-
plifiers. Switchover to the external video signal is also
1.10. The Reset Circuit and Pulse Detector
The reset pulse produced by the external reset RC network
in common for the whole DIGIT 2000 system, switches the
RGB outputs to ultra black during the power-on routine of
the TV set. At other times, high level must be applied to the
reset input pin 23.
There is an additional facility with pin 23 which is used only
in conjunction with the DTl 2223 Digital Transient Improve-
ment Processor. The hold pulse produced by the latter
which serves for stopping the R-Y and B-Y D/A converters,
is also fed to pin 23, capacitively-coupled. The pulse detec-
tor responds on positive pulses which exceed the 5 V sup-
ply by about 1 V. The two DACs are stopped as long as the
hold pulse lasts, and supply a constant output signal of the
amplitude at the begin of the hold pulse.
5. Description of the Connections and the Signals
Pins 1, 9, and 25 - Supply Voltage, +5 V
The supply voltage is +5 V. Pins 1 and 25 supply the ana-
log part and must be filtered separately.
Pins 2 to 8 - Outputs V0 to V6
Via these pins the VCU 2133 supplies the digitized video
signal in a parallel 7-bit Gray code to the VPU 2203 and the
DPU 2553. The output configuration is shown in Fig. 16.
Pins 10 to 17 - Inputs L7 to L0
Fig. 17 shows these inputs’ configuration. Via these pins,
the VCU 2133 receives the digital luminance signal from the
VPU 2203 in a paraliel 8-bit code.
Pins 18 to 21 - Inputs C0 to C3
Via these inputs, whose circuitry and data correspond to
those of pins 10 to 17, the VCU 2133 is fed with the digi-
tized color difference signals R-Y and B-Y and with the
control and alignment signals described in section 1.8., in
multiplex operation. Pin 21 is additionally used for the
plex sync signal.
Pin 22 - QSM Main Clock Input
Via this pin, whose circuitry is shown in Fig. 18, the VCU
2133 is supplied with the clock signal QSM produced by the
MCU 2600 or MCU 2632 Clock Generator IC. The clock fre-
quency is 17.7 MHz for PAL and SECAM and 14.3 MHz for
NTSC. The clock signal must be DC-coupled.
Pin 23 - Reset and Hold Pulse Input (Fig. 19)
Via this pin, the VCU 2133 is supplied with the reset and
hold signals which are supplied by pin 21 of the DTI 2223
Digital Transient Improvement Processor for stopping the
R-Y and B-Y D/A converters, and for Reset.
Pins 24 and 29 - Analog Ground, 0
These pins serve as ground connections for the supply and
for the analog signals (GND pin 24 for RGB).
Pins 26 to 28 - RGB Outputs
These three analog outputs deliver an analog signal suit-
able for driving the RGB output transistors. Their diagram
is shown in Fig. 20. The output voltage swing is 6 V total,
3 V for the black-to-white signal and 3 V for adjusting
the brightness and the black level.
Pins 30 to 32 - Additional Analog Inputs R, G and B
Fig. 21 shows the configuration of these inputs. They serve
to feed analog RGB signals, for example for Teletext or si-
milar applications, and they are clamped during the color
key pulse. At a 1 V input, full brightness is reached. The
bandwidth extends from 0 to 8 MHz.
Pin 33 - Fast Switching Input
This input is connected as shown in Fig. 22. It ser\/es for
fast switchover of the video channel between an internally-
produced video signal and an externally-applied video sig-
nal via pins 30 to 32. With 0 V at pin 33, the RGB outputs
will supply the internal video signal, and at a 1 V input
the RGB outputs are switched to the external video signal.
Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-
Pin 34 - Beam Current Limiter Input
The diagram of pin 34 is shown in Fig. 25. The input voltage
may be between +5 V and 0 V. The input impedance is 100
kQ. The function of pin 34 is described in section 1.6.
Pin 35 - Composite Video Signal Input 1
To fully drive the video A/D converter the following ampli-
tudes are required at pin 35: +5 V = sync pulse top level,
all bits low; +7 V = peak white, all bits high. Fig. 24 shows
the configuration of pin 35.
Pin 36 - Undelayed Horizontal Blanking and Color Key
The circuitry of this pin is shown in Fig. 23. Pin 36 receives
the combined undelayed horizontal blanking and color key
pulse which are “sandcastled” and are supplied by pin 19
of the DPU 2553 Deflection Processor. During the undelay-
ed horizontal blanking pulse, the input amplifiers’ gain is
doubled, and the bit enlargement circuit is also switched
by this pulse, and the counter for the data transmission
gap started. The color key pulse is used for clamping the
RGB inputs pins 30 to 32.
Pin 37 - Composite Video Signal Input 2
This pin has the same function and properties as pin 35,
except the gain of the input amplifier which is twice the
gain as that of the amplifier at pin 35. This means an input
voltage range of +5 V to +6 V.
Pin 38 - Supply Voltage, +12 V »
The 12 V supply is needed for certain circuit parts to obtain
the required input or output voltage range, as the video in-
put and the RGB outputs (see Figs. 20 and 24).
Pin 39 - Vertical Blanking and Delayed Horizontal Blanking
This pin receives the combined vertical blanking and delay-
ed horizontal blanking. pulse from pin 22 of the DPU 2553
Deflection Processor. Both pulses are “sandcastled” so
that only one connection is needed for the transfer of two
pulses. These two pulses are separated in the input circui-
try of the VCU 2133, and are used for blanking the picture
during vertical and horizontal flyback. Fig. 23 shows the cir-
cuitry of pin 39.
Pin 40 - Digital Ground, O
This pin is used as GND connection in conjunction with the
pins 2 to 8 and 10 to 21 which carry digital signals.
DPU 2553, DPU 2554 Deflection Processors UNIT
Note: lf not otherwise designated, the pin numbers
mentioned refer to the 40-pin Dil package.
These programmable VLSI circuits in n-channel mOS
technology carry out the deflection functions in digital
colorTV receivers based onthe DiGiT 2000 system and
are also suitable for text and D2~mAC application. The
three types are basically identical, but are modified ac-
cording to the intended application:
normal-scan horizontal deflection, standard CTV re-
ceivers, also equipped with Teletext and D2-mAC fa-
double-scan horizontal deflection, for CTV receivers
equipped with double-frequency horizontal deflection
and double-~frequency vertical deflection for improved
picture quality. At power-up, this version starts with
double horizontal frequency.
1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol-
lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequen-
cies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode
and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection
ln this data sheet, all information given for double~scan
mode is available with the DPU 2554 only. Type DPU
2553 starts the horizontal deflection with 15.5 kHz ac-
cording to the normal TV standard, whereas type DPU
2554 starts with 31 kHz according to the double-scan
The following characteristics are programmable:
~ selection ofthe TV standard (PAL, D2-mAC or NTSC)
- selection ofthe deflection standard (Teletext, horizon-
tal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position
for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal
correction for in-line, flat-screen and Trinitron picture
- switchover characteristics between the different syn-
~characteristic of the synchronism detector for PLL
switching and muting
Fig. 1-1 showsthe simplified block diagram ofthe video
and deflection section of a digital TV receiver based on
the DIGIT 2000 system. The analog video signal derived
from the video detector is digitized in the VCU 2133,
VCU 2134 or VCU 2136 Video Codec and supplied in a
parallel 7 bit Gray code. This digital video signal is fed to
the video section (PVPU, CVPU, SPU and DmA) and to
the DPU 2553/54 Deflection Processorwhich carries out
all functions required in conjunction with deflection, from
sync separation to the control of the deflection power
stages, as described in this data sheet.
3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors
perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and
the vertical deflection frequencies
-the various eastevvest corrections
- vertical savvtooth generation including S correction
as described hereafter. The DPU communicates, viathe
bidirectional serial lm bus, with the CCU 2050 or CCU
2070 Central Control Unit and, via this bus, is supplied
with the picture-correction alignment information stored
in the mDA 2062 EEPROM during set production, vvhen
the set is turned on. The DPU is normally clocked with
a trapezoidal 17.734 mHz (PAL or SECAm), or 14.3 mhz
(NTSC) or 20.25 mHz (D2-mAC) clock signal supplied
by the mCU 2600 or mCU 2632 Clock Generator IC.
The functional diagram of the DPU is shovvn in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse
The digitized composite video signal delivered as a 7»bit
parallel signal by the VCU 2133, VCU 2134 or VCU 2136
Video Codec is first noise-filtered by a 1 mHz digital lovv-
pass filter and, to improve the noise immunity ofthe
clamping circuit, is additionally filtered by a 0.2 mHz low-
pass filter before being routed to the minimum and back
porch level detectors (Fig. 3-3).
The DPU has tvvo different clamping outputs, no. 1 and
No. 2, one of vvhich supplies the required clamping
pulses to the video input of the VCU as shovvn in Fig.
3-1. The following values forthe clamping circuit apply
for Video Amp. l. since the gain of Video Amp. ll istwice
th at of Video Amp l, all clamping and signal levels of Vid-
eo Amp ll are halt those of Video Amp l referred to +5 V.
Afterthe TV set is switched on,thevideo clamping circuit
first of all ensures by means of horizontal-frequency
current pulses from the clamping output of the DPU to
the coupling capacitor of the analog composite video
signal, that the video signal atthe VCU’s input is optimal-
ly biased for the operation range of the A/D converter of
5 to 7 V. For this, the sync top level is digitally measured
and set to a constant level of 5.125 V by these current
pulses. The horizontal and vertical sync pulses are novv
separated by a fixed separation level of 5.250 V so that
the horizontal synchronization can lock to the correct
phase (see section 3.3. and Figs. 3-2 and 3-3).
vvith the color key pulse which is now present in syn-
chronism with the composite video signal, the video
clamping circuit measures the DC voltage level of the
porch and by means of the pulses from pin 21 (or pin4),
sets the DC level ofthe porch at a constant 5.5 V (5.25 V
for Video Amp ll). This level is also the reference black
to Video Processorffeletext Processor, D2-MAC Processor tc.
level for the PVPU 2204 or CvPU 2270 Video Proces-
When horizontal synchronization is achieved, the slice
level for the sync pulses is set to 50 % of the sync pulse
amplitude by averaging sync top and black level. This
ensures optimum pulse separation, even with small
sync pulse amplitudes (see application notes, section
3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal syn-
chronization. The choice of mode depends on whether
or not the Tv station is transmitting a standard PAL or
NTSC signal, in which there is a fixed ratio between color
subcarrier frequency and horizontal frequency. ln the
first case we speak of “color-locked” operation and in
the second case of “non-color-locked” operation (e.g.
black-and-white programs). Switching between thetwo
modes is performed automatically by the standard sig-
3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation
where there is no standard fixed ratio between the color
subcarrier frequency and the horizontal frequency ofthe
transmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3
mHz for NTSC) in the programmable fre-
quency dmder (Fig. 3-4) until the correct horizontal
frequency is obtained. The correct adjustment of fre-
quency and phase is ensured by phase comparator l.
This determines the frequency and phase deviation by
means of a digital phase comparison between the sepa-
rated horizontal sync pulses and the output signal of the
programmable dmder and corrects the dmder accordingly. For
optimum adjustment of phase iitter, capture
behavior and transient response of the horizontal PLL
circuit, the measured phase deviation is filtered in a digi-
lowpass filter (PLL phase filter). ln the case of non-
OZMH synchronized horizontal PLL, this filter is set to
wideband PLL response with a pull-in range of 1800 Hz. if the
- sync sync PLL circuit is locked, the PLL filter is
automatically switched to narrow-band response by an internal
synchronism detector in order to limit the phase jitter to a
minimum, even in the case of weak and noisy signals.
A calculator circuit in phase comparator , which analyzes the
edges of the horizontal sync pulses, increases
the resolution of the phase measurement from 56 ns at
Fig. 3-3: Principle ofvideo clamping and pulse separa- 17.7
mHz clock frequency to approx. 6 ns, or from 70 ns
NON at 14.3 MHz clock frequency to approx. 2.2 ns.
The various key and gating pulses such as the color key
pulse (tKe(,), the normal-scan (1 H) and double-scan
(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-
zontal undelayed gating pulse (t/(Z) are derived from the
output signals ofthe programmable dmder and an addi-
tional counter forthe2H signals and the 1 H and 2H skew
data output. These pulses retain a fixed phase position
with respect to the 1 H inputvideo signal andthe double-
scan output video signal from the CvPU 2270 Video Pro-
Forthe purpose of equalizing phase changes in the hori-
zontal output stage due to switching response toler-
ances or video influence, a second phase control loop
is used which generates the horizontal output pulse at
pin 31 to drivethe horizontal output stage. ln phase com-
parator li (Fig. 3~4), the phase difference between the
output signal of the programmable dmder and the lead-
ing edge (or the center) of the horizontal flyback pulse
(pin 23) is measured by means of a balanced gate delay
line. The deviation from the desired phase difference is
used as an input to an adder. ln this, the information on
the horizontal frequency derived from phase com-
parator l is added to the phase deviation originating form
phase comparator ll. The result of this addition controls
a digital on-chip sinewave generator (about 1 mHz)
which acts as a phase shifter with a phase resolution of
1/128 of one main clock period
By means of control loop ll the horizontal output pulse
(pin 31) is shifted such that the horizontal flyback pulse
(pin 23) acquiresthe desired phase position with respect
to the output signal of the programmable dmder which,
in turn, due to p
position with respect to the video signal. The horizontal
output pulse itself is generated by dmding the frequency
ofthe 1 mHz sinewave oscillator by a fixed ratio of 64 in
the case of norm al scan and of 32 in the case of double-
3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the
phase position has been set in the non-color-locked
mode, the programmable dmder is set to the standard
dmsion ratio (1135:1 for PAL, 91O:1 for NTSC) and
phase comparator is disconnected so that interfering
pulses and noise cannot influence the horizontal deflec-
tion. Because phase comparator ll is still connected,
phase errors ofthe horizontal output stage are also cor-
rected in the color»locKed operating mode. The stan-
dard signal detector is so designed that
to color-locked operation when the ratio between color
subcarrier frequency and horizontal frequency deviates
no more than 1O'7 from the standard dmsion ratio. To
ascertain this requires about 8 s (NTSC). Switching off
color-locked operation takes place automatically, in the
_ case of a change of program for example, within approx-
imately 67 ms (e.g. two NTSC fields, 60 Hz).
3.3.3. Skew Data Output and Field Number Informa-
with non-standard input signals, the TPU 2735 or TPU
2740 Teletext Processor produce a phase error vvith re-
spect to the deflection phase.
The DPU generates a digital data stream (skevv data,
pin 7 ofthe DPU), which informs the PSP and TPU on
the amount of phase delay (given in 2.2 ns increments)
used in the DPU for the 1H and 2h outp
pared With the Fm main clock signal of 17.7 mHz (PAL
or SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to
3-8. The skew data is used by the PSP and by the TPU
to adjust the double-scan video signal to the 1 H and 2H
phase of the horizontal deflection to correct these phase
For the vmC processor the skew data contains three additional
bits for information about frame number, 1 V
sync and 2 V sync start.
3.3.4. Synchronism Detector for PLL and Muting
To evaluate locking ofthe horizontal PLL and condition
of the signal, the DPU’s HSP high-speed processor
(Fig. 3~1) receives two items of information from the hor-
izontal PLL circuit (see Fig. 3-11).
a) the overall pulsevvidth of the separated sync pulses
during a 6.7 us phase window centered to the horizontal
sync pulse (value A in Fig. 3-11).
b) the overall pulsevvidth of the separated sync pulse
during one horizontal line but outside the phase window
(value B in Fig. 3-11).
Based on a) and b) and using the selectable coefficients
KS1 and KS2 and a digital lovi/pass filter, the HSP pro-
cessor evaluates an 8-bit item of information “SD” (see
Fig. 3-12). By means of a comparator and a selectable
level SLP, the switching threshold for the PLL signal
“UN” is generated. UN indicates Whether the PLL is in
the synchronous or in the asynchronous state.
To produce a muting signal in the CCU, the data SD can
be read by the CCU. The range ot SD extends from O
(asynchronous) to +127 (synchronous). Typical values
torthe comparator levels and their hysteresis B1 = 30/20
and for muting 40/30 (see also HSP Bam address Table
DPU 2553, DPU 2554
3.4. Start Oscillator and Protection Circuit
To protect the horizontal output stage of the TV set dur-
ing changing the standard and for using the DPU as a
low power start oscillator, an additional oscillator is pro-
vided on-chip (Fig. 3-4), with the output connected to
pin 31. This oscillator is controlled by a 4 mHz signalin-
dependent trom the Fm main clock produced by the
MCU 2600 or mCU 2632 Clock Generator IC and is pow-
ered by a separate supply connected to pin 35. Thefunc-
tion ofthis circuitry depends on the external standard se-
lection input pin 33 and on the start oscillator select input
pin 36, as described in Table 3-3. Using the protection
circuit as a start oscillator, the following operation modes
are available (see Table 3-3).
With pin 33 open-circuit, pin 36 at high potential (con-
nected to pin 35) and a 4 mHz clock applied to pin 34,
the protection circuit acts as a start oscillator. This pro-
duces a constant-frequency horizontal output pulse of
15.5 kHz in the case of DPU 2553, and of 31 khz in the
case of DPU 2554 while the Beset input pin 5 is at low
potential. The pulsewidth is 30 us with DPU 2553, and
16 us with DPU 2554. main clock at pin 2 or main power
supplies at pins 8, 32 and 40 are not required for this start
oscillator After the main power supply is stabilized and
the main clock generator has started, the reset input pin
5 must be switched to the high state. As long as the start
values from the CCU are invalid, the start oscillator will
continuously supply the output pulses of constant fre-
quency to pin 31 _ By means of the start values given by
the CCU via the lm bus, the register FL must be set to
zero to enable the stan oscillator to be triggered by the
horizontal PLL circuit. After that, the output frequency
and phase are controlled by the horizontal PLL only.
It the external standard selection input pin 33 is con-
nected to ground or to +5 V, the start oscillator is
switched off as soon as it ls in phase with PLL circuit. Pin
33to ground selects PAL or SECAm standard (17.7 mHz
main clock), and pin 33 to +5 V selects NTSC standard
(14.3 MHz main clock). After the main power supplies to
pins 8, 32 and 40 are stabilized, the start oscillator can
be used as a separate horizontal oscillator with a con-
stant frequency of 15.525 khz. For this option, pin 33
must be unconnected. By means ofthe lm bus register
SC the start oscillator can be switched on (SC = 0) or oft
(SC = 1). Setting SC =1 is recommended.
By means of pin 29 (horizontal output polarity selectin-
put and start oscillator pulsewidth select input), the out-
put pulsewidth and polarity ofthe start oscillator and pro-
tection circuit can be hardware-selected. Pin 29 at low
potential gives 30 us for DPU 2553 and 16 us for DPU
2554,with positive output pulses. Pin 29 at high potential
gives 36 us for DPU 2553 and 18 its for DPU 2554, with
negative output pulses. Both apply forthetime period in
which no start values are valid from the CCU. If pin 29
is intended to be in the high state, it must be connected
to pin 35 (standby power). Pin 29 must be connected to
ground or to +5 V in both cases.
Table 3-3: Operation modes ofthe start oscillator and
Operation Mode Pins
33 34 35 36
Horizontal output stage protected not connected 4 mHz Clock at
+5 V at ground
during main clock frequency changing
(for PAL and NTSC)
Horizontal output stage protected not connected 4 MHz Clock +5
V with connected to
and start oscillator function start oscilla- pin 35
(for PAL and NTSC) tor supply
Only start oscillator function with at +5 V 4 mHz Clock +5 V
with connected to
NTSC standard after Beset start oscilla- pin 35
Only start oscillator function with at ground 4 mHz Clock +5 V
with connected to
PAL or SECAM standard after Beset start oscilla~ pin 35
5 tor supply
_ with 17.7 mHz clock at ground at ground at +5 V at ground
3.5. Blanking and Color Key Pulses
Pin 19 supplies a combination ofthe color key pulse and
the undelayed horizontal blanking pulse in the form of a
three-level pulse as shown in Fig. 3-13. The high level
(4 V min.) and the low level (0.4 V max.) are controlled
by the DPU. During the low time of the undelayed hori-
zontal blanking pulse, pin 19 of the DPU i sin the high--
impedance mode and the output level at pin 19 is set to
2.8 V by the VCU.
At pin 22, the delayed horizontal blanking pulse in com-
bination with the vertical blanking pulse is available as
athree-level pulse as shown in Fig. 3-13. Output pin 22
is in high-impedance mode during the delayed horizon-
tal blanking pulse.
ln double-scan operation mode (DPU 2554), pin 22 sup-
plies the double-scan (2H) horizontal blanking pulse in-
stead ofthe 1H blanking pulse (DPU 2553). ln text dis-
play mode with increased deflection frequencies (see
section 1.), pin 22 ofthe respective DPU (DPU 2553, as
defined by register ZN) delivers the horizontal blanking
pulse with 18.7 kHz and the vertical blanking pulse with
60 Hz according to the display. At pin 24 the undelayed
horizontal blanking pulse is output.
normally,pin3suppliesthe samevertical blanking pulse
as pin 22. However, with“DVS” = 1, pin 3 will be in the
single-scan mode also with double-scan operation of
the system. The pulsewidth of the single-scan vertical
blanking pulse at pin 3 will be the same as.that of the
double-scan vertical blanking pulse at pin 22. The out-
put pulse of pin 3 is only valid if the COU register “VBE”
is set to 1 . The default value is set to 0 (high-impedance
state of pin 3).
Fig. 3-13: Shape of the output pulses at pins 19 and 22
*) The output level is externally defined
3.6. Output for Switching the Horizontal Power
Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz
This output (pin 37) is designed as a tristate output. High
levels (4 V mln.) and low levels (0.4 V max.) are con-
trolled bythe DPU. During high-impedance state an ex-
ternal resistor network defines the output level,
For changing the horizontal frequency from 15 kHz to
18 kHz, the following sequence of output levels is
derived at pin 37 (see Fig. 3-14).
After register ZN is set from ZN = 2 (15 kHz) to ZN = 0
(18 kHz) by the CCU, pin 37 is switched from High level
to high-impedance state synchronously with the fre-
quency change at pin 31. Following a delay of 20ms, pin
37 is set to Low level and remains in this state forthetime
the horizontal frequency remains 18 kHz (with ZN == 0).
This 20 ms delay is required for switching-over the hori-
zontal power stage.
To change the horizontal frequency in the opposite di-
rection, from 18 kHz to 15.6 kHz, the sequence de-
scribed is reversed.
3.7. Text Display Mode with Increased Deflection
As already mentioned, the DPU 2553 provides the fea-
ture of increase
for improved picture quality in this mode of operation. To
achieve this, the processor acting as deflection proces-
sor has its register Zn set to 0. The horizontal output fre-
quency at pin 31 is then switched to a frequency of
18746.802 Hz which is generated by dmding the Fm
main clock frequency by 946 i 46. The horizontal PLL is
then able to synchronize to an external composite sync
signal offH = 18.746 kHzi 46. The horizontal PLL isthen
able to synchronizeto an external composite sync signal
of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can
be set to an independent horizontal and vertical sync
generator by setting register VE = 1 and register VB = 0.
That means a constant dmder of 946 for horizontal fre-
quency and constant 312 lines per frame.
The DPU working in this mode supplies the TPU 2740
Teletext Processor or the respective Viewdata Proces-
sor with the 18.7 kHz horizontal blanking pulses form pin
24 and the 60 Hz vertical blanking pulses form pin 22
(see Fig. 3-8).
To be able to receive and store data from an IF video sig-
nal at the same time, the Teletext or Viewdata Processor
requires horizontal and ve
signal. Therefore, the second DPU provides video
clamping and sync separation forthe external signal and
supplies the horizontal sync pulses (pin 24) and the ver-
tical sync pulses (pin 22) to the Teletext or viewdata Pro-
cessor. For this, the second DPU is set to the PAL stan-
dard by register ZN = 2, and the clamping pulses of the
other DPU are disabled by CLD = 1.
To change the output frequency ofthe DPU acting as de-
flection processor from 18.7 kHz to 15.6 kHz, the control
switch output pin 37 prepares the horizontal output
stage for 15.6 khz operation (pin 37 is in the high-impe-
dance state) beforethe DPU changesthe horizontal out-
put frequencyto 15.6 kHz, after a minimum delay of one
vertical period. Switching the horizontal deflection fre-
quency from 15.6 kHzto 18.7 kHz is done in the reverse
sequence. Firstly, the horizontaloutput frequency of pin
31 is switched to 1 8.7 khz, and after a delay of one verti-
cal period, pin 37 is set low.
3.8. D2-MAC Operation Mode
When receiving Tv signals having the D2-mAC stan-
dard (direct satellite reception), register ZN is set to 3.
The programmable dmder is set to a dmsion ratio of
1296 i48 to generate a horizontal frequency of 15.625
khz with the clock rate of 20.25 mHz used in the
D2-mAC standard. ln this operation mode, pin 6 acts as
input forthe composite sync signal supplied by the DmA
2271 D2-mAC Decoder. The DPU is synchronized to
this sync signal, and after locking-in (status register
UN = 0), the CCU switches the DPU to a clock-locked
mode between clock signal and horizontal frequency
clock by 1024, during the vertical sync signal separated
from the received video signal. To use an 8-bit register,
the result of the count is dmded by 2 and given to the
DPU status register. ln the CCU, the vertical frequency
can be evaluated using the following equation:
fv I __lL1’_l\
1024- vP- 2
fm), = 17.734475 mHz with PAL and SECAm
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.
The interlace control output pin 39 supplies a 25 Hz (for
PAL and SECAm) or 80 Hz (for NTSC) signal for control-
ling an external interlace-off switch, which is required
with A.C.-coupled vertical output stages, becausethese
are not able to handle the internal interlace-off proce-
dure using register “ZS”.
For operation with the vmC Processor the DPU 2554
hasthree interlace control modes in double vertical scan
mode (DVS = 1). These options can be selected with the
register “IOP” and can be used together with the control
output pin 39 only. This output has to be connected to the
vertical output stage, so that the vertical phase can be
shifted by 16 us (or 32 us with DPU 2553).
TELEFUNKEN PALCOLOR HIFI 292 PIP "MILLENNIUM" CHASSIS 618 A-2 PIP (ICC5341) Raster distortion correction circuitry for a video display apparatus that includes a square-planar picture tube
1. Video display apparatus with correction of raster distortion, comprising:
a picture tube having a phosphor screen located on a faceplate having an aspherically curved surface contour, with at least one of a minor and major axis exhibiting a curvature that changes from an edge of the faceplate to the center;
deflection means including horizontal and vertical deflection windings for generating respectively therein horizontal and vertical deflection currents to enable an electron beam of said picture tube to scan a raster on said phosphor screen;
a parabola generator coupled to said deflection means for generating a generally parabolically shaped signal that produces a parabolic modulation of the scanning of said electron beam to generally provide correction of a first raster distortion while leaving uncorrected a residual raster distortion due to the change in curvature of said faceplate from said edge to the center; and
means for nonlinearly modifying said (parabolic modulation) parabolically shaped signal as a function of said change in curvature of said faceplate to provide additional modulation of the scanning of said electron beam for correcting said residual raster distortion.
2. Apparatus according to claim 1 wherein said first raster distortion results in side pincushion raster distortion and wherein said faceplate has an aspherically curved geometry that results in areas of said faceplate near the top and bottom being of increased curvature relative to the curvature in areas near the center. 3. Apparatus according to claim 2 wherein said residual raster distortion comprises a barrel-like distortion of a raster display of a vertical line pattern in said areas near the top and bottom of said faceplate. 4. Apparatus according to claim 2 wherein said nonlinearly modifying means comprises a current source coupled to said parabola generator and a switched current divider that switches from a first conductive state to a second conductive state during that portion of a vertical trace interval when a raster is being scanned on said faceplate in said areas of increased curvature. 5. Apparatus according to claim 4 wherein said parabolically shaped signal is a generally parabolically shaped input voltage repeating at a vertical deflection rate and having both a DC component voltage and an AC parabolic component voltage and wherein said switched current divider comprises an impedance receiving a constant current from said current source for establishing a bias voltage level and switching means responsive to said bias voltage level and direct current coupled to said parabola generator for shunting a portion of said constant current when said input voltage goes beyond a threshold voltage level established in accordance with said bias voltage level to modify the waveshape of said input voltage in a manner that corrects said residual raster distortion. 6. A circuit for correcting a given error of electron beam positioning in a video display apparatus, comprising:
a deflection winding;
an output stage for generating current in said deflection winding to control said electron beam positioning;
a parabolic voltage generator for developing a generally parabolically shaped input voltage repeating at a deflection rate and having both a DC component voltage and an AC parabolic component voltage;
an amplifier for driving said output stage in accordance with said parabolically shaped input voltage to generally correct said given error while retaining a residual error of said electron beam positioning;
a current source;
an impedance receiving current from said current source for establishing a bias voltage level; and
switching means responsive to said bias voltage level and direct current coupled to said parabolically shaped input voltage for shunting a portion of the current from said current source when said input voltage goes beyond a threshold voltage level established in accordance with said bias voltage level to modify the waveshape of said input voltage in a manner that corrects said residual error.
7. A circuit according to claim 6 wherein said switching means is direct current coupled to an output terminal of said parabolic voltage generator, at which terminal said input voltage is developed, and which is direct current coupled to a terminal of said impedance, at which impedance terminal said bias voltage level is developed. 8. A circuit according to claim 7 wherein said switching means comprises a diode in which there flows the shunted portion of current from said current source. 9. A circuit according to claim 7 wherein the shunted portion of current from said current source establishes a modified parabola voltage at an output terminal of said switching means that is direct current coupled to the output terminal of said parabolic voltage generator, said modified parabola voltage having a waveform that generally follows the waveform of said input voltage when said switching means is in one conductive state and having a waveform of waveshape that is substantially different than that of said input voltage when said switching means is in another conductive state. 10. A circuit according to claim 9 including means for AC coupling said modified parabola voltage to said amplifier. 11. A circuit according to claim 10 including means for adjusting said bias voltage level to adjust the switching instants of said switching means and wherein a peak amplitude of said modified parabola voltage remains substantially unchanged for different adjustments of said bias voltage level. 12. A circuit according to claim 11 including an adjustable voltage divider coupled to said AC coupling means and direct current coupled to said amplifier for adjusting the amplitude of the AC coupled modified parabola voltage, and wherein the peak amplitude of the modified parabola voltage that is established at the output terminal of said switching means remains substantially unchanged for different adjustments of said voltage divider. 13. A circuit according to claim 9 wherein said input voltage includes an AC sawtooth component voltage repeating at said deflection rate and further including means for applying said sawtooth component voltage to said impedance to provide common-mode rejection of said sawtooth component voltage with respect to the shunted portion of current from said current source. 14. A circuit according to claim 9 wherein said switching means applies an additional voltage to said terminal of said impedance that is representative of the difference between said bias voltage level and said input voltage to control the amplitude of the shunted portion of current in accordance with said additional voltage. 15. A circuit according to claim 9 wherein said current source comprises a source of DC voltage coupled to a second impedance, and wherein said switching means applies an additional voltage to said terminal of the first mentioned impedance that is representative of a difference between said bias voltage level and said input voltage. 16. A circuit according to claim 15 wherein said DC voltage of said DC voltage source is substantially greater in magnitude than that of said additional voltage to prevent significant changes from occurring in the magnitude of said current source when said switching means changes conductive states. 17. A circuit according to claim 6 wherein said video display apparatus includes a picture tube having a phosphor screen located on a faceplate having an aspherically curved geometry that produces a relatively flat surface contour and wherein said residual error of electron beam positioning is produced in accordance with said aspherically curved geometry. 18. A circuit according to claim 17 wherein said given error is produced by side pincushion distortion and wherein said residual error produces a barrel-like distortion of a raster display of a vertical line pattern in regions near the top and bottom of said faceplate where the curvature of said faceplate is increased relative to the curvature in the center region. 19. Apparatus according to claim 1 wherein said nonlinearly modifying means produces a parabolic modulation when scanning raster lines near top and bottom of said raster that is different than when scanning raster lines near raster center for correcting said residual raster distortion due to the aspherically curved geometry of said faceplate.
New, flatter faceplate picture tubes, such as the RCA Corporation square-planar picture tubes, have aspherically curved faceplate contours. A tube of this type, having a complex curvature faceplate, is described in the following U.S. patent applications, herein incorporated by reference.
1. U.S. patent application Ser. No. 469,772, filed Feb. 25, 1983, by F. R. Ragland, Jr. entitled CATHODE-RAY TUBE HAVING AN IMPROVED SHADOW MASK CONTOUR.
2. U.S. patent application Ser. No. 469,774, filed Feb. 25, 1983 by F. R. Ragland, Jr. entitled CATHODE-RAY TUBE HAVING A FACEPLATE PANEL WITH A SUBSTANTIALLY PLANAR PERIPHARY.
3. U.S. patent application Ser. No. 469,775, filed Feb. 25, 1983, by R. J. D'Amato et al., entitled CATHODE-RAY TUBE HAVING DIFFERENT CURVATURE ALONG MAJOR AND MINOR AXES.
4. U.S. patent application Ser. No. 529,644, filed Sept. 6, 1983, by R. J. D'Amato et al., entitled CATHODE-RAY TUBE HAVING A FACEPLATE PANEL WITH AN ESSENTIALLY PLANAR SCREEN PERIPHERY.
In one form of flatter faceplate picture tube, as typified by the RCA 110° COTY-SP, square-planar, 27 V, color television picture tube, A68ACC10X, the formula for the tube faceplate sagittal height, z, in millimeters, with reference to the center of the faceplate is given by: Z=A 1 X 2 +A 2 X 4 +A 3 Y 2 +A 4 X 2 Y 2 +A 5 X 4 Y 2 +A 6 Y 4 +A 7 X 2 Y 4 +A 8 X 4 Y 4 ,
where X and Y are the distance coordinates, in millimeters, from the faceplate center along the major and minor axes, respectively, and where: A 1 =-0.236424229×10 -4 A 2 =-0.363538575×10 -8 A 3 =-0.422441063×10 -3 A 4 =-0.213537355×10 -8 A 5 =+0.883912220×10 -13 A 6 =-0.100020398×10 -9 A 7 =+0.117915353×10 -14 A 8 =+0.527722295×10 -21
The picture tube faceplate defined by this formula has a relatively shallow curvature near the center of the faceplate, which increases near the edges along paths parallel to both the major and minor axes of the tube. The overall result is a faceplate of relatively flat appearance and with planar edges, namely, with points along the top, bottom, right and left edges located substantially in a common plane.
In general, the raster scanned on the phosphor screen of a picture tube may exhibit an east-west or side pincushion raster distortion. This distortion may be substantially corrected by a side pincushion correction circuit that produces a parabolic amplitude modulation of the horizontal deflection current. The required vertical rate parabola voltage may be obtained from the vertical deflection circuit by integration of the vertical sawtooth current.
When using such a conventional circuit for raster correction in a picture tube, such as a square-planar picture tube that has an aspherically curved faceplate, a small but often objectionable raster distortion may remain at the top and bottom of the display, as illustrated by the solid vertical lines of a raster R display R in FIG. 1. Due to the aspherically curved geometry of the faceplate, the vertical line bend away from the vertical direction near the top and bottom of the raster display, where the curvature of the faceplate increases. The overall appearance of the vertical lines in FIG. 1 is slightly barrel-shaped.
In accordance with an aspect of the invention, a video display apparatus includes a picture tube having a phosphor screen located on a faceplate having an aspherically curved geometry. Correction circuitry is provided that compensates for raster distortion or electron beam positioning errors, such as pincushion or convergence distortions. The correction circuitry includes a parabola generator coupled to deflection circuitry for producing a parabolic modulation of the scanning of the electron beam. The modulation generally provides correction of the raster distortion or electron beam positioning error, while retaining a residual error due to the aspherically curved geometry of the faceplate. The modulation is nonlinearly modified in accordance with the aspherically curved geometry to provide additional modulation of the scanning of the electron beam for correcting the residual error.
In accordance with another aspect of the invention, a particularly advantageous arrangement of correction circuitry smoothly straightens the bent vertical lines near the top and bottom of the raster display illustrated in FIG. 1.
The parabola generator of the correction circuit arrangement produces a generally parabolically shaped input voltage repeating at a deflection rate. An amplifier drives an output stage that generates current in a deflection winding to control the electron beam landing position. The amplifier is responsive to the output of the parabola generator for driving the output stage in accordance with the parabolically shaped input voltage to generally correct electron beam landing error, while retaining a residual error. A current source with a switched current dividing network is responsive to a threshold level of the parabolically shaped input voltage for supplying to the amplifier a portion of the current from the current source when the input voltage exceeds the threshold level to correct the residual error.
FIG. 1 illustrates vertical lines of a raster display scanned on the screen of a square-planar picture tube;
FIG. 2 illustrates in block diagram form raster scanning circuitry used in conjunction with raster scanning on the aspherically curved faceplate of a square-planar picture tube, shown schematically in FIG. 2 from a side elevation view, in partial breakaway;
FIG. 3 illustrates detailed embodiments of the horizontal and vertical deflection circuits of FIG. 2, including circuitry embodying the invention that corrects for the residual side pincushion distortion illustrated in FIG. 1;
FIG. 4 illustrates a detailed embodiment of a portion of the circuit of FIG. 3; and
FIG. 5 illustrates waveforms useful in explaining operation of the circuits of FIGS. 3 and 4.
In FIG. 1, there is illustrated vertical lines of a raster display R that is generated on the phosphor screen of a faceplate 30 of a square-planar picture tube SP of FIG. 2. Horizontal and vertical deflection circuits 20 and 40 of FIG. 2 generate horizontal and vertical deflection currents in horizontal and vertical deflection windings L H and L V , respectively. The horizontal and vertical deflection currents deflect electron beams 18 in square-planar picture tube SP to produce raster display R on faceplate 30.
Square-planar picture tube SP incorporates a glass envelope 11 comprising a generally rectangular faceplate panel 19 and a tubular neck 14 connected by a funnel 16. Panel 19 comprises viewing faceplate 30 and a peripheral flange or side wall 12, which is sealed to funnel 16 by a glass frit 17. A generally rectangular 3-color cathodoluminescent phosphor screen 15 is carried by the inner surface of faceplate 30. The screen may be a line screen, with the phosphor lines extending substantially parallel to the minor or vertical axis Y--Y of the tube. Alternatively, the screen may be a dot screen. A multi-aperture color selection electrode or shadow mask 13 is removably mounted within panel 19 in predetermined spaced relation to screen 15. An electron gun 10, shown schematically by dashed lines in FIG. 2, is centrally mounted within neck 14 to generate and accelerate the three electron beams 18 along convergent paths through mask 13 to screen 15.
The line and field deflection currents in line and field deflection windings L H and L V , respectively, subject the three electron beams 18 to vertical and horizontal magnetic flux that scans the beams horizontally in the direction of the major or horizontal axis X--X and vertically in the direction of the minor axis Y--Y, in a rectangular raster pattern over screen 15. The longitudinal axis of picture tube SP is labeled Z--Z in FIG. 2.
Faceplate 30 of square-planar color picture tube SP is relatively flat. The curvature of the faceplate is complex and may be approximated in accordance with the polynominal expression given above. In the field scanning direction, or as the electron beams are scanned from top edge to bottom edge, vertically, the curvature of the faceplate decreases from top edge to center and then increases again to the bottom edge. A similar situation holds in the line scanning direction.
Assume that horizontal and vertical deflection circuits 20 and 40 of FIG. 2 correct for distortions such as S-distortion, north-south and gullwing distortion. Furthermore, assume that horizontal deflection circuit 20 generally corrects for side pincushion distortion by parabolically modulating the amplitude of the horizontal deflection current. The display of a vertical line pattern on faceplate 30 by means of raster line scanning produces a raster display such as illustrated in solid-line in FIG. 1. The generally vertical lines exhibit a residual distortion at the top and bottom of the raster which, due to the aspherically curved geometry of faceplate 30, causes the vertical raster lines to be bent inward toward the center in a barrel-like manner.
In accordance with a feature of the invention, horizontal deflection circuit 20 nonlinearly modifies the parabolic modulation of the horizontal deflection current to straighten the vertical lines at the top and bottom of the raster, as illustrated by the dashed-line, straight line segments of FIG. 1.
FIG. 3 illustrates detailed embodiments of vertical deflection circuit 40 and horizontal deflection circuit 20 of FIG. 2 that include nonlinear waveshaping circuitry in accordance with an aspect of the invention. In horizontal deflection circuit 20 of FIG. 3, a B+ voltage is applied to the primary winding W p of a flyback transformer T1 via a small valued resistor 21. A capacitor 22 provides filtering. Primary winding W p is coupled to a horizontal output stage 70 of horizontal deflection circuit 20. Horizontal output stage 70 includes a horizontal oscillator and driver 25, a horizontal output transistor Q1, a first retrace capacitor C R1 coupled across transistor Q1, a damper diode D2, a second retrace capacitor C R2 coupled across diode D2 and the series arrangement of a linearity inductor 26, and S-shaping capacitor C s , deflection winding L H of FIG. 2, and a resonant circuit 27, comprising a capacitor C1 in parallel with the inductance of a tapped winding W1 of a transformer T2. Deflection winding L H is coupled to the tap terminal of winding W1.
Resonant circuit 27 is tuned to produce approximately two cycles of oscillation during the horizontal trace interval for introducing an oscillatory current component into horizontal deflection current i H that provides dynamic S-correction of the raster scanned on faceplate 30 of square-planar picture tube SP of FIG. 1. The function of dynamic S-correction, resonant circuit 27 is more fully described in U.S. Pat. No. 4,563,618, by P. E. Haferl, issued Jan. 7, 1986, entitled S-CORRECTED DEFLECTION CIRCUIT.
To provide side pincushion correction, the amplitude of horizontal deflection current i H is modulated at a vertical rate by a side pincushion correction modulator circuit 30 that drives horizontal output circuit 70. Side pincushion correction circuit 30 includes a damper diode D3 with a grounded anode and a cathode coupled to the anode of damper diode D2, a retrace capacitor C R3 coupled across diode D3, a modulator choke inductor L m coupled to the junction of retrace capacitors C R2 and C R3 , and a modulator control circuit 60 coupled to choke L m .
Modulator control circuit 60 modulates at a vertical rate the modulator current i m in choke L m , to concurrently modulate the retrace pulse voltage V Rm developed across modulator retrace capacitor C R3 . The modulation of retrace pulse voltage V Rm produces a concurrent but opposite sense modulation of deflection retrace pulse voltage V Rd across deflection retrace capacitor C R2 . The vertical rate modulation of deflection retrace pulse voltage V Rd produces the required vertical rate modulation of horizontal deflection current i H that provides side pincushion correction.
The opposing sense modulation of retrace pulse voltages V Rd and V Rm produces an unmodulated retrace pulse voltage V R at the collector of horizontal output transistor Q1. Retrace pulse voltage V R is applied to the primary winding W p of flyback transformer T1 for generating an unmodulated retrace pulse voltage V RH at a terminal A of a secondary winding W s . An unmodulated retrace pulse voltage is also generated in a high voltage winding W HV for developing an ultor accelerating potential at a terminal U of a high voltage generating circuit 23.
FIG. 3 also illustrates a detailed embodiment of vertical deflection circuit 40 of FIG. 2. Vertical deflection circuit 40 includes a vertical deflection amplifier U1 coupled to vertical deflection winding L V of FIG. 2 for generating a vertical deflection current i V that deflects the electron beams in picture tube SP of FIG. 2 in the vertical direction. Vertical deflection winding L V is coupled to a north-south and gullwing distortion correction circuit 34 for modulating vertical deflection current i V in a manner that corrects both north-south pincushion distortion and gullwing distortion of the raster when scanning raster lines on square-planar picture tube SP of FIG. 2. A description of the operation of north-south pincushion and gullwing correction circuit 34 may be found in U.S. patent application Ser. No. 719,227, filed Apr. 2, 1985, by P. E. Haferl entitled NORTH-SOUTH PINCUSHION CORRECTED DEFLECTION CIRCUIT, now U.S. Pat. No. 4,668,897 and in U.S. patent application Ser. No. 733,661, filed May 10, 1985, by P. E. Haferl et al, entitled GULLWING DISTORTION CORRECTED DEFLECTION CIRCUITRY FOR A SQUARE-PLANAR PICTURE TUBE, both herein incorporated by reference.
Vertical deflection current i V , after passing through correction circuit 34, flows through a coupling or vertical S-shaping capacitor C V and a current sampling resistor R s . Coupling capacitor C V intergrates vertical deflection current i V to develop across the capacitor between terminals 35 and 36 an AC parabola voltage, of almost ideal waveshape, that repeats at the vertical deflection rate. The voltage across capacitor C V comprises the AC parabola voltage superimposed upon a DC level established by vertical deflection amplifier U1. The voltage V sV developed across current sampling resistor R s is illustrated in FIG. 5a and comprises an AC, S-shaped, sawtooth voltage repeating at the vertical deflection rate. The voltage V1 developed at terminal 35 is illustrated in FIG. 5b and equals the sum of the voltages developed across capacitor C V and resistor R s . Thus, the AC component of voltage V1 during the vertical trace interval t 3 -t 7 of FIG. 5b is a generally parabolically shaped voltage that is skewed downward by the relatively small sawtooth voltage component derived from sampling resistor R s .
The voltages at terminals 35 and 36 are applied to vertical deflection amplifier U1 to provide DC and AC feeback, respectively, to the amplifier. The vertical rate voltages V1 and V sV , the horizontal rate retrace pulse voltage V RH and a voltage V ds developed across winding W2 of transformer T2 are coupled to correction circuit 34 to provide deflection synchronization information and to provide waveform information that produces the required waveshaping and modulation of vertical deflection current i v , as described in the aforementioned U.S. patent applications.
Vertical deflection circuit 40 may be considered as a low impedance voltage source 48 that generates parabola voltage V1 at output terminal 35 of the source.
Vertical parabola voltage V1 is nonlinearly waveshaped by a nonlinear network 50 and is then applied via a DC blocking capacitor C2 and a parabola amplitude adjusting potentiometer R a to the noninverting input terminal of an amplifier U2 of side pincushion control circuit 60. Vertical sawtooth voltage V sV is applied to the inverting input terminal of amplifier U2 via the wiper arm of a trapeze adjusting potentiometer R t and a resistor 31. The DC level at the inverting input terminal is controlled by a width adjusting potentiometer 33 that couples a +25 V source to the inverting input terminal via a resistor 32 and the wiper arm of potentiometer 33. The output of amplifier U2 is coupled to an inverting driver stage U3 that applies a modulation voltage V m to modulator choke inductor L m .
Side pincushion control circuit 60 is operated in the switched mode at the horizontal rate. A horizontal sawtooth voltage generator 29, synchronized by horizontal retrace pulse voltage V RH , applies a horizontal rate sawtooth voltage V sH to the noninverting input terminal of amplifier U2 via a resistor R g . Resistor R g represents the effective source impedance of sawtooth voltage generator 29. The output of amplifier U2 is a pulse width modulated, horizontal rate voltage having a duty cycle that varies at a vertical rate. Modulation voltage V m therefore is also a pulse width modulated, horizontal rate voltage having a duty cycle that varies at a vertical rate. This enables the drive provided by side pincushion modulator circuit 30 to be varied in a manner that corrects side pincushion distortion.
Side pincushion modulator circuit 30 operates in a manner similar to that described in U.S. patent application Ser. No. 651,301, filed Sept. 17, 1984, now U.S. Pat. No. 4,634,937 by P. E. Haferl, entitled EAST-WEST CORRECTION CIRCUIT. Other side pincushion correction circuits, such as switched mode diodc modulator circuits, may be used to drive horizontal output stage 70.
In accordance with an aspect of the invention, nonlinear waveshaping network 50 is interposed between terminal 35 and the noninverting input terminal of amplifier U2 of side pincushion control circuit 60. Nonlinear network 50 modifies the waveshape of parabola voltage V1 at terminal 35 to generate a modified parabola voltage V2 at a terminal 37, as illustrated by the solid-line waveform of voltage V2 in FIG. 5f. Shaped parabola voltage V2 is then applied to the noninverting input terminal of amplifier U2 via AC coupling capacitor C2 and potentiometer R a . The additional waveshaping provided by nonlinear network 50 corrects the residual side pincushion error that would otherwise exist when scanning a raster on the phosphor screen of a square-planar picture tube.
Nonlinear waveshaping network 50 comprises a constant current source CS in series with a potentiometer R2 that is coupled to the wiper arm of trapeze adjusting potentiometer R t . A diode D1, functioning as a unidirectional switch, is coupled between the wiper arm of potentiometer R2 and terminal 37, with the cathode of diode D1 being coupled to terminal 37.
In operation, constant current source CS generates an almost ideal constant current i 0 , illustrated in FIG. 5d, that does not significantly change in value throughout the entire vertical deflection interval t 3 -t 8 . Diode D1 is reverse biased by voltage V2 during the interval t b of FIG. 5. During this interval, all of current i 0 that flows into end terminal 38 of potentiometer R2 flows out of the other end terminal 39, as illustrated in FIG. 5c by the current i 3 during the interval t b . Current i 3 flows in that portion R2b of potentiometer R2 between intermediate wiper arm terminal 41 and end terminal 39 coupled to the wiper arm of potentiometer R t . The solid-line waveform of FIG. 5c also illustrates the voltage V3 developed by current i 3 in resistance R2b.
When diode D1 is nonconductive, during the interval t b of FIG. 5, constant current source CS advantageously establishes an adjustable DC bias voltage level V b at intermediate wiper arm terminal 41, as illustrated by the dotted-line waveform of FIG. 5c. Voltage V b equals the constant voltage level V 0 that is established for voltage V3 by constant current source CS, summed with the vertical sawtooth voltage developed at the wiper arm of trapeze adjusting potentiometer R t . Illustratively, voltage level V 0 is shown in FIG. 5c at a level established by the wiper arm of potentiometer R2 when the wiper arm is in a centered position.
When diode D1 is nonconductive, voltage V1 is divided by a voltage divider (R1, R a , R b , R g ) coupled between terminal 35 and the noninverting input terminal of amplifier U2 for developing voltage V2 at terminal 37, which terminal is an intermediate point of the voltage divider. As illustrated in FIGS. 5b and 5f, voltages V1 and V2 exhibit substantially the same waveshape during the interval t b .
During the second half of vertical trace, after the center of trace instant t 5 , voltages V1 and V2 decrease in amplitude. Near time t 6 , voltage V1 has decreased to a threshold voltage level V' al and voltage V2 has decreased to a threshold voltage level V a1 . The decreased voltage V2 at terminal 37 near time t 6 or time t 1 , enables diode D1 of nonlinear waveshaping circuit 50 to begin conducting, thereby coupling together terminals 37 and 41.
Diode D1 continues to conduct throughout the interval t a of FIG. 5. During this interval, voltages V1 and V2 are below the threshold levels V' a2 and V a2 , respectively. At the end of the interval t a , near time t 9 or time t 4 , voltages V1 and V2 have increased sufficiently to reestablish at terminal 41 the bias voltage level V b of FIG. 5c that forces diode D1 to become nonconductive.
During the interval t a , when diode D1 is conductive, a portion of constant current i O of FIG. 5d, that flows in the upper resistance portion R2a of potentiometer R2, is shunted away from resistance R2b via the wiper arm of potentiometer R2 and diode D1. The shunt current i c in diode D1 is illustrated in FIG. 5e during the interval t 1 -t 4 or t 6 -t 9 . Current i c substracts from constant current i 0 when diode D1 is conductive to reduce the amplitude of current i 3 in resistance R2b by the amount of current shunted. As illustrated in FIG. 5c, current i 3 , during the interval t a , has the same waveshape as current i c of FIG. 5e, but inverted in phase.
The waveshape of current i c is determined in accordance with the waveshape of the parabolic component of voltage V1 that is applied to the voltage divider (R1, R2b) formed whendiode D1 is conductive. The amplitude of current i c is related to the difference in value between the bias voltage level V b and the parabolic voltage V1.
Correction current i c , flowing into terminal 37, modifies the waveshape of voltage V2 during the interval t a to correct the residual side pincushion error that would otherwise exist in raster display R of FIG. 1. Correction current i c flows mainly in resistor R1 to provide an additional voltage drop between terminals 37 and 35 that produces a flatter slope to the sides of parabola voltage V2 during the conduction interval t a of diode D1.
The solid-line waveform of FIG. 5f during the interval t a illustrates voltage V2 with diode D1 conducting. The dashed-line waveform illustrates the waveshape that voltage V2 would have assumed had diode D1 remained nonconductive during the interval t a . Comparing the solid-line waveform with the dashed-line waveform in FIG. 5f, one notes that the presence of nonlinear network 50 waveshapes parabola voltage V2 during the intervals t 3 -t 4 and t 6 -t 7 , when the top and bottom of the raster are being scanned.
The flattening of parabola voltage V2 occurs when the raster lines between lines L3 and L4 and between lines L6 and L7 of FIG. 1 are being scanned. This flattening produces less modulation of the amplitude of deflection current i H when scanning the top and bottom raster lines. The result of the nonlinear waveshaping is the straightening of the bent vertical line segments of raster display R of FIG. 1 to correct the residual side pincushion error caused by the increased curvature of the faceplate of a square-planar picture tube in the top and bottom regions of the faceplate.
FIG. 4 illustrates a more detailed embodiment of a portion of the circuitry of FIG. 3 that includes nonlinear network 50. Items in FIGS. 3 and 4 similarly identified perform similar functions or represent similar quantities.
Inverting driver stage U3 comprises a switching transistor Q2 driven at its base by amplifier U2 and having its collector coupled to choke inductor L m and its emitter coupled to ground. During those intervals within each horizontal deflection cycle that transistor Q2 is cutoff, modulator current i m flows to the B+ supply via a flywheel diode D4. DC biasing for transistor Q2 is established by voltage dividing resistors 42 and 43. To provide stabilized operation of driver transistor Q2, negative feedback from the collector of the transistor to the noninverting input terminal of amplifier U2 is provided via a resistor 44.
Horizontal sawtooth generator 29 comprises an RC network including a resistor 45 coupled to flyback transformer terminal A and a capacitor 46 coupled to the noninverting input terminal of amplifier U2. DC biasing of the noninverting input terminal is provided by resistor R b . Horizontal retrace pulse voltage V RH is integrated by the RC network to develop the horizontal sawtooth voltage V sH that produces the horizontal rate switching of transistor Q2. The duty cycle of the horizontal rate switching is modulated by means of the vertical rate modulation of the AC-zero level of voltage V sH .
In FIG. 4, constant current source CS comprises a DC voltage source of relatively large magnitude, such as the 140 volt, B+ voltage source, coupled to a resistor R3 of relatively large value, such as 180 kilohm. The amplitude of constant current i 0 is mainly determined by the value of the B+ voltage divided by the sum of the values of resistors R3 and R2. Current i 0 establishes an adjustable bias voltage level V b at the wiper arm of potentiometer R2 that maintains diode D1 nonconductive during the interval t b of FIG. 5 when parabola voltage V1 is sufficiently large in amplitude to keep the diode reverse biased. During the remaining interval t a , parabola voltage V1 is sufficiently small in amplitude to enable diode D1 to shunt some of current i 0 away from resistance portion R2b of potentiometer R2 to provide the correction current i c that waveshapes parabola voltage V2.
Advantageously, diode D1 is DC coupled to parabola voltage source 48 via resistor R1, with the cathode of diode D1 being coupled on the DC side (with respect to parabola voltage V1) of coupling capacitor C2. By means of the DC connection of diode D1 to parabola voltage source 48, the diode switching instants t 4 and T 6 may be adjusted by potentiometer R2 independently of the adjustment of east-west parabola amplitude potentiometer R a . When potentiometer R a is adjusted for the desired parabola amplitude, the AC-zero level of the parabola voltage applied to the noninverting input terminal of amplifier U2 also varies. This variation of the AC-zero level has little or no effect on the switching of diode D1.
For example, assume amplitude potentiometer R a is adjusted to provide the proper amount of side pincushion correction when the central raster lines are being scanned between raster line L4 and raster line L6 of FIG. 1 during the interval t 4 -t 6 of FIG. 5. Potentiometer R2 may then be adjusted to establish a bias voltage level V b that enables diode D1 to switch conductive states near times t 4 and t 6 . The switching of diode D1 near times t 4 and t 6 provides the required additional waveshaping of voltage V2 that corrects the residual side pincushion error in the top and bottom regions of raster display R.
The instants when diode D1 switches conductive states are controlled by the DC bias level V b established by potentiometer R2 rather than by amplitude potentiometer R a . The adjustment of potentiometer R2 has no significant effect on the previous amplitude adjustment provided by potentiometer R a .
When the wiper arm of potentiometer R2 is moved towards end terminal 39, the conduction interval t a of diode D1 decreases and the cutof interval t b increases. The location of raster lines L4 and L6 where nonlinear waveshaping begins moves away from center raster line L5 towards top and bottom raster lines L3 and L7, respectively. The peak downward excursion of voltage V2, that occurs near the beginning of retrace near times t 2 and t 7 , also moves downward toward the dashed-line level that represents the peak downward excursion when diode D1 is cutoff for the entire vertical deflection interval t 2 -t 7 .
The amount of nonlinear waveshaping of parabola voltage V2 may be defined as the voltage difference between the dashed and solid-line waveforms V2 of FIG. 5f at times t 3 and t 7 , the start and end of vertical trace, respectively. This voltage difference relative to the dashed-line waveform V2 represents the amount of correction resulting on the raster display of FIG. 1.
When the wiper arm of potentiometer R2 is moved toward end terminal 38, the amount of nonlinear waveshaping increases until the conduction interval t a of diode D1 equals the nonconduction interval t b . As the wiper arm of potentiometer R2 is moved further toward end terminal 38, the amount of waveshaping begins to decrease and reaches zero when bias voltage level V b is set at a sufficiently high level to enable diode D1 to conduct for the entire vertical deflection interval.
The amplitude of current i c changes when potentiometer R2 is adjusted. However, the peak amplitude that parabola voltage V2 attains remains substantially the same at all levels of adjustment because correction current i c of FIGS. 3 and 4 flows mainly in resistor R1 and does not add any significant charge to AC coupling capacitor C2. No significant portion of current i c flows in capacitor C2 because of the long time constant associated with capacitor C2 and resistors R a , R b , R g . Current i c causes a very small increase of the average DC voltage at terminal 37, not illustrated in waveform FIG. 5. This increase amounts to approximately 75 millivolt, which is 1/4 the voltage difference between the dashed and solid-line waveforms of voltage V2 in FIG. 5f, at times t 3 and t 7 .
When diode D1 becomes conductive, parabola voltage source 48 becomes DC coupled to current source CS. At the same time an additional load impedance becomes coupled to current source CS derived from the voltage divider (R1, R a , R b , R g ). Because of the DC connection provided by diode D1 between the wiper arm of potentiometer R2 and parabola voltage source 48, the additional voltage that is coupled in-circuit with current source CS during the interval t a of FIG. 5 is relatively small. The additional voltage, ΔV3, equals the voltage difference between the constant voltage level V 0 of FIG. 5c and the voltage V3 developed across resistance R2b.
The peak-to-peak amplitude of voltage ΔV3 is relatively small, approximately one volt peak-to-peak for the values given in FIG. 4. Because the peak-to-peak amplitude ΔV3 is much smaller than the B+ voltage of constant current source CS, the shunt current i c that source CS supplies when diode D1 is conductive is also small relative to current i 0 and has substantially no effect on the amplitude of the constant current. For the values given in FIG. 4, the amplitude of current i 0 changes less than one percent during the conduction interval t a shown in FIG. 5.
End terminal 39 of potentiometer R2 may be advantageously coupled to trapeze adjusting potentiometer R t rather than to ground. This connection enables nonlinear network 50 to provide a common-mode rejection of the sawtooth voltage component of parabola voltage V1. Thus, diode D1 nonlinearly waveshapes only the parabolic component of voltage V1 and not the sawtooth component. The common-mode rejection of the waveshaping of the sawtooth component of voltage V1 may be noted from the waveforms of FIGS. 5c and 5e, which are symmetrical about the center of trace instant t 5 .
Nonlinear waveshaping network 50 advantageously produces gradual changes in the slope of parabola voltage V2 at the switching instants of diode D1 that smoothly straightens the bent segments of the vertical lines of raster display R in FIG. 1, without introducing wiggly line excursions of the vertical line pattern near raster lines L4 and L6.
Nonlinear network 50 operates as a current divider to divide current i 0 into current i 3 and current i c during conduction of diode D1. Thus, the change in the forward voltage drop of diode D1, produced by variations in ambient temperature, has little influence on the waveshaping of the parabola voltage.