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One of the first PRANDONI B/W television chassis fully transistorized and with implementation of ASIC ICs ..
The chassis is awesome divided in 2 main panels carrying the power and deflection+EHT and all signal processing part on the left side.
Furthermore the chassis is manis isolated and it's running with low voltages via a transformer for this scope.
Based mainly on TCA311 AND TBA311A17 AND TBA120S (SOUND IF) and many discretes.
NOTE:
- The tuner is directly applicated on the front tuning keyboard assy's.
- The EHT Output is realized with a selenium rectifier.
The EHT selenium rectifier which is a Specially designed selenium rectifiers were once widely used as EHT rectifiers in television sets and photocopiers. A layer of selenium was applied to a sheet of soft iron foil, and thousands of tiny discs (typically 2mm diameter) were punched out of this and assembled as "stacks" inside ceramic tubes. Rectifiers capable of supplying tens of thousands of volts could be made this way. Their internal resistance was extremely high, but most EHT applications only required a few hundred microamps at most, so this was not normally an issue. With the development of inexpensive high voltage silicon rectifiers, this technology has fallen into disuse.
TBA 311 TV SIGNAL PROCESSING CIRCUIT
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The TBA 311 is a monolithic integrated circuit in a 16-lead clual in-line or quad in—Iine
plastic package. It is intended for use as signal processing circuit for black and
white and colour television sets.
The circuit is designed for receivers equipped with tubes or transistors in the deflection
and video output stages, and with PNP or NPN transistors in the tuner and NPN in
the IF amplifier.
Only signals with the negative modulation can be handled by the circuit. The circuit
is protected against short circuit between video output and GND. The TBA 311 includes:
0 VIDEO PREAMPLIFIER with EIMITTER FOLLOWER OUTPUT
0 GATED AGC for VIDEO» IF AMPLIFIER and TUNER
0 NOISE INVERTER CIRCUIT for GATING AGC and SYNC. PULSE SEPARATOR
o HORIZONTAL SYNC. PIULSE SEPARATOR
0 VERTICAL SYNC. PULSE SEPARATOR
0 BLANKING FACILITY for the VIDEO AMPLIFIER.
All circuits were made by:
SGS is Società Generale Semiconduttori - Aquila Tubi E Semiconduttori (SGS-ATES, "Semiconductor General Society - Tubes and Semiconductors Aquila"), later SGS Microelettronica, a former Italian company now merged into STMicroelectronics
- ATES (Aquila Tubi e Semiconduttori), a vacuum tube and semiconductor maker headquartered in the Abruzzese city of l'Aquila, who in 1961 changed its name into Azienda Tecnica ed Elettronica del Sud and relocated its manufacturing plant in the outskirts of the Sicilian city of Catania
- Società Generale Semiconduttori (founded in 1957 by Adriano Olivetti).
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Power supply is realized with mains transformer and Linear transistorized power supply stabilizer, A DC power supply apparatus includes a rectifier circuit which rectifies an input commercial AC voltage. The rectifier output voltage is smoothed in a smoothing capacitor. Voltage stabilization is provided in the stabilizing circuits by the use of Zener diode circuits to provide biasing to control the collector-emitter paths of respective transistors.A linear regulator circuit according to an embodiment of the present invention has an input node receiving an unregulated voltage and an output node providing a regulated voltage. The linear regulator circuit includes a voltage regulator, a bias circuit, and a current control device.
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The bias circuit may include a bias device and a current source. The bias device has a first terminal coupled to the output terminal of the voltage regulator and a second terminal coupled to the control electrode of the current control device. The current source has an input coupled to the first current electrode of the current control device and an output coupled to the second terminal of the bias device. A capacitor may be coupled between the first and second terminals of the bias device.
In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
A circuit is discl
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PLANET (PRANDONI) Mod. 437 CHASSIS MF15-73B B-W TELEVISION DIAGRAM AND DEFLECTION CIRCUIT:
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In present day transistor deflection circuits, for example, those used in the horizontal output stage of a television receiver; the output transistor is normally operated in a switching mode, that is, the transistor is driven into saturation during a trace interval of each deflection cycle and driven out of conduction during the retrace portion of each deflection cycle. By operating the transistor in its saturation region, average power losses are minimized. With saturated operation, however, the accumulation of minority carriers in the base region will effect a continuation in the flow of collector current after the trace interval during the initial portion of the retrace interval while the transistor is being driven into its non-conducting state. In addition to causing this undesirable delay time in turning off the transistor, losses occurring during this period may be localized in small areas commonly referred to as "hot spots." These losses are characterized in being regenerative and tend to cause second breakdown of the device. This effect is explained in greater detail in a paper authored by the present inventor and entitled "Thermal Regeneration in Power Dissipating Elements" which appeared in "The Electronic Engineer" publication in the January 1967 issue. Although operating the horizontal output transistor in its saturated region may reduce the average power dissipated in this device during its conduction interval, it increases the possibility of second breakdown during the turn-off time. With the advent of high voltage (1,500 volts) transistors, it is possible to develop the necessary output energy utilizing one of these transistors which can be operated in a non-saturated mode. The circuit of the present invention insures that the deflection output transistor will not be driven into saturation.
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In the solid state deflection art, however, it is desirable to reduce the turn-off time of the device not to increase the frequency of operation of the circuit, but rather to prevent second breakdown of the device as the relatively large inductive voltage pulse appears during the initial portion of the flyback interval, when current flowing through the deflection winding is interrupted to initiate the retrace portion of each deflection cycle.
The non-saturated operation of the deflection output transistor is achieved in circuits embodying the present invention by automatically holding the collector voltage above the saturation level by shunting excess base drive from the base to emitter junction into the collector circuit. Prior transistor deflection systems employ only the saturated operation of the deflection output device.
Circuits embodying the present invention include a deflection output transistor having a diode coupled between its base and collector terminals and poled to prevent the transistor from being driven into saturation during its conduction period of each deflection cycle.
The invention can be more fully understood by referring to the drawings together with the description below and the accompanying claims.
In the drawings:
FIG. 1 illustrates in block and schematic diagram form, a television receiver including a solid state deflection output stage embodying the present invention;
FIG. 2a is a waveform diagram of the voltage present at the collector terminal 55c of transistor 55 in FIG. 1;
FIG. 2b shows the drive current to terminal A in FIG. 1;
FIG. 2c is a waveform diagram of the current in diode 56 in FIG. 1;
FIG. 2d is a waveform diagram of the base current flowing in transistor 55 of FIG. 1;
FIG. 3 is a schematic diagram of an alternative embodiment of the present invention;
FIG. 4a is a waveform diagram of the voltage appearing at the terminal 366 in FIG. 3;
FIG. 4b is a waveform diagram of the drive current to terminal A in FIG. 3;
FIG. 4c is a waveform diagram of the current in diode 356 in FIG. 3; and
FIG. 4d is a waveform diagram of the base drive current to transistor 355 in FIG. 3.
Referring specifically to FIG. 1,
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The horizontal output stage 50 includes an output transistor 55 having a base, a collector and an emitter terminal 55b, 55c and 55e, respectively. A resistor 52 and a capacitor 53 are coupled in parallel between the horizontal driver stage 48 and the base terminal 55b of transistor 55.
The output stage includes a unidirectional conductive device such as a diode 56 coupled between the base and collector terminals 55b and 55c of transistor 55. Stage 50 also includes a damper diode 57 coupled across transistor 55, a retrace capacitor 58 coupled across transistor 55 and the series combination of a horizontal deflection winding 59 and an S-shaping capacitor 60 also coupled across transistor 55. Output stage 50 also includes a flyback transformer 61 with a primary winding 61p coupled from a source of operating potential (B+) to the collector terminal 55c of transistor 55. A secondary winding 61s on transformer 61 develops high voltage pulses which are coupled to a high voltage rectifier 63 to provide the ultor voltage for application to a terminal 32 on kinescope 30. Flyback transformer 61 may also include additional windings (not shown) for providing, for example, keying pulses to the AGC stage 25.
The output stage 50 in FIG. 1 is a conventional shunt fed trace driven circuit with the exception of the diode 56 and the bias network including resistor 52 and capacitor 53. Beginning at the center of the trace interval of the deflection cycle, the yoke current is zero and capacitor 60 has a maximum charge. The drive signal applied to the base terminal 55b of transistor 55 turns this device on, thereby completing the conduction path for yoke current which includes capacitor 60, yoke 59 and the collector to emitter current path through transistor 55. During this portion of scan the yoke current is supplied by the charge on capacitor 60 and increases to a maximum value in one direction at which time scan retrace is initiated by driving transistor 55 out of conduction by applying an appropriate signal from the driver stage 48 to the base 55b of transistor 55. During the latter portion of the trace interval when the magnitude of the yoke current is increasing, the output transistor of prior circuits is normally driven into saturation and is in this conduction state at the instant retrace is initiated. During the first portion of retrace, the yoke current is at a maximum and resonates with the retrace capacitor 58 by charging capacitor 58 in a polarity to reverse bias the damper diode 57. As the yoke current decreases to zero, capacitor 58 has a maximum charge impressed upon it; and during the second portion of retrace, the capacitor (58) drives current through the yoke in a reverse direction until it is discharged and the voltage across it reverses sufficiently to forward bias damper diode 57. Diode 57 then conducts during this first portion of trace to complete the current path for yoke current which is, at this instant, at a maximum value in a direction in yoke 59 to charge capacitor 60 and is increasing toward zero. At the mid-point of trace the yoke current has reached zero and the cycle is completed by driving transistor 55 into conduction once again.
Turning now to the operation of the circuitry of FIG. 1 including the present invention, reference is made to the waveform diagrams of FIG. 2. The initial portion of trace is represented in FIG. 2 by the time period between t 0 and t 1 in the figure. It is recalled that during this period damper diode 57 is conducting. The voltage at collector terminal 55c of transistor 55 is represented by the voltage waveform (V c ) in FIG. 2a and is equal to the forward voltage drop across diode 57 which is of the order of -0.7 volts. At some non-critical time before t 1 , the horizontal driver 48 provides a drive current (I A ), as is shown in FIG. 2b. This current flows through diode 56 as is illustrated in FIG. 2c, since the diode is forward biased. [The cathode of diode 56 is at the same voltage as collector terminal 55c (-0.07 volts) and the drive current produces a positive voltage at point A which is at the anode of diode 56.] As time t 1 (the center of trace) is reached, damper diode 57 turns off allowing the collector voltage on transistor 55 to increase as shown in FIG. 2a. At the same time, a portion of the drive current flowing into terminal A is conducted by the now forward biased base to emitter junction of transistor 55 as is illustrated by the waveform of FIG. 2d. Transistor 55 is now conducting the increasing yoke current during the latter portion of scan represented by the period from t 1 to t 2 in FIG. 2. As the magnitude of the yoke current increases during the t 1 to t 2 interval, the base current in transistor 55 increases as shown in FIG. 2d. Diode 56 conducts as illustrated in FIG. 2c to shunt the remaining portion of the applied drive current at terminal A. It is noted that the sum of the currents shown in FIGS. 2c and 2d will equal the current shown in FIG. 2b. T
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At time t 2 retrace is initiated by applying a relatively large negative drive signal as shown in FIG. 2b to the base terminal of transistor 55. During the retrace interval (t 2 to t 0 in FIG. 2), the collector voltage increases in a typical manner as illustrated in FIG. 2a. At time t 0 the cycle is again repeated.
The circuit modification illustrated in FIG. 3 is another embodiment of the invention which reduces the change in voltage applied to the yoke 59 of FIG. 1 at time t 1 . As shown in FIG. 2a, when diode 57 turns off and transistor 55 conducts, the voltage at the collector terminal 55c of transistor 55 changes by as much, for example, as 6 volts. This voltage change, which is coupled to the yoke 59, will vary the rate of change of yoke current during the center of trace and may, in certain circuits, cause an undesirable non-linearity in the scanning rate. As FIG. 4a illustrates, the circuit of FIG. 3 reduces this change in voltage at the mid-point of trace (t 1 ).
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During the latter portion of trace, the transistor tends to saturate and the collector voltage at terminal 355c tends to decrease. As this occurs, more current will flow from the B+ terminal through the upper portion of transformer 364. Due to the relatively tight coupling of the segments of transformer 364, terminal 366 experiences a decrease in voltage which controls the forward bias applied to diode 356 to shunt sufficient drive current to hold the transistor 355 out of saturation. The collector voltage of transistor 355 is thus held at some preselected value depending on the location of tap point 365 on transformer 364. Since transformer 364 is utilized, terminal 366 wil
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Although the specific embodiments of the invention are illustrated in the horizontal deflection output stage of a black and white television receiver, the invention has equal applicability to other deflection systems and may be utilized in a color television receiver.
How AFC Circuit Works in B/W Analog Television Receiver:
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If the tuning is not correct then the discriminator output is not zero and if this output is applied to change the reverse bias on a tuning diode mounted in the oscillator section of the u.h.f. tuner it will correct most of the error. Tuning, varicap or varactor diodes-to give them a few of their names-are junction diodes normally operated with reverse bias but not sufficient to bias them into the breakdown region in which zener diodes operate. The greater the reverse bias the lower their capacitance: a typical curve, for the PHILIPS BB105 or STC BA141 tuning diode, is shown in Fig. 2. All diodes e
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Basic AFC System
To return to our TV set, if the oscillator frequency is too high then the vision carrier frequency will also be too high and in the simple arrangement shown in Fig. 3 the discriminator will give a negative signal to decrease the bias on the tuning diode thus increasing its
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AFC Loop Gain:
The amount by which the error is reduced depends on the gain of the circuit. An estimate of the gain required must first be made by guessing how much error is likely to be given by your push -buttons or hand tuning: 1MHz would be an outside figure as a tuning error of that magnitude would produce a very bad picture of low definition in one direction and badly broken up in the other. This error should be reduced to
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EXAMPLE of Circuit Description:
The driver stage Tr1 takes a small sample signal from the i.f. strip but this should be large enough to drive Tr1 into saturation. That is to say Tr1 is a limiter stage so that the signal amplitude applied to the discriminator coil L2 stays constant over the normal range of signal levels. Trl is biased at approximately 7mA which, according to the original report ("Simple a.f.c. system for 625 -line TV receivers" by P. Bissmire, PHILIPS Technical Communications, March, 1970), gives the best limiting performance. C1, R
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The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the developed apparates both tubes or transistors.
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