PHILIPS 14PT1562 CHASSIS L6.1 INTERNAL VIEW.

The PHILIPS CHASSIS L6 is the most compact mini chassis for a color tv.

The chassis was even featured for a 110° degree crt tube large screen (L6.2) but was a nightmare on reliability.

This here was the contrary offering a discrete reliability and durability with good to excellent picture performances.



TDA8361 Integrated PAL and PAL/NTSC TV processor
PHILIPS TDA8362 (TDA8361) MAIN CHARACTERISTICS
The TDA8362 television processor microcircuit contains an intermediate frequency (IF) signal processing circuit, a multi-standard demodulator of a frequency-modulated sound signal, automatically tuned notch and band-pass filters in the video signal processing channel, a luminance signal delay line, a color signal decoder in the PAL and NTSC system with automatic detection systems, TV / AV input selector, RGB signal switching scheme, horizontal and vertical scanning synchronization circuits.
Variant TDA8362A also contains automatic white balance circuits. Thus, the TDA8362 includes all the basic low signal circuits needed to build a color television receiver.
The minimum number of elements connected to external circuits and only one element requiring adjustment (reference circuit of the IF signal demodulator) creates an exceptional usability of the TDA8362. As a result, the TDA8362 processor has become one of the most widely used chips in modern television technology.
The main characteristics of TDA8362 are given in table. 1.

Parameter	Value
Supply voltage	8 ± 0.8
Current consumption, mA	80
Power consumption	0.7
Sensitivity of the IFI, μV	70
Sensitivity UPCHZ, mV	1
Sound signal from an external input, mVeff	350
Video signal from external input, Vp_p	1
Signals at the inputs in RGB, Bn n	0.7
Demodulated PTsTS, Vp-p	2,4
Tuner AGC control current, mA	0 ... 5
The range of voltage changes AFCG, V	6
Audio output signal (vyv. 50), mV	700
Output signals in RGB, Bn_n	4
Horizontal line output current, mA	10
Framing output current, mA	1
Control voltage range, V	0 ... 5

Table 1. Key Features of the TDA8362 Processor

The construction, pinout and basic parameters of all modifications of the TDA8362 microcircuits (with the exception of the TDA8362A variant) are the same. Features of their application will be discussed below.
 

DESCRIPTION OF STRUCTURAL SCHEME

Table 2 gives the pin assignment of TDA8362, and also shows the difference in pinout of the TDA8362 and TDA8362A options.
The latter contains a circuit for automatic white balance, the measuring signal at the input of which comes from pin 14 of TDA8362.

TDA8362	TDA8362A	Pin assignment
1	1	Pre-emphasis correction of sound signal and switching to positive modulation
2	2	IF signal demodulator reference circuit
3	3	IF signal demodulator reference circuit
4	4	Video identification circuit output, sound switch input
5	5	IF signal input and volume control
6	6	Audio input from external connectors
7	7	PCTS output
8	8	Decoupling capacitor of the power supply circuit of the digital part
9	41	Earth 1 (common)
10	10	Power input
eleven	eleven	Earth 2 (common)
12	12	Decoupling capacitor filter settings
thirteen	thirteen	Internal video input
14	14	RF correction circuit adjustment input (sharpness)
fifteen	fifteen	External video input
16	16	Chroma input
17	17	Brightness adjustment
18	18	Exit to
19	19	Output G
20	20	Output R
21	21	RGB switch and blanking output
22	22	Signal output R (from external sources)
23	23	Signal output G (from external sources)
24	24	Signal output B (from external sources)
25	25	Contrast adjustment
26	26	Saturation Adjustment
27	27	Color tone adjustment (or color signal output)
28	28	CV input BY (from delay line)
29th	29th	RRS input RY (from delay line)
thirty	thirty	RCS RY output (to delay line)
31	31	TsRS BY output (to the delay line)
32	32	4.43 MHz reference signal output on TDA8395
33	33	Phase detector filter
34	34	Conclusion connection of a quartz resonator of 3.58 MHz
35	35	4.43 MHz quartz resonator connection terminal
36	36	Power output to trigger horizontal scanning
37	37	Horizontal scan trigger output
38	38	Horizontal Flyback Pulse Input / Gating Pulse Output (SSC)
39	39	Phase Detector Filter 2
40	40	Phase Detector Filter 1
41	42	Frame Reverse Pulse Input
42	43	Conclusion conclusion of an RC chain of ZG frame scan
43	44	Firing trigger pulses output
44	9	AFC output
45	45	IF signal input 1
46	46	IF signal input 2
47	47	AGC circuit output
48	48	A conclusion of the connection of the decoupling capacitor of the AGC circuit
49	49	Tuner AGC adjustment input
fifty	fifty	Sound output
51	51	Conclusion connection output decoupling capacitor demodulator sound
52	52	Decoupling capacitor of the power control circuit

Table 2. TDA8362 Processor Pin Assignment

 IF SIGNAL PROCESSING CIRCUIT
The IF image signal amplifier (IFI) is a three-stage differential amplifier with an adjustable gain and a symmetrical differential input (vyv. 45 and 46 TDA8362). The gain variation range is at least 64 dB. The sensitivity of the IFI (70 μV) is comparable to the parameters of modern specialized TDA8362 IFI.
Maximum input signal up to 100 mV eff. The IF signal is demodulated using a reference carrier frequency generated by passive regeneration of the carrier image. The reference circuit of the demodulator is connected to pin 2 and 3 of the TDA8362. It is the only item that needs to be configured. The demodulator provides the ability to process IF signals with both negative and positive modulation. The automatic frequency control circuit (AFC) generates a signal at pin 44 of TDA8362, which provides tuning of the tuner local oscillator frequency with an error of no more than 50 kHz.
The circuit uses the same reference signal as for the demodulator.
The built-in sampling-storage circuit ensures the protection of the AFC circuit from the penetration of a video signal. A storage capacitor is built into the TDA8362. The steepness of the characteristics of the AFC circuit (33 mV / kHz) directly depends on the quality factor of the reference circuit. To reduce the steepness, a resistor is connected to pin 44 of the TDA8362. The output voltage range is 6 V (at a nominal frequency of 3.5 V). The characteristic of the AFC for the TDA8362-N5 modification is optimized for the European IF standard. The automatic gain control (AGC) circuit generates the control voltage of the amplifier and the tuner (vv. 47 TDA8362), ensuring a constant amplitude of the signals at the input of the amplifier and at the output of the video amplifier.
To exclude the influence of the AGC circuit on the tuner at low levels of the input signal, an AGC response delay is introduced. The delay value is regulated by applying a control voltage to pin 49 of the TDA8362. The voltage variation range is 0.5 ... 4.5 V. The minimum and maximum signal levels at pin 49, at which the tuner AGC is triggered, are 0.2 mV eff and 150 mV eff, respectively.
The AGC detector monitors the amplitude of the clock pulses with negative modulation of the IF signal and white peaks with positive modulation. To ensure noise immunity, the gating of the detector is used. Gating is disabled for the duration of the reverse frame scan. This allows you to avoid changing the amplitude of the video signal in the playback mode from the VCR due to phase shifts that occur during the switching of video heads. A capacitor (usually 2.2 μF) is connected to pin 48 of the TDA8362, which sets the time constant of the AGC circuit.

The external connection of this capacitor provides the flexibility of using the TDA8362. The permissible leakage current of the capacitor is 10 μA for negative and 200 nA for positive modulation. An increase in leakage current degrades the characteristics of the AGC circuit and leads to a change in the amplitude of the video signal during the field. The voltage at the output of the AGC circuit (vyv. 47) is at maximum gain (U pit +1) V and at minimum gain (saturation voltage) - 0.3 V.
Switching the demodulator and the AGC circuit to the IF signal processing mode with positive modulation is carried out by supplying voltage (U pit -1) V to pin 1 of TDA8362. The video signal identification circuit works independently of the synchronization circuit, which ensures that the setting is saved to the received television channel during translation TV to monitor mode.
The circuit generates the following signals at the output (pin 4 of TDA8362):

• voltage no more than 0.5 V in the absence of a video signal (in this case, the sound detector is turned off);
• voltage of 6 V when receiving a signal with a frequency of a subcarrier of color of 3.58 MHz;
• voltage of 8 V when receiving a signal with a frequency of a subcarrier of color 4.43 MHz.

In the modification of TDA8362-N5, an identification mode is provided for tuner detuning. To do this, when the signal is weak, the gating of the tuner AGC circuitry for the time of receiving horizontal synchronization pulses is disabled, which prevents erroneous identification of color subcarrier outbreaks by signals. The video amplifier provides amplification of the detected video signal, matching with the load and limiting noise emissions in the video signal.
The signal amplitude at the output (pin 7 of TDA8362) is 2.4 V. The output impedance of the amplifier is not more than 50 Ohms, the load current is not more than 5 mA. The bandwidth of the video amplifier (at the level of -3 dB) is up to 9 MHz, which makes it possible to use TDA8362 in all broadcasting standards. The emission control scheme provides the inversion of white peaks exceeding 4.8 V, noise emissions having a level below 1.4 V (the tops of the clock pulses have a level of 2 V), and their introduction into the video signal at 3.2 V and 2.6 V , respectively. At the same time, the noise emission inversion circuit only works during the reception of a large signal, since with a weak signal it negatively affects the operation of the audio signal processing channel.
In the modification of TDA8362-N4, an ultra-white peaks binding scheme is used in the video signal. The TDA8362-N5 modification does not use a white peak limiting scheme, since when there are a large number of white peaks, inverting and introducing them at 3.2 V results in the image becoming gray.

SOUND PROCESSING CHAIN

The sound signal to the second PC sound extracted from the full television signal is fed to pin 5 of the television processor (TDA8362). To the same output, a control voltage is supplied through the resistor to adjust the volume. The control voltage range is 0 ... 5 V.
The IF signal of the sound is limited and fed to the demodulator, made in the form of a phase locked loop (PLL). The PLL system is automatically tuned to the input frequency and does not require adjustments. The PLL system capture range is 4.2 ... 6.8 MHz.
The preliminary amplifier (PU) provides amplification of the detected sound signal to a level of 350 mV eff. This signal, which is not adjustable in magnitude, is fed to pin 1 of the TDA8362, to which an external capacitor is connected to correct the distortion of the sound signal, and to the switching and volume control circuitry. PU also provides mute when there is no identification of the video signal.
The signal from pin 1 of the TDA8362 is used to output to external connectors (for example, SCART). The sound signal from external connectors is fed to pin 6 of the TDA8362, its magnitude is 350 mV eff. The switching circuit, controlled by the voltage supplied to pin 16 of the TDA8362, provides for the output of pin 50 of the TDA8362 sound output signal, which then goes to the low-frequency amplifier.
The value of the output signal, which is -6 dB from the maximum is 700 mB eff, when adjusting the volume changes in the range of 80 dB. DC voltage at the terminal 50 TDA8362 3.3 V (when turning off the sound 10 ... 50 mB). The TDA8362-N5 modification provides click protection in the speakers when the sound is turned on, while using the previous TDA8362 modifications, a 290 kOhm resistor was needed between pin 1 of the TDA8362 and the +8 B bus to solve this problem.
Switching the TDA8362 to the signal processing mode with positive modulation is carried out by supplying at least 1 (U pit - 1) V to pin 1 of the TDA8362.

SYNCHRONIZATION CHAIN

The selection of clock pulses (SI) from the video signal arriving at vyv.13 or 15 TDA8362 is carried out by a selector containing an amplifier, an amplitude selector and a circuit for the selection of lowercase and frame SI.
Lower case SIs are supplied to the first phase detector (PD1) and a coincidence detector, which identifies the presence of a video signal and controls the synchronization of the master oscillator (ZG) of horizontal scanning. In the absence of synchronization, the voltage at pin 14 of the TDA8362 becomes low, which can be used to identify the presence of a video signal. PD1, together with a low-pass filter (LPF) connected to pin 40 of TDA8362, and a horizontal scan line generator form a PLL that provides frequency and phase adjustment of the pulse pulses to lower case SI parameters.
The time constant ФД1 is automatically switched (by switching internal resistance) according to the signals from the noise detector and from the coincidence detector. With an increase in the noise level in the video signal at pin 13 of TDA8362, the PD1 time constant increases (the output current is 30 μA). In the absence of a video signal, the time constant increases even more (output current 6 μA), which ensures synchronization in the on-screen display (OSD) mode.
When a normal signal is received, as well as when processing a signal fed to pin 15 of the TDA8362, the time constant decreases (output current 180 μA) to expand the capture band and increase the noise immunity of the synchronization circuit.
To ensure quick compensation of the phase error that occurs in the signal from the VCR when switching the video heads, the time constant is further reduced by about 1.5 times for the reverse scan time of the vertical scan (output current 270 μA). Thus, good synchronization circuit characteristics are achieved both in the case of receiving a weak signal and in the case of signal processing from a VCR.
The video signal span on pin 13 of the TDA8362 (including sync pulses) must be at least 2 V when a normal signal is received. Otherwise, the noise detector will switch the time constant at a lower IF signal level (switching occurs at a signal-to-noise ratio of 20 dB), which will lead to a “jitter” phase of the horizontal scanning signal.
To ensure the independence of the image phase from the horizontal frequency (15.625 or 15.734 kHz), the PD1 static characteristic has a very high slope. Horizontal scanning operates at a double horizontal scanning frequency. Its frequency is automatically calibrated using the tuning circuit by comparing it with the frequency of the generator with quartz stabilization of the color decoder. As a result, the frequency of free oscillations of the GB has a deviation of no more than 2% of the central value. At startup, calibration is always performed with 4.43 MHz quartz, unless the 3.58 MHz quartz forced mode is selected.
The second phase detector (FD2) ensures the formation of horizontal line triggering pulses on pin 37 of the TDA8362 and maintaining the phase of these pulses relative to 3G pulses in the capture mode in PD1. PD2 together with the low-pass filter connected to pin 39 of the TDA8362 and the 3G form a PLL. The initial phase of the image is set by changing the external load connected to pin 39 of TDA8362. The shift range is ± 2 μs when the control current changes within ± 6 μA. The horizontal flyback pulses necessary for the operation of PD2 are received at pin 38 of TDA8362.
At the same output, combined strobe pulses are formed, which are necessary for operation of integrated delay line microcircuits (TDA4661 or TDA4665) and SECAM decoder (TDA 8395).
Gating pulses have the following parameters:

• binding voltage during the reverse pulse: 3 ± 0.4 V;
• voltage during the quenching pulse: 2 ± 0.2 V;
• voltage during the color subcarrier flash: 5.3 ± 0.5 V;
• field blanking pulse width: 14 lines;
• flash highlight pulse width: 3.5 ± 0.2 μs.

When using the TDA8362 in question, X-ray protection can be implemented. For this, the external detector must provide switching of a constant voltage (at least 6 V) on pin 39 of TDA8362. In this case, the formation of horizontal line triggering pulses stops, and the voltage at pin 37 of the TDA8362 becomes approximately equal to the supply voltage. If the voltage on pin 39 returns to its normal level, then trigger pulses reappear on pin 37.
Parameters of pulses of start of horizontal scanning:

• lower level of output voltage: 0.3 V;
• maximum level: U pit;
• pulse duty cycle: 2;
• maximum permissible output current: 10 mA.

The launch of the horizontal scanning line is carried out by applying a voltage of 8 V to terminal 36 of the TDA8362 (minimum starting current of 6.5 mA). It should be noted that it is possible to start when the current is 5.5 mA. At the same time, calibration of the ZG is not carried out and its frequency will be higher than the nominal (maximum frequency deviation is 75%).
 In TDA8362-N5, the maximum trigger pulse frequency is limited to 20 kHz. When the voltage on pin 36 of TDA8362 decreases to 5.8, the formation of start pulses immediately stops. If the pre-start mode of the ЗГ is not used, then pin 36 and 10 of the TDA8362 are connected to the 8 V power bus. With separate power supply, the voltage at pin 36 must always be greater than or equal to the voltage at pin 10 of the TDA8362.

The control pulses for the HR horizontal scan, which is a sawtooth voltage generator, are obtained by dividing the frequency of the horizontal horizontal scan.
The frequency divider has two operating modes.
The “large window” mode is activated when there is no synchronization or when a non-standard signal is received (the number of lines in a half-frame is from 311 to 314 in 50 Hz mode and from 261 to 264 in 60 Hz mode). In this case, the divider is in search mode and switches from a frequency of 45 Hz to a frequency of 64.5 Hz.
The narrow window mode is activated when more than 15 consecutive frame sync pulses are detected.
This is the standard mode of operation. In the absence of clock pulses, the reverse motion of Zr turns on at the end of the half-frame (window), which ensures minimal image distortion.
The divider switches back to search mode if there are no frame sync pulses for 6 consecutive periods of frame scan. To pin 42 of TDA8362 is connected an external RC chain of a 3G frame scan.
The amplitude of the sawtooth voltage at pin 42 is 1.5 ... 1.8 V. At pin 41 of the TDA8362, reverse-frequency pulses of a vertical sweep (from the output stage) are applied to ensure the linearity of the output voltage.
The constant voltage on pin 41 is 2.5 ± 0.5 V, the alternating voltage is 1 V. In the TDA8362, the kinescope is protected against burn-through in the event of a frame scan failure, which dampens the rays when the direct voltage on pin 41 of the TDA8362 increases or decreases by 1 5 in (relative to the above). Framing control pulses are formed on pin 43 of TDA8362. The maximum and minimum voltage are respectively 4 and 0.3 V.
The maximum permissible output current is 1 mA. The delay in turning on the vertical scan at power-on is 140 ms, and the output voltage is high. When you start the HR frame scan is turned on at a frequency of 60 Hz.
In the TDA8362-N5 modification, the launch is carried out at a frequency of 50 Hz, which is used for the on-screen display. The voltage at pin 43 of the TDA8362 when turned on is low, which makes it easier to start the frame sweep.
TDA8362 synchronization circuit The TDA8362 provides reliable horizontal and frame synchronization of the image when processing a signal from a VCR, both in the case of phase displacement of the clock pulses (with a stretched tape), and in the case of playing back video tapes with copy protection.

TDA8362 VIDEO PROCESSING CIRCUIT
The full color television signal allocated on pin 7 of the TDA8362 passes notch filters to suppress the second intermediate frequency of the sound and goes to pin 13 of the TDA8362 (internal signal). On pin 15 of the TDA8362, a signal is supplied from external inputs (external signal).
The signal swing at pin 13 (including sync pulses) is 2 ... 2.8 V, and at pin 15 is TDA8362 1 ... 1.4 V. Switching the input video signal is carried out by a switching circuit controlled by voltage level on pin 16 of TDA8362 (U 16). At U 16 <0.5B, internal video and audio signals are processed (a notch filter that suppresses the color signal is turned on). With 3 <U16 <5V, external video and audio signals in the S-VHS standard are processed. In this case, a color signal is supplied to pin 16 of the TDA8362, and a brightness signal to pin 15. The notch filter is disabled in this mode. At U16> 7.5 V, external video and audio signals are processed (notch filter on).
The TDA8362 contains notch and bandpass filters to separate color and luminance signals.
The filter tuning scheme provides automatic adjustment of the filters in accordance with the frequency of the crystal oscillator included in the decoder. A pin 12 of the TDA8362 is connected to a decoupling capacitor of the tuning circuit.

In modification TDA8362-N5, the resonant frequency of the notch filter during signal processing in the SECAM system is reduced to 4.2 MHz to provide better suppression of the DR and DB subcarriers in the luminance signal. Filters are calibrated during the reverse frame scan. The luminance signal enters the delay line (480 ns) and the RF correction circuit, which provides an increase in the frequency response in the high-frequency region, and then to the matrixing circuit. pin 14 TDA8362 is used to control the RF correction circuit (image sharpness). The control voltage range is 0 ... 5 V. When a voltage of 7 V is applied to pin 14, the correction circuit is switched off (nominal mode). In the absence of a video signal, the current consumed by TDA8362 according to pin 14 increases to 1 mA (in versions N3 and N4 - up to 200 μA). The voltage on pin 14 is reduced. This information can be used to identify the video signal.

 The color signal is fed to a band-pass filter and an amplifier with AGC, and then to a decoder, which includes a generator with quartz frequency stabilization, a color difference signal demodulator (CRS), and a color off circuit.
The generator generating the signal of the reference subcarrier, the PD, and the low-pass filter connected to pin 33 of the TDA8362 form a PLL system that provides synchronization in frequency and phase of the signals of the reference subcarrier with a color burst signal (SCC). Quartz resonators are connected to pin 34 and 35 of the TDA8362, while a resonator with a frequency of 4.43 MHz is connected to pin 35. This frequency is used for calibrating 3G horizontal scanning, and to pin 34 - a resonator with a frequency of 3.58 MHz.
When using one quartz or connecting two quartz to one pin (usually to pin 34) and using an external switching circuit, pin 35, the TDA8362 is connected to the power bus through a 47 kOhm resistor. This ensures the forced inclusion of the generator.

When using modifications N4 and N5 TDA8362, the value of the resistor is reduced to 8.2 kOhm. This is essential to enable 3G line scan calibration. The system's automatic detection circuitry provides recognition of color signals in PAL and NTSC systems and switching of signal processing circuits.
To process the color signal in the SECAM system, a TDA8395 decoder is used, to which a 4.43 MHz reference signal is supplied from pin 32 of the TDA8362. The amplitude of the reference signal is 0.25 ± 0.5 V. In the case of identifying a color signal in a PAL or NTSC system, the voltage at pin 32 of the TDA8362 is 1.5 V. If there is no identification, the color scheme disables the outputs of the demodulator central circuit (pin 30 and 31) , and the voltage on pin 32 of the TDA8362 increases to 5 V. This voltage blocks the TDA8395 color shutdown circuit in m / s and connects its outputs to the central control system.

The current consumed by TDA8395 with pin 32 of TDA8362 when identifying a color signal in the SECAM system is 150 μA. Increasing the current to this value forces the TDA8362 to SECAM mode. In this case, the system automatic detection circuit does not search for color signals in PAL and SECAM systems. Forcing the TDA8362 to NTSC mode is not possible.

The color signal for the TDA8395 can be obtained on pin 27 of the TDA8362 by connecting this output to the power bus via a 4.7 ... 12 kΩ resistor. The signal span is 330 mV. This combination of chips can only be used as a PAL / SECAM decoder. In the case of color signals processing, PAL / SECAM / NTSC systems use an external color signal extraction circuit for TDA8395.

It should be noted that when using modifications N4 and N5 of TDA8362, to prevent erroneous identification of the signal from the video recorder in the SECAM system as NTSC, it is necessary to provide a voltage at the terminal 27 of TDA8362 of at least 6 V.

FEATURES
Available in TDA8360, TDA836

1
and TDA8362
· Vision IF amplifier with high
sensitivity and good differential
gain and phase
· Multistandard FM sound
demodulator (4.5 MHz to 6.5 MHz)
· Integrated chrominance trap and
bandpass filters (automatically
calibrated)
· Integrated luminance delay line
· RGB control circuit with linear RGB
inputs and fast blanking
· Horizontal synchronization with two
control loops and alignment-free
horizontal oscillator without
external components
· Vertical count-down circuit
(50/60 Hz) and vertical preamplifier
· Low dissipation (700 mW)
· Small amount of peripheral
components compared with
competition ICs
· Only one adjustment (vision IF
demodulator)
· The supply voltage for the ICs is
8 V. They are mounted in a shrink
DIL envelope with 52 pins and are
pin compatible.
Additional features
TDA8360
· Alignment-free PAL colour decoder
for all PAL standards, including
PAL-N and PAL-M.
TDA8361
· PAL/NTSC colour decoder with
automatic search system
· Source selection for external
audio/video (A/V) inputs (separate
Y/C signals can also be applied).
TDA8362
· Multistandard vision IF circuit
(positive and negative modulation)
· PAL/NTSC colour decoder with
automatic search system
· Source selection for external
A/V inputs (separate Y/C signals
can also be applied)
· Easy interfacing with the TDA8395
(SECAM decoder) for
multistandard applications.
GENERAL DESCR

IPTION
The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
deflection.
Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.
The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
possible).
The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.
For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.

TDA8361
The TDA8361 has the following
differences to the pinning:
Pin 1: only audio de-emphasis
Pin 27: only hue control
Pin 32: 4.43 MHz output for TDA8395
is not connected.
FUNCTIONAL DESCRIPTION
Video IF amplifier
The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.
The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.
In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.
The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.
The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.
The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.
To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.
The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependen

t on the frequency of the
incoming chrominance signal.

Sound circuit
The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.
The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of -6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.
The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.
Synchronization circuit
The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
amplitude.
The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.
The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
typical value.
The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.
X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.
The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8

V supply line.
The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.
Integrated video filters
The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
decoder.
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.
When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
applications.
The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.
Colour decoder
The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.
TDA8360
This IC contains only a PAL decoder.
Depending on the frequency of the
crystals which are connected to the IC
the decoder can demodulate all PAL
standards. Because the horizontal
oscillator is calibrated by using the
crystal frequency as a reference the
4.4 MHz crystal must be connected to
pin 35 and the 3.5 MHz crystal to
pin 34. When only one crystal is
connected to the IC the other crystal
pin must be connected to the positive
supply rail via a 47 kW resistor. For
applications with two 3.5 MHz
crystals both must be connected to
pin 34 and the switching between the
crystals must be made externally.
Switching of the crystals is only
allowed directly after the vertical
retrace. The circuit will indicate
whether a PAL signal has been
identified by the colour decoder via
the saturation control pin.
When two crystals are connected to
the IC the output voltage of the video
identification circuit indicates the
frequency of the incoming
chrominance signal.

The conditions are:
· Signal identified at
fosc = 3.6 MHz; VO = 6 V
· Signal identified at
fosc = 4.4 MHz (or no colour);
VO = 8 V.
This information can be used to
switch the sound bandpass filter and
trap filter.
TDA8361
This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5 kW or 10 kW resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.
TDA8362
In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
decoder TDA8395.
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 mA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R-Y and B-Y outputs
and increase the voltage level on
pin 32.
This voltage will switch off the
colour-killer in the TDA8395 and
switch on the R-Y and B-Y outputs of
the TDA8395. Forcing the system to
the SECAM standard can be
achieved by loading

pin 32 with a
current of 150 mA. Then the system
manager in the TDA8362 will not
search for PAL or NTSC signals.
Forcing to NTSC is not possible.
For PAL/SECAM applications the
input signal for the TDA8395 can be
obtained from pin 27 (hue control)
when this pin is connected to the
positive supply rail via the 5 kW or
10 kW resistor. An external source
selector is required by the
TDA8395/TDA8362 combination for
PAL/SECAM/NTSC applications.
RGB output circuit
The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.
The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.