It was the first PHILIPS model series type introducing the FSQ Screen type with the 45AX System CRT TUBE with CHASSIS K40:
- Signal processing board + Tuning control drive TRD (Tuning Remote Digital)
- 8204 004 04271 CITAC CONTROL UNIT WITH SAB3035 Computer Interface for Tuning and Control (CITAC)
- 8220 280 3593.2 STEREO MATRIX DECODER UNIT WITH TDA3803A + TBA120S + TC4066B
- 3122 127 37490 8220 280 4514.0 LUMINANCE TRANSIENT IMPROVEMENT (CRISP PICTURE)
- 8222.280.3372.2 AV GROUPING SIGNAL UNIT.
- 3113 108 70060 TELETEXT UNIT WITH SAB5231 + SAA5241P + M2128 + MAB8420P
- 3112 128 01440 SOUND POWER AMPLIFIER + TONE CONTROL WITH + TDA3810 Spatial, stereo and pseudo-stereo sound circuit
(NOTE the RUBYCON ELECTROLYTHICS CAPACITORS)
TDA2545A Quasi-split-sound circuit
GENERAL DESCRIPTION The TDA2545A is a monolithic integrated circuit for quasi-split-sound processing in television receivers. Features · 3-stage gain controlled i.f. amplifier · A.G.C. circuit · Reference amplifier and limiter amplifier for vision carrier (V.C.) processing · Linear multiplier for quadrature demodulation.TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
TDA3803A Stereo/dual TV sound decoder circuit
GENERAL DESCRIPTION The TDA3803A is a stereo/dual TV sound decoder circuit with static switching for processing two AF signals in TV and VCR equipment. The LOW/HIGH static switching signals control the AF output selector. Two operational amplifiers perform bandpass filtering of the identification signals. Features · Amplification of the two AF input signals by integrated operational amplifiers · Low distortion stereo de-matrix · All operational amplifiers offset compensated · De-emphasis with operational amplifiers, preferably applied to the output terminals · Two output ports each with two channels for headphones and loudspeakers · Dual sound information at one port, each port individually switchable from sound I to sound II and sound II to sound I · Mute function; while mute is active, it is possible to connect an external mono AF input signal to pin 10 appearing at pins 20 to 23. · Identification without additional signals (horizontal etc.)TDA1524A Stereo-tone/volume control circuit
GENERAL DESCRIPTION The device is designed as an active stereo-tone/volume control for car radios, TV receivers and mains-fed equipment. It includes functions for bass and treble control, volume control with built-in contour (can be switched off) and balance. All these functions can be controlled by d.c. voltages or by single linear potentiometers. Features · Few external components necessary · Low noise due to internal gain · Bass emphasis can be increased by a double-pole low-pass filter · Wide power supply voltage range.TDA3810 Spatial, stereo and pseudo-stereo sound circuitDESCRIPTION The TDA3810 integrated circuit provides spatial, stereo and pseudo-stereo sound for radio and television equipment. Features · Three switched functions: – spatial (widened stereo image) – stereo – pseudo-stereo (artificial stereo from a mono source) · Offset compensated operational amplifiers to reduce switch noise · LED driver outputs to facilitate indication of selected operating mode · Start/stop circuit to reduce switch noise and to prevent LED-flicker · TTL-compatible control inputs.
MAB8420P
8-Bit Microcontroller-Microcomputer
Various
8-Bit Microcontrollers
Clock Frequency - Max. (Hz)=4.43M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=16
Number of Addressing Modes=5
On-Chip RAM (Bytes)=64
On-Chip ROM (bytes)=2k
Number of Interrupt Lines=1
Number of Maskable Interrupts=1
Vsup Nom.(V) Supply Voltage=5.0
Status=Discontinued
Package=DIP
Pins=N/A
Military=N
Technology=NMOS
SAB3035 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)
GENERAL DESCRIPTION
The SAB3035 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver
FUNCTIONAL DESCRIPTION
The SAB3035 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).
The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50 l
PHILIPS 27CS6895 CHASSIS K40 Circuit for improving picture quality in a television receiver:
1. A circuit for improving picture quality in a television receiver adapted to receive video signals, with light picture areas corresponding to a high video signal level bounded by inclined rising and falling edges, comprising, means for forming a differentiated video signal from the received video signal, means for adding the differentiated video signal to the falling edge of the received video signal in phase opposition to the received video signal, a terminal for receiving the video signal, a differentiation stage including said means for forming a differentiated video signal connected to said terminal for forming respective positive and negative pulses corresponding to the inclined rising and falling edges of the high video signal level, amplifier and phase shifter means connected to said differentiation stage for inverting said pulses, phase clipper means connected to said amplification and phase shifter means for clipping the negative pulse, and adder means including said means for adding connected to said pulse clipper means and to said terminal for adding the differentiated, inverted and clipped video signal from said pulse clipper means only to the falling edge of the received video signal from said terminal.2. A circuit for improving picture quality in a television receiver according to claim 1 further including a phase shifter connected to said adder means, a decoupler connected to said phase shifter, said decoupler adapted to be connected to a chroma unit of the television receiver, said decoupler being connected to a velocity modulation circuit which is connected to a deflection coil of the television receiver.
Description:
FIELD AND BACKGROUND OF THE INVENTION The present invention relates in general to circuits for improving the quality of a television picture and, in particular to, a new and useful circuit for improving picture quality in a television receiver where light picture areas correspond to a high video signal level bounded by inclined rising and falling edges and where a pulse is added to the falling edge of the high video signal level.
As is known, the video signal obtained from the IF-stage is transmitted in a television receiver directly or over filters to the chroma-stages or the electron beam tube. The video signal originally supplied by a television station has a band width of about 5 MHz. Due to errors in the receiving station and band limitations in the transmission of the signal or filter with limited pass range, it is not possible in practice to reproduce the entire originally emitted frequency spectrum on the picture screen. The result is that steep black and white transitions are blurred or fine structures can no longer be recognized on the screen.
Various methods have been suggested in the literature to increase the picture quality on the picture screen by which the picture definition can be more or less improved. In the so-called aperture compensation method, the intensity of the electron beam is first reduced in those parts of the picture where the brightness passes from a low to a high level or vice versa by adding a twice differentiated video signal to the video signal, and then increasing it again or vice versa. Peak levels in the brightness of the compensated video signal may lead to beam currents which are substantially increased, compared to the beam currents existing in the original video signal, so that the picture elements on the picture screen increase again and the method does not lead to the desired result.
In order to eliminate this drawback, DOS No. 23 47 573 suggests a method for producing rapid brightness variations on a picture screen, where a control signal characterizing the amplitude value of the video signal is derived from the video signal, which is used to vary the horizontal deflection velocity. In this method the video signal is differentiated twice, and the deflection velocity of the electron beam is modulated with this signal in the line direction by a special deflection coil. In order to effect the modulation of the deflection velocity at the same point where the video signal jumps, it is necessary to delay the video signal by a delay line for a certain time interval. Since the video signal is fed in this method uninfluenced to the cathode, the deflection velocity modulation method does not lead to a variation of the size of the luminous spot, so that this method offers certain advantages over the aperture compensation method. A disadvantage of this method is that light or white areas of the reproduced picture are narrowed in the line direction, so that the information is falsified.
DOS No. 27 53 196 describes a method which uses the deflection velocity modulation method in combination with a waveform circuit. It starts from the known velocity modulation method, but it avoids the disadvantage that the white portions are narrowed in the video signal. The waveform circuit used contains an OR-gate circuit which receives the uninfluenced video signal and a video signal delayed over a delay line, so that a widened video signal appears at the output of the waveform circuit. In addition, the deflection velocity modulation method is used, so that a picture appears on the picture screen whose white portions are reproduced in the correct width, but the picture has still a greater definition. This method required a delay arrangement in the waveform circuit.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a circuit which increases picture definition of a reproduced video signal, leaves the width of the reproduced white and black portions unchanged, and is simple in design without needing a delay arrangement. The circuit of the invention requires no delay arrangement and still has the effect that the picture appears much sharper without any loss of information.
Accordingly, an object of the present invention is to provide a circuit for improving picture quality in a television receiver adapted to receive video signals, with light picture areas corresponding to a high video signal level bounded by inclined rising and falling edges comprising, means for forming a differentiated video signal from the received video signal, and means for adding the differentiated video signal to the falling edge of the received video signal in phase opposition to the received video signal. A further object of the present invention is to utilize pulse clipper means in the circuit for rendering the differentiated video signal unidirectional.
A still further object of the present invention is to provide a circuit for improving picture quality in a television receiver wherein the means for adding the differentiated video signal to the falling edge of the received video signal in phase opposition to the received video signal is adjustable.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure.
- Deflection Board on the right called large signal board. Line deflection output (BU508A) + EHT, E/W
Correction, FRAME Deflection Output with IC TDA3650 (PHILIPS)
Chrominance + Luminance with TDA3561A,
GENERAL DESCRIPTION
The TDA3561A is a decoder for the PAL colour television standard. It combines all functions required for the identificationand demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
Synchronization With TDA3576B.12V 70mA sync combination with transmitter identification and vertical 625 divider system
PHILIPS TDA3576B SYNC COMBINATION WITH TRANSMITTER IDENTIFICATION
AND VERTICAL 625 DIVIDER SYSTEM.
GENERAL DESCRIPTION
The TDA3576B is a monolithic integrated circuit for use in colour television receivers. The circuit is
optimized for a horizontal and vertical frequency ratio of 625.
Features
• Horizontal sync separator (including noise inverter) with sliding bias such that the sync pulse is
always sliced between top sync level and blanking level
• Phase detector which compares the horizontal sync pulse with the oscillator voltage; this phase
detector is gated
• Phase detector which compares the horizontal flyback pulse with the oscillator voltage
• Horizontal oscillator (31,25 kHz)
• Time constant switching of the first control loop (short time constant during catching and reception
of VCR signals)
• Burst key pulse generator (sandcastle pulse with three levels)
• Very stable automatic vertical synchronization due to the 625 divider system, without delay after
channel change
• Vertical sync pulse separator
• Three voltage level sensor on coincidence detector circuit output
• Video transmitter identification circuit for sound muting and search tuning systems
• Inhibit of vertical sync pulse when no video transmitter is detected.
FUNCTIONAL DESCRIPTION
The video input voltage to drive the sync separator must have negative-going sync, which can be
obtained from synchronous demodulators such as TDA2540 and TDA2541.
The slicing level of the sync separator is determined by the value of the resistor between pins 6 and 7. A
4, 7 kr2 resistor provides a slicing level midway between the top sync level and the blanking level. Thus
the slicing level is independent of the amplitude of the sync pulse input at pin 5.
The nominal top sync level at pin 5 is 3 V, and the amplitude selective noise inverter is activated at
0,7 V.
To
obtain good stability the circuit contains three control loops. In the
first loop the phase of the horizontal sync pulse is compared with a
reference output pulse from the horizontal oscillator. In the second
loop the phase of the flyback pulse is compared with the same reference
output pulse. The first loop is designed for good noise immunity and the
second loop has a fast time constant to compensate quickly for storage
variations of the output stage. The second loop also generates a gating
signal of about 5,5 μs for use in the transmitter identification
circuit. The third control loop generates a second gating signal which
is used in the first phase detector. The pulse width is typically 14 μs.
For a short catching time the output current of the first phase
detector is not gated but is increased by 5 times during catching. This
is caused by the voltage of the coincidence detector at pin 9. For VCR
playback conditions the first control loop must be forced to a fast time
constant, this is achieved by applying an external voltage of~ 2,7 V to
pin 9.
The free running output frequency of the horizontal
oscillator is 31,25 kHz. The vertical frequency output is obtained by
dividing this double horizontal frequency by 625. The double horizontal
fre- quency is fed via a binary divider to provide the normal 15,625 kHz
horizontal output to pin 11. The sandcastle pulse is generated at pin 2
and has three levels. The burst key pulse is of short duration,
typically 4 μs, with an amplitude of 10 Vandis the highest level. The
second level has a pulse duration equal to the horizontal flyback pulse
with an amplitude of 4,5 Vandis used for horizontal blanking. The third
level, amplitude 2,5 V, is used for vertical blanking and has a pulse
duration of 1,34 ms. The last pulse is internal Iv generated by the
divider circuit and is only available when a standard video input signal
is received. An external vertical blanking pulse can be added to this
pin via a suitable series resistor. This pulse will be automatically
clamped to 2,5 V.
The automatic vertical sync block contains the following:
• 625 divider
• In/out-sync detector
• Direct/indirect sync switch
• Identification circuit
It
is fed by a signal obtained by integration of the composite video
signal and an internally generated, clipped video signal. The vertical
sync pulse is sliced out of this integrated signal by an automatically
biased clipper. The video part of the signal helps to build up a
vertical sync when heavy negative-going reflections (mountains) distort
the video signal. The in/out sync-detector considers a signal
out-of-sync when fourteen or more successive incoming vertical sync
pulses are not in phase with a reference signal from the 625 divider.
Therefore a distorted vertical sync signal needs only one
out-of-fourteen pulses to be in phase to keep the system in sync. When
the fifteenth successive out-of-sync pulse is detected, the
direct/indirect sync switch is activated to feed the vertical sync
signal directly out of the block at pin 3 (direct sync vertical output).
At the same time the 625 divider is reset by one of the sync pulses.
After the reset pulse, if the 7th sliced vertical sync pulse coincides
with a 625 divider window, the sync output pulse is presenteu again by
the divider system and switch-over to indirect mode occurs. In the
direct mode, every 7th non-coinciding sliced vertical sync pulse will
reset the counter. A non- standard video signal will result in
continuous reset pulses and the direct/indirect switch will remain in
the direct position.
To avoid delay in vertical synchronization, caused by waiting time of the divider circuit after channel
change or an unsynchronized camera change in the studio, information is fed from the horizontal
coincidence detector to the automatic switch for the vertical sync pulse. The loss of horizontal
synchronization sets the automatic switch to direct vertical sync.
When an external voltage between 2,7 V and 8,2 V is applied via pin 9 to the coincidence detector, the
horizontal phase detector is switched to a short time constant and the automatic switch to direct
vertical sync. A voltage level on pin 9 between 9,2 V and 12 V switches the horizontal phase detector
to a short time constant, without affecting the indirect/direct vertical sync system which remains
operational. Thus when standard signals are received vertical sync pulses are generated by the divider
system.
To avoid disturbance of the horizontal phase detector by the vertical sync pulse the 625 divider system
generates an anti-top-flutter pulse. This pulse is applied to the phase 1 detector when a standard video
signal is received. The anti-top-flutter pulse is also active for standard VCR signal conditions, voltage at
pin 9;;. 9,2 V.
The video transmitter identification circuit detects when a sync pulse occurs during the internal 5,5 μs
gating pulse. This indicates the presence of a video transmitter and results in the capacitor connected
to pin 1 being charged to 8,4 V. When no sync pulse is present the capacitor discharges to< 1 V. The
voltage at pin 1 is compared with an internal d.c. voltage. The identification output at pin 18 is active
when pin 1 is.;; 1,5 V (no video transmitter) and inactive (high impedance) when pin 1 is> 3,5 V,
this information can be used for search tuning.
The vertical sync output pulse at pin 3 is inhibited when no video transmitter is identified, which
prevents interference or noise affecting the frequency of the vertical output stage. This results in a
vertical stable picture, plus vertical stable position information for tuning systems.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (pin 17) Vp = V17-10 max. 13,2 v
Total power dissipation max. 1200 mW
Storage temperature range -55 to + 125 oc
Operating ambient temperature range -25 to +65 oc
THERMAL RESISTANCE From junction to ambient (in free air) Rthj-a 50 K/W
The function is described against the corresponding pin number.
1. Video transmitter identification
A 47 nF capacitor must be connected to this pin. It charges to a level of 8 V when a sync pulse is
detected, and discharges to a level of< 1 V when no sync pulse is detected.
2. Sandcastle output pulse
This output has three levels. The first and highest level (10 V) is the burst key pulse with a typical
duration of 4,0 μs. The second level, for the horizontal blanking, is typically 4,5 V with a pulse duration
equal to the horizontal flyback pulse. For the third level an external vertical flyback pulse must be
applied to this pin. This pulse will be clamped to 2,5 V by an internal clamping circuit. The input
current is typically 2 mA.
3. Vertical output pulse
This pulse is obtained from the 625 divider circuit when standard input signals are received or from the
sync separator when the signals are non-standard. The pulse is inhibited when no video transmitter is
detected. Both pulses have good stability and accuracy and are used to trigger the vertical oscillator.
4. Vertical sync pulse integrator biasing network
The vertical sync pulse is obtained by integrating the composite sync signal in an internal RC-network. An
external capacitor of 10 μF is required for biasing the vertical sync separator, this provides the vertical
sync output pulse with a delay of 37 μs. This value can be changed by an external resistor. A resistor of
470 kn between pin 3 and +12 V gives a delay of 45 μs.
5. Video input
The video input signal must have negative-going sync pulses. The top-sync level can vary between 1 V
and 3,5 V without affecting the sync separator operation. The slicing level is fixed at 50% for the
sync pulse amplitude range 0,1 to 1 V which provides good sync separation down to pulses with an
amplitude of 100 mV peak-to-peak. The slicing level is increased for sync pulses in excess of 1 V
peak-to-peak. The noise gate is activated at an input level< 1 V, thus when noise gating is required the
top sync level should be close to the minimum level of 1 V.
6. Sync separator slicing level output
The sync separator slicing level is determined on this pin. A slicing level of 50% is obtained by
comparing this level with the black level of the video signal, which is detected at pin 7.
7. Black level detector output
The black level of the input signal is detected on this pin. This is required to obtain good sync
separator operation. A 22 μF capacitor in series with a resistor of 82 n must be connected to this pin.
A 4,7 kU resistor connected between pins 6 and 7 results in a slicing level of 50%.
8. Horizontal phase detector output and control oscillator input
The flywheel filter must be connected to this pin. Typical values for the components are a capacitor of
100 nF in parallel with an RC-network of 1 kr2 and 10 μF. Furthermore, a resistor of 270 kH should
be connected between pins 8 and 13 to limit the free running frequency drift.
The output current of the phase detector depends on the condition of the coincidence detector. The
output current is high when the oscillator is out-of-sync. The result is a large catching range, and the
phase detector not gated. The output current is low when the oscillator is synchronized and the phase
detector is gated; this provides good noise immunity.
9. Coincidence detector output
A 1 μF capacitor must be connected to this pin. The output voltage depends on the oscillator condition
(synchronized or not) and on the video input signal. The following output voltages can occur:
• when in-sync
1,3 V
• when out-of-sync
2,7 V
• during noise at the input
2, 1 V
There are two switching levels at pin 9. At the first switching level when the output voltage is< 2, 1 V,
the phase detector output is low and the gating of the phase detector is switched on. When the output
voltage is> 2,7 V, the output current of the phase detector is high and the gating of the phase detector
is switched off. The result is a large catching range and a high dynamic steepness of the PLL. At the
second switching level when the output voltage is> 9,2 V the sync system is switched to a short time
constant while the indirect/direct vertical sync system remains fully operational. This condition is
suitable for VCR application.
10. Negative supply (ground)
11. Horizontal sync pulse output
This is an open collector output. The collector resistor mus be chosen such that sufficient current is
supplied
to the driver stage. The maximum current is 60 mA. The circuit is
designed such that the horizontal output transistor cannot be switched
on during flyback, but is switched on directly after flyback.
12. Control voltage second loop
This voltage controls the output pulse at pin 11 (positive-going edge). The capacitor connected to this
pin must have a minimum value of 6,8 nF. A higher value decreases the dynamic-loop gain in the second
control loop. When a high dynamic-loop gain is not required a capacitor value of 100 nF is recommended.
Horizontal shift is possible by applying an external current to pin 12.
13. Reference voltage control loops
The reference voltage must be decoupled by a capacitor of 10 μF.
14. Decoupling internal power supply
The IC has two power terminals. The main terminal (pin 17) supplies the output stages, the sync
separator and the divider circuit. The specially decoupled terminal (pin 14) supplies the horizontal
oscillator. The decoupling capacitor should be 22 μF.
15. Flyback input pulse
This pulse is required for the second phase control loop and for generating the horizontal blanking
pulse in the sandcastle output. The input current must be at least 0,2 mA and not exceed 3 mA.
16. RC-network horizontal oscillator
Stable components should be chosen for good frequency stability. For adjusting the frequency a part of
the total resistance must be variable. This part must be as small as possible, because of poor stability of
variable carbon resistors. The oscillator can be adjusted when pins 8 and 13 are short circuited (see Fig. 3).
17. Positive supply
The supply voltage may vary between 10,5 and 13,2 V. The current-draw is typ. 70 mA and the range is
50 to 85 mA.
·
18. Video transmitter identification output
This is an emitter-follower output which will be inactive (high-impedance) when the level at pin 1 is
> 4 V (video transmitter detected). The output will be active high when the level at pin 1 is< 1,7 V
(no videotransmitterdetected).This feature can be used for search-tuning and sound-muting.
- Audio amplifier Unit.
- Power supply on the bottom of the cabinet (SOPS Supply).
PHILIPS 27CS6895 CHASSIS K40 / PHILIPS CHASSIS K40 Switched-mode self oscillating supply voltage circuit:CHASSIS K40 POWER SUPPLY (SOPS - Self Oscillating Power Supply).
A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of t
1. A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage, comprising a transformer having a primary and a feedback winding, a first controllable switch connected in series with the primary winding, the series arrangement thus formed being coupled between terminals for the input voltage, a second controllable switch coupled via a turn-off capacitor to the control electrode of the first switch to turn it off, means coupling the feedback winding to said control electrode, a transf
ormer winding being coupled via a rectifier to an output capacitor having terminals which supply the output voltage, an output voltage-dependent control voltage being present on a control electrode of the second switch for controlling the conduction period of the first switch, the circuit being switchable between an operating state and a stand-by state in which relative to the operating state the supply energy supplied to the load is considerably reduced, a starting network connected to a terminal for the input voltage, means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off, a connection which carries current during the conduction period for the second controllable switch being provided between the starting network and said second switch, and means providing a connection between the starting network and the control electrode of the first switch, which connection does not carry current in the stand-by state.2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.
4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.
Description:
The invention relates to a switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage. This circuit comprises a transformer having a primary and a feedback winding and a first controllable switch arranged in series with the primary winding. The series arrangement thus formed is coupled between the terminals of the input voltage. A second controllable switch which is coupled via a turnoff capacitor to the control electrode of the first switch to turn it off. The feedback winding is coupled to this control electrode and the primary winding is coupled via a rectifier to an output capacitor the terminals of which are the terminals for the output voltage. An output voltage-dependent control voltage is present on a control electrode of the second switch for controlling the conduction period of the first switch. The circuit is switchable between an operating state and a stand-by state in which relative to the operating state the energy supplied to the load is considerably reduced, and the circuit further comprises a starting network connected to a terminal for the input voltage. Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
In the stand-by state the transistor is non-conducting in a large part of the period of the generated oscillation so that little energy is stored in the transformer. However, the starting resistor is connected via a diode to the second controllable switch, which is a thyristor. As the sum of the voltages across these elements is higher than the base-emitter threshold voltage of the transistor, the diode and the thyristor cannot simultaneously carry current. This implies that current flows through the starting resistor to the base of the transistor via the feedback winding after a capacitor connected to the feedback winding has been charged.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.
The invention will now be further described by way of example with reference to the accompanying drawing, which shows a basic circuit diagram of a switched-mode self-oscillating supply voltage circuit.
The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V B of, for example, 300 V. Voltage V B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2. The series arrangement of a diode D1 and a 2.2 Ohm-limiting resistor R3 is arranged between the other terminal of capacitor C2 and the other end of winding L2 and the series arrangement of a resistor R4 of 12 Ohm and a diode D2 is arranged between the same end of winding L2 and the emitter of transistor Tr1. A 150 nF capacitor C3 is connected in parallel with diode D2. The anode of diode D1 is connected to that end of winding L2 which is not connected to capacitor C2, while the anode of diode D2 is connected to the emitter of transistor Tr1. In the FIGURE the winding sense of windings L1 and L2 is indicated by means of dots.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because of the feedback the described circuit oscillates independently as soon as the steady state is achieved. It will be described hereinafter how this state is obtained. During the time transistor Tr1 conducts the current flowing through the resistor R1 increases linearly. The resistor R4 then partly determines the base current of transistor Tr1. Capacitor C4 and resistor R7 form a voltage source the voltage of which is subtracted from the voltage drop across resistor R1. As soon as the voltage on the base of transistor Tr3 is equal to approximately 0.7 V this transistor becomes conductive, as a result of which the thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive and remains so. Across capacitor C2 there is a negative voltage by means of which transistor Tr1 is turned off. The inverse base current thereof flows through thyristor Tr2, Tr3. This causes charge to be withdrawn from capacitor C2, while the charge carriers stored in transistor Tr1 are removed with the aid of inductance L3. As soon as the collector current of transistor Tr1 has been turned off, the voltage across winding L2 reverses its polarity, which current recharges the capacitor. Now the voltage at the junction of components C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish. Secondary windings L4, L5 and L6 are provided on the core of transformer T with the indicated winding senses. When transistor Tr1 is turned off, a current which recharges a smoothing capacitor C5, C6 or C7 via a rectifier D3, D4 or D5 flows through each of these windings. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in the FIGURE, are, for example, portions of a television receiver.
In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flows via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V B and to a Zener diode Z1 which has a positive voltage of approximately 7.5 V, while the base is unconnected. The other end of diode Z1 is connected to ground. A light-emitting diode D8, whose cathode is connected to the collector of an npn-transistor Tr5, is optically coupled to transistor Tr4. By means of a potentiometer R11 the base of transistor Tr5 can be adjusted to a d.c. voltage which is derived from the voltage V 0 of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V 1 of approximately 13 V. A resistor R12 is also connected to voltage V 1 , the other end of the resistor being connected to the emitter of transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage of approximately 7.5 V and to a smoothing capacitor C10. The other ends of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can be generated by means of a transformer connected to the electric AC supply and a rectifier, which are not shown for the sake of simplicity, more specifically for a remote control to which constantly supply energy is always applied, even when the majority of the components of the receiver in what is referred to as the stand-by state are not supplied with supply energy. The circuit is protected from overvoltage. This is ensured by a thyristor which is formed by a pnp-transistor Tr6 and an npn-transistor Tr7. The anode of a diode D9 is connected to the junction of components R3 and C2 and the cathode to the base of transistor Tr6 and to the collector of transistor Tr7. The base of transistor Tr7, which base is connected to the collector of transistor Tr6, is connected via a zener diode Z3 to a voltage which, by means of a potentiometer R13 is adjusted to a value derived from the voltage across capacitor C7. The emitter of transistor Tr6 also is connected to the voltage of capacitor C7, more specifically via a resistor R14 and a diode D10. If this voltage increases to above a predetermined value then thyristor Tr6, Tr7 becomes conductive. Since the emitter of transistor Tr7 is connected to ground, the voltage at its collector becomes very low, as a result of which diode D9 becomes conductive, which keeps transistor Tr1 in the non-conducting state. This situation is maintained as long as thyristor Tr6, Tr7 continues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
The circuit comprises a 1 MOhm starting resistor R16, one end of which is connected to the base of transistor Tr2 and the other end to the conductor which carries the voltage V B . Upon turn-on of the circuit current flows through resistors R16 and R5 and through capacitor C2, which has as yet no charge, to the base of transistor Tr1. The voltage drop thus produced across resistor R5 keeps transistor Tr2, and consequently also transistor Tr3, in the non-conductive state, while transistor Tr1 is made conductive and is maintained so by this current. Current also flows through winding L2. In this manner the circuit can start as energy is built up in transformer T.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state. If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur.
If in the operating state transistor Tr1 conducts while thyristor Tr2, Tr3 is cut-off, then the current flows through resistor R16 in the same manner as it flows during the start to the base of transistor Tr1, but has relatively little influence as the base current caused by the energy stored in winding L2 is many times larger. If both transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the current through resistor R16 flows through components R5, C2, L2, R4, C3 and R1. In this stand-by state capacitor C2 has indeed substantially no negative charge any longer but, in spite thereof, transistor Tr1 cannot become conductive since no current flows to its base. It will furthermore be noted that the circuit is protected in the event that thyristor Tr2, Tr3 has an interruption. Namely, in such a case the circuit cannot start. In the foregoing a circuit is described which may be considered to be a switched-mode supply voltage circuit of the parallel ("flyback") type. It will be obvious that the invention may alternatively be used in supply voltage circuits of a different type, for example converters of the type commonly referred to as up-converters. It will also be obvious that transistor Tr1 may be replaced by an equivalent switch, for example a gate-turn-off switch.
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PHILIPS 27CS6895 CHASSIS K40 Television receiver including a teletext Videotext decoder circuit :
In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.
1. A receiver for television signal s including a teletext decoder circuit for decoding teletext signals constituted by character codes which are transmitted in the television signal, and comprising:
a video input circuit receiving the television signal and converting it into a serial data flow;
an acquisition circuit for receiving the serial data flow supplied by the video input circuit and selecting that part therefrom which corresponds to the teletext page described by the viewer;
a character generator comprising:
a memory medium addressed by the character codes which together represent the teletext page desired by the user and which in response to each character code successively supply m2 series of m1 simultaneously occurring character picture element codes each indicating wether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m1 character picture element codes of a series one after the other and at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed;
characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulse to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.
2. A character generator for use in a receiver teletext claim 1, comprising:
a memory medium which is addressable by character codes and successively applies m2 series of m1 simultaneously occurring character picture element codes in response to a character code applied as an address thereto, each character picture element code indicating whether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour; a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes and the display clock pulses for supplying the m1 character picture element codes of the series one after the other at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed; characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.
Description:
BACKGROUND OF THE INVENTION 1. Field of the Invention
The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.
2. Description of the Prior Art
As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.
Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.
A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.
For the purpose of display each character is considered as a matrix of m 1 ×m 2 picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m 1 qμsec, each line has a length of 40 m 1 μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m 1 =6 have been chosen.
The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m 1 ×m 2 memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m 1 memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m 1 substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m 1 character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).
OBJECT AND SUMMARY OF THE INVENTION
A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.
According to the invention,
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m 1 clockpulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m 1 picture elements, m 1 reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
REFERENCES
1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.
3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.
4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;
FIG. 2 shows different matrices of picture elements constituting a character;
FIG. 3 shows diagrammatically the general structure of a character generator;
FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 5 shows some time diagrams to explain its operation;
FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 7 shows some time diagrams to explain its operation;
FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.
EXPLANATION OF THE INVENTION
General structure of a TV receiver
FIG. 1 shows diagra
mmatically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2 receiving a television signal modulated on a high-frequency carrier, which signal is processed in a plurality of processing circuits. More particularly, it is applied to a tuning circuit 23 (tuner or channel selector). This circuit receives a band selection voltage V B in order to enable the receiver to be tuned to a frequency within one of the frequency bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning voltage V T with which the receiver is tuned to the desired frequency within the selected frequency band. This tuning circuit 3 supplies an oscillator signal having a frequency of f OSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.
The signal CVBS thus obtained is also applied to a colour decoder circuit 5. this circuit supplies the three primary colour signals R', G' and B' which in their turn are applied via an amplifier circuit 6 to a display device 7 in the form of a display tube for the display of broadcasts on a display screen 8. In the colour decoder circuit 5 colour saturation, contrast and brightness are influenced by means of control signals ANL. The circuit also receives an additional set of primary colour signals R, G and B and a switching signal BLK (blanking) with which the primary colour signals R', G' and B' can be replaced by the signals R, G and B of the additional set of primary colour signals. A Philips IC of the TDA 356X family described in Reference 3 can be used for this circuit 5.
The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency f o from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.
The Philips IC SAA 5030 may be used as video input circuits 91, the Philips IC SAA 5040 may be used as teletext acquisition and control circuit, a 1K8 RAM may be used as page memory, a modified version of the Philips IC SAA 5050 may be used as character generator 94 and a modified version of the Philips IC SAA 5020 may be used as control circuit 95, the obvious modification being a result of the fact that this IC is originally intended to receive reference clock pulses at a rate of 6 MHz for which 13.5 MHz has now been taken.
The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage V B and a given tuning voltage V T so that the receiver is tuned to the desired transmitter.
For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.
The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receiv
es operating instructions and activates, via the bus system 11, one of the circuits connected thereto. It is to be noted that an operating instruction may be a single instruction, that is to say, it is complete after depressing only one key. It may also be multiple, that is to say, it is not complete until two or more keys have been depressed. This situation occurs, for example, when the receiver is operating in the teletext mode. Operation of figure keys then only yields a complete operating instruction when, for example, three figure keys have been depressed. As is known, such a combination results in the page number of the desired teletext page. The character generator
As already stated, a character is a matrix comprising m 2 rows of m 1 picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m 1 =6 and m 2 =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.
FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m 1 ×m 2 memory elements each comprising a character picture element code. Each m 1 ×m 2 char
acter picture element code corresponds to a picture element of the character and defines, as already stated, whether the relevation picture element must be displayed in the so-called foreground colour or in the so-called background colour. Such a character picture element code has the logic value "0" or "1". A "0" means that the corresponding picture element must be displayed in the background colour (for example, white). The "1" means that the corresponding picture element must be displayed in the foreground colour (for example, black or blue). At C in FIG. 2 there is indicated, the contents of the sub-memory for the character shown at B in FIG. 2. The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.
The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.
The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f 0 . In the character generator described in Reference 2, page 391, f 0 is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.
When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f 0 is not a rational multiple of 6 MHz, for example, if f 0 =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.
FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec. An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding network 9442 each time supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse in a group of fourteen reference clock pulses. More particularly the display clock pulse, which is obtained each time in response to the first reference clock pulse of a group, is applied to the output line 9443, whilst the other display clock pulses are applied to the output line 9444. Thus, the pulse series shown at B and C in FIG. 5 occur at these output lines 9443 and 9444, respectively.
The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.
This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register el
ements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422. Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.
The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.
The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.
As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner. In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6
by ensuring that two consecutive picture elements partly overlap each other. This is realized in the converter circuit shown in FIG. 4 by means of a rounding circuit 9427 which receives the character picture element codes occurring at the output of the shift register circuit 9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D flip-flop 9427(2). The T input of this flip-flop receives the clock pulses shown at E in FIG. 5, which pulses are derived from the reference clock pulses TR by means of a delay circuit 9427(3). This circuit has a delay time t 0 for which a value in the time diagram indicated at E in FIG. 5 is chosen which corresponds to half a clock pulse period of the reference cock pulses. The character picture element codes supplied by the shift register circuit 9420 are now applied directly and via the D flip-flop 9427(2) to the OR gate which thereby supplies the six character picture element codes CH(.) in the time intervals as indicated at F in FIG. 5. The result of this measure for the display of the character with the letter A is shown at F in FIG. 2. The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providin
g it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 h
ave the same reference numerals. The converter circuit 942 shown in FIG. 8 differs from the circuit shown in FIG. 6 in that the said rounding circuit denoted by the reference numeral 9428 is incorporated between the pulse widening circuit 9426 and the AND gate circuits 9424(.). More particularly this rounding circuit is a pluriform version of the rounding circuit 9427 shown in FIG. 4 and is constituted by six D flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the respective control signals S(1) to S(6) directly and via the D flip-flops. The T inputs of these D flip-flops again receive the version of the reference clock pulses delayed over half a reference clock pulse period by means of the delay circuit 94210. This rounding circuit thus supplies the control signals S'(.) shown in FIG. 7.
Other References:
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5030 Series", pp. 1-10. Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.
PHILIPS 27CS6895 CHASSIS K40 Teletext / Videotext Error correction circuit using character probability :
An error correction circuit in a television receiver for receiving, for example, Teletext information, Viewdata information or information of comparable systems. The codes representing symbol information received by the receiver are classified into one out of two or more classes in dependence on the frequency of their occurrence, this classification being an indication of the extent to which it is probable that a received code is correctly received.
In FIG. 1, a picture text television receiver has a receiving section, audio and video amplifiers 4 and 9 and a picture tube 10, 11. A text decoder 21 receives symbol information which is stored in a store 25 for display. An error detector circuit 40 including a comparison circuit 43 and two parity circuits 41 and 42, and checks for parity between newly received and already stored symbol information. A reliability circuit 60 is also included.1. An error correction circuit for a receiving device for receiving digitally transmitted symbol information, the transmission of this information being repeated one or more times, the receiving device having a decoding circuit for decoding the received information, an information store coupled to said decoding circuit for storing the information, a circuit for generating synchronizing signals and a video converter circuit coupled to said information store and said generating circuit for converting information and synchronizing signals into a composite video signal for application to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of video lines greater than one, the error correction circuit being coupled to said decoding circuit and said information store and including means coupled between said decoding circuit and said information store for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, a write-switch having one input coupled to said decoding circuit and an output coupled to said information store, and a write-setting circuit, coupled to another input of said write-switch, which determines whether the newly received information is written or not written into the information store, said write-setting circit having an input coupled to said checking means whereby the results of said checking are a factor in the setting of said write-switch by said write-setting circuit, characterized in that the error correction circuit further comprises a classification circuit coupled to the output of said decoding circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, the input of the classification circuit being coupled to another input of the write-setting circuit. 2. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the write-setting circuit includes a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to the information store for accessing the additional storage elements, for determining, from the additional storage element corresponding with the symbol address position of newly received symbol information, a new reliability bit, an output of the reliability circuit being coupled back to the information store for writing this new reliability bit into the corresponding additional storage element when the reliability bit for this symbol address changes its value. 3. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the checking means comprises a comparison circuit for bit-wise comparing a newly received and decoded symbol with a symbol read from an address of the information store, this address corresponding with the symbol location, a comparison output of the comparison circuit being coupled to a further input of the reliability circuit. 4. An error correction circuit for a receiving device as claimed in any one of the preceding claims, characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store. 5. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the reliability circuit comprises a reliability flipflop and a reliability read circuit for this flipflop, an output of which also constitutes the output of the reliability circuit. 6. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the error correction circuit comprises a second classification circuit, coupled between said other classification circuit and said write-setting circuit and having inputs coupled to said information store, for classifying a symbol read from the information store. 7. An error correction circuit for a receiving device as claimed in claim 1 characterized in that the information store comprises, for each symbol address in the information store, at least one further storage element for storing the classification associated with the symbol for that symbol address.
Description:
BACKGROUND OF THE INVENTION
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking.
Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity.
For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 8 ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European languages, in so far they are written in latin characters, have all sorts of "extra" characters, for example Umlaut letters, accent letters, etc. When all these extra characters are totalled, including Icelandic, Maltese and Turkish, then it appears that a total of approximately 220 symbols is required, namely the 128 known symbols plus further symbols for these "extra" characters.
Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds.
As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the symbols for one text line of 40 characters in one video line, whereas on the other hand the average transmission rate decreases if more video lines are needed for the information transmission. This solution is generally considered to be unacceptable, also because the compatibility with existing receivers would be fully lost.
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.
SUMMARY OF THE INVENTION
It is the object of the invention to provide an error correction circuit of the type referred to for a receiving device for Teletext and comparable systems, which offers such a solution for the problem outlined above that also for an 8-bit code without a parity bit substantially all errors, if any, can be corrected in the second transmission cycle which is received.
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A x will never be received as another A-symbol A y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839.
For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be considered to be somewhat suspect. This also applies to each B-symbol recorded in the first cycle, which may lead to a further improvement when a decision is taken.
Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
When the transmitter successively transmits an A-symbol for a certain symbol and location and symbols ABA are successively received, then the A-symbol may be recorded as being "non-suspect" after the first cycle, indicated by an R (reliable) hereinafter. An R' after the second (A), the brackets indicating that the information is retained (not written into the information store) indicates the assumed non-reliability of this retained (A)-symbol, and an A and an R in the third cycle indicates the reliability of the correctly received A-symbol. The A-symbol in the information store is now again assumed to be reliable for this symbol sequence.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for
reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used.
As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.
It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:
In this case only one 8-bit parity circuit is needed.
It is of course alternatively possible to realize the second classification circuit virtually by using the first classification circuit twice on a time-sharing basis, first as the first and then as the second classification circuit. This requires some additional control logic and some additional time, so that the provision of a second classification circuit will be preferred, especially in the case where a simple parity check is performed.
The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A receiving section 1 having an aerial input 2 comprises the high-frequency receiving section, the intermediate-frequency amplifier section, the detection and the synchronizing circuits of the receiver. An audio output 3 is coupled to one or more loudspeakers 5 via an audio amplifier 4. Via control switches 7 and 8 a video output 6 is coupled for normal television reception to a video amplifier 9 for a picture tube 10 comprising the picture screen 11. Via a control switch 13 a synchronizing output 12 is coupled during normal television reception to a time-base circuit 14 which supplies the deflection voltages for the picture tube 10 via an output 15.
However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.
The decision whether the content of the buffer register 23 must be transferred or not transferred to the storage register 24 is taken by an error correction circuit, which would, in the known Teletext system, consist of a parity check circuit.
The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having two inputs and an output. An input 45-i of each of the write switches is always connected to a corresponding output 46-i of the buffer register 23, these outputs also being connected respectively to inputs 47-1 to 47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7 inclusive, of the comparison circuit 43.
The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK R =CLK, obtained from the clock signal generator 29. J R =R/WR G +(R/W)'EP (I) K R =R/WR G +(R/W)'EB (II)
in which R G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2.
Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S x in consecutive cycles 0 to 7, inclusive, indicated as S x ,0 to S x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S 0 to S x -1, inclusive, and S x +1 to S 959 , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.
The states, indicated by an x, of J R and K R are irrelevant for the position of the flipflop. The equations I and II have been chosen thus that the required values "0" and "1" for J R and K R are produced.
FIG. 2 shows the states and EP, EB and R in the line sections 112, 113 and 105, respectively, by means of an example which shows an unprobable burst of received errors, such that each one of the decisions occurs at least once.
When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R G remains "0" because J R =0, K R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.
In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1" at the output "odd parity".
This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:
Again this embodiment can be easily realized by one normally skilled in the art, using what has been described herein.
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking. Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity. For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 8 ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European languages, in so far they are written in latin characters, have all sorts of "extra" characters, for example Umlaut letters, accent letters, etc. When all these extra characters are totalled, including Icelandic, Maltese and Turkish, then it appears that a total of approximately 220 symbols is required, namely the 128 known symbols plus further symbols for these "extra" characters.
Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds. As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the symbols for one text line of 40 characters in one video line, whereas on the other hand the average transmission rate decreases if more video lines are needed for the information transmission. This solution is generally considered to be unacceptable, also because the compatibility with existing receivers would be fully lost.
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.
SUMMARY OF THE INVENTION
It is the object of the invention to provide an error correction circuit of the type referred to for a receiving device for Teletext and comparable systems, which offers such a solution for the problem outlined above that also for an 8-bit code without a parity bit substantially all errors, if any, can be corrected in the second transmission cycle which is received.
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A x will never be received as another A-symbol A y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839. For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be considered to be somewhat suspect. This also applies to each B-symbol recorded in the first cycle, which may lead to a further improvement when a decision is taken.
Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
When the transmitter successively transmits an A-symbol for a certain symbol and location and symbols ABA are successively received, then the A-symbol may be recorded as being "non-suspect" after the first cycle, indicated by an R (reliable) hereinafter. An R' after the second (A), the brackets indicating that the information is retained (not written into the information store) indicates the assumed non-reliability of this retained (A)-symbol, and an A and an R in the third cycle indicates the reliability of the correctly received A-symbol. The A-symbol in the information store is now again assumed to be reliable for this symbol sequence.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for
reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used. As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.
It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:
| TABLE I |
| ______________________________________ |
| Modified Class Symbol (n+1) Parity symbol (n+1) Parity |
| ______________________________________ |
A xxxxxxx 1 1 xxxxxxx 1 1 A xxxxxxx 0 1 xxxxxxx 1 0 B xxxxxxx 1 0 xxxxxxx 0 1 B xxxxxxx 0 0 xxxxxxx 0 0 |
| ______________________________________ |
It is of course alternatively possible to realize the second classification circuit virtually by using the first classification circuit twice on a time-sharing basis, first as the first and then as the second classification circuit. This requires some additional control logic and some additional time, so that the provision of a second classification circuit will be preferred, especially in the case where a simple parity check is performed.
The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A receiving section 1 having an aerial input 2 comprises the high-frequency receiving section, the intermediate-frequency amplifier section, the detection and the synchronizing circuits of the receiver. An audio output 3 is coupled to one or more loudspeakers 5 via an audio amplifier 4. Via control switches 7 and 8 a video output 6 is coupled for normal television reception to a video amplifier 9 for a picture tube 10 comprising the picture screen 11. Via a control switch 13 a synchronizing output 12 is coupled during normal television reception to a time-base circuit 14 which supplies the deflection voltages for the picture tube 10 via an output 15. However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.
The decision whether the content of the buffer register 23 must be transferred or not transferred to the storage register 24 is taken by an error correction circuit, which would, in the known Teletext system, consist of a parity check circuit.
The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having two inputs and an output. An input 45-i of each of the write switches is always connected to a corresponding output 46-i of the buffer register 23, these outputs also being connected respectively to inputs 47-1 to 47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7 inclusive, of the comparison circuit 43. The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK R =CLK, obtained from the clock signal generator 29. J R =R/WR G +(R/W)'EP (I) K R =R/WR G +(R/W)'EB (II)
in which R G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2. Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S x in consecutive cycles 0 to 7, inclusive, indicated as S x ,0 to S x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S 0 to S x -1, inclusive, and S x +1 to S 959 , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.
| TABLE II |
| ______________________________________ |
| Decision Read Write SR EP EB R G 23➝24 Written S R K R |
| ______________________________________ |
1 0 0 0 1 0 0 x 2 1 0 0 1 1 1 x 3 1 1 0 1 1 1 x 5 1 1 1 0 1 x 1 6 1 0 1 0 0 x 0 7 0 0 1 0 0 x 0 (4) 1 0 0 1 0 0 x |
| ______________________________________ |
FIG. 2 shows the states and EP, EB and R in the line sections 112, 113 and 105, respectively, by means of an example which shows an unprobable burst of received errors, such that each one of the decisions occurs at least once. When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R G remains "0" because J R =0, K R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.
In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1" at the output "odd parity".
This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:
| TABLE III |
| ______________________________________ |
| Read Write Written Decision EP R G 23-24 R G |
| ______________________________________ |
1A 1 0 1 1 2A 1 1 1 1 3A 0 0 1 0 4A 0 1 0 0 |
| ______________________________________ |
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.
Testing Flyback Transformer
Nowadays, more and more monitor comes in with flyback transformers problems.
Testing flyback transformer are not difficult if you carefully follow the
instruction. In
many cases, the flyback transformer can become shortcircuit after using not more than 2 years. This is partly due to bad design
and low quality materials used during manufactures flyback transformer.
The question is what kind of problems can be found in a flyback transformer
and how to test and when to replace it. Here is an explanation that will help
you to identify many flyback transformer problems.
There are nine common problems can be found in a flyback transformer.
a) A shorted turned in the primary winding.
b) An open or shorted internal capacitor in secondary section.
c) Flyback Transformer becomes bulged or cracked.
d) External arcing to ground.
e) Internal arcing between windings.
f) Shorted internal high voltage diode in secondary winding.
g) Breakdown in focus / screen voltage divider causing blur display.
h) Flyback Transformer breakdown at full operating voltage (breakdown when under load).
i) Short circuit between primary and secondary winding.
Testing flyback transformer will be base on (a) and (b) since problem
(c) is visible while problem (d) and (e) can be detected by hearing the arcing
sound generated by the flyback transformer. Problem (f) can be checked with multimeter
set to the highest range measured from anode to ABL pin while (g) can be solved by
adding a new monitor blur buster (For 14' & 15' monitor only.) Problem (h) can only be
tested by substituting a known good similar Flyback Transformer. Different monitor have
different type of flyback transformer design. Problem (i) can be checked using an
ohm meter measuring between primary and secondary winding. A shorted turned or open
in secondary winding is very uncommon.
What type of symptoms will appear if there is a shorted turned in primary winding?
a) No display (No high voltage).
b) Power blink.
c) B+ voltage drop.
d) Horizontal output transistor will get very hot and later become shorted.
e) Along B+ line components will spoilt. Example:- secondary diode UF5404 and B+ FET IRF630.
f) Sometimes it will cause the power section to blow.
What type of symptoms will appear if a capacitor is open or shorted in a flyback transformer?
Capacitor shorted
a. No display (No high voltage).
b. B+ voltage drop.
c. Secondary diode (UF5404) will burned or shorted.
d. Horizontal output transistor will get shorted.
e. Power blink.
f. Sometimes power section will blow, for example: Raffles 15 inch monitor.
g. Power section shut down for example: Compaq V55, Samtron 4bi monitor.
h. Sometimes the automatic brightness limiter (ABL) circuitry components will get burned.
This circuit is usually located beside the flyback transformer. For example: LG520si
Capacitor open
a. High voltage shut down.
b. Monitor will have ‘tic - tic’ sound. Sometimes the capacitor may measure O.K. but
break down when under full operating voltage.
c. Horizontal output transistor will blow in a few hours or days after you have replaced it.
d. Sometimes it will cause intermittent "no display".
e. Distorted display i.e., the display will go in and out.
f. It will cause horizontal output transistor to become shorted and blow the power section.
How to check if a primary winding is good or bad in a Flyback Transformer?
a) By using a flyback/LOPT tester, this instrument identifies faults in primary winding by
doing a ‘ring’ test.
b) It can test the winding even with only one shorted turned.
c) This meter is handy and easy to use.
d) Just simply connect the probe to primary winding.
e) The readout is a clear ‘bar graph’ display which show you if the flyback transformer
primary winding is good or shorted.
f) The LOPT Tester also can be used to check the CRT YOKE coil, B+ coil and switch mode power transformer winding.
NOTE: Measuring the resistance winding of a flyback transformer, yoke coil, B+ coil and
SMPS winding using a multimeter can MISLEAD a technician into believing that a shorted
winding is good. This can waste his precious time and time is money.
How to diagnose if the internal capacitor is open or shorted?
By using a normal analog multimeter and a digital capacitance meter. A good capacitor have the range from 1.5 nanofarad to 3 nanofarad.*
1) First set your multimeter to X10K range.
2) Place your probe to anode and cold ground.
3) You must remove the anode cap in order to get a precise reading.
4) Cold ground means the monitor chassis ground.
5) If the needle of the multimeter shows a low ohms reading, this mean the internal capacitor
is shorted.
6) If the needle does not move at all, this doesn’t mean that the capacitor is O.K.
7) You have to confirm this by using a digital capacitance meter which you can easily get one
from local distributor.
8) If the reading from the digital capacitance meter shows 2.7nf, this mean the capacitor is
within range (O.K.).
9) And if the reading showed 0.3nf, this mean the capacitor is open.
10) You have three options if the capacitor is open or shorted.
- Install a new flyback transformer or
- Send the flyback transformer for refurbishing or
- Send the monitor back to customers after spending many hours and much effort on it.
* However certain monitors may have the value of 4.5nf, 6nf and 7.2nf.
Note: Sometimes the internal capacitor pin is connected to circuits (feedback) instead of ground.
Tv rca flyback transformer circuits usually do not have a internal capacitor in it.
If you have a flyback diagram and circuits which you can get it from the net, that would be an advantage to easily understand how to check them.
HR DIEMEN TV FLYBACK TR
AFO HR6040 FOR MODELS BELOW WITH PHILIPS CHASSIS K40:Analogue replacement FBT:KN-381804, F3818, 140.10246, 003390003, 031562, 10810246, 13836070, 13836072, 14010246, 14010269, 16CT4218, 17701MH, 20C051, 22C051, 22C052, 22CS3740, 22CS4360, 22CS4363, 22CS4460, 22CS4560, 22CS4850, 22CS4860, 22CS4861, 22CS5240, 22CS5242, 22CS5250, 22CS5350, 22CS5351, 22CS5355, 22CS5445, 22CS5447, 22CS5735, 22CS5739, 22CS5744, 22CS5745, 22CS5748, 22CS5750, 22CS5751, 22CS5755, 22CS5758, 26CD4895, 26CS4376, 26CS4377, 26CS4378, 26CS4379, 26CS4385, 26CS4386, 26CS4387, 26CS4390, 26CS4391, 26CS4392, 26CS4393, 26CS4396, 26CS4490, 26CS4590, 26CS4880, 26CS4895, 26CS5270, 26CS5272, 26CS5275, 26CS5280, 26CS5380, 26CS5382, 26CS5383, 26CS5385, 26CS5387, 26CS5390, 26CS5395, 26CS5475, 26CS5573, 26CS5577, 26CS5578, 26CS5770, 26CS5774, 26CS5775, 26CS5777, 26CS5780, 26CS5781, 26CS5785, 26CS5787, 26CS5790, 26CS5793, 26CS5795, 26CS5799, 26CS6573, 27CS657302, 27CS6590, 27CS6895, 36070, 36071, 36072, 36073, 36074, 36075, 36076, 36077, 36078, 36079, 37CS5600, 40001M, 4398, 4612080, 56KS4508, 56KS4509, 56KS5402, 56KS5418, 56KS5447, 56KS5457, 56KS5487, 66KS4808, 66KS5617, 66KS5702, 66KS5787, 66KS5917, BACH, BEETHOVEN, BELLINI, BREGENZSTEREO, CHASISK40, CHOPIN, DONATELLO, DONIZETTI, EXPERT, F3818, GIOTTO, GOJA, GOYA, GUARDI, INTERFUNK8349, INTERFUNK8399, INTERFUNK8499, INTERFUNK8599, K40, KN35018N, KN3818, KREFELD, LIPPI, LOT111, LT279P, MAGNASCO, MATCHLINEMONIT, MATCHLINERECEI, ME/540300, ME540300, MICHELANGELO, MORANDI, PHILETTAROYAL, PICASSO, PIRANESI, PUCCINI, REMBRANDT, RO146, ROSSINI, RUBENS, STRAUSS, SUPERSCREEN, TIEPOLO, TIZIANO, TR146, TRR246, TTR246, TURNER, V6720, V6721, V6820, V6821, V6830, V6850, V6851, VANGOGH, VERONESE, VIVALDI.
You can see the complexity of the tellye even only from the wiring around it.
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