SUPPLY 4822 212 20302
MATRIX 3122 133 31460
CHROMA 4822 212 20306
SOUND 4822 212 20599
MULTISTABILIZER 4822 212 20304
IF AMPLIFIER 4822 212 20309
3122 133 31490
E/W + 29 /32/225V SUPPLY 4822 212 20305
SYNCRONIZATION 3122 133 31470
IF DETECTOR 3131 118 58690 4822 212 20438
FRAME DEFLECTION 20AX 4822 212 20303
TRD UNIT 8212 860 06032 SAB2015 SAB2024
OSD TUNING TRD UNIT 8212 860 06083
TDA2581 CONTROL CIRCUIT FOR SMPS
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) E/W CORRECTION Circuit arrangement in an image display apparatus for (horizontal) line deflection:
Line deflection circuit in which the deflection coil is east-west modulated. In order to cancel an east-west dependent horizontal linearity defect the inductance value of the linearity correction coil is made independent of the field frequency, for example by means of a compensating current. In an embodiment this current is supplied by the shunt coil of the east-west modulator.
1. Circuit arrangeme
nt for use with a line deflection coil, said circuit comprising a generator means adapted to be coupled to said coil for producing a sawtooth line-deflection current through said line deflection coil, said deflection current having a field-frequency component current, a horizontal linearity correction coil adapted to be coupled in series with said deflection coil and including an inductor having a bias-magnetized core, and means for making the inductance value of the linearity correction coil substantially independent of the field frequency component current. 2. Circuit arrangement as claimed in claim 1, wherein said making means includes a current supply source means for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the compensating current having a field-frequency variation. 3. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is opposite to the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have the same direction. 4. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is the same as the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have opposite directions. 5. Circuit arrangement as claimed in claim 2, wherein said correction coil further comprises an additional winding disposed on the core, said additional winding being coupled to said supply source means to receive the compensating current. 6. Circuit arrangement as claimed in claim 5, further comprising modulator means for modulating the line deflection current with said field frequency component, said modulator including a compensation coil coupled in series with said additional winding. 7. Horizontal linearity correction coil comprising a core made of a magnetic material and bias-magnetized by at least one permanent magnet, and an additional winding disposed on the core. 8. Image display apparatus including a circuit arrangement as claimed in claim 1.
Description:
The invention relates to a circuit arrangement in an image display apparatus for (horizontal) line deflection, which apparatus also includes a circuit arrangement for (vertical) field deflection, provided with a generator for generating a sawtooth line-frequency deflecting current through a line deflection coil and with a modulator for field-frequency modulation of this current, the deflection coil being connected in series with a linearity correction coil in the form of an inductor having a bias-magnetized core.
By means of the linearity correction coil the linearity error due to the ohmic resistance of the deflection circuit is corrected. The sign
of the bias magnetisation is chosen so that it is cancelled by the deflection current at the beginning of the deflection interval, so that the inductance of the correction coil is a maximum, whereas the voltage drop across the deflection coil then is a minimum. This voltage drop is adjustable by adjustment of the starting inductance of the correction coil. During the deflection interval the core gradually becomes saturated so that the inductance of, and the voltage drop across, the correction coil decrease. Thus the linearity error can be cancelled exactly at the beginning of the interval, that is to say on the left on the screen of the image display tube, and with a certain approximation at other locations.
In image display tubes using a large deflection angle, raster distortion, which generally is pincushion-shaped, of the image displayed occurs. This distortion can be removed in the horizontal direction, the so-called east-west direction, by means of field-frequency modulation of the line deflection current, the envelope in the case of pincushion-shaped distortion being substantially parabolic so that the amplitude of the line deflection current is a maximum at the middle of the field deflection interval.
It was found in practice that the said two corrections are not independent of one another, that is to say the adjustment of the east-west modulation affects horizontal linearity. As long as the modulation depth is not excessive, a satisfactory compromise can be found. However, in display tubes having a deflection angle of 110° and particularly in colour display tubes in which the deflection coils have a converging effect also, it is difficult to find such a compromise. A tube of this type is described in "Philips Research Reports," volume Feb. 14, 1959, pages 65 to 97; the distribution of the deflection field is such that throughout the display screen the landing points of the electron beams coincide without the need for a converging device. Owing to this field distribution, however, the pin-cushion-shaped distortion in the image displayed in the east-west direction is greater than in comparable display tubes of another type. Hence there must be east-west modulation of the line deflection current to a greater depth. It is true that under these conditions horizontal linearity can correctly be adjusted over a given horizontal strip after the east-west modulation has been adjusted correctly, i.e., for a rectangular image, but it is found that in other parts of the display screen a serious linearity error remains. When vertical straight lines are displayed as straight lines in the right-hand part of the screen, they are displayed as curved lines in the left-hand part.
It is an object of the present invention to remove the said defect so that horizontal linearity can satisfactorily be adjusted throughout the screen, and for this purpose the circuit arrangement according to the invention is characterized in that it includes means by which the inductance of the linearity correction coil is made substantially independent of the field frequency.
The invention is based on the recognition that the defect to be removed is due to a field-frequency variation of the said inductance because the latter is current-dependent. According to a further recognition of the invention the circuit arran
gement is characterized in that it includes a current supply source for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the current being field-frequency modulated. The circuit arrangement according to the invention may further be characterized in that an additional winding is provided on the core of the linearity correction coil and is traversed by the compensating current. A circuit arrangement in which the modulator for modulating the line deflection current includes a compensation or bridge coil may according to the invention be characterized in that the additional winding is connected in series with the said coil.
The invention also relates to a linearity correction coil for use in a line deflection circuit having a core which is made of a magnetic material and is bias magnetized by at least one permanent magnet, which coil is characterized in that an additional winding is provided on the core.
Embodiments of the invention will now be described by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is the circuit diagram of a known circuit arrangement for line deflection in which the line deflection current is east-west modulated,
FIG. 2 shows the distorted image which is displayed on the screen when the circuit arrangement of FIG. 1,
FIG. 3 is a graph explaining the observed defect, and
FIGS. 4 and 7 show embodiments of the circuit arrangement according to the invention by which this defect can be cancelled.
FIG. 1 is a greatl
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG.
To the base of transistor Tr line-frequency switching pulses are supplied. In known manner the said series combination is connected to the supply voltage source during the deflection interval (the trace time), diode D and transistor Tr conducting alternately. During the retrace time these elements are both cut off. Under these conditions the current i y is a sawtooth current. The coil L, which has a saturable ferrite core which is bias-magnetized by means of at least one permanent magnet, serves to correct the linearity of the current i y during the trace time, whilst the capacitance of the capacitor C t is chosen so that the currenct i y is subjected to what is generally referred to as S correction. During the retrace time, at point A pulses are produced the amplitude of which is much higher than that of the voltage V b and would be constant in the absence of modulation source M. Information from the field deflection circuit, not shown, of the image display apparatus and line retrace pulses, the latter for example by means of a transformer, are supplied in known manner to modulation source M. Amplitude-modulated line retrace pulses having a field-frequency parabolic envelope, as indicated in the FIG., are produced at point B. During the line trace time the voltage at point B is zero. Thus the current i y is given the desired field-frequency modulated form which is also shown in FIG. 1.
The amplitude of the envelope in point B at the beginning and at the end of the field trace time and the amplitude of this envelope at the middle of the said time can both be adjusted so that the image displayed on the display screen of the display tube (not shown) has the correct substantially rectangular form. If, however, the required modulation depth is comparatively large, a linearity error of the line deflection is produced which cannot be removed by means of the correction coil L.
FIG. 2 shows the image of a pattern of vertical straight lines as it is displayed on the screen with the correction coil L adjusted so that horizontal linearity is satisfactory along and near the central horizontal line. In FIG. 2 the defect is exaggerated. It is found that horizontal linearity is defective in other areas of the screen so that the vertical lines are displayed correctly in the right-hand half of the screen but as curves in the left-hand path, the defect increasing as the line is farther to the left.
This phenomenon can be explained with reference to FIG. 3. In this FIG. the inductance L of the linearity correction coil is plotted as a function of the magnetic field strength H. In the absence of current, H has a value H 0 owing to the bias magnetization. If an approximately linear sawtooth current i (t) as shown in the b
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t .
Because owing to the east-west modulation the amplitude of current i(t) varies, the amplitude of L(t) also varies. This implies a field-frequency variation of L which is non-linear. This variation is undesirable. In the case of a small variation of the amplitude of current i(t) the variation of L(t) can be more or less neglected, but this is no longer possible when the amplitude of current i(t) varies greatly owing to the east-west modulation. L(t) varies according to different curves. FIG. 3 shows two of such curves and also illustrates the fact that the undesirable variation of L(t) is greatest at the beginning of the trace time and smallest at the end thereof.
FIG. 4 shows a circuit arrangement in which the defect described can be corrected. On the core of the correction coil L of the circuit of FIG. 1 an additional winding L 2 is provided. Winding L 2 is connected to a current source which produces a compensating current i 2 which has a line-frequency sawtooth variation and a field-frequency amplitude modulation. The envelope here also is parabolic, however, with a shape opposite to that of deflection current i y , that is to say having a minimum at the middle of the field trace time. The direction of current i 2 and the winding sense of winding L 2 relative to that of coil L are chosen so that the magnetic field produced in the core by winding L 2 has the same direction as the field produced by coil L. Hence the two field strengths are added. The amplitude of current i 2 and the turns number of winding L 2 can be chosen so that current i y flows through inductances the total value of which is not dependent upon the field frequency. The curve L(t) of FIG. 3 remains substantially unchanged. Consequently the undesirable field-frequency modulation is removed without variation of the bias magnetization, which would have been varied if current i 2 were a field-frequency current. Obviously the same result can be achieved by a choice such of the direction of current i 2 and of the winding sense of winding L 2 that the two field strengths are subtracted one from the other, whilst the curvature of the envelope of current i 2 has the same direction as that of the envelope of current i y .
The current source of FIG. 4 may be formed in known manner by means of a modulator in which a line-frequency sawtooth signal is field-frequency modulated, the envelope being parabolic. FIG. 5 shows a circuit arrangement in wh
ich current i 2 is produced by the modulation source which provides the east-west correction. In FIG. 5, the source M of FIG. 1 comprises a diode D', a coil L' and two capacitors C' r and C' t , which elements constitute a network of the same structure as the network formed by elements D, L y , C r and C t . The capacitor C' t is shunted by a modulation source V m which supplies a field-frequency parabolic voltage having a minimum at the middle of the field trace time.
With the exception of the linearity correction means to be described hereinafter, the circuit arrangement of FIG. 5 was described in more detail in U.S. Pat. No. 3,906,305. Hence it will be sufficient to mention that the capacitances of capacitors C r and C' r and of a capacitor C 1 connected between junction point A and earth and the inductance of coil L' are chosen so that the three sawtooth currents flowing through L y , L' and L 1 have the same retrace time. The capacitances of capacitors C t and C' t , which are large, are ignored. When voltage V b is constant, current i y is subjected to the desired east-west modulation having the form shown in FIG. 1.
Coil L y is connected in series with correction coil L, and winding L 2 is connected in series with coil L'. FIG. 5 shows that the current flowing through winding L 2 has the same waveform as the current i 2 of FIG. 4, for its envelope has the same shape as the voltage supplied by source V m . By a suitable choice of the number of turns of winding L 2 it can be ensured that the linearity correction remains the same for every line during the field trace time.
Modified embodiments of the circuit arrangement of FIG. 5 can also be used. FIG. 6 shows such a modified embodiment in which the capacitive voltage divider C r , C' r of FIG. 5 is replaced by an inductive voltage divider by means of a tapping on coil L 1 . A capacitor C 2 is included between the tapping and the junction point of diodes D and D', whilst capacitor C' t here forms part of two networks C t , L y and C' t , L' traversed by a sawtooth current. In FIG. 6 modulation source V m is connected via a choke coil L 3 to the junction point of D, D', C 2 and
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 .
Other east-west modulators are known in which the step of FIGS. 5 and 6 can be used. An example is the modulator described in the publication by Philips, Electronic Components and Materials: "110° Colour television receiver with A66-140X standard-neck picture tube and DT 1062 multisection saddle yoke," May 1971, pages 19 and 20, which modulator also comprises two diodes and a compensation coil L', which are arranged in a slightly different manner. In another example the east-west modulator and the line deflection generator are included in a bridge circuit whilst they are decoupled from one another by means of a bridge coil which has the same function as coil L' in FIGS. 5 and 6. In these circuit arrangements coil L and winding L 2 may be arranged in the same manner as in FIG. 6. The same applies to an east-west modulator using a transductor the operating winding of which is in series with the deflection coil.
In the abovedescribed embodiments of the circuit arrangement according to the invention the compensating current i 1 is provided by transformer action. In the embodiment of FIG. 7 the current source which supplies the current i 2 is connected in parallel with correction coil L, i.e., without an auxiliary winding. In this embodiment the east-west modulation is achieved not by means of a modulator, but by means of the fact that the supply voltage V b is the super-position of a field-frequency parabolic voltage on the direct voltage. In this known manner the supply source also is the modulator.
It will be seen that in the embodiments of FIGS. 4, 5 and 6 current i 2 counteracts the east-west modulation of deflection current i y . It was found in practice, however, that this counteraction is slight.
By means of the linearity correction coil the linearity error due to the ohmic resistance of the deflection circuit is corrected. The sign
of the bias magnetisation is chosen so that it is cancelled by the deflection current at the beginning of the deflection interval, so that the inductance of the correction coil is a maximum, whereas the voltage drop across the deflection coil then is a minimum. This voltage drop is adjustable by adjustment of the starting inductance of the correction coil. During the deflection interval the core gradually becomes saturated so that the inductance of, and the voltage drop across, the correction coil decrease. Thus the linearity error can be cancelled exactly at the beginning of the interval, that is to say on the left on the screen of the image display tube, and with a certain approximation at other locations. In image display tubes using a large deflection angle, raster distortion, which generally is pincushion-shaped, of the image displayed occurs. This distortion can be removed in the horizontal direction, the so-called east-west direction, by means of field-frequency modulation of the line deflection current, the envelope in the case of pincushion-shaped distortion being substantially parabolic so that the amplitude of the line deflection current is a maximum at the middle of the field deflection interval.
It was found in practice that the said two corrections are not independent of one another, that is to say the adjustment of the east-west modulation affects horizontal linearity. As long as the modulation depth is not excessive, a satisfactory compromise can be found. However, in display tubes having a deflection angle of 110° and particularly in colour display tubes in which the deflection coils have a converging effect also, it is difficult to find such a compromise. A tube of this type is described in "Philips Research Reports," volume Feb. 14, 1959, pages 65 to 97; the distribution of the deflection field is such that throughout the display screen the landing points of the electron beams coincide without the need for a converging device. Owing to this field distribution, however, the pin-cushion-shaped distortion in the image displayed in the east-west direction is greater than in comparable display tubes of another type. Hence there must be east-west modulation of the line deflection current to a greater depth. It is true that under these conditions horizontal linearity can correctly be adjusted over a given horizontal strip after the east-west modulation has been adjusted correctly, i.e., for a rectangular image, but it is found that in other parts of the display screen a serious linearity error remains. When vertical straight lines are displayed as straight lines in the right-hand part of the screen, they are displayed as curved lines in the left-hand part.
It is an object of the present invention to remove the said defect so that horizontal linearity can satisfactorily be adjusted throughout the screen, and for this purpose the circuit arrangement according to the invention is characterized in that it includes means by which the inductance of the linearity correction coil is made substantially independent of the field frequency.
The invention is based on the recognition that the defect to be removed is due to a field-frequency variation of the said inductance because the latter is current-dependent. According to a further recognition of the invention the circuit arran
gement is characterized in that it includes a current supply source for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the current being field-frequency modulated. The circuit arrangement according to the invention may further be characterized in that an additional winding is provided on the core of the linearity correction coil and is traversed by the compensating current. A circuit arrangement in which the modulator for modulating the line deflection current includes a compensation or bridge coil may according to the invention be characterized in that the additional winding is connected in series with the said coil. The invention also relates to a linearity correction coil for use in a line deflection circuit having a core which is made of a magnetic material and is bias magnetized by at least one permanent magnet, which coil is characterized in that an additional winding is provided on the core.
Embodiments of the invention will now be described by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is the circuit diagram of a known circuit arrangement for line deflection in which the line deflection current is east-west modulated,
FIG. 2 shows the distorted image which is displayed on the screen when the circuit arrangement of FIG. 1,
FIG. 3 is a graph explaining the observed defect, and
FIGS. 4 and 7 show embodiments of the circuit arrangement according to the invention by which this defect can be cancelled.
FIG. 1 is a greatl
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG. To the base of transistor Tr line-frequency switching pulses are supplied. In known manner the said series combination is connected to the supply voltage source during the deflection interval (the trace time), diode D and transistor Tr conducting alternately. During the retrace time these elements are both cut off. Under these conditions the current i y is a sawtooth current. The coil L, which has a saturable ferrite core which is bias-magnetized by means of at least one permanent magnet, serves to correct the linearity of the current i y during the trace time, whilst the capacitance of the capacitor C t is chosen so that the currenct i y is subjected to what is generally referred to as S correction. During the retrace time, at point A pulses are produced the amplitude of which is much higher than that of the voltage V b and would be constant in the absence of modulation source M. Information from the field deflection circuit, not shown, of the image display apparatus and line retrace pulses, the latter for example by means of a transformer, are supplied in known manner to modulation source M. Amplitude-modulated line retrace pulses having a field-frequency parabolic envelope, as indicated in the FIG., are produced at point B. During the line trace time the voltage at point B is zero. Thus the current i y is given the desired field-frequency modulated form which is also shown in FIG. 1.
The amplitude of the envelope in point B at the beginning and at the end of the field trace time and the amplitude of this envelope at the middle of the said time can both be adjusted so that the image displayed on the display screen of the display tube (not shown) has the correct substantially rectangular form. If, however, the required modulation depth is comparatively large, a linearity error of the line deflection is produced which cannot be removed by means of the correction coil L.
FIG. 2 shows the image of a pattern of vertical straight lines as it is displayed on the screen with the correction coil L adjusted so that horizontal linearity is satisfactory along and near the central horizontal line. In FIG. 2 the defect is exaggerated. It is found that horizontal linearity is defective in other areas of the screen so that the vertical lines are displayed correctly in the right-hand half of the screen but as curves in the left-hand path, the defect increasing as the line is farther to the left.
This phenomenon can be explained with reference to FIG. 3. In this FIG. the inductance L of the linearity correction coil is plotted as a function of the magnetic field strength H. In the absence of current, H has a value H 0 owing to the bias magnetization. If an approximately linear sawtooth current i (t) as shown in the b
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t . Because owing to the east-west modulation the amplitude of current i(t) varies, the amplitude of L(t) also varies. This implies a field-frequency variation of L which is non-linear. This variation is undesirable. In the case of a small variation of the amplitude of current i(t) the variation of L(t) can be more or less neglected, but this is no longer possible when the amplitude of current i(t) varies greatly owing to the east-west modulation. L(t) varies according to different curves. FIG. 3 shows two of such curves and also illustrates the fact that the undesirable variation of L(t) is greatest at the beginning of the trace time and smallest at the end thereof.
FIG. 4 shows a circuit arrangement in which the defect described can be corrected. On the core of the correction coil L of the circuit of FIG. 1 an additional winding L 2 is provided. Winding L 2 is connected to a current source which produces a compensating current i 2 which has a line-frequency sawtooth variation and a field-frequency amplitude modulation. The envelope here also is parabolic, however, with a shape opposite to that of deflection current i y , that is to say having a minimum at the middle of the field trace time. The direction of current i 2 and the winding sense of winding L 2 relative to that of coil L are chosen so that the magnetic field produced in the core by winding L 2 has the same direction as the field produced by coil L. Hence the two field strengths are added. The amplitude of current i 2 and the turns number of winding L 2 can be chosen so that current i y flows through inductances the total value of which is not dependent upon the field frequency. The curve L(t) of FIG. 3 remains substantially unchanged. Consequently the undesirable field-frequency modulation is removed without variation of the bias magnetization, which would have been varied if current i 2 were a field-frequency current. Obviously the same result can be achieved by a choice such of the direction of current i 2 and of the winding sense of winding L 2 that the two field strengths are subtracted one from the other, whilst the curvature of the envelope of current i 2 has the same direction as that of the envelope of current i y .
The current source of FIG. 4 may be formed in known manner by means of a modulator in which a line-frequency sawtooth signal is field-frequency modulated, the envelope being parabolic. FIG. 5 shows a circuit arrangement in wh
ich current i 2 is produced by the modulation source which provides the east-west correction. In FIG. 5, the source M of FIG. 1 comprises a diode D', a coil L' and two capacitors C' r and C' t , which elements constitute a network of the same structure as the network formed by elements D, L y , C r and C t . The capacitor C' t is shunted by a modulation source V m which supplies a field-frequency parabolic voltage having a minimum at the middle of the field trace time. With the exception of the linearity correction means to be described hereinafter, the circuit arrangement of FIG. 5 was described in more detail in U.S. Pat. No. 3,906,305. Hence it will be sufficient to mention that the capacitances of capacitors C r and C' r and of a capacitor C 1 connected between junction point A and earth and the inductance of coil L' are chosen so that the three sawtooth currents flowing through L y , L' and L 1 have the same retrace time. The capacitances of capacitors C t and C' t , which are large, are ignored. When voltage V b is constant, current i y is subjected to the desired east-west modulation having the form shown in FIG. 1.
Coil L y is connected in series with correction coil L, and winding L 2 is connected in series with coil L'. FIG. 5 shows that the current flowing through winding L 2 has the same waveform as the current i 2 of FIG. 4, for its envelope has the same shape as the voltage supplied by source V m . By a suitable choice of the number of turns of winding L 2 it can be ensured that the linearity correction remains the same for every line during the field trace time.
Modified embodiments of the circuit arrangement of FIG. 5 can also be used. FIG. 6 shows such a modified embodiment in which the capacitive voltage divider C r , C' r of FIG. 5 is replaced by an inductive voltage divider by means of a tapping on coil L 1 . A capacitor C 2 is included between the tapping and the junction point of diodes D and D', whilst capacitor C' t here forms part of two networks C t , L y and C' t , L' traversed by a sawtooth current. In FIG. 6 modulation source V m is connected via a choke coil L 3 to the junction point of D, D', C 2 and
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 . Other east-west modulators are known in which the step of FIGS. 5 and 6 can be used. An example is the modulator described in the publication by Philips, Electronic Components and Materials: "110° Colour television receiver with A66-140X standard-neck picture tube and DT 1062 multisection saddle yoke," May 1971, pages 19 and 20, which modulator also comprises two diodes and a compensation coil L', which are arranged in a slightly different manner. In another example the east-west modulator and the line deflection generator are included in a bridge circuit whilst they are decoupled from one another by means of a bridge coil which has the same function as coil L' in FIGS. 5 and 6. In these circuit arrangements coil L and winding L 2 may be arranged in the same manner as in FIG. 6. The same applies to an east-west modulator using a transductor the operating winding of which is in series with the deflection coil.
In the abovedescribed embodiments of the circuit arrangement according to the invention the compensating current i 1 is provided by transformer action. In the embodiment of FIG. 7 the current source which supplies the current i 2 is connected in parallel with correction coil L, i.e., without an auxiliary winding. In this embodiment the east-west modulation is achieved not by means of a modulator, but by means of the fact that the supply voltage V b is the super-position of a field-frequency parabolic voltage on the direct voltage. In this known manner the supply source also is the modulator.
It will be seen that in the embodiments of FIGS. 4, 5 and 6 current i 2 counteracts the east-west modulation of deflection current i y . It was found in practice, however, that this counteraction is slight.
PHONOLA (PHILIPS) 66K6720/38Z CHASSIS K12 (20AX) Line oscillator synchronizing circuit:
A television receiver having a line synchronizing circuit wherein gate pulses for keying the synchronizing signal are derived from the oscillator signal, the gate pulses being positioned, by means of an auxiliary phase control loop, substantially symmetrical relative to
an edge of a reference signal also derived from the oscillator signal. The auxiliary control loop also eliminates the influence of phase variations occurring in the line deflection circuit.1. A television receiver having a line deflection circuit and a line synchronizing circuit, said line synchronizing circuit comprising a controllable oscillator, a signal derived therefrom being applicable to said line deflection circuit; a pulse generator coupled to said oscillator for deriving pulse-shaped gate signals; a coincidence detector; means for applying said pulse-shaped gate signals and pulse-shaped line synchronizing signals to said coincidence detector; a first phase discriminator coupled to said coincidence detector for determining the phase difference between said line synchronizing signal and a reference signal derived from said oscillator signal; a first low-pass filter for smoothing the output voltage from said first phase discriminator, said controllable oscillator being coupled to said first low-pass filter whereby the output therefrom controls the frequency and/or phase of said controllable oscillator; a second phase discriminator for determining the interval between the center instant of a pulse of said pulse-shaped gate signal and the center instant of an edge occurring in said reference signal; a second low-pass filter for smoothing the output voltage from said second phase discriminator; and means for controlling the center instant of the edge in said reference signal using the output from said second low-pass filter; wherein said line synchronizing circuit further comprises gate means having a first input terminal for receiving the output from said pulse generator and a second input terminal for receiving an output signal from said line deflection circuit, said gate means also having an output terminal for generating the gate pulses for said coincidence detector and said second phase dis
Description:
BACKGROUND OF THE INVENTION
The invention relates to a television receiver comprising a line synchronizing circuit and also comprising a line deflection circuit, the line synchronizing circuit comprising a controllable oscillator for generating an oscillator signal applicable to the line deflection circuit and being provided with means for applying a pulse-shaped line synchronizing signal and a pulse-shaped gate, which which is derived from the oscillator signal by means of a pulse generator, to a coincidence stage, an output terminal of which is connected to a first phase discriminator for determining the phase difference between the synchronizing signal and a reference signal which is also derived from the oscil
lator signal, the line synchronizing circuit being further provided with a first low-pass filter for smoothing the output voltage of the first phase discriminator, the frequency and/or phase of the oscillator being controllable by the first smoother voltage thus obtained, with a second phase discriminator for determining the interval between the center instant of a gate pulse and the center instant of an edge occurring in the reference signal, and with a second low-pass filter for smoothing the output voltage of the second phase discriminator, the center instant of said edge being controllable by means of the second smoothed voltage thus obtained. Such a line synchronizing circuit is disclosed in Applicant's Dutch Patent Application No. 7511633 (PHN.8169). In this known circuit a second phase control loop, which comprises the second discriminator and the second low-pass filter ensures that said two instants substantially coincide so that the gate pulses are substantially symmetrical relative to the edge of the reference signal. Consequently, the gate pulses may be of a very short duration, so that the insensitivity to noise is increased. The output signal of the circuit can be applied to the line deflection circuit ensuring that its phase is fixed relative to that of the received line synchronizing pulses.
It may, however, happen that phase variations occur in the line deflection circuit, for example because the turn-off time of a switch, usually a power transistor, present in said circuit is not constant. In order to reinstate the desired fixed phase relation between the deflection and the received synchronizing pulses, it is proposed in said patent application to apply the output signal of the present circuit first to a phase discriminator in which it is compared in known manner to a signal originating from the deflection circuit. This implies a third phase control loop. Consequently, the synchronizing circuit becomes complicated and more difficult to be implemented in integrated form.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a synchronizing circuit comprising only two phase-controlled loops and, to this end, the receiver according to the invention is characterized by a gate having a first input terminal for receivng the output signal of the pulse generator and a second input terminal for receiving an output signal of the line deflection circuit and having an output terminal for applying the gate pulses thus obtained to the coincidence state and to the second phase discriminator.
DESCRIPTION OF THE DRAWINGS
The invention will be further explained by way of non-limitative example with reference to the accompanying figures in which
FIG. 1 shows a block diagram of an implementation of a portion of a television receiver according to the invention and
FIGS. 2 and 3 show wave forms which may be used therein.
In FIG. 1 reference numeral 1 denotes the input terminal of the line synchronizing circuit. Line synchronizing pulses, having the line repetition frequency f H , i.e., for example, 15,625 or 15,750 Hz, are present at the input terminal. These pulses are derived, in known manner in the television receiver, not shown, of which the circuit forms part, from the received signal in a synchronizing-separation stage and are applied to an input terminal of an AND-gate 2. FIG. 2a shows the variation versus the time of these pulses. Herein the symbol T H denotes the line period, i.e. approximately 64 μs.
FIG. 2b shows the variation of gate pulses which are applied to another input terminal of gate 2 and which are generated in the circuit in a manner still to be explained hereafter. FIG. 2b shows each gate pulse symmetrically relative to the center instant t o of the corresponding line synchronising pulse of FIG. 2a. As known this pulse has a duration of, for example, 4.5 to 5 μs. The gate pulses have a somewhat longer duration of, for example, 7.7 μs. The output signal of gate 2 is applied to a controllable switch 3. If the pulses at the inputs of gate 2, as in FIG. 2, occur at least partly simultaneously, then switch 3 is made conductive for the duration of that portion of the line synchronizing pulses.
Switch 3 is supplied with a line frequency reference signal which is generated in a manner still to be explained hereafter and which is shown in FIG. 2c. In the synchronized state it has a falling edge at instant t o and a rising edge at an instant which is, for example, in the center of the time interval between instant t o and the corresponding instant t 1 one cycle later.
In these circumstances the voltage shown in FIG. 2d is present at the output terminal of switch 3. After smoothing by means of a low-pass filter 4, a d.c. voltage is produced which is supplied to a voltage controlled oscillator 5, whose frequency and/or phase is adjusted hereby. Switch 3 behaves as a phase discriminator by means of which the falling edge of the signal of FIG. 2c is adjusted to the center instant t o of the pulse of FIG. 2a. If the frequency of the signal of FIG. 2c deviates from the value f H , then the phase difference between this signal and that of FIG. 2a varies continuously. The control voltage supplied
to oscillator 5 is then an a.c. voltage, namely until the two frequencies are equal again, wherafter the control voltage is a d.c. voltage.
Oscillator 5 is also supplied with a d.c. voltage V o of, for example, 3 V on which the control voltage just mentioned is superimposed. Voltage V o may correspond to the nominal frequency of the line synchronizing pulses in accordance with the television standard for which the television receiver is suited. In the described implementation, however, the signal generated by oscillator 5 has, in the nominal case, a frequency 2f H which is double the line frequency. This signal is applied to a frequency divider circuit 6 in which the frequency is divided by the number of lines per picture in the relevant standard, being, for example, 625 or 525. A field frequency signal of, for example, 50 or 60 Hz, is available at an output terminal of divider circuit 6 in the synchronized state of the line phase-controlled loop, which signal can be applied to a field synchronizing circuit of known type.
The sawtooth signal shown in FIG. 3a is derived from the signal of oscillator 5, the sawtooth signal being applied to a pulse generator 7. By means of a d.c. voltage level V 1 which is applied to generator 7 and which is generated in a manner still to
be explained, the sawtooth signal is converted in this generator into a pulse-shaped signal (FIG. 3b). The leading edges of these pulses and the rising edges in FIG. 3a occur simultaneously; while the instant of occurrence of the trailing edges of the pulses is determined by the value of voltage V 1 . These pulses are applied to a frequency dividing circuit 8 which, for example, is a binary divider circuit of known type, for example a master-slave flip-flop. The output signals thereof have the line frequency f H . The signal at an output terminal Q s thereof (see FIG. 3c) changes levels each time a falling edge occurs in the signal of FIG. 3b, while the signal at an output terminal Q m of circuit 8 (see FIG. 3d) changes levels each time a rising edge occurs in the signal of FIG. 3b. This implies that the signal of FIG. 3b is fixed relative to the time axis while the position of the signal of FIG. 3c depends on the value of voltage V 1 .
The signal at terminal Q m is the signal which is applied as a reference signal to switch 3, while the signal at terminal Q s is applied to a pulse shaper 9. The output signal thereof has the variation which is suitable for being applied, possibly via a driver stage, to a line output stage 10. Stage 10 supplies a line frequency current to the deflection coil, not shown, for the horizontal deflection in the picture display tube. Stage 10 comprises a switch usually a power transistor, whose turn-on time is relatively short, while its turn-off time is considerable, namely in the order of 10 μs. This is caused by the fact that the charge carriers, which are present in an excess in the saturated transistor, must first be removed. As known, the turn-off time depends on variations in the load of stage 10, for example the beam current in the picture display tube. In known manner, the adverse influence of such variations can be compensed for, for example by including a phase-controlled loop between oscillator 5 and the output of stage 10, this loop comprising a phase discriminator, a low-pass filter as well as an oscillator or a phase-shifting network. A signal originating from the output of stage 10 is used as a reference signal for this loop. Dutch Patent Application No. 7103465 (PHN.5499) discloses such a phase-controlled loop. A compensation is effected in the circuit of FIG. 1 in a different manner, which will be explained in the further course of this description.
The sawtooth voltage of FIG. 3a is also applied to a pulse generator 11 in which the sawtooth signal is converted into the pulse-shaped signal of FIG. 3e by means of a d.c. voltage V 2 applied thereto. The rising edges thereof occur simultaneously with those of FIG. 3a while the falling edges occur at the instants at which the sawtooth signal attains the value V 2 . In this manner the frequency of these pulses would have the double line frequency 2f H . However, the signal at the terminal Q m of divider circuit 8 is also applied to generator 11, thus, each rising edge of this signal cuts off generator 11. Other line frequency signals, for example line flyback pulses originating from stage 10, can also be used for this same purpose. The pulses obtained are applied to an input terminal of an OR-gate 12.
FIG. 3f shows line flyback pulses present in output stage 10, for example across a winding of a transformer thereof. For simplicity they are depicted as sine-shaped waves. They occur from approximately the instant at which the switch in stage 10 is switched-off, that is to say a time 96 after the occurrence of a falling edge of signal Q s (FIG. 3c) which time τ may be variable, while the duration of these pulses is substantially constant. The pulses of FIG. 3f are applied to an input terminal of an AND-gate 13, while another input terminal is connected to terminal Q m of the frequencies divider 8. The output terminal of gate 13 is connected to an input terminal of gate 12.
From FIGS. 3d and 3f it appears that the output signal of gate 13 has a leading edge from a time τ after the occurrence of a falling edge of signal Q s , and a trailing edge at the instant at which a falling edge of signal Q m occurs. The output signal of gate 12 has a leading edge at the same instant at which the leading edge of the output signal of gate 13 occurs and a trailing edge at the same instant at which the trailing edge of generator 11 occurs. The pulses at the output terminal of gate 12 are shown in FIG. 3g and are the gate pulses of FIG. 2b which are applied to gate 2. The leading edges thereof occur at instants which depend on the delay τ produced in output stage 10, while the instants at which the trailing edges occur depend only on the, optionally adjustable, voltage V 2 . These pulses do not contain any information concerning the signal Q m , in spite of the fact that Q m is one of the input signals of gate 13, which information is, for the rest not necessary. Said input signal is only used for removing the portion of the pulse of FIG. 3f occurring after the falling edge of signal Q m . The same result can be achieved by means of, for example, a bistable multivibrator, the output signal of which has a leading edge at the same instant as the flyback pulse and a trailing edge at the same instant as the signal of generator 11.
A phase discriminator 14, implemented as a controllable switch, is supplied with the reference signal at the output terminal Q m of divider circuit 8 (FIG. 3d) as well as with the gate pulses originating from gate 12. Switch 14 conducts during the occurrence of the gate pulses and its output voltage is smoothed by a low-pass filter 15.
The smoothed voltage obtained, as well as a d.c. voltage V 3 , derived from the supply voltage of the circuit, are supplied to a differential amplifier 16. The output voltage thereof is the voltage V 1 which is supplied to pulse generator 7. As a result thereof the duration of the pulses of FIG. 3b and, consequently, also the position along the time axis of the edges of signal Q s , depend on the value of the smoothed voltage. Elements 7 to 16 inclusive constitute an auxiliary control loop which operates so that each gate pulse of FIG. 3g remains symmetrical relative to the edge of the reference signal of FIG. 3d and, consequently, also relative to the center instant of the synchronizing pulse of FIG. 2a. This determines the duration of the gate pulse. Since, if the duration of the synchronizing pulse is 4.7 μs while the duration of the flyback pulse is 12 μs and if the interval between the starting instant of the flyback pulse (that is to say that of the blanking pulse in the received video signal) and the starting instant of the synchronizing pulse is equal to 1.5 μs, then the period of time between the leading edge in FIG. 2b and instant t o is equal, in the ideal case, to 1.5 +(4.7/2)=3.85 μs. Due to the action of voltage V 2 in stage 11 and of the auxiliary control loop, the trailing edge in FIG. 2b occurs 3.85 μs after instant t o , so that the duration of the gate pulse is 7.7 μs. In practice the pulse will be somewhat longer but it is obvious that, due to this rather short period of time, it is ensured that the sensitivity of the circuit to noise and disturbances is low, which especially holds for disturbances caused by reflection.
The final state of the auxiliary control loop is attained after a time which is independent of the frequency of oscillator 5, while the auxiliary control loop cannot experience an adverse influence from noise and disturbances. The time constant of filter 15 can therefore be chosen at will. Dutch Patent Application No. 7511633 (PHN.8169) describes all this more extensively. Because, however, the variations of delay τ can be rapid, this time constant must be many times smaller, for example ten times as small as that of filter 4.
If the frequency of oscillator 5 varies, for example due to a variation in the supply voltage, or if the frequency of the received line synchronisation pulses varies, for example because a switch-over to another transmitter is effected, the oscillator 4 is so adjusted by the operation of the control loop formed by elements 3 to 8 inclusive that the situation indicated in FIG. 2 occurs. This implies that the waveforms of the FIGS. 3a, 3b, 3c, 3d and 3e are shifted along the time axis until the leading edges of the pulses of FIG. 3a occur at the center instants of the synchronizing pulses of FIG. 2a. In this way it is ensured that also the trailing edges of the pulses of FIG. 3e and, consequently, also those of the gate pulses of FIGS. 3g and 2b are fixed relative to the synchronizing pulses.
If now the delay τ between the falling edge of the signal of FIG. 3c and the starting instant of the flyback pulse of FIG. 3f vary and/or if a shift of the gate pulses of FIG. 3g occurs relative to the reference signal of FIG. 3d as a result of spread in the properties of the various components and/or of inequalities of the transition times in the various transistors etc., then the pulse generator 7 is so adjusted by the operation of auxiliary control loop 7 to 16 inclusive that the situation shown in FIG. 3d occurs. In this situation the input voltage, originating from filter 15, of differential amplifier 16 is substantially equal to the voltage V 3 . Prior to the occurrence of this situation, said voltages deviate from one another, so that voltage V 1 varies. As a result, the position of the trailing edges of the pulses of FIG. 3b and, consequently, also the position of the edges of the signal Q s of FIG. 3 c change. Thus, the signal Q s is shifted along the time axis until the flyback pulses of FIG. 3f are fixed relative to the synchronizing pulses of FIG. 2a. Therefore, it is ensured, by means of the auxiliary control loop, that the influence of variations in time τ are considerably reduced and that the gate pulses shift only a little relative the reference signal, so that they may be of a short duration.
As in the previously mentioned Dutch Patent Application No. 7511633, the d.c. voltage V o , which is supplied to oscillator 5 in the absence of a control voltage originating from filter 4 and cause the oscillator to generate a signal having the nominal frequency, may be derived from the output voltage of filter 15. Also a pulse may be derived from one of the signals of FIG. 2 or FIG. 3, for example the sawtooth signal of FIG. 3a, for keying out the color synchronizing signal, which pulse may also be used for stabilising the black level. A coincidence detector may be used with which it is possible to reinstate the at least partly simultaneous occurrence of the gate pulses and the synchronizing pulses. In the case of non-coincidence, the gate pulses assume a longer duration, or the supply load for the gate pulses to gate 2 is interrupted, while the loop gain of control loop 3 to 8 inclusive is increased. As known, the locking-in property of the loop is improved by means of this switch-over.
As this loop gain cannot be infinitely large, the situation shown in FIG. 2 does not as a rule occur, that is to say there always remains a residual error. This means that the edge of the reference signal of FIG. 2c occurs, in the nominal state, at an instant which slightly deviates from instant t o , so that the voltage supplied to oscillator 5 slightly deviates from the value V o . The circuit of FIG. 1 is improved in this respect.
The control voltage which is supplied to oscillator 5 is also supplied to an amplifier 17. The output voltage thereof is the voltage V 2 which is supplied to pulse generator 11. Amplifier 17 is so dimensioned that the abovementioned error is corrected. If the error is, for example, such that the falling edge of the signal of FIG. 2c occurs somewhat too early relative to instant t o then amplifier 17 must have a gain of such a value and such a sign that voltage V 2 in FIG. 3a increases by a suitable value. This cause the falling edges in FIG. 3e and, consequently, in FIG. 3g to be shifted to the left. Due to the operation of the auxiliary control loop, when the gate pulses of FIG. 3g are substantially symmetrical in the synchronized state relative to instant t o , the rising edges in FIG. 3g are shifted to the right so that the gate pulses are given a shorter duration. The consequence of the outlined shift is that the flyback pulses occur somewhat later than is the case in FIG. 3f, so that also the signal Q s of FIG. 3c is shifted to the right. This means an identical shift of the falling edges of the signal of FIG. 3b and, consequently, a decrease of voltage V 1 . In this manner a small error is introduced in the auxiliary control loop so that the flyback pulses are slightly shifted relative to the reference signal, whose position along the time axis does not depend on voltage V 1 but, as a consequence of which, with a suitable design of amplifier 17, the flyback pulses are fixed relative to the synchronizing pulses. The center instant of a flyback pulse thus occurs at instant t o . A certain value can be assigned to voltage V 2 in the absence of a control voltage at the input terminal of amplifier 17; the duration of the gate pulses is adjusted by this setting. It will be obvious that a similar adjustment can also be applied in the case amplifier 17 is not present.
The foregoing discusses the idealised wave forms of FIGS. 2 and 3. It is obvious that both the leading and trailing edges in, for example, FIG. 2b and the edges in, for example, FIG. 2c have in practice no infinitely steep slope but a kind of sawtooth shape. Consequently, the symmetry aimed at means that the center instants of the pulses in FIG. 2b and of the edges in FIG. 2c occur substantially simultaneously, wherein center instant must be understood to mean in the first-mentioned case the instant located in the center of the time interval between which the signal is higher than half its maximum value and in the second case the instant at which half of the maximum value is achieved.
During the locking-in of the auxiliary control loop the position of the gate pulses varies in the described circuit along the time axis while that of the reference signal remains unchanged. It is clear that an implementation can be realised in which the position of the gate pulses is not affected
by the control, while the position of the reference signal varies.
With the exception of capacitors which are part of filters 4 and 15, the described circuits can be integrated in a semiconductor body. In the preceding the oscillator has in the nominal state double the line frequency. It will be obvious that this is not essential for the invention, that is to say the invention can also be used if the nominal frequency is the line frequency or another multiple thereof.
The invention relates to a television receiver comprising a line synchronizing circuit and also comprising a line deflection circuit, the line synchronizing circuit comprising a controllable oscillator for generating an oscillator signal applicable to the line deflection circuit and being provided with means for applying a pulse-shaped line synchronizing signal and a pulse-shaped gate, which which is derived from the oscillator signal by means of a pulse generator, to a coincidence stage, an output terminal of which is connected to a first phase discriminator for determining the phase difference between the synchronizing signal and a reference signal which is also derived from the oscil
lator signal, the line synchronizing circuit being further provided with a first low-pass filter for smoothing the output voltage of the first phase discriminator, the frequency and/or phase of the oscillator being controllable by the first smoother voltage thus obtained, with a second phase discriminator for determining the interval between the center instant of a gate pulse and the center instant of an edge occurring in the reference signal, and with a second low-pass filter for smoothing the output voltage of the second phase discriminator, the center instant of said edge being controllable by means of the second smoothed voltage thus obtained. Such a line synchronizing circuit is disclosed in Applicant's Dutch Patent Application No. 7511633 (PHN.8169). In this known circuit a second phase control loop, which comprises the second discriminator and the second low-pass filter ensures that said two instants substantially coincide so that the gate pulses are substantially symmetrical relative to the edge of the reference signal. Consequently, the gate pulses may be of a very short duration, so that the insensitivity to noise is increased. The output signal of the circuit can be applied to the line deflection circuit ensuring that its phase is fixed relative to that of the received line synchronizing pulses. It may, however, happen that phase variations occur in the line deflection circuit, for example because the turn-off time of a switch, usually a power transistor, present in said circuit is not constant. In order to reinstate the desired fixed phase relation between the deflection and the received synchronizing pulses, it is proposed in said patent application to apply the output signal of the present circuit first to a phase discriminator in which it is compared in known manner to a signal originating from the deflection circuit. This implies a third phase control loop. Consequently, the synchronizing circuit becomes complicated and more difficult to be implemented in integrated form.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a synchronizing circuit comprising only two phase-controlled loops and, to this end, the receiver according to the invention is characterized by a gate having a first input terminal for receivng the output signal of the pulse generator and a second input terminal for receiving an output signal of the line deflection circuit and having an output terminal for applying the gate pulses thus obtained to the coincidence state and to the second phase discriminator.
DESCRIPTION OF THE DRAWINGS
The invention will be further explained by way of non-limitative example with reference to the accompanying figures in which
FIG. 1 shows a block diagram of an implementation of a portion of a television receiver according to the invention and
FIGS. 2 and 3 show wave forms which may be used therein.
In FIG. 1 reference numeral 1 denotes the input terminal of the line synchronizing circuit. Line synchroniz
ing pulses, having the line repetition frequency f H , i.e., for example, 15,625 or 15,750 Hz, are present at the input terminal. These pulses are derived, in known manner in the television receiver, not shown, of which the circuit forms part, from the received signal in a synchronizing-separation stage and are applied to an input terminal of an AND-gate 2. FIG. 2a shows the variation versus the time of these pulses. Herein the symbol T H denotes the line period, i.e. approximately 64 μs. FIG. 2b shows the variation of gate pulses which are applied to another input terminal of gate 2 and which are generated in the circuit in a manner still to be explained hereafter. FIG. 2b shows each gate pulse symmetrically relative to the center instant t o of the corresponding line synchronising pulse of FIG. 2a. As known this pulse has a duration of, for example, 4.5 to 5 μs. The gate pulses have a somewhat longer duration of, for example, 7.7 μs. The output signal of gate 2 is applied to a controllable switch 3. If the pulses at the inputs of gate 2, as in FIG. 2, occur at least partly simultaneously, then switch 3 is made conductive for the duration of that portion of the line synchronizing pulses.
Switch 3 is supplied with a line frequency reference signal which is generated in a manner still to be explained hereafter and which is shown in FIG. 2c. In the synchronized state it has a falling edge at instant t o and a rising edge at an instant which is, for example, in the center of the time interval between instant t o and the corresponding instant t 1 one cycle later.
In these circumstances the voltage shown in FIG. 2d is present at the output terminal of switch 3. After smoothing by means of a low-pass filter 4, a d.c. voltage is produced which is supplied to a voltage controlled oscillator 5, whose frequency and/or phase is adjusted hereby. Switch 3 behaves as a phase discriminator by means of which the falling edge of the signal of FIG. 2c is adjusted to the center instant t o of the pulse of FIG. 2a. If the frequency of the signal of FIG. 2c deviates from the value f H , then the phase difference between this signal and that of FIG. 2a varies continuously. The control voltage supplied
Oscillator 5 is also supplied with a d.c. voltage V o of, for example, 3 V on which the control voltage just mentioned is superimposed. Voltage V o may correspond to the nominal frequency of the line synchronizing pulses in accordance with the television standard for which the television receiver is suited. In the described implementation, however, the signal generated by oscillator 5 has, in the nominal case, a frequency 2f H which is double the line frequency. This signal is applied to a frequency divider circuit 6 in which the frequency is divided by the number of lines per picture in the relevant standard, being, for example, 625 or 525. A field frequency signal of, for example, 50 or 60 Hz, is available at an output terminal of divider circuit 6 in the synchronized state of the line phase-controlled loop, which signal can be applied to a field synchronizing circuit of known type.
The sawtooth signal shown in FIG. 3a is derived from the signal of oscillator 5, the sawtooth signal being applied to a pulse generator 7. By means of a d.c. voltage level V 1 which is applied to generator 7 and which is generated in a manner still to
be explained, the sawtooth signal is converted in this generator into a pulse-shaped signal (FIG. 3b). The leading edges of these pulses and the rising edges in FIG. 3a occur simultaneously; while the instant of occurrence of the trailing edges of the pulses is determined by the value of voltage V 1 . These pulses are applied to a frequency dividing circuit 8 which, for example, is a binary divider circuit of known type, for example a master-slave flip-flop. The output signals thereof have the line frequency f H . The signal at an output terminal Q s thereof (see FIG. 3c) changes levels each time a falling edge occurs in the signal of FIG. 3b, while the signal at an output terminal Q m of circuit 8 (see FIG. 3d) changes levels each time a rising edge occurs in the signal of FIG. 3b. This implies that the signal of FIG. 3b is fixed relative to the time axis while the position of the signal of FIG. 3c depends on the value of voltage V 1 . The signal at terminal Q m is the signal which is applied as a reference signal to switch 3, while the signal at terminal Q s is applied to a pulse shaper 9. The output signal thereof has the variation which is suitable for being applied, possibly via a driver stage, to a line output stage 10. Stage 10 supplies a line frequency current to the deflection coil, not shown, for the horizontal deflection in the picture display tube. Stage 10 comprises a switch usually a power transistor, whose turn-on time is relatively short, while its turn-off time is considerable, namely in the order of 10 μs. This is caused by the fact that the charge carriers, which are present in an excess in the saturated transistor, must first be removed. As known, the turn-off time depends on variations in the load of stage 10, for example the beam current in the picture display tube. In known manner, the adverse influence of such variations can be compensed for, for example by including a phase-controlled loop between oscillator 5 and the output of stage 10, this loop comprising a phase discriminator, a low-pass filter as well as an oscillator or a phase-shifting network. A signal originating from the output of stage 10 is used as a reference signal for this loop. Dutch Patent Application No. 7103465 (PHN.5499) discloses such a phase-controlled loop. A compensation is effected in the circuit of FIG. 1 in a different manner, which will be explained in the further course of this description.
The sawtooth voltage of FIG. 3a is also applied to a pulse generator 11 in which the sawtooth signal is converted into the pulse-shaped signal of FIG. 3e by means of a d.c. voltage V 2 applied thereto. The rising edges thereof occur sim
ultaneously with those of FIG. 3a while the falling edges occur at the instants at which the sawtooth signal attains the value V 2 . In this manner the frequency of these pulses would have the double line frequency 2f H . However, the signal at the terminal Q m of divider circuit 8 is also applied to generator 11, thus, each rising edge of this signal cuts off generator 11. Other line frequency signals, for example line flyback pulses originating from stage 10, can also be used for this same purpose. The pulses obtained are applied to an input terminal of an OR-gate 12. FIG. 3f shows line flyback pulses present in output stage 10, for example across a winding of a transformer thereof. For simplicity they are depicted as sine-shaped waves. They occur from approximately the instant at which the switch in stage 10 is switched-off, that is to say a time 96 after the occurrence of a falling edge of signal Q s (FIG. 3c) which time τ may be variable, while the duration of these pulses is substantially constant. The pulses of FIG. 3f are applied to an input terminal of an AND-gate 13, while another input terminal is connected to terminal Q m of the frequencies divider 8. The output terminal of gate 13 is connected to an input terminal of gate 12.
From FIGS. 3d and 3f it appears that the output signal of gate 13 has a leading edge from a time τ after the occurrence of a falling edge of signal Q s , and a trailing edge at the instant at which a falling edge of signal Q m occurs. The output signal of gate 12 has a leading edge at
the same instant at which the leading edge of the output signal of gate 13 occurs and a trailing edge at the same instant at which the trailing edge of generator 11 occurs. The pulses at the output terminal of gate 12 are shown in FIG. 3g and are the gate pulses of FIG. 2b which are applied to gate 2. The leading edges thereof occur at instants which depend on the delay τ produced in output stage 10, while the instants at which the trailing edges occur depend only on the, optionally adjustable, voltage V 2 . These pulses do not contain any information concerning the signal Q m , in spite of the fact that Q m is one of the input signals of gate 13, which information is, for the rest not necessary. Said input signal is only used for removing the portion of the pulse of FIG. 3f occurring after the falling edge of signal Q m . The same result can be achieved by means of, for example, a bistable multivibrator, the output signal of which has a leading edge at the same instant as the flyback pulse and a trailing edge at the same instant as the signal of generator 11. A phase discriminator 14, implemented as a controllable switch, is supplied with the reference signal at the output terminal Q m of divider circuit 8 (FIG. 3d) as well as with the gate pulses originating from gate 12. Switch 14 conducts during the occurrence of the gate pulses and its output voltage is smoothed by a low-pass filter 15.
The smoothed voltage obtained, as well as a d.c. voltage V 3 , derived from the supply voltage of the circuit, are supplied to a differential amplifier 16. The output voltage thereof is the voltage V 1 which is supplied to pulse generator 7. As a result thereof the duration of the pulses of FIG. 3b and, consequently, also the position along the time axis of the edges of signal Q s , depend on the value of the smoothed voltage. Elements 7 to 16 inclusive constitute an auxiliary control loop which operates so that each gate pulse of FIG. 3g remains symmetrical relative to the edge of the reference signal of FIG. 3d and, consequently, also relative to the center instant of the synchronizing pulse of FIG. 2a. This determines the duration of the gate pulse. Since, if the duration of the synchronizing pulse is 4.7 μs while the duration of the flyback pulse is 12 μs and if the interval between the starting instant of the flyback pulse (that is to say that of the blanking pulse in the received video signal) and the starting instant of the synchronizing pulse is equal to 1.5 μs, then the period of time between the leading edge in FIG. 2b and instant t o is equal, in the ideal case, to 1.5 +(4.7/2)=3.85 μs. Due to the action of voltage V 2 in stage 11 and of the auxiliary control loop, the trailing edge in FIG. 2b occurs 3.85 μs after instant t o , so that the duration of the gate pulse is 7.7 μs. In practice the pulse will be somewhat longer but it is obvious that, due to this rather short period of time, it is ensured that the sensitivity of the circuit to noise and disturbances is low, which especially holds for disturbances caused by reflection.
The final state of the auxiliary control loop is attained after a time which is independent of the frequency of oscillator 5, while the auxiliary control loop cannot experience an adverse influence from noise and disturbances. The time constant of filter 15 can therefore be chosen at will. Dutch Patent Application No. 7511633 (PHN.8169) describes
all this more extensively. Because, however, the variations of delay τ can be rapid, this time constant must be many times smaller, for example ten times as small as that of filter 4. If the frequency of oscillator 5 varies, for example due to a variation in the supply voltage, or if the frequency of the received line synchronisation pulses varies, for example because a switch-over to another transmitter is effected, the oscillator 4 is so adjusted by the operation of the control loop formed by elements 3 to 8 inclusive that the situation indicated in FIG. 2 occurs. This implies that the waveforms of the FIGS. 3a, 3b, 3c, 3d and 3e are shifted along the time axis until the leading edges of the pulses of FIG. 3a occur at the center instants of the synchronizing pulses of FIG. 2a. In this way it is ensured that also the trailing edges of the pulses of FIG. 3e and, consequently, also those of the gate pulses of FIGS. 3g and 2b are fixed relative to the synchronizing pulses.
If now the delay τ between the falling edge of the signal of FIG. 3c and the starting instant of the flyback pulse of FIG. 3f vary and/or if a shift of the gate pulses of FIG. 3g occurs relative to the reference signal of FIG. 3d as a result of spread in the properties of the various components and/or of inequalities of the transition times in the various transistors etc., then the pulse generator 7 is so adjusted by the operation of auxiliary control loop 7 to 16 inclusive that the situation shown in FIG. 3d occurs. In this situation the input voltage, originating from filter 15, of differential amplifier 16 is substantially equal to the voltage V 3 . Prior to the occurrence of this situation, said voltages deviate from one another, so that voltage V 1 varies. As a result, the position of the trailing edges of the pulses of FIG. 3b and, consequently, also the position of the edges of the signal Q s of FIG. 3 c change. Thus, the signal Q s is shifted along the time axis until the flyback pulses of FIG. 3f are fixed relative to the synchronizing pulses of FIG. 2a. Therefore, it is ensured, by means of the auxiliary control loop, that the influence of variations in time τ are considerably reduced and that the gate pulses shift only a little relative the reference signal, so that they may be of a short duration. As in the previously mentioned Dutch Patent Application No. 7511633, the d.c. voltage V o , which is supplied to oscillator 5 in the absence of a control voltage originating from filter 4 and cause the oscillator to generate a signal having the nominal frequency, may be derived from the output voltage of filter 15. Also a pulse may be derived from one of the signals of FIG. 2 or FIG. 3, for example the sawtooth signal of FIG. 3a, for keying out the color synchronizing signal, which pulse may also be used for st
abilising the black level. A coincidence detector may be used with which it is possible to reinstate the at least partly simultaneous occurrence of the gate pulses and the synchronizing pulses. In the case of non-coincidence, the gate pulses assume a longer duration, or the supply load for the gate pulses to gate 2 is interrupted, while the loop gain of control loop 3 to 8 inclusive is increased. As known, the locking-in property of the loop is improved by means of this switch-over. As this loop gain cannot be infinitely large, the situation shown in FIG. 2 does not as a rule occur, that is to say there always remains a residual error. This means that the edge of the reference signal of FIG. 2c occurs, in the nominal state, at an instant which slightly deviates from instant t o , so that the voltage supplied to oscillator 5 slightly deviates from the value V o . The circuit of FIG. 1 is improved in this respect.
The control voltage which is supplied to oscillator 5 is also supplied to an amplifier 17. The output voltage thereof is the voltage V 2 which is supplied to pulse generator 11. Amplifier 17 is so dimensioned that the abovementioned error is corrected. If the error is, for example, such that the falling edge of the signal of FIG. 2c occurs somewhat too early relative to instant t o then amplifier 17 must have a gain of such a value and such a sign that voltage V 2 in FIG. 3a increases by a suitable value. This cause the falling edges in FIG. 3e and, consequently, in FIG. 3g to be shifted to the left. Due to the operation of the auxiliary control loop, when the gate pulses of FIG. 3g are substantially symmetrical in the synchronized state relative to instant t o , the rising edges in FIG. 3g are shifted to the right so that the gate pulses are given a shorter duration. The consequence of the outlined shift is that the flyback pulses occur somewhat later than is the case in FIG. 3f, so that also the signal Q s of FIG. 3c is shifted to the right. This means an identical shift of the falling edges of the signal of FIG. 3b and, consequently, a decrease of voltage V 1 . In this manner a small error is introduced in the auxiliary control loop so that the flyback pulses are slightly shifted relative to the reference signal, whose position along the time axis does not depend on voltage V 1 but, as a consequence of which, with a suitable design of amplifier 17, the flyback pulses are fixed relative to the synchronizing pulses. The center instant of a flyback pulse thus occurs at instant t o . A certain value can be assigned to voltage V 2 in the absence of a control voltage at the input terminal of amplifier 17; the duration of the gate pulses is adjusted by this setting. It will be obvious that a similar adjustment can also be applied in the case amplifier 17 is not present.
The foregoing discusses the idealised wave forms of FIGS. 2 and 3. It is obvious that both the leading and trailing edges in, for example, FIG. 2b and the edges in, for example, FIG. 2c have in practice no infinitely steep slope but a kind of sawtooth shape. Consequently, the symmetry aimed at means that the center instants of the pulses in FIG. 2b and of the edges in FIG. 2c occur substantially simultaneously, wherein center instant must be understood to mean in the first-mentioned case the instant located in the center of the time interval between which the signal is higher than half its maximum value and in the second case the instant at which half of the maximum value is achieved.
During the locking-in of the auxiliary control loop the position of the gate pulses varies in the described circuit along the time axis while that of the reference signal remains unchanged. It is clear that an implementation can be realised in which the position of the gate pulses is not affected
With the exception of capacitors which are part of filters 4 and 15, the described circuits can be integrated in a semiconductor body. In the preceding the oscillator has in the nominal state double the line frequency. It will be obvious that this is not essential for the invention, that is to say the invention can also be used if the nominal frequency is the line frequency or another multiple thereof.
TV and radio receivers have conventionally used analogue tuning and control systems. However, the development of LSI technology has now progressed to the state where these functions can be economically performed by mass-produced digital lsi circuits. Bulky and unreliable multi-way switches and potentiometer can be replaced by simple single-pole switches. Moreover, the digital circuitry allows the use of remote control systems, again developed using lsi techniques. New functions for the TV receiver, such as Teletext and video games, can easily be accommodated using digital control techniques. This handbook describes a complete range of lsi circuits designed to perform all tuning, control and remote control functions required for TV and radio receivers. The processes used to fabricate these ICs vary according to the function, for example, ECl for high-frequency circuits, lOCMOS for low-power circuits, etc. However, all circuits are produced by basically simple processes, providing good yield and reliability.
Available systems
• Remote control systems: three different remote control systems are available which cope with
different.market or system requirements.
• DICS (Digital Channel Select) system (also referred to as the TRD system): the well-known system
in volume production; closed loop digital tuning, based on the Fll (frequency locked loop) principle; including remote control and display features.
• VTS (Video Tuning System): the next generation system for microcomputer based closed loop
tuning systems (Fll principle); a full range of microcomputer peripherals.
• Teletext and View-data systems: the new digital text communication systems with on-screen text
display.
• RTS (Radio Tuning System): digital tuning, control and display system for radio receivers, with or
without remote control.
• Digital Frequency Counter system: frequency measurement and display system for radio receivers. The systems are designed so that they can be operated independently or built into a single system. Their compatible design philosophy means that basic systems can easily be expanded when design requirements are changed. Moreover, the TV and radio systems can be operated independently via a single remote control unit, while sub-systems such as TV games, slide and film projectors and recorders can be operated via the TV or radio equipment. Figure 1 shows a typical system approach, controlling TV, radio etc. from a Single transmitter unit.
SURVEY OF THE DICS system (TRD)
This is a remote control and digital tuning system intended primarily for use in TV receivers; provision has been made, however, for using the remote control with radio receivers and other sub-systems. The system incorporates a memory for station storage and analogue settings.
Control system.
The control system comprises:
• SAB3011 remote transmitter;
• SAB3012, SA83022 or SA83032 receiver and analogue memory circuits;
• TD81033 signal amplifier;
• SAB2021 command encoder (local use);
• SA83017 serial to parallel command translator.
Tuning system
SA82024 frequehcy comparator and ROM;
SAB2015 control circuit and RAM (station storage);
SA810098 + SAB 1046 input amplifier and frequency divider (prescaler).
This combination will be superseded by the SA81018 one chip prescaler;
SAB2022 analogue memory for fine de-tuning.
Display system
• SA81016 control circuit for on-screen display of station and/or channel number.
Features of the DICS system are:
Tuning
Highly accurate tuning allows optimum reception of Teletext;
AFC compensation for drift in frequency converters, vcr, TV games;
Fully automatic direct digital selection and tuning of all current and future TV channels in the VHF and UHF range, including those outside the standard tuning range;
Stable closed-loop tuning system with an error of less than 10 kHz;
Simple storage of preferred-station frequencies;
Fine de-tuning of stored station according to personal preference;
Non-volatile station storage;
Fast search tuning; Search tuning will also locate stations outside the normal channel pattern.
Control
Large command set of 2 groups of 64 commands allows operation of two receiver systems from one transmitter, e.g. TV and radio;
8 SUb-systems select-able per command group, leaving 56 commands for each sub-system (Teletext,View-data, TV games etc.);
Transmitter modulation method provides reliable error-free reception of commands;·
31 local commands directly available, expandable up to 64.
Display
• Transmitter identified by display of channel and station numbers by on-screen display;
• On-screen display uses character rounding and background blanking.
The digital tuning section comprises the channel selector, an input amplifier and frequency divider, and q frequency comparator with ROM. The ROM is used to store all the standard CCI R-allocated TV carrier frequencies. The output of the frequency comparator drives the AFC circuit to lock the tuner to the desired frequency. After reception of a tuning command, the ROM is addressed by the required channel number (from the SAB2015) to load the control loop with the frequency information for the required station. This information is also used to provide station and channel numbers for display purposes. These numbers can be presented as an on-screen display using the SAB 1016. The fine de-tuning circuit, SAB2022, delivers an offset voltage for the I F/AFC module. The de-tuning voltage can be set to one of 32 levels for each of the 16 stored stations.
Non-volatile station storage;
Fast search tuning; Search tuning will also locate stations outside the normal channel pattern.
Control
Large command set of 2 groups of 64 commands allows operation of two receiver systems from one transmitter, e.g. TV and radio;
8 SUb-systems select-able per command group, leaving 56 commands for each sub-system (Teletext,View-data, TV games etc.);
Transmitter modulation method provides reliable error-free reception of commands;·
31 local commands directly available, expandable up to 64.
Display
• Transmitter identified by display of channel and station numbers by on-screen display;
• On-screen display uses character rounding and background blanking.
The digital tuning section comprises the channel selector, an input amplifier and frequency divider, and q frequency comparator with ROM. The ROM is used to store all the standard CCI R-allocated TV carrier frequencies. The output of the frequency comparator drives the AFC circuit to lock the tuner to the desired frequency. After reception of a tuning command, the ROM is addressed by the required channel number (from the SAB2015) to load the control loop with the frequency information for the required station. This information is also used to provide station and channel numbers for display purposes. These numbers can be presented as an on-screen display using the SAB 1016. The fine de-tuning circuit, SAB2022, delivers an offset voltage for the I F/AFC module. The de-tuning voltage can be set to one of 32 levels for each of the 16 stored stations.
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PHILIPS SAB2015 CONTROL AND STATION MEMORY CIRCUIT
GENERAL DESCRIPTION
The SAB2015 is the station memory and control circuit for the frequency control IC SAB2024. The
device is implemented in LOCMOS, which requires only a small back-up battery to retain the station
memory contents during power interruptions. The SAB2015 is driven and controlled 'via the serial data
instruction bus (IBUS). The instructions applied via the I BUS control the following functions:
• The storage of up to 16 stations of the viewer's choice.
• Direct station selection.
• The bidirectional step station function.
• Direct channel number access.
• The bidirectional channel number step function.
• Bidirectional search tuning through all channels with automatic stop on location of a television
transmission.
• The recall of last viewed station at POWER RON.
• Automatic muting in case of absence of transmission.
Information is transferred to the frequency control IC SAB2024 and the on-screen display IC SAB1016
via the DB US station and/or channel select and display.
OPERATION DESCRIPTION
Data input
The SAB2015 can perform the instructions as listed in Table 1. The instructions are received in IBUS
code; the instruction code, synchronized with-the system clock, must be applied to input DATA. It
will be accepted only if the data enable input DLEN is HIGH at the same time (for details see IBUS
description) .
Four modes of I BUS instructions are available:
• Station call instructions CAN MODIFY only the station counter, the memory contents, and the channel
counter.
• Channel mode instruction will only alter the contents of the channel counter.
• Recall instructions reproduce only the last DBUS output and can change the display mode control
signals.
• The 'standby' instruction resets the system, while an unfinished instruction sequence will be aborted.
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PHILIPS SAB2024 FREQUENCY CONTROL CIRCUIT
Features
•Automatic band switching, determined by the channel numbers.
• Micro-step tuning for unallocated frequencies.
• Control signal for AFC on/off.
• CATV channels available.
• Improved selection in respect of adjacent channels.
GENERAL DESCRIPTION
The frequency control circuit SAB2024 measures continuously the oscillator frequency of the TV
tuner. Together with the prescalerand the tuner it forms the frequency locked-loop in the DICS
system (Digital Char.nel Selection). When a tuning procedure is started, the oscillator frequency of the
TV tuner is measured and corrected until the deviation in frequency found is within the specified limit.
After that the automatic frequency control (AFC) part of the TV set is switched on to complete the
tuning.
Frequency measurement
The actual measurement is done within a fixed time of 2048 flS, which is derived from the 4 MHz
crystal oscillator. Before the measurement starts, the frequency counter is loaded 'with the addressed
contents from the frequency ROM. This content is the binary equivalent of the desired oscillator
frequency of the tuner in MHz. The frequency counter is now decremented with the incoming
frequency applied at input FDIV within the 2048 flS. Any remaining frequency in the frequency
counter at the end of the measuring time generates a pulse to outputs FUP or FDN with a duration
proportional to the tuning error. This pulse is used to modify the tuning voltage. By means of this, the
oscillator returns to the desired frequency within the range -337,5 kHz to + 787,5 kHz. When the
digital tuning is complete, the offset inaccuracy is set to -1337,5 kHz to + 787,5 kHz. The AFC is
then switched on to 'complete the tuning operation.
ROM program
As 'already mentioned, the ROM is programmed with the binary coded local oscillator frequencies
(x + 39) MHz, calculated from
fosc = fcarrier + Lt. = (x,25 + 38,9) MHz,associated with 100 (00 to 99) channels as shown in Tables 1 and 2.
Channels 77 to 99 are reserved for the S-band, used in CATV systems. The unused channels are automatically bypassed, indicated by signal GAP being HIGH. The ROM also generates the required band switch information as given in Tables 1 and 3. An adaption to Italian channels is possible (with the SAB2034).
Micro-step tuning
To enable the location of transmission of unallocated frequencies, the DICS system incorporates the micro-step tuning facility. Whenever a channel is selected and the TV transmission is not present, the micro-step tuning will automatically come into operation (see Fig. 3). The local oscillator frequency is detuned in five discrete steps away from the centre frequency in such a way that a complete cover- age of the entire band is obtained.
If a station is not detected, the micro-step will be automatically continued, except for search tuning. In that case a channel step will be done. Whenever a TV carrier drifts in frequency and comes outside the AFC control range (see Fig. 2), the micro-step tuning is restarted, thus within the channel range, the system follows the TV carrier.
Band switching and band ends
During band switching or during micro-step tuning, the system can tune to frequency areas outside the specified band ends. This results in an out of order situation for the control loop. A time constant is generated to avoid unwanted system blocks. If the tuner does not deliver the desired frequency in a ' time td (see Fig. 7) the output AFCON pulse will be set HIGH am;! the normal transmitter identification will be started. The delay time td is externally controlled by an RC network connected to input TICO. This delay time must be long enough, for the system to tune properly and reliably under all conditions (see Fig. 12).
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Agree The TV of the future is here . . . in the Heathkit Digital-Design
GR-2000 TV," magazine , source unknown, pp. 28-29.
"If you can use any of these tools . . . ," Radio Electronics, date unknown, pp. 46-47.
Page from article, Radio Electronics, date unknown, p. 50.
Pat. Abs. of Japan, vol.
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