TELEFUNKEN PALCOLOR 8108 CHASSIS 714A UNITS VIEW.

- NETZ EINGANG BS422 MAINS INPUT ET309378996

- ANSTEUERUNG BS423 SMPS UNIT AT 349354067 WITH THOSHIBA BU208A

- SYNCHRONISIERUNG BS533 AT 349354133 WITH TDA1950

- VERTIKAL ENDSTUFE BS453 AT 349354096 WITH TDA1170

- SEC. SPANNUNGSERZEUGUNG BS426 AT349354095

- VIDEO BS 349354141 WITH TDA3560


-TON BS BS157 AT349354131

- BILD-ZF-VERST BS105 AT349354129


- ESS3 BS650 AT349354136 WITH U336M (REMOTE DECODER) +

AY-3-8210 Miscellaneous Digital Circuit - ECONOMEGA II,A digital tuning system

FEATURES
I 16/32 Program Options
I 4 Bands
I 14 Elit Tuning Resolution on B3
I Program Copying
I Non-Volatile Memory without Battery
I Manual Up/Down Tuning
I Manual Band Switching
I Mute Output at Program Selection
I Search Active Output
I Local Program Llp/Down Control
I Validate Circuitry
I Referenced Tuning Waveform Output
I Band Step Option 3/4 Select
DESCRIPTION
The Economega IIA Digital Tuning system is a voltage synthesizer
for both Ftadio and TV manual tuning applications.
The AY-3-8211 N-Channel control chip interfaces directly with an
ER140() non-volatile memory enabling storage of up to 32 programs.
Variable mark space ratio tuning information from the AY-3-8211
is amplified and filtered, and the resulting DC level used to con-
trol the TV or Radio tuner,
OPERATION
Tuning-Resolutions are as follows:
0 tlon1 Option 2
B1 (Band 1) 11 bits (16mV) 12 bits (8mV)
B2 (Band III), B4 12 bits tamv). 13 bits (4mv)
B3 (UHF) 14 bits (2rnVl 14 bits (2mV)
These are the tuning information incrementing resolutions con-
trolled bythe Tune Up/ Down, Band Inputs, and Fine Tune inputs.
Voltages relate to approximately 30 volt tuning range.
Fine Tune-The Fine Tune steps approximately 8 times per second
(related to system clock). The Fine Tune input is disabled when
searching (Band inputs pressed orTune Llp/Down active) and when
Mute is active. Tuning resolutions as above.
Scanning-The actual tuning rates, fixed bythe Tuning Clock, may
be adjusted over a wide limit. typical figures are quoted below.
Operation of a Band Input or Tune Up/Down initiates scanning on
the selected band, and the Search O/P goes low.
Typical Scan rates are as follows:
Scan 1'Ime
Band Opt|on1 Option 2
1 1.25 sec 2.5 sec
2, 4 2.5 sec 5 sec
3 10 sec 10 sec
This corresponds to a Tuning Clock of approximately 1.6KHz.
When the Tuning Output overflows, scanning pauses for 256ms to
allow time for the tuning voltage, and il in Band Step Mode, the
Band outputs to settle.
This pause occurs at the bottom ot the tuning range when tuning
up and at the top ofthe tuning range when tuning down.
Mutlng-When a program change is made, at Power ON, and

Standby to OFF, the mute output is activated for 256 msecs and
disables the Fine Tune inputsfor this time, Mute O/Pis also active
while scanning; i.e. when a Band l/P or Tune Up/Down I/P is
active.
Tuning Procedure-Three tuning procedures are available:
(a) 1. Select required program number (1 to 16 or 32).
2. Press required band button, scanning commences from
the station currently tuned, scanning stops immediately
upon release of button.
3. Fine tune if required.
4. Tuning information is stored automatically upon release
of band button or release of Fine Tune button.
5. Tuning information may be copied by pressing Copy
and selecting a new program number.
(b)With Tuning Option selected:
1. Select Band-this is latched on,
2. Tune Up or Down using Tune Up/Down Input.
3. Fine Tune if required.
4. Tuning information is stored automatically upon release
of Tune Up/Down or release of Fine Tune Up/Down.
5. A program location is selected by first pressing Copy and
then selecting the required Program number.
(c) With Band Step 3 or4 selected and Tuning Option Selected:
1. Select band-this is latched on.
2. Tune Up or Down (Tuning will now follow from band to
band).
3. Once a station is tuned, release Tu ne Up/Down and Fine
Tune, if required.
4. Tuning information is stored automatically upon release
of Tune Up/Down or release of Fine tune Up/Down.
5. A Program location is selected by first pressing copy and
then selecting required program number.
Output Signals-Tuning voltage and Band outputs are not dis-
turbed by internal sequences, for example; STORE and COPY
Only program change will disturb these outputs-program change
being either a change of band and/or tuning information.



- TUNER FOR VST SEARCH TYPE



TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUITGENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power ratio.






TDA1950 (itt), Line Circuits for TV Receivers (18-Pin Plastic Package)
These integrated circuits are advanced versions of the well-known types TDA1940, TDA1940F, TDA1950 and TDA1950F are identical
TBA940/950, TDA9400/9500 etc. integrated line oscillator circuits. except the following: at pin 2 the types having the suffix "F" supply ,
They comprise all stages for sync separation and line synchronisation horizontal output pulses of longer duration compared with the basic I
in TV receivers in one single silicon chip. Due to their high degree of types Integration, the number of external components is very small.
This integrated circuit contains the horizontal sweep generator (HO), the amplitude filter (AS), the sync-signal separating circuit (SA) and the frequency/phase comparator (FP). For the purpose of suppressing noise pulses which are caused via the operating voltage during the upper and the lower inversion point of the horizontal sweep generator (HO) which contains a single capacitor (C) and a first threshold stage circuit (SS1) with two fixed thresholds, there are provided a second and a third threshold stage circuit (SS2, SS3), to the inputs of which the sawtooth signal is applied, and with the thresholds thereof, approximately 2 μs prior to reaching the upper or the lower peak value of the sawtooth signal, are being passed through thereby. The output signal of the second threshold circuit (SS2) and the output signal of the third threshold stage circuit (SS3) which is applied via the pulse shaper circuit (IF), are superimposed linearly and, via the stopper circuit (blocking stage) (SP) serve to control the application of the composite video signal (BAS) to the amplitude filter (AS), or else they are applied to a clamping circuit which serves to apply the operating points of the amplitude filter (AS) and/or of the sync-signal separating circuit (SA) to such a potential that these two stages, for the time duration of these output pulses, are prevented from operating.
1. An integrated circuit for color television receivers, comprising a voltage- or current-controlled horizontal sweep generator (HO), an amplitude filter (AS), a synchronizing-signal separating circuit (SA) and a frequency/phase comparator (FP) which serves to synchronize the horizontal sweep generator (HO), with said generator being a sawtooth generator containing a single capacitor (C) and a first threshold stage circuit (SS1) having two fixed thresholds, said integrated circuit further comprising:
a second and a third threshold stage circuit (SS2, SS3) each being supplied with the sawtooth signal on the input side, comprising each time one threshold which, approximately 2μs prior to the reaching of the upper or the lower peak value of the sawtooth signal, is being passed thereby;
a pulse shaper circuit (IF) coupled to the output of said third threshold stage circuit (SS3) which pulse shaper circuit reduces the duration of the output pulse thereof to about the duration of the output pulse of said second threshold stage circuit (SS2), and
a stopper circuit (blocking stage) (SP) coupled to the outputs of both said pulse shaper circuit (IF) and said second threshold stage circuit (SS2), said stopper circuit having a signal input to which there is applied a composite video signal (BAS) and a signal output which is coupled to the input of said amplitude filter (AS).


2. The invention of claim 1 wherein the outputs of both said pulse shaper circuit (IF) and said second threshold stage circuit (SS2) are coupled to a clamping circuit which applies the operating points of said amplitude filter (AS) and said sync-separating signal (SA) to such a potential that they are prevented from operating.

3. An integrated horizontal sweep circuit comprising:
a generator for generating a sawtooth signal;
an amplitude filter having an input for receiving a composite video signal and having an output;
a sync-signal separating circuit having an input coupled to said amplitude filter output and having an output;
a frequency/phase comparator having a first input coupled to said separating circuit output,
a second input receiving said sawtooth signal and an output for controlling said generator; and
a control circuit responsive to said sawtooth signal for inhibiting said composite video signal when said sawtooth signal is within predetermined signal level ranges about the upper and lower inversion points of said sawtooth signal.


4. An integrated circuit in accordance with claim 3 wherein:
said generator comprises a capacitor, circuit means for charging and discharging said capacitor, and a first threshold circuit controlling said circuit means in response to said sawtooth signal reaching a first level corresponding to said first inversion point and a second level corresponding to said second inversion point.


5. An integrated horizontal sweep circuit comprising:
a sawtooth signal generator;
an amplitude filter having an input receiving a composite video signal and having an output;
a sync-signal separating circuit having an input coupled to said amplitude filter output and having an output;
a frequency/phase comparator having a first input coupled to said separating circuit output, a second input receiving said sawtooth signal and an output for controlling said generator; and
a control circuit responsive to said sawtooth signal for inhibiting operation of said amplitude filter and/or said sync-signal separating circuit when said sawtooth signal is within predetermined signal level ranges about the upper and lower inversion point of said sawtooth signal.


6. An integrated circuit in accordance with claim 5 wherein:
said generator comprises a capacitor, circuit means for charging and discharging said capacitor and a first threshold circuit controlling said circuit means in response to said sawtooth signal reaching a first level corresponding to said first inversion point and a second level corresponding to said second inversion point.

Description:

BACKGROUND OF THE INVENTION
The invention relates to an integrated circuit for (color) television receivers, comprising a voltage- or current-controlled horizontal-sweep generator, an amplitude filter, a synchronizing signal separating circuit (sync-separator) and a frequency/phase comparator which serves to synchronize the horizontal sweep generator which is a sawtooth generator consisting of a single capacitor and of a first threshold stage having two fixed switching thresholds, cf. preamble of the patent claim. Such types of integrated circuits, for example, are known from the technical journal "Elektronik aktuell", 1976, No. 2, pp. 7 to 14 where they are referred to as TDA 9400 and TDA 9500.
Especially on account of the fact that the amplitude filter as well as the horizontal sweep generator in the form of the aforementioned sawtooth generator, are integrated on a single semiconductor body, it is likely that noise interference pulses coming from the individual stages, and via the supply voltage line, may have a disturbing influence upon the horizontal sweep generator, i.e. upon the threshold stage thereof, in such a way that either the lower or the upper or successively both switching thresholds are exceeded before the time by the voltage at the capacitor, owing to the noise superposition, so that the generator will show to have a "wrong" frequency or phase position. This frequency/phase variation, of course, is compensated for by the circuit, with the aid of the synchronzing pulses, but only in such a way that the noise effect remains visible in the television picture.
SUMMARY OF THE INVENTION
The invention is characterized in the claim is aimed at overcoming this drawback by solving the problem of designing an integrated circuit of the type described in greater detail hereinbefore, in such a way that noise pulses acting upon the capacitor voltage or the internal reference voltages for the switching thresholds (see below) in the proximity of the two switching thresholds, are prevented from having the described disadvantageous effect. Accordingly, an advantage of the invention results directly from solving the given problem.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiment, the appended claims and the accompanying drawing in which:
BRIEF DESCRIPTION OF THE INVENTION
The invention will now be described in greater detail with reference to the accompanying drawing. This drawing, in the form of a schematical circuit diagram, shows the construction of an integrated circuit according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
The horizontal sweep generator HO comprises the capacitor C as connected to the zero point of the circuit, and which is charged and discharged via the two shown constant current sources CS1 and CS2, thus causing the intended sawtooth voltage to appear thereat. Moreover, the horizontal sweep generator HO comprises the first threshold stage circuit SS1, having an upper and a lower threshold. As soon as the capacitor voltage exceeds one of the thresholds, the first threshold stage circuit SS1 switches over to the other threshold. The two thresholds are defined by the voltage divider P as connected to the operating voltage U, and in which the corresponding threshold inputs are connected to corresponding tapping points. The output of the threshold stage circuit SS1 controls the electronic switch S, so that the constant current source CS2 as connected thereto, is either disconnected from or connected to the zero point of the circuit. Accordingly, in the disconnected state, the capacitor C is charged via the constant current source CS1 arranged in series therewith while in the connected state the capacitor C is discharged across the aforementioned constant current source CS2 arranged in parallel therewith, if, as a matter of fact, the current of the constant current source CS1 arranged in series with the capacitor C, is smaller than that of the parallel-arranged constant current source CS2.
Now, for the purpose of avoiding the aforementioned drawbacks, there is provided a second and a third threshold stage circuit SS2 and SS3, respectively, as well as the pulse shaper circuit IF. To the respective input of the two threshold stage circuits SS2, SS3, there is applied the capacitor voltage, in the form of the sawtooth signal, and these stages have a threshold voltage which, approximately 2 μs prior to the reaching of the upper or the lower peak value of the sawtooth voltage, is being passed thereby. This means to imply that the threshold voltage of the second threshold stage circuit SS2 is somewhat lower than the voltage of the upper threshold of the first threshold stage circuit SS1, and that the threshold voltage of the third threshold stage circuit SS3 is somewhat higher than the voltage of the lower threshold of the first threshold stage circuit SS1. The two thresholds of the threshold stage circuits SS2, SS3 can thus be realized in a simple way by providing further tapping points at the voltage divider P, as is shown in the accompanying drawing. Thus, the second threshold stage circuit SS2 is provided for at a voltage divider tapping point below the tapping point chosen for the upper threshold, and the tapping point for the third threshold stage circuit SS3 is provided for above the tapping point which has been chosen for the lower threshold of the first threshold stage circuit SS1.
Since, within the area of the lower inversion point of the sawtooth signal there results an excessively wide output pulse of the third threshold stage circuit SS3, the pulse shaper circuit IF is arranged subsequently thereto, for reducing the duration of the output pulse as applied to its input, to about the duration of the output pulse of the second threshold stage circuit SS2. This pulse shaper circuit IF, for example, may be realized by a monoflop, in particular by a digital monoflop (=monostable circuit).
The output pulses of the second threshold stage circuit SS2 and of the pulse shaper circuit IF are then super-positioned linearly, with this being denoted in the drawing by a simple interconnection of the two respective lines. The combined signal is applied to the input of the stopper circuit (blocking stage) SP, to the signal input of which there is fed the composite video signal BAS, and the output thereof controls both the amplitude filter AS and the synchronizing signal separating circuit SA.
The combined signal may also be used to control a clamping circuit applying the operating points of the amplitude filter AS and/or of the sync-signal-separating circuit SA to such a potential which prevents it from operating.
If now the sawtooth signal reaches the range of its upper or its lower inversion point, the composite video signal BAS is not applied to either the amplitude filter AS or the sync-signal separating circuit SA, so that shortly before and shortly after the inversion points, signals are prevented from being processed in the two stages AS, SA. This, in turn, has the consequence that during these times noise pulses are prevented from superimposing upon the operating voltage U, so that there is also prevented an unintended triggering of the first threshold stage circuit SS1.
Moreover, it is still shown in the drawing that the amplitude filter AS, the sync-signal separating circuit SA and the frequency/phase comparator FP are arranged in series in terms of signal flow, with the latter, in addition, receiving the sawtooth signal, and with the output signal thereof acting upon the two current sources in a regulating sense. In the drawing, this is indicated by the setting arrows at the two current sources.
While the present invention has been disclosed in connection with the preferred embodiment thereof, it should be understood that there may be other embodiments which fall within the spirit and scope of the invention as defined by the following claims.



GENERAL DESCRIPTION
The TDA3560A is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.

APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.


Video signal processing circuit for a color television receiver  PHILIPS TDA3560:  In a video signal processing circuit for a color television receiver, a brightness setting, which is operative for external color signals as well as for internal color signals and which does not produce a color shift, can be obtained by combining with the luminance signal (Y) a level shift signal (H) the amplitude of which is adjustable by the brightness setting and by employing in each color channel two clamping circuits, the first one of which clamps a first reference level (RL₁) in the external color signal (ER, EG, EB) onto a combination of the level shift signal and the internal color signal (R, G, B) and the second clamping circuit clamps a second reference leve (RL₂) which occurs in the sum signal of the internal and the external color signal when the level shift signal has zero value, onto the cutoff level of the relevant electron gun of a picture display tube.
1. A video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals and for external color signals, comprising respective matrix circuits for combining the respective color difference signals with the luminance signal to form respective color signals, respective first clamping circuits for clamping the respective external color signals onto the respective color signals, respective combining circuits for combining the respective clamped external color signals with the respective color signals, respective second clamping circuits for clamping the outputs of the respective combining circuits onto a predetermined level, and a brightness setting circuit, characterized in that the first clamping circuits act on a first reference level in said respective external color signals occurring in a first group of periods and the second clamping circuits act on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal, which is combined with the luminance signal prior to processing the color difference signals, with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.

2. A video signal processing circuit as claimed in claim 1, characterized in that the respective first and second clamping circuits are operative alternately and every other line flyback period.

Description:

BACKGROUND OF THE INVENTION
The invention relates to a video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals, and for external color signals, comprising a matrix circuit for combining a color difference signal with the luminance signal to form a color signal, a first clamping circuit for clamping an external color signal onto the corresponding color signal, a combining circuit for combining a clamped external color signal with the corresponding color signal, a second clamping circuit acting on an output signal of the combining circuit and a brightness setting circuit.
A video signal processing circuit of the type defined above is described in Philip Data Handbook for Integrated Circuits, Part 2, May, 1980 as IC TDA3560. The brightness setting, which is common for internal and external video signals, is obtained by means of a common direct current level setting of the second clamping circuits. The settings of the three electron guns of a picture display tube coupled to the outputs of the video signal processing circuit are changed to an equal extent by this direct current level setting as a result whereof, due to the mutual differences in the efficiency of the phosphors of the picture display tube, a color shift may occur at a brightness adjustment. It is an object of the invention to prevent this.
SUMMARY OF THE INVENTION
According to the invention, a video signal processing circuit of the type defined in the preamble is therefore characterized in that the first clamping circuit acts on a first reference level occurring in a first group of periods and the second clamping circuit acts on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
Owing to the measure in accordance with the invention, the common setting of the brightness for internal video signals is maintained and a color shift is prevented from occurring at a brightness setting.
DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be further described by way of example with reference to the accompanying drawings.
In the drawings:
FIG. 1 illustrates, by means of a block schematic circuit diagram, a video signal processing circuit in accordance with the invention; and
FIG. 2 shows some waveforms such as they may occur in the circuit shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1, an external red color signal ER' is applied to an input 1, a red color difference signal (R-Y) to an input 3, an external green color signal EG' to an input 5, a luminance signal Y to an input 7, a green color difference signal (G-Y) to an input 9, an external blue color signal EB' to an input 11, a blue color difference signal (B-Y) to an input 13 and a synchronizing signal S to an input 15.
The luminance signal at the input 7 is shown in FIG. 2 as a waveform 207. In the line flyback periods this luminance signal has a black level Z which, for simplicity, is assumed to occur in all cases during the whole line flyback period but which may, of course, alternatively occur during only a portion of that line flyback period.
The luminance signal Y is applied to an input 17 of a combining circuit 19. To a further input 21 thereof, a level shift signal H is applied which, via an amplitude setting circuit 23, is obtained from an output 25 of a pulse generator 27, to an input 29 of which the synchronizing signal S is applied.
The level shift signal H is shown in FIG. 2 as a waveform 221 which in this case has a zero amplitude every other line flyback period and at other times an amplitude which depends on the setting of the amplitude setting circuit 23.
The respective color difference signals (R-Y), (G-Y) and (B-Y) at the respective inputs 3, 9 and 13, are applied to inputs 31, 33 and 35, respectively, of matrix circuits 37, 39 and 41, respectively, to respective inputs 43, 45 and 47 of which the combination Y+H of the luminance signal (Y) and the level shift signal (H) is applied, and from respective outputs 49, 51 and 53, the red (R) and green (G) and blue (B) color signals are obtained. FIG. 2 shows the red color signal of said color signals as a waveform 249.
The respective external color signals ER', EG' and EB' at the respective inputs 1, 5 and 11 are applied to respective inputs 61, 63 and 65 of respective combining circuits 67, 69 and 71 via respective capacitors 55, 57 and 59. Further inputs 73, 75 and 77, respectively, of the combining circuits 67, 69 and 71, respectively, are connected to the outputs 49, 51 and 53, respectively, of the matrix circuits 37, 39 and 41, respectively, and receive the red, green and blue color signals, respectively.
Arranged between the inputs 61 and 73, 63 and 75, and 65 and 77, respectively, there are first clamping circuits 79, 81 and 83, respectively, which, under the control of a pulse signal K₁ coming from an output 84 of the pulse generator 27, clamps a first reference level RL₁ in the respective external color signals ER', EG' and EB' onto the respective color signals R, G and B, as a result of which the respective clamped external color signals ER, EG and EB at the respective inputs 61, 63 and 65 of the combining circuits 67, 69 and 71 are produced, the signal level ER at the input 61 of the combining circuit 67 being shown in FIG. 2 as the waveform 261. The pulse signal K1 is shown in FIG. 2 as the waveform 284.
At respective outputs 85, 87 and 89 of the combining circuits 67, 69 and 71, respectively, there are now produced signals which are the sums of the respective clamped external color signals ER, EG and EB and the respective color signals R, G and B. Via respective capacitors 91, 93 and 95, said sum signals (ER+R), (EG+G) and (EB+B), respectively, are applied to respective inputs 97, 99 and 100 of respective video output amplifiers 102, 104 and 106, respective outputs 108, 110 and 112 of which being connected to respective cathodes of a picture display tube 114.
Second clamping circuits 116, 118 and 120, respectively, which are rendered operative by a pulse signal K2 coming from an output 122 of the pulse generator 27 and whereby a second reference level RL2 in the signals at the respective inputs 97, 99 and 100 is adjusted to a fixed potential, zero potential here, are connected to the respective inputs 97, 99 and 100 of the respective video output amplifiers 102, 104 and 106. This is shown in FIG. 2 by means of the waveform 297 for the signal (ER+R) at the input 97 of the video output amplifier 102. For the sake of clearness, the luminance signal (Y) and the red color difference signal (R-Y) are assumed to have zero values.
The picture display tube 114 has a deflection circuit 124 which is controlled by signals coming from outputs 126 and 128, respectively, of the pulse generator 27.
On the basis of FIG. 2, it will now be demonstrated that the brightness of the color signals as well as of the external color signals is adjustable by means of the amplitude setting circuit 23, more specifically in such a ratio, occurring at the picture display tube 114, that no color shift is produced.
If a luminance signal Y and a color difference signal (R-Y) are produced and the external color signal ER' has zero value, the signal at the output 49 of the matrix circuit 37 has the waveform 249 and likewise the signal at the input 97 of the video output amplifier 108, as during the occurrence of the signal K2 (waveform 222), the second clamping circuit 116 has adjusted the second reference level RL₂ to zero, which corresponds to the cutoff level of the relevant cathode of the picture display tube 114. Outside the periods in which signal is clamped to the second reference level RL₂, the black level, shown in the waveform 249 by means of a dashed line, of the color signal at the input 97 of the video amplifier is determined by the amplitude of the level shift signal H, which, in response to the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube, are applied in the relevant signal paths to the cathodes of the picture display tube 114 to said cathodes in such an amplitude ratio that no color shift can be produced.
If there is an external color signal but no luminance and color difference signals (Y=O, R-Y=O, G-Y=O, B-Y=O), then a signal is produced at the input 97 of the video output amplifier 102 which has the waveform 297 and which, during the occurrence of the second reference level RL₂, is clamped onto zero by the second clamping circuit 116 by means of the clamping pulses K2 and which consequently corresponds to the cutoff level of the relevant cathode of the picture display tube 114. During the occurrence of the first reference level RL₁ in the signal ER', the first clamping circuit 79 clamps the signal ER (waveform 261) at the input 61 of the combining circit 61 onto the output signal of the matrix circuit 37 during the occurrence of the clamping pulses K1 (waveform 284). Now this output signal has the waveform 221, as R-Y and Y have zero values. From the waveform 297, it now appears that the signal ER+R, which in this case is equal to ER+H, has, outside the periods in which the second reference level RL₂ occurs in the waveform 297, a black level which is indicated by means of a dashed line and is determined by the amplitude of the level shift signal H. Also now this amplitude is applied in the proper ratio to the cathodes of the picture display tube 114 by the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube 114, so that no color shift can be produced.
It will be obvious that it is not imperative that the clamping pulses K1 and K2 be produced alternately and every other line flyback period. If so desired, the clamping pulses K1 may, for example, occur in a number of line trace periods of the field trace which are located outside the visible picture plane, and the clamping pulses K2 may occur in the line flyback periods. The clamping pulses K2 must be produced in the period in which the level shift signal causes the second reference level RL₂ and the clamping pulses K1 outside said periods and in the periods the first level reference level RL₁ occurs.
In the above-described embodiment the clamping circuits are provided in the form of short-circuiting switches which are arranged subsequent to capacitors which have for their function to block direct current signals. It will be obvious, that, if so desired, clamping circuits in the form of control circuits may alternatively be used and that in that event, if so desired, blocking the direct current component by a capacitor may be omitted.
If so desired, instead of an adder circuit 19, an insertion circuit may be employed by means of which, in the appropriate periods of the luminance signal, when the signal K2 is produced the reference level Z then present, is replaced by a new level which is influencable by the brightness setting .

BU208(A)

Silicon NPN
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.

DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.

APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.

ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C


TELEFUNKEN CHASSIS 714A Drive circuit for an infrared remote control transmitter:

An infrared remote control transmitter includes at least one infrared light-emitting diode poled with respect to a point of reference potential so as to be conductive in response to voltages having the opposite polarity of a DC supply voltage and to be nonconductive in response to voltages having the same polarity as the DC supply voltage. A push-pull amplifier is responsive to a pulse signal encoded to represent a remote control message to selectively couple the DC supply voltage or the reference potential to a capacitor coupled in series between the push-pull amplifier and the light-emitting diode. The capacitor is charged and discharged and an alternating drive voltage for the light-emitting diode having portions with polarities both the same as and opposite to the polarity of the DC supply voltage is generated. The push-pull amplifier is arranged so that when a component failure occurs, the portions of the alternating drive voltage having the polarity opposite to the polarity of the DC supply voltage are at least inhibited to prevent the continuous (i.e., DC) emission of infrared radiation.

1. In an infrared remote control transmitter for controlling a television system, apparatus comprising:
a reference circuit point for receiving a reference potential;
a supply circuit point for receiving a DC supply voltage;
a battery connected with a predetermined polarity connected between said supply and reference circuit points;
at least one light-emitting diode for emitting infrared radiation when rendered conductive, said light emitting diode having a cathode and an anode, one of said cathode and anode being connected to said reference circuit point, said light-emitting diode being poled with respect to said reference circuit point so as to be conductive in response to the application of a voltage to the other one of said cathode and anode having the opposite polarity to said battery with respect to said reference circuit point and non-conductive in response to the application of a voltage to said other one of said cathode and anode having the same polarity as said battery with respect to said reference circuit point;
a source cir

cuit point for receiving an input signal having pulses encoded to represent information for controlling a predetermined function of said television receiver;
a drive circuit point;
a capacitor directly connected between said drive circuit point and said other one of said cathode and anode;
a diode directly connected between said other one of said cathode and anode and said reference circuit point and poled in the opposite sense to said light-emitting diode with respect to said reference circuit point;
push-pull amplifier means for developing a drive voltage at said drive point including first and second bipolar transistors of opposite conduction types, each of said transistors having a collector-emitter path and a base electrode for controlling the conduction of said collector-emitter path, said collector-emitter path of said first transistor being directly connected between said supply circuit point and said drive circuit point, said collector-emitter path of said second transistor being connected between said drive circuit point and said reference point; and
input means coupled between said source circuit point and said bases of said first and second transistors for rendering said collector-emitter path of said first transistor conductive and said collector-emitter path of said second transistor non-conductive in response to a first portion of said pulses of said input signal and for rendering said collector-emitter path of said second transistor conductive and said collector-emitter path of said first transistor non-conductive in response to a second portion of said pulses of said input signal.
2. The apparatus recited in claim 1 wherein:
three light-emitting diodes poled in the same direction are connected in series between said capacitor means and said reference circuit point.
3. The apparatus recited in claim 1 wherein:
a second capacitor is directly connected between said drive point and said other one of said cathode and anode in parallel with said first mentioned capacitor directly connected between said drive point and said other one of said cathode and anode.
4. The apparatus recited in claim 1 wherein:
said input means includes a first capacitor connected between said source circuit point and said base of said first transistor; first means connected between said supply circuit point and said base of said first transistor for discharging said first capacitor; a second capacitor connected between said source circuit point and said base of said second transistor; and second means connected between said base of said second transistor and said reference circuit point for discharging said second capacitor.
5. The apparatus recited in claim 4 wherein:
said first means includes a further diode poled to be conductive when said collector-emitter path of said first transistor is non-conductive and non-conductive when said collector-emitter path of said first transistor is conductive; and
said second means includes a still further diode poled to be conductive when said collector-emitter path of said second transistor is non-conductive and non-conductive when said collector-emitter path of said second transistor is conductive.
6. In an infrared remote control transmitter for controlling a television system, apparatus comprising:
a reference circuit point for receiving a reference potential;
a supply circuit point for receiving a DC supply voltage;
a battery connected with a predetermined polarity connected between said supply and reference circuit points;
three light-emitting diodes which emit infrared radiation when rendered conductive directly connected in series between a voltage application circuit point and said reference circuit point, all of said light-emitting diodes being poled with respect to said reference circuit point so as to be conductive in response to the application of a voltage to said voltage application circuit point having the opposite polarity to said battery with respect to said reference circuit point and non-conductive in response to the application of a voltage to said voltage application circuit point having the same polarity as said battery with respect to said reference circuit point;
a source circuit point for receiving an input signal having pulses encoded to represent information for controlling a predetermined function of said television receiver;
a drive circuit point;
a first capacitor directly connected between said drive circuit point and said voltage application circuit point;
a second capacitor directly connected between said drive circuit point and said voltage application circuit point;
a diode directly connected between said voltage application circuit point and said reference circuit point and poled in the opposite sense to said light-emitting diode with respect to said reference circuit point;

push-pull amplifier means for developing a drive voltage at said drive point including first and second bipolar transistors of opposite conduction types, each of said transistors having a collector-emitter path and a base electrode for controlling the conduction of said collector-emitter path, said collector-emitter path of said first transistor being directly connected between said supply circuit point and said drive circuit point, said collector-emitter path of said second transistor being connected between said drive circuit point and said reference point; and
input means coupled between said source circuit point and said bases of said first and second transistors for rendering said collector-emitter path of said first transistor conductive and said collector-emitter path of said second transistor non-conductive in response to a first portion of said pulses of said input signal and for rendering said collector-emitter path of said second transistor conductive and said collector-emitter path of said first transistor non-conductive in response to a second portion of said pulses of said input signal.

Description:

BACKGROUND OF THE PRESENT INVENTION
The present invention relates to drive circuits for infrared remote control transmitters.
Infrared remote control systems for television receivers and the like are known. The chief advantage of infrared remote control systems in comparison to ultrasonic remote control systems is that they are less susceptible to erroneously-generated interference signals. Unfortunately, the human eye may be harmed under conditions of prolonged, continuous and direct exposure to infrared radiation.
In order to reduce the possibility of harm to the eyes of users, infrared remote control systems utilize special pulse codes which minimize the duration of infrared radiation during the transmission of remote controlled messages. However, since in conventional drive circuits for infrared remote control transmitters the infrared light source, e.g., a light-emitting diode or diodes, is typically included in a direct current path from a supply voltage, infrared radiation may be continuously emitted should there be a component failure in the remote control transmitter. Therefore, there is a requirement for drive circuits for use in infrared remote control transmitters in which component failures do not result in the continuous emission of infrared radiation. The present invention concerns such a "fail-safe" drive circuit.
SUMMARY OF THE PRESENT INVENTION
In a remote control transmitter, at least one infrared light-emitting diode is coupled to a point of reference potential and poled so as to be substantially nonconductive in response to voltages having the same polarity as a DC supply voltage for the transmitter and substantially conductive in response to voltages having the polarity opposite to the polarity of the DC supply voltage. Driver means responsive to an input signal is coupled between the source of the DC supply voltage and the light-emitting diode. The driver means normally generates an alternating drive voltage for the light-emitting diode having portions with polarities both the same as and opposite to the polarity of the DC supply voltage. The driver means is arranged so that the portions of the drive signal having the polarity opposite to that of the DC supply voltage are at least inhibited when a component failure occurs.
BRIEF DESCRIPTION OF THE DRAWING
The sole FIGURE of the drawing shows, partially in block diagram form and partially in schematic diagram form, an infrared remote control system constructed in accordance with the present invention as it may be employed in a television receiver arrangement.
DETAILED DESCRIPTION OF THE DRAWING
A television receiver 1 includes an antenna 3, a tuner 5, an IF signal processing unit 7, a picture signal processing unit 9, a sound signal processing unit 11, a picture tube 13 and a speaker 15 arranged in a conventional fashion to produce visual and audio responses. A power supply 17 is selectively energized to generate DC supply voltages for the portions of the receiver so far described from the AC line voltage in response to an ON/OFF control signal generated by a remote control receiver 19. Receiver 1 also includes a standby power supply 20 which continuously couples a DC supply voltage to remote control receiver 19 so that it is ready to accept messages from a remote control transmitter 21.
Remote control receiver 19 includes a photosensitive diode 23. The conduction of photo diode 23 is controlled in response to encoded optical signals having frequencies in the infrared range generated by remote control transmitter 21. A detector 25 senses the changes in the conduction of diode 23 and generates electrical signals corresponding to the encoded optical signals. The electrical signals are decoded by a decoder 27 to generate the ON/OFF control signal for tuning receiver 1 on and off, a CHANNEL SELECTION control signal for controlling the frequency to which a tuner 5 is tuned, and a VOLUME control signal for controlling the sound level of receiver 1.
Remote control transmitter 21 includes a keyboard 29 including push buttons (not shown) by which a user may control the various receiver functions enumerated above. When a push button is depressed a corresponding electrical signal is generated by keyboard 29. A pulse encoder 31 is responsive to these electrical signals to generate respective coded pulse signals. The coded pulse signals are processed by a driver 33 to cause infrared light-emitting diodes 35, 37 and 39 to generate corresponding optical signals in the infrared frequency range.
Various codes for infrared remote control systems and encoders and decoders for these codes are known. For example, encoder 31 and decoder 27 may comprise S2600 and S2601 integrated circuits manufactured by American Microsystems, Inc. of Santa Clara, Calif.
The exact nature of the codes is not directly germane to the present invention. However, it is desirable for the reasons of safety discussed earlier that the code formats are arranged so that the duration of infrared radiation during a transmission is minimized. Since the pulses of the pulse signals generated by pulse encoder 31 correspond to the intervals of infrared radiation, this may be accomplished by causing the electrical pulse signals generated by encoder 31 to have a relatively low duty cycle, e.g., less than 20 percent. In addition, for safety reasons, it is desirable that light-emitting diodes 35, 37 and 39 be physically separated on transmitter 21 from one another by a distance selected so that the power of the infrared radiation they generate is distributed rather than concentrated in a relatively small area.
While these safety precautions to some extent minimize the danger to users, they do not account for component failures which may cause the continuous, i.e., DC, emission of infrared radiation. Unfortunately, the human eye may be injured when directly exposed to continuous infrared radiation for prolonged periods. While such situations are extremely rare, since they would involve not only a component failure but the misuse of the transmitter, they may occur under extraordinary circumstances. For example, a curious child may point an infrared transmitter with a failed component directly into his eye.
Drive circuit 33 is arranged to prevent the continuous emission of infrared radiation under any foreseeable component failure mode. Driver 33 includes a push-pull amplifier 41 comprising a PNP transistor 43 and an NPN transistor 45 having their collector-emitter junctions coupled in series between a battery 47 and signal ground. Battery 47 is the source of DC supply voltage for transmitter 21. The output of pulse encoder 31 is coupled to the bases of transistors 43 and 45 through capacitors 49 and 51, respectively. Diodes 53 and 55 are coupled in shunt with the base-emitter junctions of transistors 43 and 45, respectively. The junction of the collectors of transistors 43 and 45 is coupled through parallel connected capacitors 57 and 58 to the cathode of light-emitting diode 35. Light-emitting diodes 35, 37 and 39 are connected in series with the same polarity between capacitors 57 and 58 and signal ground. The polarity of light-emitting diodes 35, 37 and 39 is selected so that they are rendered nonconductive in response to the application of voltages to the cathode of light-emitting diode 35 having the same polarity (i.e., positive) with respect to signal ground as the DC supply voltage provided by battery 47 and only rendered conductive in response to the application of voltages having the opposite polarity (i.e., negative) with respect to signal ground to the DC supply voltage. A diode 59 is connected in shunt with series connected light-emitting diodes 35, 37 and 39 and poled in the opposite direction.
In operation, pulse encoder 31 generates a pulse signal encoded as described above. The pulse signal includes positive-going pulses. In response to the leading edges of the positive-going pulses, transistor 45 is rendered conductive. In response to the trailing edges of the positive-going pulses, transistor 43 is rendered conductive. Diodes 53 and 55 serve as discharge paths for capacitors 49 and 51 during the intervals when transistors 43 and 45, respectively, are nonconductive. Diodes 53 and 55 also clamp the voltage at the bases of transistors 43 and 45 close to the battery voltage and the voltage at signal ground, respectively, in order to protect the base-emitter junctions of transistors 43 and 45 from reverse breakdown failure voltages. Desirably, capacitors 49 and 51 have relatively small values so that capacitors 49 and 51 are charged and discharged in response to each pulse. As a result, transistors 43 and 45 are alternately rendered conductive and nonconductive in response to each pulse of the pulse signal.
When transistor 43 is conductive (and transistor 45 is nonconductive) capacitors 57 and 58 are charged from battery 47. When transistor 45 is conductive (and transistor 43 is nonconductive) capacitors 57 and 58 are discharged to signal ground. As a result, an alternating drive voltage, i.e., one having polarity excursions above and below the potential at signal ground, are generated at the cathode of light-emitting diode 35. Light-emitting diodes are conductive in response to the negative portions of the drive voltage and are nonconductive in response to the positive portions of the drive voltage. Diodes 35, 37 and 39 only emit infrared radiation when they are conductive. Therefore, infrared radiation is only emitted by transmitter 21 when the drive voltage has a polarity (i.e., negative opposite to the polarity of the DC supply voltage.
Desirably, the capacitance of the combination of capacitors 57 and 58 is relatively large, e.g., 1 microfarad, so that sufficient drive current is provided to light-emitting diodes 35, 37 and 39 to cause them to emit infrared radiation. For the same reason, two capacitors rather than one are used, since the effective series resistance associated with the parallel combination is smaller than the series resistance of a single capacitor.
In the event that there is a component failure within drive circuit 33, drive voltage developed at the cathode of light-emitting diode 35 will be reduced and, in most cases, substantially inhibited. Under these conditions, since the amplitude of the negative portions of the drive signal will at least have a lower than normal amplitude, the infrared radiation will have a lower than normal energy.
Briefly, any failure of a component within driver 33 causing the component to open or short, substantially prevents the development of an alternating drive signal at the cathode of light-emitting diode 35. Since diodes 35, 37 and 39 are rendered conductive only in response to negative-going voltages, no infrared radiation is generated. Any component failure between the extremes of an open or short causes a reduction in the amplitude of the alternating drive signal. By way of example, consider the following failure modes. If either transistor 43 or 45 fails, e.g., by shorting from collector to emitter, capacitors 57 and 58 will be either permanently charged or discharged, thereby preventing the development of an alternating drive signal. If one of capacitors 57 and 58 shorts, only positive-going voltages are developed at the cathode of light-emitting diode 35. If the collector to emitter junction of transistor 43 and one of capacitors 57 and 58 short, a DC signal is coupled to the cathode of light-emitting diode 35, thereby rendering diode 59 conductive and preventing light-emitting diodes 35, 37 and 39 from being rendered conductive. If diode 59 opens, capacitors 57 and 58 will not be charged thereby preventing the development of an alternating voltage at the cathode of diode 35. If diode 59 fails so as to lose its unidirectional conductive characteristics, i.e., in essence becomes a passive element, an alternating drive signal will be developed but it will have a lower than normal amplitude. Furthermore, failures in pulse encoder 31 causing generation of a DC signal rather than a pulse signal will also cause the loss of an alternating drive signal.
Driver circuit 33 may be modified in some respects without causing the loss of its "fail-safe" nature. For example, any or all of diodes 53, 55 and 59 may be replaced with resistors. While this modification causes a reduction in efficiency of the normal operation of drive circuit 33, it does not alter its "fail-safe" nature. These and other modifications are intended to be within the scope of the present invention as set forth in the following claims.