The chassis is an awesome example of enegineering.
The chassis is fully modularized and has a technology like a high grade professional monitor.
The Beovision 7702 replaced the Beovision 7700 for the reason of the introduction of the new 77XX 30AX series chassis. This was in many ways similar to the final version of the previous 33XX type, to the point where most of the circuit modules were interchangeable, though there was one big change: electronic tuning.
The 78XX models included a microprocessor controlled “search and store” tuning system that offered a number of advantages over the bank of tuning knobs that the 33XX models used. 32 programmes could be stored, tuning was automatic and could be operated from either the set or the remote control. In the case where the channel number was known, this could be entered directly, making the tuning “instant”.
Teletext was a standard fitting for the 1984 season but it reverted to being an option for the rest of the production run. A single A/V socket (DIN A/V standard) was standard though a dual A/V interface could be specified, providing an extra DIN A/V socket (SCART in later versions), at extra cost.
BANG & OLUFSEN BEOVISION 7802 CHASSIS TYPE 7510 30AX Horizontal deflection output circuit:
A horizontal deflection output circuit, such as used in a TV receiver or a display device, includes a series circuit composed of a ringing preventing resistor and a one-way switching element connected in parallel with a linearity correcting coil. That one-way switching element is turned on at the beginning of a horizontal scanning period to feed a current to the ringing preventing resistor but is turned off in the vicinity of a fly-back period to block the flow of the current to the ringing preventing resistor. Thus, the power loss due to the current flowing through the ringing preventing resistor for the fly-back period can be reduced according to the present invention.
a switching element;
a resonant capacitor connected in parallel with said switching element; and
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil,
wherein the improvement comprises:
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for a first half of said horizontal scanning period and turns off for the last half of the horizontal scanning period and for a fly-back pulse period, thereby limiting current flow through said load means to the first half of said horizontal scanning period.
2. A horizontal deflection output circuit according to claim 1, wherein said load means includes a resistor. 3. A horizontal deflection output circuit according to claim 2, wherein a capacitor is connected in parallel with said linearity correcting coil. 4. A horizontal deflection output circuit according to claim 2, wherein said one-way switching element is a diode. 5. A horizontal deflection output circuit according to claim 1, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 6. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil; and
7. A horizontal deflection output circuit according to claim 6, wherein a capacitor is connected in parallel with said linearity correcting coil. 8. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is turned off at least for a fly-back pulse period. 9. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is a diode. 10. A horizontal deflection output circuit according to claim 6, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 11. A horizontal deflection output circuit according to claim 10, wherein a capacitor is connected in parallel with said linearity correcting coil. 12. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is turned off at least for a fly-back pulse period. 13. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is a diode. 14. A horizontal deflection output circuit according to claim 10, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 15. A horizontal deflection output circuit according to claim 14, wherein a capacitor is connected in parallel with said linearity correcting coil. 16. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is a diode. 17. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is turned off at least for a fly-back pulse period. 18. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for the first half of said horizontal scanning period and turns off for the last half of said horizontal scanning period and a fly-back pulse period, thereby limiting current flow through said load means to said first half of said horizontal scanning period;
a choke coil connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
19. A horizontal deflection output circuit according to claim 18, wherein said choke coil is a fly-back transformer. 20. A horizontal deflection output circuit according to claim 19, wherein said load means includes a resistor. 21. A horizontal deflection output circuit according to claim 20, wherein a capacitor is connected in parallel with said linearity correcting coil. 22. A horizontal deflection output circuit according to claim 20, wherein said one-way switching element is a diode. 23. A horizontal deflection output circuit according to claim 19, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 24. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor;
a choke coil in the form of a fly-back transformer connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
25. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is turned off at least for a fly-back pulse period. 26. A horizontal deflection output circuit according to claim 24, wherein a capacitor is connected in parallel with said linearity correcting coil. 27. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is a diode. 28. A horizontal deflection output circuit according to claim 24, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 29. A horizontal deflection output circuit according to claim 28, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 30. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is turned off at least for a fly-back pulse period. 31. A horizontal deflection output circuit according to claim 28, wherein a capacitor is connected in parallel with said linearity correcting coil. 32. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is a diode.
Description:
BACKGROUND OF THE INVENTIONIn a conventional TV receiver, a horizontal deflection current having a saw-tooth waveform reaches saturation as it approaches its maximum, causing a problem in that the scanning rate of the electron beam is reduced at the extreme right-hand side, as viewed toward the frame of the display, so that the picture reproduced on the face plate is distorted.
The circuit for solving the above-specified problem to form a symmetrical picture is called a "linearity correcting circuit". In order to correct the linearity of the raster scanned on the face plate, the linearity correcting circuit of the prior art is equipped with a linearity correcting coil which is connected in series with a horizontal deflection coil. That linearity correcting coil is so magnetically biased by means of a permanent magnet that its magnetic saturation characteristics are set differently depending upon the direction of the horizontal deflection current. This horizontal deflection circuit is exemplified by Japanese Patent Laid-Open Nos. 40615/1982, 128949/1981, 124850/1980 and U.S. Pat. No. 3,962,603, as shown schematically in FIGS. 1A and 1B.
As shown in FIG. 1A, the horizontal deflection circuit is composed of an input terminal 1, an output transistor 2, a damper diode 3, a resonant capacitor 4, a horizontal deflection coil 5, a linearity correcting coil 6, an S-shaped correction capacitor 7, a choke coil 8, a supply terminal 9, and a permanent magnet 12 for setting the magnetic bias of the linearity correcting coil 6.
The permanent magnet 12 has its polarity arranged so as to apply a magnetic field in the same direction as that of the magnetic field established in the linearity correcting coil in case a horizontal deflection current IDY flows in the direction of arrow a to the horizontal deflection coil 5.
In case the horizontal deflection current IDY flows in the direction of the arrow a, therefore, the linearity correcting coil 6 is more liable to be magnetically saturated than when the horizontal deflection current IDY flows in the reverse direction.
As a result, the inductance of the linearity correcting coil 6 is least in the vicinity of the maximum of the horizontal deflection current so that this current increases.
Thus, the drop of the scanning rate of the electron beam at the right side of the display frame is corrected. In the display, however, the use of a linearity correcting coil will form longitudinal shading streaks at the left side of the display frame. Those streaks are formed as a result of the fact that a ringing current is established in the horizontal deflection current by the resonance of a resonant circuit which is composed of the inductance of the linearity coil 6 and a stray capacity 17, as shown in FIG. 1B.
As the horizontal deflection current has its frequency increased and its output raised in accordance with the fineness in the structure of the display, however, there arises another problem that the power loss at the ringing current preventing resistor is increased.
SUMMARY OF THE INVENTION
BANG & OLUFSEN BEOVISION 7802 CHASSIS SERIES 77XX 30AX Horizontal deflection circuit with a start-up power supply
I
n a horizontal deflection circuit, a horizontal oscillator, energized by a supply voltage, develops a horizontal frequency switching signal. A deflection outputs stage is responsive to the switching signal and generates scanning current in a horizontal deflection winding. After commencement of oscillator operation, the voltage developed across a secondary winding of a flyback transformer is rectified and filtered and applied to the horizontal oscillator as the oscillator energizing supply voltage. A start-up supply for developing the oscillator supply voltage during an initial interval includes a source of voltage that is available for use prior to the commencement of oscillator operation, a capacitor, a charging circuit for charging the capacitor from the available voltage source, and a controllable switch coupled to the capacitor and to the oscillator. After the charging circuit has charged the capacitor to a predetermined threshold voltage level, the controllable switch is made conductive to apply the capacitor voltage to the oscillator to commence oscillator operation. The switch is arranged with the capacitor as a relaxation oscillator to begin discharging the capacitor by the load current drawn by the horizontal oscillator. Should the capacitor discharge to a lower threshold level before the flyback-derived supply voltage is developed, the relaxation oscillator changes states to disconnect the horizontal oscillator from the capacitor to initiate a capacitor recharging cycle.1. An oscillator-derived power supply with start-up circuitry, comprising:
a supply terminal;
an oscillator being energized by the voltage developed at said supply terminal for producing an oscillator output signal;
a start-up voltage supply to energize said oscillator into commencing operation, said start-up voltage supply comprising:
a capacitor,
a source of DC input voltage available prior to commencement of oscillator operation,
means for charging said capacitor from said DC input voltage source, and
switching means interposed between said capacitor and said supply terminal for applying said capacitor voltage to said oscillator after said capacitor has charged to a first threshold level, to commence oscillator operation;
means responsive to said oscillator output signal for developing a steady-state voltage; and
means for applying said steady-state voltage to said supply terminal via said switching means to maintain oscillator energization during steady-state operation.
a horizontal oscillator energized by a supply voltage for developing a horizontal frequency switching signal after commencement of oscillator operation;
a horizontal deflection winding;
a deflection output stage responsive to said horizontal frequency switching signal for generating scanning current in said deflection winding;
a flyback transformer having a first winding coupled to said deflection output stage for developing a horizontal frequency alternating polarity output voltage across a plurality of secondary windings;
supply voltage producing means responsive to the horizontal frequency alternating polarity output voltage developed across one of said plurality of secondary windings for producing said supply voltage after commencement of horizontal oscillator operation; and
a start-up supply for developing said supply voltage during an initial interval to enable said horizontal oscillator to commence operation, said start-up supply comprising:
a source of voltage available prior to commencement of horizontal oscillator operation,
a capacitor,
means for charging said capacitor from said prior available voltage source, and
switching means coupled to said capacitor and to said horizontal oscillator for applying said capacitor voltage to said horizontal oscillator as said supply voltage to commence horizontal oscillator operation after said charging means has charged said capacitor to an upper threshold voltage level, said switching means arranged with said capacitor as a relaxation oscillator that begins discharging said capacitor by the load current drawn by said horizontal oscillator after said charging means has charged said capacitor to said upper threshold voltage level and begins recharging said capacitor from said charging means when said capacitor discharges to a lower threshold voltage level.
Description:
This invention relates to start-up supplies for horizontal deflection circuits.
In a television receiver, the supply voltages to power various television receiver circuits such as the vertical deflection circuit and the audio and video circuits are derived from rectified and filtered flyback pulses developed by the horizontal deflection circuit. After the horizontal oscillator in the deflection circuit has commenced operation, the supply voltage for the oscillator is also derived from rectified and filtered flyback pulse voltages.
When the television receiver is turned on, the flyback pulse voltages are absent. A start-up supply for the horizontal oscillator is therefore required in order to energize the oscillator and develop the flyback-derived power supply voltages for the television receiver. A voltage that is available to power the oscillator during the start-up interval after the television receiver is turned on is the DC input voltage obtained by rectifying and filtering the AC mains supply voltage.
Since the horizontal oscillator is designed to use a relatively low supply voltage, the DC input voltage during start-up may be applied to the oscillator through a dropping resistor. The value of the resistor is selected to be relatively large in order to minimize the dissipation in the resistor while at the same time providing the horizontal oscillator with at least the minimum amount of current required to initiate oscillator operation. After the flyback-derived supply voltage becomes available, the normal load current for the oscillator is provided from this supply excluding the load current still being provided by the dropping resistor. Thus, the dropping resistor dissipates a significant amount of power even during steady-state television receiver operation after the start-up interval has elapsed.
To eliminate power dissipation in the dropping resistor during steady-state operation, some start-up circuits include a transistor switch in series with the dropping resistor. When the steady-state flyback-derived supply voltage for the oscillator is developed, the switch becomes reverse biased, disconnecting the dropping resistor from the oscillator. A relatively expensive switch is required that is capable of withstanding the off-state voltage stress applied to it. This off-state voltage equals the difference between the DC input voltage and the oscillator supply voltage.
A feature of the invention is the design of an oscillator-derived power supply with start-up circuitry that dissipates relatively little power during steady-state operation after the oscillator has commenced operation. An oscillator energized by the voltage developed at a supply terminal produces an output signal that is used by a subsequent power supply stage to develop a steady-state voltage to energize the load circuit. The steady-state voltage is also applied to the oscillator to maintain it energized after commencement of oscillator operation. A start-up voltage supply to energize the oscillator into commencing operation comprises a capacitor, a source of energy that is available prior to the commencement of oscillator operation, a charging circuit for charging the capacitor from the energy source, and switching means interposed between the capacitor and the oscillator. The switching means applies the capacitor voltage to the oscillator after the capacitor has charged to a first threshold level, thereby commencing oscillator operation and the development of the steady-state voltage by the oscillator responsive power supply.
With such an arrangement, the charging current flowing to the capacitor may be selected to be of relatively low magnitude, much lower than even the minimum amount of load current required to energize the oscillator. Dissipation in the charging circuit is substantially reduced, even though the charging circuit may still be supplying current during steady-state operation after commencement of oscillator operation.
During the start-up interval, the oscillator draws more current from the capacitor than is being supplied by the charging circuit, resulting in the capacitor being discharged. Another feature of the invention is that should the capacitor discharge to a lower threshold level, indicating that the steady-state voltage supply is still unavailable for use, the switching means disconnects the capacitor from the oscillator, enabling the capacitor to recharge and reinitiate the start-up sequence.
FIG. 1 illustrates a horizontal deflection circuit with derived power supplies and with a start-up circuit for the deflection oscillator; and
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1.
In FIG. 1, a source 20 of AC mains supply voltage is coupled to input terminals 23 and 24 of a full-wave bridge rectifier 27. Source 20 is coupled to input terminal 23 through an on/off switch 21 and a current limiting resistor 22. A filter capacitor 28 is coupled across output terminal 25 of bridge rectifier 27 and the current return or ground terminal 26. A filtered but unregulated DC input voltage Vin is developed at terminal 25 and applied to a regulator 29. Regulator 29 may be a conventional switching regulator, such as described
in U.S. Pat. No. 4,147,964, D. W. Luz et al., entitled "COMPLEMENTARY LATCHING DISABLING CIRCUIT", using an SCR regulator switch operated at the horizontal deflection frequency of a television receiver to produce a regulated B+ voltage at a terminal 30. Feedback of the B+ voltage to the switching regulator is provided by a conductor line 74. A filter capacitor 31 is provided to filter out horizontal rate ripple voltage from terminal 30.
The B+ voltage developed at terminal 30 is applied through the primary winding 32a of a flyback transformer 32 to the collector of a horizontal output transistor 35 in a horizontal deflection output stage 34 of a horizontal deflection circuit 80. Horizontal deflection circuit 80 includes a horizontal oscillator 43, energized by a supply voltage Vcc developed at a supply terminal 45 and drawing a load current iL therefrom, a horizontal driver transistor 44 and horizontal output stage 34. Horizontal output stage 34 comprises horizontal output transistor 35, a damper diode 36, a retrace capacitor 38 and the series arrangement of a horizontal deflection winding 39 and an S-shaping or trace capacitor 40.
Horizontal oscillator 43, when energized by the voltage developed at supply terminal 45, produces a horizontal frequency, 1/TH, output switching signal 37 that is inverted by horizontal driver transistor 44 and applied to horizontal output transistor 35 through a driver transformer 42 to produce the switching action needed to generate horizontal scanning current in horizontal deflection winding 39. A waveshaping and filtering network 41 is coupled between the secondary winding 42b of driver transformer 42 and the base and emitter electrodes of output transistor 35.
Horizontal output transistor 35 is turned on early within the trace interval of each deflection cycle to conduct the horizontal scanning current after damper diode 36 is cut off and is turned off to initiate the horizontal retrace interval. During horizontal retrace, a retrace pulse voltage Vr is developed at the collector of horizontal output transistor 35 and applied to flyback transformer primary winding 32a to develop alternating polarity horizontal retrace pulse voltages across secondary windings 32b-32d.
The high voltage developed across winding 32b is applied to a high voltage circuit 33 to develop a DC ultor accelerating potential at a terminal U. The voltage across flyback transformer secondary winding 32c is rectified by a diode 46 during the horizontal trace interval and filtered by a capacitor 47 to develop a DC supply voltage V1 at a terminal 49. Supply voltage V1 energizes and provides current to such television receiver load circuits as the vertical deflection circuit and the audio circuit, designated in FIG. 1 generally as a resistor 48. The voltage across flyback transformer secondary winding 32d is rectified during the horizontal retrace interval by a diode 51 and applied to a supply terminal 53 through a current limiting resistor 52 to develop a DC supply voltage V2 across a filter capacitor 54. The DC supply voltage V2 energizes and provides current to such television receiver load circuits as the video driver circuit designated in FIG. 1 generally as a resistor 55.
The rectified and filtered voltage from flyback transformer winding 32d also supplies the collector voltage for horizontal driver transistor 44. The substantially DC voltage developed at the cathode of diode 51 at terminal 50 is applied through a resistor 57 and primary winding 42a of driver transformer 42 to the collector of driver transistor 44. A capacitor 56 provides horizontal rate filtering.
When the television receiver is turned on, after closure of on/off switch 21, the unregulated DC input voltage Vin is developed at terminal 25 and applied to switching regulator 29 to develop a voltage at B+ terminal 30. During the initial or start-up interval following closure of on/off switch 21, the flyback-derived supply voltages V1 and V2 are absent. To generate these voltages, switching action of horizontal output transistor 35 must be initiated by initiating or commencing the switching actions of horizontal oscillator 43 and driver transistor 44. Energization of these two elements, 43 and 44, must be obtained from voltage or energy sources that are available for use prior to commencement of operation of horizontal oscillator 43 and driver transistor 44.
The voltage used during start-up for providing collector supply voltage to driver transistor 44 is the voltage developed at B+ terminal 30 after closure of on/off switch 21. Terminal 30 is coupled to terminal 50 through a resistor 59 and a diode 60. Collector voltage for driver transistor 44 is obtained from B+ terminal 30 during start-up by way of resistor 59 and diode 60.
A start-up supply 90 is provided to initially develop supply voltage for horizontal oscillator 43 to energize the oscillator into commencing operation. Start-up supply 90 comprises a capacitor 63, a transistor switch 66 interposed between capacitor 63 and horizontal oscillator 43 at the supply terminal 45, a source of energy or voltage available prior to commencement of oscillator operation, namely the source of the DC input voltage Vin, and a charging resistor 61 that is used to charge capacitor 63 during the start-up interval from the DC input voltage terminal 25 by way of a resistor 62. Resistor 62 is a relatively low valued resistor used for a purpose hereinafter to be described.
Upon closureof on/off switch 21 and the development of a DC voltage Vin at terminal 25, a charging current ic begins to flow through resistor 61 and resistor 62 to terminal 73, the junction of capacitor 63 and the emitter of controllable transistor switch 66. Capacitor 63 is initially uncharged and the voltage Vc at terminal 73 is zero, maintaining transistor switch 66 in the off-state immediately after closure of on/off switch 21.
The base of transistor switch 66 is coupled to the collector of a transistor 67 through a resistor 72. A biasing network for transistors 66 and 67, comprising resistors 68-72, establishes at terminal 73 an upper threshold voltage level Va and a lower threshold voltage level Vb so as to enable transistors 66 and 67 to form with capacitor 63 a relaxation oscillator arrangement. When transistor 66 is cut off, resistor 70 is effectively in parallel with resistor 69, thereby establishing the upper threshold voltage level Va of FIG. 2; and when transistor 66 is in saturated conduction, resistor 70 is effectively in parallel with resistor 68, thereby establishing the lower threshold voltage level Vb.
As illustrated in FIG. 2 by the solid-line waveform of the voltage Vc, at a time t0, on/off switch 21 is closed and the charging current ic flowing from terminal 73 begins to charge capacitor 63. At time t1, capacitor 63 has charged to the upper threshold voltage level Va, turning on transistor 67 which turns on transistor switch 66 into saturated conduction. After transistor 66 becomes conductive, the voltage across capacitor 63 is applied to horizontal oscillator 43 at supply terminal 45 as a start-up supply voltage for the horizontal oscillator. Horizontal oscillator 43 commences operation and begins producing the horizontal rate switching signal 37 to initiate the switching action of horizontal driver transistor 44 and horizontal output transistor 35, thereby initiating the development of the horizontal retrace pulse voltage Vr and the horizontal retrace pulse voltages across flyback transformer secondary windings 32b-32d.
The load current iL being drawn by horizontal oscillator 43 durin
g the initial or start-up interval, after time t1 of FIG. 2, is of greater magnitude than the charging current ic flowing to terminal 73 from charging resistor 61. Thus, after time t1, horizontal oscillator 43 begins discharging capacitor 63 as illustrated in FIG. 2 by the decreasing voltage Vc after time t1. Even though the voltage Vc applied to horizontal oscillator 43 during the start-up interval after time t1 is decreasing, it is still sufficiently greater than the minimum voltage needed to maintain the oscillator operating. Thus, the horizontal rate switching signal is still being produced by horizontal oscillator 43 after time t1. By time t2 of FIG. 2, a sufficient period has elapsed so as to enable a substantial buildup of the flyback-derived supply voltage V1 at terminal 49. Supply voltage V1 is then applied to horizontal oscillator 43 by way of a diode 64 that has its cathode coupled to terminal 65, the junction of charging resistor 61 and resistor 62. Diode 64 blocks the flow of charging current to flyback supply terminal to prevent undue shunting of the current from oscillator 43 during start-up.
Near time t2, the flyback-derived supply voltage V1 has increased sufficiently so as to be able to generate a current i1 flowing out of supply terminal 49 that is greater than the load current iL being drawn by horizontal oscillator 43. Thus, after time t2, capacitor 63 ceases discharging and becomes charged shortly thereafter to a relatively constant voltage level Vcc0, as illustrated by the solid-line waveform of FIG. 2 after time t2.
The voltage Vcc0 maintains transistor switch 66 conducting and is applied via the transistor to horizontal oscillator 43 as the steady-state supply voltage. Thus, the steady-state supply voltage Vcc0 is obtained from the flyback-derived supply voltage V1. Because the flyback-derived supply voltage V1 also functions as a supply voltage for other television receiver loads, the voltage V1 is not necessarily of the ideal magnitude to energize horizontal oscillator 43. Typically, the voltage V1 is slightly greater in magnitude than is desirable for use by horizontal oscillator 43. Resistor 62 is therefore provided to generate a voltage drop to establish the correct lower voltage Vcc0 at supply terminal 45.
During steady-state operation, the load current iL for horizontal oscillator 43 comprises the sum of the current i1 obtained from flyback supply terminal 49 and the charging current ic obtained from charging resistor 61, if the biasing currents to transistors 66 and 67 are neglected. Thus, even during steady-state operation, the charging current ic flows through resistor 61.
To keep power dissipation in charging resistor 61 to a relatively small amount especially during steady-state operation, the magnitude of the charging current ic is kept at a relatively small value, illustratively at 5% or less of the steady-state load current of horizontal oscillator 43 and 10 times less than the minimum load current needed to maintain horizontal oscillator 43 operating at start-up. By providing a transistor 66 interposed between capacitor 63 and oscillator supply terminal 45, the current required to flow through the resistance that is coupled between the DC input voltage Vin and oscillator 43 may be kept relatively small to reduce steady-state dissipation. Sufficient start-up load current to horizontal oscillator 43 is available, nonetheless, due to the charge buildup on capacitor 63 and the subsequent discharge of the capacitor.
The values of the upper threshold voltage level Va and of the capacitance of capacitor 63 may be selected such that for almost every deflection circuit operating condition encountered, sufficient time is available after capacitor 63 begins to be discharged by the load current drawn by horizontal oscillator 43 to enable the flyback-derived supply voltage V1 to subsequently take over energization of the oscillator before the capacitor has discharged to a voltage less than the minimum required to maintain operation of the oscillator.
Another feature of the invention is to arrange transistor switch 66, transistor 67 and capacitor 63 as a relaxation oscillator. By providing a relaxation oscillator arrangement, start-up of horizontal deflection circuit 80 is ensured for practically all operating conditions encountered by horizontal deflection circuit 80. For example, a situation may be encountered during start-up where the DC input voltage Vin is extremely low and the loading on flyback transformer 32 is extremely high. In such an operating situation, a much longer interval after the initiation of start-up may be required to build up the flyback-derived supply voltage V1 to a satisfactory level. If capacitor 63 discharges to a level below the minimum necessary to maintain horizontal oscillator 43 in operation before the voltage V1 builds up to a satisfactory level, start-up of deflection circuit 80 is defeated.
To prevent such a situation from occurring, the relaxation oscillator arrangement of start-up supply 90 establishes a lower threshold voltage level Vb when transistor switch 66 is conductive. Should capacitor 63 discharge to the lower threshold voltage level Vb, as illustrated by FIG. 2 by the dashed-line waveform of the voltage Vc after time t2, indicating a failure of the flyback-derived supply voltage V1 to build up to a satisfactory level, transistor 67 is biased off, thereby turning off transistor switch 66. The value of the lower threshold voltage level Vb may be selected as greater than the minimum voltage needed to maintain oscillator 43 functioning.
With transistor switch 66 cut off at time t3, a start-up charging cycle for capacitor 63 is reinitiated. As illustrated in FIG. 2 by the dashed-line waveform, capacitor 63 recharges from time t3 to time t4, at which time the upper threshold voltage level Va is again reached at terminal 73 to turn on transistor switch 66 at time t4. The voltage across capacitor 63 is again applied to horizontal oscillator 43 to recommence oscillator operation and to continue the buildup of flyback-derived supply voltage V1 so that by time t5 the supply voltage V1 has increased sufficiently to take over supplying current to horizontal oscillator 43. Shortly after time t5, the steady-state supply voltage Vcc0 at supply terminal 45 is established.
The relaxation oscillator arrangement of start-up supply 90 can provide as many charge/discharge cycles for capacitor 63 as may be required in order to build up the flyback-derived supply voltage V1 to the levels needed to maintain steady-state deflection circuit operation.
In a television receiver, the supply voltages to power various television receiver circuits such as the vertical deflection circuit and the audio and video circuits are derived from rectified and filtered flyback pulses developed by the horizontal deflection circuit. After the horizontal oscillator in the deflection circuit has commenced operation, the supply voltage for the oscillator is also derived from rectified and filtered flyback pulse voltages.
When the television receiver is turned on, the flyback pulse voltages are absent. A start-up supply for the horizontal oscillator is therefore required in order to energize the oscillator and develop the flyback-derived power supply voltages for the television receiver. A voltage that is available to power the oscillator during the start-up interval after the television receiver is turned on is the DC input voltage obtained by rectifying and filtering the AC mains supply voltage.
To eliminate power dissipation in the dropping resistor during steady-state operation, some start-up circuits include a transistor switch in series with the dropping resistor. When the steady-state flyback-derived supply voltage for the oscillator is developed, the switch becomes reverse biased, disconnecting the dropping resistor from the oscillator. A relatively expensive switch is required that is capable of withstanding the off-state voltage stress applied to it. This off-state voltage equals the difference between the DC input voltage and the oscillator supply voltage.
With such an arrangement, the charging current flowing to the capacitor may be selected to be of relatively low magnitude, much lower than even the minimum amount of load current required to energize the oscillator. Dissipation in the charging circuit is substantially reduced, even though the charging circuit may still be supplying current during steady-state operation after commencement of oscillator operation.
During the start-up interval, the oscillator draws more current from the capacitor than is being supplied by the charging circuit, resulting in the capacitor being discharged. Another feature of the invention is that should the capacitor discharge to a lower threshold level, indicating that the steady-state voltage supply is still unavailable for use, the switching means disconnects the capacitor from the oscillator, enabling the capacitor to recharge and reinitiate the start-up sequence.
FIG. 1 illustrates a horizontal deflection circuit with derived power supplies and with a start-up circuit for the deflection oscillator; and
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1.
In FIG. 1, a source 20 of AC mains supply voltage is coupled to input terminals 23 and 24 of a full-wave bridge rectifier 27. Source 20 is coupled to input terminal 23 through an on/off switch 21 and a current limiting resistor 22. A filter capacitor 28 is coupled across output terminal 25 of bridge rectifier 27 and the current return or ground terminal 26. A filtered but unregulated DC input voltage Vin is developed at terminal 25 and applied to a regulator 29. Regulator 29 may be a conventional switching regulator, such as described
in U.S. Pat. No. 4,147,964, D. W. Luz et al., entitled "COMPLEMENTARY LATCHING DISABLING CIRCUIT", using an SCR regulator switch operated at the horizontal deflection frequency of a television receiver to produce a regulated B+ voltage at a terminal 30. Feedback of the B+ voltage to the switching regulator is provided by a conductor line 74. A filter capacitor 31 is provided to filter out horizontal rate ripple voltage from terminal 30. The B+ voltage developed at terminal 30 is applied through the primary winding 32a of a flyback transformer 32 to the collector of a horizontal output transistor 35 in a horizontal deflection output stage 34 of a horizontal deflection circuit 80. Horizontal deflection circuit 80 includes a horizontal oscillator 43, energized by a supply voltage Vcc developed at a supply terminal 45 and drawing a load current iL therefrom, a horizontal driver transistor 44 and horizontal output stage 34. Horizontal output stage 34 comprises horizontal output transistor 35, a damper diode 36, a retrace capacitor 38 and the series arrangement of a horizontal deflection winding 39 and an S-shaping or trace capacitor 40.
Horizontal output transistor 35 is turned on early within the trace interval of each deflection cycle to conduct the horizontal scanning current after damper diode 36 is cut off and is turned off to initiate the horizontal retrace interval. During horizontal retrace, a retrace pulse voltage Vr is developed at the collector of horizontal output transistor 35 and applied to flyback transformer primary winding 32a to develop alternating polarity horizontal retrace pulse voltages across secondary windings 32b-32d.
The rectified and filtered voltage from flyback transformer winding 32d also supplies the collector voltage for horizontal driver transistor 44. The substantially DC voltage developed at the cathode of diode 51 at terminal 50 is applied through a resistor 57 and primary winding 42a of driver transformer 42 to the collector of driver transistor 44. A capacitor 56 provides horizontal rate filtering.
When the television receiver is turned on, after closure of on/off switch 21, the unregulated DC input voltage Vin is developed at terminal 25 and applied to switching regulator 29 to develop a voltage at B+ terminal 30. During the initial or start-up interval following closure of on/off switch 21, the flyback-derived supply voltages V1 and V2 are absent. To generate these voltages, switching action of horizontal output transistor 35 must be initiated by initiating or commencing the switching actions of horizontal oscillator 43 and driver transistor 44. Energization of these two elements, 43 and 44, must be obtained from voltage or energy sources that are available for use prior to commencement of operation of horizontal oscillator 43 and driver transistor 44.
The voltage used during start-up for providing collector supply voltage to driver transistor 44 is the voltage developed at B+ terminal 30 after closure of on/off switch 21. Terminal 30 is coupled to terminal 50 through a resistor 59 and a diode 60. Collector voltage for driver transistor 44 is obtained from B+ terminal 30 during start-up by way of resistor 59 and diode 60.
A start-up supply 90 is provided to initially develop supply voltage for horizontal oscillator 43 to energize the oscillator into commencing operation. Start-up supply 90 comprises a capacitor 63, a transistor switch 66 interposed between capacitor 63 and horizontal oscillator 43 at the supply terminal 45, a source of energy or voltage available prior to commencement of oscillator operation, namely the source of the DC input voltage Vin, and a charging resistor 61 that is used to charge capacitor 63 during the start-up interval from the DC input voltage terminal 25 by way of a resistor 62. Resistor 62 is a relatively low valued resistor used for a purpose hereinafter to be described.
Upon closure
of on/off switch 21 and the development of a DC voltage Vin at terminal 25, a charging current ic begins to flow through resistor 61 and resistor 62 to terminal 73, the junction of capacitor 63 and the emitter of controllable transistor switch 66. Capacitor 63 is initially uncharged and the voltage Vc at terminal 73 is zero, maintaining transistor switch 66 in the off-state immediately after closure of on/off switch 21. The base of transistor switch 66 is coupled to the collector of a transistor 67 through a resistor 72. A biasing network for transistors 66 and 67, comprising resistors 68-72, establishes at terminal 73 an upper threshold voltage level Va and a lower threshold voltage level Vb so as to enable transistors 66 and 67 to form with capacitor 63 a relaxation oscillator arrangement. When transistor 66 is cut off, resistor 70 is effectively in parallel with resistor 69, thereby establishing the upper threshold voltage level Va of FIG. 2; and when transistor 66 is in saturated conduction, resistor 70 is effectively in parallel with resistor 68, thereby establishing the lower threshold voltage level Vb.
As illustrated in FIG. 2 by the solid-line waveform of the voltage Vc, at a time t0, on/off switch 21 is closed and the charging current ic flowing from terminal 73 begins to charge capacitor 63. At time t1, capacitor 63 has charged to the upper threshold voltage level Va, turning on transistor 67 which turns on transistor switch 66 into saturated conduction. After transistor 66 becomes conductive, the voltage across capacitor 63 is applied to horizontal oscillator 43 at supply terminal 45 as a start-up supply voltage for the horizontal oscillator. Horizontal oscillator 43 commences operation and begins producing the horizontal rate switching signal 37 to initiate the switching action of horizontal driver transistor 44 and horizontal output transistor 35, thereby initiating the development of the horizontal retrace pulse voltage Vr and the horizontal retrace pulse voltages across flyback transformer secondary windings 32b-32d.
The load current iL being drawn by horizontal oscillator 43 durin
g the initial or start-up interval, after time t1 of FIG. 2, is of greater magnitude than the charging current ic flowing to terminal 73 from charging resistor 61. Thus, after time t1, horizontal oscillator 43 begins discharging capacitor 63 as illustrated in FIG. 2 by the decreasing voltage Vc after time t1. Even though the voltage Vc applied to horizontal oscillator 43 during the start-up interval after time t1 is decreasing, it is still sufficiently greater than the minimum voltage needed to maintain the oscillator operating. Thus, the horizontal rate switching signal is still being produced by horizontal oscillator 43 after time t1. By time t2 of FIG. 2, a sufficient period has elapsed so as to enable a substantial buildup of the flyback-derived supply voltage V1 at terminal 49. Supply voltage V1 is then applied to horizontal oscillator 43 by way of a diode 64 that has its cathode coupled to terminal 65, the junction of charging resistor 61 and resistor 62. Diode 64 blocks the flow of charging current to flyback supply terminal to prevent undue shunting of the current from oscillator 43 during start-up. Near time t2, the flyback-derived supply voltage V1 has increased sufficiently so as to be able to generate a current i1 flowing out of supply terminal 49 that is greater than the load current iL being drawn by horizontal oscillator 43. Thus, after time t2, capacitor 63 ceases discharging and becomes charged shortly thereafter to a relatively constant voltage level Vcc0, as illustrated by the solid-line waveform of FIG. 2 after time t2.
During steady-state operation, the load current iL for horizontal oscillator 43 comprises the sum of the current i1 obtained from flyback supply terminal 49 and the charging current ic obtained from charging resistor 61, if the biasing currents to transistors 66 and 67 are neglected. Thus, even during steady-state operation, the charging current ic flows through resistor 61.
The values of the upper threshold voltage level Va and of the capacitance of capacitor 63 may be selected such that for almost every deflection circuit operating condition encountered, sufficient time is available after capacitor 63 begins to be discharged by the load current drawn by horizontal oscillator 43 to enable the flyback-derived supply voltage V1 to subsequently take over energization of the oscillator before the capacitor has discharged to a voltage less than the minimum required to maintain operation of the oscillator.
To prevent such a situation from occurring, the relaxation oscillator arrangement of start-up supply 90 establishes a lower threshold voltage level Vb when transistor switch 66 is conductive. Should capacitor 63 discharge to the lower threshold voltage level Vb, as illustrated by FIG. 2 by the dashed-line waveform of the voltage Vc after time t2, indicating a failure of the flyback-derived supply voltage V1 to build up to a satisfactory level, transistor 67 is biased off, thereby turning off transistor switch 66. The value of the lower threshold voltage level Vb may be selected as greater than the minimum voltage needed to maintain oscillator 43 functioning.
The relaxation oscillator arrangement of start-up supply 90 can provide as many charge/discharge cycles for capacitor 63 as may be required in order to build up the flyback-derived supply voltage V1 to the levels needed to maintain steady-state deflection circuit operation.
BANG & OLUFSEN BEOVISION 7802 CHASSIS TYPE 7510 30AX CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
BANG & OLUFSEN BEOVISION 7802 CHASSIS TYPE 7510 30AX Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.
Description:
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
BANG & OLUFSEN BEOVISION 7802 CHASSIS TYPE 7510 30AX - VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)
TDA3300 3301 TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.
Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUITGENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
Description:
BACKGROUND OF THE INVENTION The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
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