MIVAR MOD: 16" 82 C4 CHASSIS TV2244 TV2247 TV2250
MIVAR 14C1V CHASSIS TV2697 + TV2633
CIRCUITS DESCRIPTIONS:
PAL decoder tda3560A
The TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
.SUPPLYVOLTAGE : 12V TYP .SUPPLYCURRENT : 50mATYP .I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP .VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP .I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP .A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
POWER SUPPLY COMBINED WITH BU208A TRANSISTOR HORIZONTAL DEFLECTION CIRCUIT, EXPLANATION AND CONCEPT VIEW.
NORDING MOD. 14 CHASSIS TYPE PORTABLE
A combination deflection circuit and switching mode power supply uses only a single switching element. Across certain diodes in this circuit is a stable voltage. A capacitor and a transformer p
rimary are series coupled to each other and together parallel coupled across at least one of the diodes. A rectifier is coupled to the transformer secondary to provide power to other portions of a television set.1. A line deflection circuit for generating from a direct voltage source a sawtooth current flowing through a deflection coil, said circuit comprising a parallel resonant circuit comprising said coil, a trace capacitor coupled to said coil, and a retrace capacitor coupled to said coil; a first diode coupled to said retrace capacitor, the deflection current flowing during a first part of the trace period through said first diode and during a second part of the trace period through a controllable switch, energy being applied from said direct voltage source during the trace period to a first winding arranged between said direct voltage source and the switch, and being applied through a second diode conducting during the retrace period from a second winding to the parallel resonant circuit which is connected to the switch through a third diode conducting during the second part of the trace period, at least one of the second and third diodes being shunted by the series arrangement of a capacitor and a primary winding of a current supply transformer, and means for rectifying coupled to said transformer for the direct current supply to other stages of the device. 2. A circuit as claimed in claim 1 wherein said switch comprises a transistor. 3. A circuit for generating from a direct voltage source a sawtooth current having trace and retrace periods through a deflection coil, said circuit comprising a trace capacitor, means for coupling said trace capacitor to said coil, a retrace capacitor coupled to said trace capacitor, diode coupled to said retrace capacitor, a first diode means coupled to said retrace capacitor for conveying said current during a first part of said trace period, a first winding having a first end means for coupling to said source and a second end, a controllable switch means coupled to said second end for conveying said current during a second part of said trace period, a second winding, a second diode means coupled between said first diode and said second winding for conducting during said retrace period, a third diode means coupled between said first diode and said switch for conducting during said second part of said trace period, and means for supplying direct current power comprising a transformer having primary and secondary windings, a capacitor series coupled to said primary, said primary and capacitor being parallel coupled to at least one of sai
Such a circuit arrangement is known from "IEEE Transaction on Broadcast and Television Receivers", August 1972, vol. BTR-18, No. 3, pages 177 to 182. The known circuit arrangement is the combination of a transistorized line deflection stage for a television receiver and a stabilised switch mode power supply, whereby one single switching element, the above mentioned transistor is both the switching transistor and the line deflection transistor.
An object of the invention was to further develop this circuit arrangement. It was found that an alternating voltage is present at the above mentioned second and third diode, which voltage is stabilized. The object according to the invention was to utilize this available and unilaterally stabilized rectangular voltage in a particularly advantageous manner.
This object is solved in that in a line deflection circuit of the kind described in the preamble the second and/or third diode is shunted by the series arrangement of a capacitor and a primary winding of a current supply transformer serving via rectifying for the direct current supply to other stages of the device.
An embodiment of the invention is shown in the drawings and will be further described hereinafter.
FIG. 1 shows the circuit improved according to this invention.
FIG. 2 shows different voltage variations as a function of time.
For the description of FIG. 1 th
e description of the Figures of the previously cited known circuit may be essentially used as a reference. A transformer is denoted by T1, a primary winding is L1; it is connected through a coupling capacitor CK to a secondary winding L2. A direct voltage source is UB. Furthermore a winding L3 is provided on the transformer secondary side which may serve for the high voltage generation UH through the diode Db.The switching transistor is TR; rectangular pulses with the line frequency and originating from a driver stage (not represented) are applied to this transistor. The entire circuit arrangement thus serves for generating a sawtooth current flowing through a deflection coil L. The deflection coil L is part of a parallel resonant circuit consisting of a retrace capacitor C2, the deflection coil L itself and a trace capacitor C3.
In the operative condition a first diode D2 which is parallel connected to the said resonant circuit conducts during a first part of the trace period and conveys the negative part of the deflection current I 2 during the period from t1 to t3 (compare FIG. 2d). During this period the switching transistor TR is separated from the deflection circuit consisting of D2, L, C2, C3 by a third diode Dd biassed in the blocking direction.
Meanwhile the zero crossing of the deflection current occurs at instant t3. D2 is blocked. Due to the polarity change of the current I L the third diode Dd becomes conducting and the deflection current may be taken over by the switching transistor TR. This current is superimposed uninterfered on the part of the collector current originating from the power supply function of TR.
It is often essential to provide further stages in the television display apparatus with a stabilized voltage. Conventionally such supply voltages are obtained by trace rectification on an auxiliary winding of the line transformer. In this circuit this simple possibility is not given due to the connection with the power supply function. As can be seen in FIG. 2a the secondary voltage US consists of a rectangular voltage on which the
flyback pulse of the deflection circuit is superimposed. When the trace part of US is rectified no stabilized direct voltage can be obtained due to the duty cycle variations caused by the control since the value of the voltage US between the instants t 2 and t 4 depends on that of the voltage UB.A flyback rectification is feasible in this case. However, due to the small conduction angle an inadmissibly high internal resistance of the obtained supply voltage is to be taken into account.
According to the invention a rectangular voltage present alternatively across the diodes D1 and D2, respectively is used. These voltages do not contain a flyback pulse FIG. 2c shows the voltage variation UN on the secondary side L5 of a transformer T2 introduced for potential separation. A primary winding L 4 thereof is arranged in series with a capacitor C 4 and this series arrangement shunts the diode D1. The capacitor C 4 prevents a dc short circuit of the diode D1 by the winding L 4 and has a capacitance which is large enough for preventing an influence upon the variation of UN. The voltage across the capacitor C 4 is thus equal to the dc-component of the voltage across the capacitor C 3 , which component is stabilised since the voltage UA is. The voltage across the winding L 4 is equal to the difference between that across the diode D1 and that across the capacitor C 4 , the first mentioned voltage being equal to U A -U S . The voltage UN across the winding LS, which winding has the indicated winding sense, has the variation shown in FIg. 2c and between the instants t o and t 2 it is equal to the stabilised dc-component of the voltage present across the capacitor C 3 . The voltage UN is rectified with the aid of a diode DN and smoothed with the aid of a capacitor CN. The rectified voltage UL is applied to the parts of the apparatus using a low voltage which in this case are represented by a load resistor RL.
DN must have such a polarity that it conveys current during the time t o -t 2 . Then the rectified voltage is stabilised to the same extent as the deflection voltage. The conduction angle is large so that the internal impedance of the voltage source is low. The primary side L4 of the transformer T2 is connected to D1 as is shown in FIG. 1. D1 and DN are then conducting simultaneously so that the internal resistance of UN is further reduced. In the same manner the series arrangement of L4 and C4 in parallel with Dd is alternatively possible.
The transformer T2 may be formed with a relatively small core due to the high operating frequency. On account of the switching properties (Dd and D1 alternately conducting) the rectangular voltage cannot become larger than the direct voltage on CK (corresponds to the voltage UB). Overvoltages as a result of for example picture tube flash-overs are thus prevented.
Circuit arrangement for generating a sawtooth deflection current through a line deflection coil:
1. Circuit arrangement for generating a sawtooth deflection current flowing through a line deflection coil in an image display apparatus, which circuit arrangement comprises a deflection network including trace and retrace capacitor means coupling to said coil, and a first diode coupled to said retrace capacitor through which the deflection current flows during part of the trace interval, means for conveying the deflection current during the remainder of the trace interval including a second diode and a controllable switch coupled to said diode, said switch and second diode together being coupled in parallel with the first diode, the circuit arrangement further comprising an inductive element coupled to the switch, a third diode coupled to the deflection network and to said inductive element, a transformer having a core of a magnetic material and a winding, and a capacitor coupled to said winding and to the deflection network, characterized in that the inductive element is coupled via the third diode to the series combination of the above-mentioned series capacitor and part of the transformer winding less than all of said winding.
2. Circuit arrangement as claimed in claim 1, in which the inductive element comprises a winding, characterized in that the winding of the inductive element is wound on the transformer core.
3. Circuit arrangement as claimed in claim 1, characterized in that a first capacitor is coupled in parallel with the said part of the transformer winding and a second capacitor is coupled in parallel with the remainder of the winding, the ratio between the reactances of the said capacitors being equal to the ratio between the number of turns of the said parts of the winding.
4. Circuit arrangement as claimed in claim 1 in which the inductive element has a primary winding and a secondary winding which are coupled with one another, characterized in that the ratio of the number of turns of the secondary winding to that of the primary winding is substantially equal to ##EQU19## where m is the ratio of the turns number of the part of the transformer winding between the connection to the third diode and the series capacitor to the turns number of the entire winding, α is the ratio of the amplitude of the retrace voltage to the trace voltage, and δmax is the value of that ratio of the conduction time of the switch to the line period which is associated with the maximum value of a voltage supply source which supplies energy to the circuit arrangement.
5. A circuit arrangement as claimed in claim 1 wherein said core has two limbs, a tapped transformer winding and at least one high-voltage winding wound on one limb, a primary winding and a secondary winding wound on the other limb, the ratio of the number of turns of the secondary winding to that of the primary winding being greater than the ratio of the number of turns of the part of the transformer winding between the tapping and an end adapted to be connected to a series capacitor to the number of turns of the entire winding and being less than 1.
The invention relates to a circuit arrangement for generating a sawtooth deflection current through a line deflection coil in an image display apparatus, which circuit arrangement comprises a deflection network including the deflection coil, a trace capacitor and a retrace capacitor and a first diode through which the deflection current flows during part of the trace interval whilst during the remainder of the trace interval this current flows through a second diode and a controllable switch, which switch and which second diode are connected in parallel with the first diode, the circuit arrangement further comprising an inductive element which is connected to the switch and is coupled to the deflection network via a third diode, and a transformer which has a core of a magnetic material and a winding of which is coupled, in series with a capacitor, to the deflection network.
Such a circuit arrangement is described in "IEEE Transactions on Broadcast and Television Receivers," August 1972, volume BTR-18, Nr. 3, pages 177 to 182, and is a combination of a line deflection circuit and a switched-mode supply voltage stabilizing circuit, the controllable switch being used to perform both the said functions. This known circuit arrangement has the advantage that it can be fed with an unstabilised supply voltage and is capable of supplying a satisfactorily stabilized deflection current, a stabilized high voltage and, if desired, auxiliary voltages, the stabilization being obtained by control of the conduction time of the swtich.
When such a circuit arrangement is to be designed, amongst other problems the three following ones arise. Firstly care must be taken to ensure that the maximum voltage set up across the switch (a transistor) during the retrace interval does not exceed the permissible limit value for this element. Secondly the variation of the conduction time of the transistor must be capable of accommodating the supply voltage variations to be expected. Thirdly the (stabilized) trace capacitor voltage applied to the deflection coil during the trace interval must be selectable at will, for with a given deflection coil this voltage determines the intensity of the deflection current produced.
The said problems are not independent of one another. If, for example, the trace voltage is low, the maximum collector voltage of the transistor also is low; it may be further reduced by making the conduction time of the transistor as short as possible. It will therefore be clear that several degrees of freedom are required. One degree of freedom is available to a certain extent, namely the transformation ratio between two windings of the inductive element, one winding being connected between a terminal of the supply voltage source and the junction point of the collector and the second diode, whilst the other winding, which is coupled to the first one, is connected to the third diode, for the choice of the said ratio enables a freer choice of the trace voltage. However, the two other problems, specifically that of maximum collector voltage, are not solved thereby.
It is an object of the present invention to provide a circuit arrangement having one more degree of freedom, permitting the maximum permissible collector voltage to be freely determined, and for this purpose the circuit arrangement according to the invention is characterized in that the inductive element is connected via the third diode to the series combination of the abovementioned series capacitor and part of the transformer winding.
The introduction of a new parameter not only enables the maximum collector voltage to be reduced without the trace voltage being affected but also proves to enable a larger range of supply voltage variations to be accommodated. Hence, the step according to the invention permits of designing a circuit arrangement in which conflicting requirements can simultaneously be satisfied.
In a possible embodiment in which the inductive element has a winding the circuit arrangement is characterized in that the winding of the inductive element is wound on the transformer core.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is a circuit diagram showing schematically the basic elements of an embodiment of the circuit arrangement according to the invention,
FIG. 2 shows waveforms of voltages produced in said embodiment,
FIGS. 3a and 3b show graphs which may be used in the selection of the parameters, and
FIG. 4 is a circuit diagram of a modified part of the circuit arrangement of FIG. 1.
The circuit arrangement shown in FIG. 1 includes a driver stage Dr to which signals from a line oscillator, not shown, are applied and which delivers switching pulses to the base of a switching transistor Tr. One end of a primary winding L 1 of a transformer T 1 is connected to the collector of the transistor Tr, which is of the n-p-n type, the other end of the winding L 1 being connected to the positive terminal of a direct-voltage source B to the negative terminal of which the emitter of the transistor Tr is connected. This negative terminal may be connected to the earth of the circuit arrangement.
A trace capacitor C t is connected in series with a line deflection coil L y of the image display apparatus, not shown further, of which the circuit arrangement of FIG. 1 forms part, the resulting series combination being shunted by a diode D 1 having the conductive direction shown and by a retrace capacitor C r . The capacitor C r may alternatively be connected in parallel with the coil L y . The said four elements represent the schematic circuit diagram including the basic elements of the deflection section only. This section may, for example, in known manner be provided with one or more transformers for mutual coupling of the elements, with devices for centering and linearity correction and the like.
A secondary winding L 2 of the transformer T 1 is connected to the anode of a diode D 3 , and the anode of a diode D 2 is connected to the junction point A of the elements D 1 , C r and L y . The cathode of the diode D 2 is connected to the collector of the transistor T r whilst the cathode of the diode D 3 is connected to a tapping Q on a winding L 3 of a transformer T 2 . One end of the winding L 3 is connected to the point A, the other end being connected to earth via a capacitor C 1 . The core of the transformer T 2 carries further windings across which voltages are produced which serve as supply voltages for other components of the image display apparatus. FIG. 1 shows one of said windings, the windings L 4 , which by means of a rectifier D 4 produces a positive direct voltage across a smoothing capacitance C 2 . One of said windings, for example the winding L 4 , is the high voltage winding, so that the voltage set up across the capacitor C 2 is the high voltage for the final accelerating anode of the display tube (not shown). The free ends of the windings L 2 and L 4 are connected to earth, and the winding senses of the windings shown are indicated in the Figure by polarity dots.
The operation of the circuit arrangement is similar to that described in the abovementioned paper and may be summarized as follows. During a first part of the line trace interval the diode D 1 is conducting. The voltage across the capacitor C t is applied to the deflection coil L y through which a sawtooth deflection current i y flows. At a given instant the transistor TR becomes conducting. When in about the middle of the trace interval the current i y reverses direction the diode D 1 is cut off, so that the current i y then flows through the diode D 2 and the transistor Tr. At the end of the trace interval the transistor Tr is cut off. As a result an oscillation, the retrace pulse, is produced across the capacitor C r whilst the energy derived from the source B and stored in the winding L 1 causes a current to flow through the diode D 3 . When the voltage across the capacitor C r has become zero again, the diode D 1 becomes conducting: this is the beginning of a new trace interval. The diode D 3 remains conducting until the transistor Tr is rendered conducting, the energy stored in the winding L 2 being transferred to the winding L 1 . Stabilisation is provided, for example, by feeding back the voltage across the capacitor C t to the driver circuit Dr, in which a comparison stage and a modulator ensure that the conduction time of the transistor Tr is varied so that the said voltage and hence the amplitude of the deflection current remain constant. Compared with the known case in which the cathode of the diode D 3 is connected to the point A instead of to the tapping Q operation is different, the difference being as follows. In the known case the current passed by the diode D 3 flows to earth via the diode D 1 during the first part of the trace interval. In the arrangement shown in FIG. 1, during this same part energy is stored in the series combination L 3 , C 1 . The voltage v A across the capacitor C r , the voltage v c at the collector of the transistor T r and the voltage v 1 across the winding L 1 are plotted against time in FIGS. 2 a, 2b and 2c respectively. The symbol T indicates the line period, τ 1 indicates the retrace interval, τ 2 that part of the period T in which the transistor Tr is non-conducting, and τ 3 = δ T indicates the part of the period T in which this transistor is conducting. The number δ is the ratio between the time τ 3 and the period T.
The voltage v A consists of the retrace pulse of amplitude V during the time τ 1 and is zero during the time τ 2 . At the instant at which the transistor Tr is rendered conducting, i.e. the instant of transition t 1 between τ 2 and τ 3 , the voltage v C becomes substantially zero. Thus the volage V B of the source B is set up across the winding L 1 .
In the circuit arrangement of FIG. 1 two ratios are significant, namely the transformation ratio between the windings L 1 and L 2 , i.e. the ratio between the number of turns of the winding L 1 and that of the winding L 2 , which is equal to 1 : p, and the ratio of the turns number of the entire winding L 3 and that of the part of this winding between the tapping Q and the end connected to the capacitor C 1 , which ratio is 1 : m. First it will be assumed that the points Q and A coincide (m = 1).
During the time τ 3 the voltage cross the winding L 2 is equal to -pV B . During the time τ 1 the voltage v c is equal to V/p + V B . Let V o be the direct voltage across the capacitor C t , if the capacitance of this capacitor is large enough, or the direct voltage component of the voltage across this capacitor, if it has a comparatively small capacitance for the purpose of the S correction; in either case it is equal to the mean value of the voltage v A , for no direct-voltage component can be set up across the coil L y . The capacitor C 1 has a large capacitance, so that a direct voltage equal to V o is set up across it. The following equation applies: ##EQU1##
The mean value of the voltage across the winding L 3 also is zero, so that the equation applies: ##EQU2## In this formula the integral can be substituted, Yielding V o T = pV B . τ 3 , that is; V o = pδ. V B (1)
At given values of the ratios δ and p the diode D 2 will conduct during the time τ 1 . Because during this time the diode D 3 is conducting, the windings L 1 and L 2 will be short-circuited by the diodes D 2 and D 3 , causing the retrace pulse across the capacitor C r to be clipped and the deflection current to be distorted. U.S. Pat. Application No. 443,863 filed Feb. 19, 1974 describes steps for avoiding such an effect, for example by including in series with the diode D 2 a transistor which is cut off during the time τ 1 . A capacitor C 3 is connected between the ends of the windings L 1 and L 2 or between tappings thereon for the purpose of preventing the occurrence of parasitic oscillations which may be produced by the leakage inductance between the said windings in a manner such that no line-frequency voltage is set up across the capacitor C 3 . FIG. 1 shows the case where p <1.
The maximum value of the collector voltage v c of the transistor is equal to ##EQU3## where α is the ratio V/V o which depends upon the retrace ratio Z = τ1/T. The maximum value of V c is obtained when V B has its maximum value V B max, for which δ has the value δ min , for from the relationship (1) it follows that δ and V B are inversely proportional to one another because the voltage V o is maintained constant.
The voltage V o can be chosen by choosing the ratio p, so that the deflection current y is determined for a given deflection coil L y . However, from the above it follows that the maximum value of the voltage V c , which is highly critical for the transistor, is not controllable. Moreover, the relationship (1) can be written:
V o = p δ min . V B max = p δ max . V B min, where V B min is the minimum value of V B for which δ = δ max , and from which follows: ##EQU4## The ratio δ min has its minimum value δ 1 if the instant t 1 coincides with the middle of the trace interval, and δ max has its maximum value δ 2 if the instant t 1 coincides with the beginning t o of the trace interval. Hence the above ratio cannot exceed 2, so that the arrangement cannot accommodate larger variations of the voltage V B .
According to the invention the points A and Q do not coincide. The voltage across the winding L 3 is equal to v A - V o so that the voltage v Q in the point Q is equal to v Q = V o + m(v A - V o ) = mv A + (1 - m) V o . With the aid of the waveform of the voltage v A of FIG. 2a the waveform of the voltage v 1 across the winding L 1 between the positive terminal of the source B and the collector of the transistor Tr can be plotted (FIG. 2c), allowing for the fact that the diode D 3 is conducting during the times τ 1 and τ 2 .
Thus we have: ##EQU5## during time τ 3 : v 1 = - V B . Writing the condition for the mean value of the voltage v 1 being zero after some calculations yields. ##EQU6## The maximum value of the collector voltage v c is ##EQU7## from which follows: ##EQU8## after substitution of the formula (2). It can be shown that this function steadily decreases with decrease of the ratio m. It is plotted in FIG. 3a for z = 0.2, from which follows α ≉ π/2z ≉ 7,8, and with δ min = δ 1 = 1/2 (1 - z) = 0.4. The Figure shows that by making m less than 1 a reduction of the maximum collector voltage is obtained and that this result is independent of the ratio p.
From the formula (2) the following relationship can be derived: ##EQU9## ##EQU10## This function also is independent of the ratio p and it increases as m decreases. It is plotted in FIG. 3b for δ min = δ 1 = 0.4 and δ max = δ 2 = 0.8 (Z = 0.2), so that the entire δ range is used, whilst the Figure shows that a larger range of supply voltage variations can be accommodated, for when m is less than 1 the ratio V B max /V B min exceeds 2.
Similarly to the preceding case, the voltage V o can be determined by the choice of the ratio p. If the means described in the abovementioned U.S. Pat. Application No. 443,863 are to be dispensed with, it is found that an upper limit can be set to p. The diode D 2 will just be conducting during the time δ 1 if the lowest value of the voltage V c which is found in practice, that is ##EQU11## is equal to the voltage V. In the above expression, according to the formula (2), ##EQU12## from which we can derive: ##EQU13##
The above will be explained by means of two numerical examples. If the voltage V B can vary between 230 volts and 345 volts (with a mains voltage of 220 volts) V B max /V B min is less than 2, so this does not provide difficulty. If the transistor Tr is not capable of withstanding a voltage exceeding 1200 volts, it will be seen from FIG. 3a that m = 0.64. From the formula (2) it follows that ##EQU14## with δ min = δ 1 and ##EQU15## so that δ max = 0.56 < δ 2 . The formula (5) yields: ##EQU16## so that V o = 0.87 times 161 = 140 volts.
If now the voltage V B can vary between 115 volts and 345 volts (the mains voltage is 110 volts or 220 volts), then V B max /V B min = 3. FIG. 3b shows that m = 0.38, for which FIG. 3a yields V c max = 2.9 times 345 = 1000 volts. Formula (2) yields: ##EQU17## whilst ##EQU18## so that V o = 0.54 times 183 volts = 99 volts. Because m cannot be increased, a higher V o if desired requires p to exceed 0.54, and hence the step according to the abovementiond Patent Application must be used.
Similarly to what is the case in U.S. Pat. Application No. 473,771, filed June 1, 1973, the cores of the transformers T 1 and T 2 of FIG. 1 may be one and the same core, that is to say the windings L 1 , L 2 and the winding L 3 may be coupled to one another in spite of the fact that voltages of different waveforms are set up across the said windings. This is possible because the said voltage waveforms are not affected by the coupling, since the voltages V o and V B are "hard," that is to say they are externally impressed, and hence are not affected by the coupling. The currents flowing through the windings, however, are affected. In the lastmentioned Patent Application it is shown that the operation of the circuit arrangement is not adversely affected thereby, but on the contrary important advantages are obtained. It should be mentioned that instead of the tapping Q an additional winding may be wound on the same core as the winding L 3 , which additional winding has a smaller number of turns than the winding L 3 and is included between the cathode of the diode D 3 and the junction point of L 3 and the capacitor C 1 .
Formula (5) shows that the ratio m should not be excessively small, because in this case the ratio p also is small, with the result that large currents flow on the secondary side of the transformer T 1 . In addition, large currents then will flow through the leakage inductance of the said transformer, which gives rise to ringing at the instant t 1 . Furthermore difficulties will arise in designing the abovementioned embodiment using a single transformer. If for these reasons the formula (5) is not complied with, that is to say if p is made greater than the preferred value p max , the steps according to the abovementioned U.S. Pat. Application No. 443,863 have to be employed. This requires an additional transistor, which is expensive, or an additional diode, which does not prevent the production of a high V c max, whilst it was the very purpose of using a low m to obtain a low V c max.
In practice there is a leakage inductance between the two parts of the winding L 3 . In FIG. 4, which shows only part of the circuit arrangement, this leakage inductance is shown as an inductance L 5 between the point Q and an imaginary tapping Q' on the winding L 3 . The inductance L 5 prevents abrupt current transistions which in conjunction with the stray capacitances may give rise to ringing. This can be avoided by connecting a capacitor C 4 between points A and Q and a capacitor C 5 between the point Q and the junction point of the winding L 3 and the capacitor C 1 . If the ratio between the reactances of C 4 and C 5 is equal to that between the numbers of turns of the upper and lower parts of the winding L 3 , no alternating voltage is set up across the inductance L 5 so that no ringing can occur. The parallel connection of the capacitor C r and of the network C 4 , C 5 together with the inductive components of the circuit arrangement results in a resonant frequency the period of which is about equal to twice the time τ 1 .
Hereinbefore it has been assumed that the capacitance of the capacitor C 1 is sufficiently large to enable the voltage across it to be regarded as constant (= V o ). It should be mentioned that this is necessary only if one or more of the auxiliary voltages produced by means of windings of the transformer T 2 are obtained by means of trace rectification.
NORDING MOD. 14 CHASSIS TYPE PORTABLE Self-regulating deflection circuit with resistive diode biasing:
"A New Horizontal Output Deflection Circuit" by Peter L. Wessel,
A self-regulating deflection circuit includes a first inductor and switching transistor coupled across the unregulated voltage supply. A damper diode, retrace capacitor and second inductor are coupled in parallel, and the parallel combination is coupled across the transistor by a first rectifier poled to prevent current from flowing from the first inductor to the second inductor. A second rectifier is coupled between the first and second inductors for transferring energy from the first inductor to the second during the retrace interval. A control circuit coupled to the second inductor and to the base of the switching transistor controls the time during the first half of the trace interval during which the transistor conducts to allow energy to be stored in the first inductor. A storage capacitor is coupled in series with the second rectifier. Charge accumulation on the storage capacitor and resultant blocking of the second rectifier is prevented by a resistor coupled across the storage capacitor.
1. A self-regulating deflection circuit adapted to be energized from a source of unregulated direct voltage, said deflection circuit including
first inductance means;
controllable switch means including a unidirectional main current conducting path and a control electrode, said main current controlling path being serially coupled with said first inductance means across the source of unregulated direct voltage thereby forming a first series path for storing energy in said first inductance means during those intervals in which said main current conducting path is conductive;
first rectifier means;
a parallel combination of elements coupled by said first rectifier means across said main current conducting path, said parallel combination including second inductance means, damper diode means and retrace capacitance means, said first rectifier means being poled for current conduction in the same direction as said main current conducting path;
control means coupled with said second inductance means and with said control electrode for recurrently switching said main current conducting path for promoting current flow in said second inductance means during recurrent trace and retrace intervals and for maintaining the peak value of said current flow at a constant level;
second capacitance means;
second rectifier means coupled by said capacitance means with said parallel combination of elements and to a point on said first series path for transferring energy from said first inductance means to said parallel combination of elements during said retrace intervals;
wherein the improvement comprises
resistance means coupled with said second capacitance means for equalizing charge on said second capacitance means during said trace interval.
2. A circuit according to claim 1 wherein said resistance means is coupled in parallel with said second capacitance means. 3. A circuit according to claims 1 or 2 wherein said capacitance means is serially coupled with said second rectifier means. 4. A circuit according to claim 3 wherein said point on said first series path is a point along said first inductance means. 5. A circuit according to claim 4 wherein said point along said first inductance means is an end of said first inductance means. 6. A circuit according to claims 1 or 2 wherein said second rectifier means is coupled by said capacitance means with said second inductance means in said parallel combination of elements. 7. A circuit according to claims 1 or 2 wherein said second inductance means is a winding of a transformer and said second inductance means is paralleled by a deflection winding. BACKGROUND OF THE INVENTION
This invention relates to self-regulating horizontal deflection circuits with diode steering in which one of the diodes is biased.
Horizontal deflection circuits are used in conjunction with television picture tubes in television display devices. Typically, the horizontal deflection circuit includes a magnetic winding associated with the picture tube and a switching circuit by which energy from a dc voltage source is coupled to the winding and its associated reactances. The switching circuit is synchronized with synchronizing signals associated with the information content of the video to be displayed on the picture tube. In order to avoid distorted images on the displayed raster, the size of the horizontal scanning line and the peak deflection or scanning current must be maintained constant over substantial periods of time.
Many conditions can cause the size of the horizontal scanning line to vary. If the direct energizing voltage for the horizontal deflection circuit varies, the scanning energy and hence the width of the horizontal scanning line may vary. It has in the past been customary to regulate the direct voltage applied to the horizontal deflection circuit by the use of a dissipative regulator. Requirements for low power consumption in television receivers is reducing the use of such dissipative regulators in favor of nondissipative types.
Another approach to regulating the scan width involves the use of a self-regulating deflection circuit, such as is described in the article "A New Horizontal Output Deflection Circuit" by Peter L. Wessel, which appeared in the IEEE Transactions on Broadcast and Television Receivers, August, 1972, Vol. BTR-18, No. 3, pages 117-182. The Wessel deflection circuit may be energized from an unregulated direct voltage, and uses a single switching transistor to perform the switching function for the horizontal deflection and for nondissipative switching regulation. In the Wessel circuit, the unregulated direct voltage is applied across the primary winding of a transformer by the switching transistor. The deflection winding, retrace capacitor and damper diode associated with the horizontal deflection are coupled across the collector-emitter path of the switching transistor by a first diode poled for conduction in the same direction as the collector-emitter path. A secondary winding of the transformer is coupled across the deflection winding by a second diode poled to conduct and transfer energy from the primary to the deflection winding during the retrace interval. It is desirable to eliminate the secondary winding, and thereby reduce the total number of windings.
A horizontal deflection circuit in which the secondary winding is eliminated is described in U.S. Pat. No. 3,906,307 issued Sept. 16, 1975 in the name of J. Van Hattum. However, in the Van Hattum arrangement, an additional inductor and capacitor are used. The necessity for the additional inductor negates the advantage of elimination of the secondary winding.
SUMMARY OF THE INVENTION
A self-regulating deflection circuit includes a first inductor and controllable switch serially coupled across a source of unregulated direct voltage to form a first series path for storing energy in the first inductance during the intervals in which the switch is conductive. A first rectifier couples a parallel combination of elements across the switch, the parallel combination including a second inductance, a damper diode and retrace capacitor. The first rectifier is poled for current conduction in the same direction as the switch. A control circuit coupled to the second inductance and with the switch recurrently operates the switch for promoting current flow in the second inductance during recurrent trace and retrace intervals, and maintains the peak value of the current flow at a constant level. A second rectifier is coupled by a second capacitance with the parallel combination of elements and to a point on the first series path for transferring energy from the first inductance to the parallel combination of elements during the retrace intervals. A resistance is coupled to the second capacitance for equalizing charge on the second capacitance during the trace interval.
DESCRIPTION OF THE DRAWING
FIG. 1 illustrates partially in block and partially in schematic form a portion of the deflection circuit of a television display device embodying the invention; and
FIG. 2 illustrates voltage-and current-time waveforms occurring in the arrangement of FIG. 1 during operation.
DESCRIPTION OF THE INVENTION
In FIG. 1, a power supply designated generally as 10 includes a rectifier represented by a diode 16 and a filter capacitor 18 coupled to terminals 12 and 14 adapted to be coupled to the alternating-current power mains. Unregulated direct voltage appearing across capacitor 18 energizes a horizontal deflection circuit designated generally as 20.
Deflection generator 20 includes an inductor 22 connected at one end to capacitor 18 and at the other end to the collector of an NPN switching transistor 24, the emitter of which is connected to ground. The cathode of a diode 26 is connected to the collector of transistor 24, and its anode is connected to the cathode of a damper diode 32, the anode of which is connected to ground. A retrace capacitor 28 is coupled in parallel with diode 32. A deflection winding 34 is serially coupled with an S-shaping capacitor 36, and the serial combination is coupled in parallel with capacitor 28. A primary winding 38a of a transformer 38 is coupled at a terminal 37 with the anode of diode 26. The other end of primary winding 38a is connected at a terminal 39 with one end of a storage capacitor 40, the other end of which is grounded. A high-voltage secondary winding 38b of transformer 38 has one end grounded and the other end connected to an ultor rectifier represented as a diode 44 for producing high voltage for application to the ultor of a kinescope, not shown. Another secondary winding 38c of transformer 38 has a grounded center-tap and the ends connected to rectifier diodes 46 and 48 for producing operating voltages for the low-voltage portions, not shown, of the television device.
A dc blocking capacitor 52 is serially connected with a diode 50, and the serial combination is coupled between the collector of transistor 24 and a point on winding 38a. The cathode of diode 50 is connected to winding 38a, and the anode is coupled to the collector of transistor 24. A resistor 54 has one end connected to capacitor 52 at a circuit point 56, and the other end is coupled to the end of capacitor 52 remote from point 56 so as to form a parallel connection.
A synchronized pulse-width modulator illustrated as a block 60 is coupled to capacitor 40 for sampling the voltage appearing thereacross. Modulator 60 receives horizontal synchronizing pulses illustrated as 64 at an input terminal A. Modulator 60 produces pulses in known manner, the time duration or width of which are controlled in response to the voltage across capacitor 40, and the pulses are applied by way of a conductor B to a driver circuit illustrated as a block 66. Driver 66 replicates or, if desired, shapes the pulses in a known manner and applies them to the base of switching transistor 24 to control its collector-emitter conduction in a switching manner.
The waveforms of FIG. 2 in the intervals T0-T5, T5-T10 and T10-T15 exemplify operation for low, correct, and excessive deflection energy, respectively. The interval T4-T10 is representative and will be used to describe details of the circuit operation.
In operation during the last half of the horizontal scanning or trace intervals preceding time T5, the collector-emitter path of transistor 24 is conductive, and current is increasing in inductor 22 as illustrated by waveform I22 of FIG. 2f in the interval following time T4. The current in inductor 22 flows through the collector-emitter path of transistor 24. During this same interval immediately following the time T4, which is the time of the center of the horizontal trace interval, current is flowing in deflection winding 34 as illustrated by waveform I34 of FIG. 2d, and is increasing under the impetus of the voltage on capacitor 36. The current in winding 34 flows through diode 26 and adds to the collector-emitter current flowing in transistor 24, as illustrated by waveform I24 of FIG. 2h. A current flows through winding 38a under the impetus of the voltage on capacitor 40, which current adds to the deflection current flowing through diode 26 and transistor 24. Winding 38a is in parallel with winding 34 and they may be viewed as being a single inductor through which a single current proportional to the deflection current flows. In the interval between times T4 and T5, diode 50 is reversed-biased by a voltage, poled as shown, on capacitor 52.
The deflection current and the current in inductor 22 continues to increase until a time such as T5 at which a horizontal synchronizing pulse 64 as illustrated in FIG. 2a is applied to modulator 60. Modulator 60 responds by producing a transition of voltage V60 on conductor B as illustrated in FIG. 2b. Voltage V60 causes driver 66 to render the collector-emitter path of transistor 24 nonconductive. This initiates the retrace interval, which extends from time T5 to T7. During the first portion T5-T6 of the retrace interval, winding 34 (together with winding 38a) transfers the energy stored in its magnetic field to capacitor 28 in a resonant manner, causing the voltage at circuit point 37 to rise as illustrated by V37 of FIG. 2c.
The voltage at terminal point 39 remains substantially unchanged during the retrace interval because of the filtering effect of capacitor 40. Consequently, the voltage at a point along winding 38a will rise during the retrace interval in an amount depending upon how remote the point is from circuit point 39. Thus, the voltage at the cathode of diode 50 will depend upon the exact point on winding 38a at which the cathode is connected.
When transistor 24 is rendered nonconductive at time T5, the voltage across inductor 22 rises so as to maintain the current of transistor 24 therefore rises and forces the current through capacitor 52 and forward-biased diode 50 to winding 38a and capacitor 40, resulting in an energy transfer thereto. The voltage across inductor 22 during the retrace interval determines the rate at which energy is transferred during this interval from winding 22 to winding 38a and the remainder of the deflection circuit. The voltage across winding 22 during this interval is the algebraic sum of the voltage which is then on capacitors 18, 40 and 52, the voltage produced by the inductance of winding 38a, and the forward voltage drop of diode 50. During this retrace interval, voltage is coupled from winding 38a to windings 38b and 38c for rectification and energization of the remainder of the television device.
The first half of the retrace interval ends at a time T6 as the current in windings 34 and 38a is reduced to zero and the voltage on retrace capacitor 28 peaks. Voltage V37 represents the voltage across the retrace capacitor. During the second half of the retrace interval, diode 50 continues to conduct a decreasing current as illustrated by I50 of FIG. 2i as energy is transferred to winding 38a and capacitor 40 from winding 22. Also during the second half of the retrace interval, the current in windings 34 and 38a reverses and increases to a peak at a time 27 as illustrated by I34. As the current in winding 34 increases to a peak in the negative direction, the voltage at circuit point 37 decreases towards zero as illustrated by V37 of FIG. 2c. The retrace interval ends at a time T7 as V37 reaches zero and damper diode 32 conducts.
During the first half T7-T9 of the following trace interval, the current in winding 34 decreases as its energy is transferred to capacitor 36. During a first portion T7-T8 of the trace interval, transistor 24 is maintained nonconductive. The remaining energy in winding 22 continues to cause current to flow through capacitor 52 and diode 50. The collector voltage VC24 of transistor 24 during this interval is maintained at a voltage equal to the algebraic sum of the voltage on capacitors 40 and 52, the voltage caused by winding 38a, and the forward junction potential of diode 50, as illustrated in FIG. 2e.
At a time T8, modulator 60 produces a gating pulse V60 which is coupled to transistor 24 to render it conductive. When transistor 24 becomes conductive, its collector goes to ground potential, coupling winding 22 across capacitor 18 to commence the energy storage portion of the deflection cycle. At the same time, the positive end of capacitor 52 is coupled to ground, placing a negative potential as illustrated by V56 of FIG. 2g on the anode of diode 50, which cuts it off. During the remainder of the trace interval, the increasing current in winding 22 flows through the collector-emitter path of transistor 24.
At a time T9, the deflection current in winding 34 reaches zero, and capacitor 36 has reached its maximum potential. Diode 32 becomes nonconductive. The voltage at junction point 37 rises until diode 26 becomes conductive, and current begins to flow through deflection winding 34 under the impetus of the voltage on capacitor 36. This current flows through diode 26 and the collector-emitter path of transistor 24, as illustrated by I24. The currents in windings 22 and 34 continue to increase until the end T10 of the deflection interval, at which time transistor 24 is rendered nonconductive to create a retrace voltage pulse at circuit point 37 and cause energy transfer from winding 22 to winding 38a.
In the interval between times T5 and T10, modulator 60 produces a gating pulse V60 rendering transistor 24 conductive at times during the first half of trace interval. During the interval T5-T8 in which transistor 24 is nonconductive, current in inductor 22 decreases and energy is transferred therefrom into winding 38a and capacitor 40. In the interval T8-T10 in which transistor 24 is conductive, current increases in winding 22 as it stores energy derived from the unregulated direct voltage. Time T8 is selected as that time which results in the peak value of current I22 being equal from one horizontal cycle to the net so as to maintain substantially the same transfer of energy from winding 22 to the deflection components in order to compensate for the losses during the deflection cycle. These losses include dissipative losses and energy transferred to the kinescope ultor.
In the event that the losses during successive deflection cycles exceed the energy transferred from inductor 22, less energy than desired will circulate through deflection system during each cycle, resulting in reduced raster width. The voltage across capacitor 40 will decrease as a result of this decreased energy and modulator 60 will produce a gating waveform V60 at a time T3 occurring earlier during the deflection cycle than corresponding time T8. This reduces the time T0-T3 in which current I22 decreases, and increases the interval T3-T5 in which voltage is applied to inductor 22 in a polarity to increase the current. Consequently, at a time T5 at the end of the deflection interval, the energy stored in the magnetic field of inductor 22, as measured by current I22, will exceed that at time T0. This results in an increased energy transfer which restores the circulating energy and the voltage across capacitor 40.
Similarly, when the loads on winding 38a decrease and the circulating energy increases, the voltage on capacitor 40 will increase, and modulator 60 will gate transistor 24 into conduction at a time T13 which is later relative to the deflection cycle than time T8. This allows a greater time T10-T13 in which current I22 can decrease and reduces the time T13-T15 in which the current can increase, thereby resulting in reduced current in inductor 22 at the end of the deflection cycle and reduced energy available for transfer to the deflection components, thereby restoring the voltage across capacitor 40 and maintaining the raster width. Time T13 at which transistor 24 is rendered conductive cannot be selected later than time T14 of the center of scan, because of the resulting raster distortion.
The point on winding 38a at which the cathode of diode 50 is connected may be selected at the end of winding 38a corresponding to circuit point 39. Substantial regulation results at all points along winding 38a to which the cathode of diode 50 may be connected. However, some changes in the waveforms occur. Current I222 of FIG. 2f represents the current in winding 22 when the cathode of diode 50 is coupled to circuit point 37, and current I250 of FIG. 2i represents the corresponding current in diode 50.
In the absence of resistor 54, the unidirectional current flow through capacitor 52 and diode 50 will tend to raise the voltage across capacitor 52 to a very high value in the polarity shown. If charge is allowed to accumulate on capacitor 52 in this manner, the voltage across capacitor will soon equal the maximum voltage which can occur at the collector of transistor 24, and diode 50 will cease to conduct during the retrace intervals, no energy will be transferred to the deflection components to compensate for the losses during the deflection cycle, and the circuit will cease to operate.
Resistor 54 is provided as a path for preventing accumulation of excess charge across capacitor 52. As the voltage across capacitor 52 increases, the rate at which charge is drained away through resistor 54 also increases. The end of resistor 52 remote from circuit point 56 can be coupled to any point of reference potential, such as B+ or ground, in order to achieve the desired discharge of capacitor 52. Reduced power dissipation results from coupling resistor 54 in parallel with capacitor 52, as illustrated in FIG. 1. With this arrangement, circuit point 56 takes on a negative potential during those portions of the horizontal scanning interval in which transistor 24 is conductive as illustrated by V56.
Other embodiments of the invention will be apparent to those skilled in the art. In particular, the positions of serially coupled diode 50 and capacitor 52 may be interchanged. Impedance-matching considerations may require either the collector of transistor 24 or the serial combination of diode 50 and capacitor 52 to be coupled to a tap on winding 22.
WITH 1 ANALOG CONTROL:
16-STATION MEMORY - 7-SEGMENT LED
DISPLAY .VOLTAGESYNTHESIZER : 13 BITS .4-BAND PRESET CAPABILITY .NON-VOLATILEMEMORY : 304 BITS
- 16 WORDS OF 19 BITS FORTUNING VOLTAGE
(13 bits) - BAND (2 bits) - FINE DETUNING
(4 bits)
- 104 MODIFY CYCLES PER WORD
- MIN 10 YEARS DATA RETENTION .PCM REMOTE CONTROL RECEIVER : DECODES
SIGNAL TRANSMITTED BY M708 .VOLUME D/A : 6-BIT RESOLUTION / 8kHz .MEMORY SKIP FUNCTION .AUTOMATIC SEARCH WITH DIGITAL AFT
CONTROL .FINE DETUNING D/A ACTING ON AFT DISCRIMINATOR
(16 steps) WITH SEPARATE
STORAGE FOR EACH MEMORY POSITION.
ALTERNATIVELYIT CAN BE USED TO CONTROL
BRIGHTNESS OR COLOUR SATURATION
.MANUAL SEARCH WITH DIGITAL AFT CONTROL
.MANUAL SEARCHWITH LINEAR AFT .SWEEP SEARCH DISPLAY OUTPUT .SUPPLYVOLTAGES : VDD = + 5V,
VPP = + 25V FOR THE MEMORY .CLOCK OSCILLATOR: 445 TO 510kHz .INTEGRATED DIGITAL POWER ON RESET
(no external initialization circuitry required)
DESCRIPTION(All timings at fclock = 500kHz)
PIN 1 : VSS
The substrateof the IC isconnectedto thispin. This
is the reference pin for all parameters of the IC.
PIN 2 : MEMORY SUPPLYVOLTAGE
A supply voltage of 25 ± 1 V has to be applied to
this pin during the modify and read cycles.
MODIFY CYCLE
A modify cycle consists of three steps :
1. All ”1”s arewritten in thebits of the selected word.
2. All bits of the selected word are erased (all ”0”s)
3. The new content is written.
Thus a constant aging of all the bits of the word is
obtained.
During both write and erase cycles the memory
status is checked continuously ; therefore after
each writeor erase pulsea read operationis carried
out. The write or the erase operations are stopped
as soon as the result of the read operation is valid.
WRITE CYCLE. The peak of the current flowing
through pin 2 during a write operation is shown in
fig. 1, while fig. 2 shows the envelope of the same
current.
The typical write time is 3-4 ms for the first cycles
and increases to about 30 ms after 1000 cycles.
PIN 3 : MEMORY TIMING OUTPUT
This output gives the timing for the pulses to be
applied at Pin 2 during the modify and read cycles.
The output consists of an open drain transistor.
PIN 4 : FINE TUNING D/A (see Figure 5)
A D/A converter with 16-step resolution and a frequency
of 15kHz can be used to generatea voltage
which, if fed to a varicap diode in parallel to the AFC
discriminator, will detune the receiver by a small Df
while maintainingthe action of the Digital AFT. This
output can be used in conjunction with both Linear
and Digital AFT modes of operations.
The Fine tuning function operates as follows :
- At the start of any automatic or manual search,
the output is set at the mid range.
- When the search has been completed it is possible
to operate on FT ± commands.
The store command memorizes this information
together with the 13 tuning voltage bits and 2
information bits.
- Modification time of FT D/A is of 1 step every
200ms if issued locally or every 2 received signals
from Remote control transmitter.
PIN 5 : TUNING D/A (see Figure 6)
A 213 = 8192 step pulse modulated signal for the
tuning voltage is available on this pin.
Pulse modulation is implemented by combination
of a rate multiplier and pulse width principle.
With a tuning voltage increasing from zero, the
number of pulses increases continuously up to
28 = 256 ; starting from this point the number of
pulses remains the same but the pulses get larger
until they reach the maximum content of the internal
counter. The output consists of an open drain
transistor which offers a low impedance to ground
when in the ON state.
PIN 6 : DIGITAL AFT STATUS OUTPUT
(see Figure 7)
This output shows the status of the digital AFT. It is
low when the digital AFT is enabled and it can
directly drive a LED.
The output consists of an open drain transistor.
PINS 7 & 8 : OSCILLATORINPUT/OUTPUT
(see Figure 8)
The frequency of the clock oscillator should be
between 445 and 510kHzusing a low-cost ceramic
resonator. In these conditions the value of the
reference frequency of the transmitter can be in the
same range. In other words the transmitter and the
receiver can operate with different reference frequencies.
PIN 9 : VDD
The supply voltage has to be comprised in the
range 4.75 to 5.25V. When it is applied an internal
power on reset of 0.5s is generated.
The memory position 1 is automatically read if the
mains on option input (Pin 25) is grounded.
PIN 10 : TEST
This pin is used for testingand has to be connected
to VSS.
PIN 11 : I.R. SIGNAL INPUT (see Figure 9)
The integrated receiver decodes signals transmitted
by M708, address 9.
The minimum signal to be applied is 0.5V peak-topeak.
(AC-coupled).
The receiver input section performs the following
tests on the incoming signal to achieve the necessary
noise immunity :
- measurement of the pulse distance (time base
synchronization)
- check of the position of the received bits opening
window at the time bases
- check of the parity bit
- checkof the absenceof pulsesbetween theparity
bit and the stop pulse
- checkof noiselevel ; the receiver checks parasitic
transients inside and outside the time windows.
If the above test conditions are not fulfilled, the
received word is rejected and not decoded. If the
received signal is acknowledged as a valid word it
is stored an decoded.
The end of transmission will be acknowledged by
receiving the end of transmission code or bymeans
of an internal timer if the transmission remains interrupted for more than about 550ms.
These pins are enabled during the automatic
search and during normal operation, when the
digital AFT is enabled (see description of Pin 17).
The STOP/AFT inputs are also disabled internally
duringany programor bandchange for the duration
of the Mute signal.
These inputs have two different functions depending
on whether the system is in the search or in
normal operation (AFT control).
The inputs have internal pull-up resistors of 30kW
typ.
A) Searchmode : after depressing the Automatic
search or preset keys, the levels of the signals
coming from the TDA4433, applied to these
pins, control the search function and determine
when the searchmust stop, i.e. a TV stationhas
been recognized.
The circuit operates in the following sequence
(see Figure 10 for reference) :
1 - after pressing the search start key the
search occurs in the FAST UP mode.
2 - eventual transitions available on these
inputs are ignored during the first 15 search
steps if the system is in the UHF or CATV
bands.
If the system operates in VHF I and III bands,
the first 60 search steps are ignored. The
acceptance delay of 15 (60) search steps has
been introduced to prevent the system from
stopping at the previous station.
After this time the FAST UP speed is
automatically reduced to half during each UP
signal (MEDIUM UP = FAST UP/2).
A DOWN signal preceded by at least an UP
signal will set the search to MEDIUM DOWN
mode (FAST UP/4).
3 - the next UP signal will switch the search to
SLOWUP speed (61Hz).
At this point the systems is in normal AFT
operation.
B) Digital AFT operation : when a station is
perfectly tuned, the input signals coming from
TDA4433 are at middle condition.
If the tuning moves lower than the threshold
below 38.9MHz, the Pin 12 is put H and Pin 13
is put L ; the 13 bit internal counter is moved
SLOW UP speed to increase the varicap
voltage.
When a detuning occurs in the opposite
direction the input 12 goes Low and 13 goes
High and the tuning voltage falls at VERY
SLOWDOWN speed (7.6Hz).
The increase or decrease of the tuning voltage
is stopped as soon as the input returns to
middle conditions.
Therefore during normal operation Pins 12 and
13 act as digital AFT control commands.
C) Recall from memory : when the digital AFT is
enabled and data is recalled from Memory, a
fixed value of 8 steps (9 31.2mV) is subtracted
from the tuning voltage.
This corresponds to a detuning of 0.6MHz
(UHF) and of 0.3MHz in VHF III into that part of
the IF response curve which correspondsto the
fully transmitted sideband.
At this point the AFT operation takes over as
described in point B above and the exact tuning
is achieved in about 0.2 sec.
This feature increases the AFT capture range
and fullfills the stability requirements of the
tuner, vol tage references and the D/A
converter.
If the Digital AFTis disabled (Pin 17 at VSS), the
memory content is read without any change.
PIN 14 : SWEEP SEARCH DISPLAYOUTPUT
This output, which is normally Low, goes High
during automatic search automatic preset et intervals
of 160ms for about 40ms to blank the LED of
band display.
PIN 15 : VOLUME D/AOUTPUT
This output delivers a square wave signal of 7.8
kHz and duty cycle variable in 63 steps. In case of
a continuouscommand for varying the volume, the
duty cycle is changed at the rate of the transmitted
signal (approximately every 102ms with fref =
500kHz) or every 112ms if issued locally.
Overflow and underflow protection are provided.
The volume output can be switched to VSS and
reset to the previous level by means of the Mute
On/Off command. It is also reset by the Volume
Up/Down and the Mains On/Off commands.
The volume is muted for about 1s at each mains
on and off commandduring the power on reset time
and program change (0.5s).
At the first power on reset of VDD the volume D/A
is set at the level 21/64. The last level is preserved
until VDD is not removed.
PIN 16 : LINEAR AFT DEFEAT OUTPUT
This output is normally High and goes Low when a
Manual Up/Down command is issued.
It returns High with a 1 second delay from the
release of the key, in order to give the user the
possibility of the tuning adjustmentwithout the AFT
intervention. It goes Low for 0.5s during program
change.
20
MEMORY
UP
DIGITAL
AFT ON
BAND
SEQ.
BAND
I
MEMORY
DOWN
AUTOMATIC
SEARCH
POWER
ON/OFF
BAND
III
VOLUME
UP
BAND
UHF
MAN SEARCH
DOWN
MAN SEARCH
UP
FT.
DOWN
FT.
UP
VOLUME
DOWN
BAND
CATV
19 18
AUTOMATIC
PRESET
MEMORY
ADDRESSING
STORE
MUTE
23 22 21 24
V1 V2 V3 X1 X2 X3 X4
491B-15.EPS
Figure 13
PIN 17 : DIGITAL AFT ENABLE INPUT
If this input is connected to VSS (GND), the digital
AFT loop is always disabled. If pin 17 is left open
or is connected to VDD, the digital AFT is automatically
enabled at power on. When a manual
up/down search commandis issued, the digitalAFT
loop is disabled and the digital AFT status output is
inhibited.
The digital AFT loop is restored by the commands:
Digital AFT on/Automaticsearch/Automaticpreset.
PINS 18-19-20-21-22-23-24:
KEYBOARD MATRIX (see Figure 13)
A command is accepted if the corresponding contact
has been closed for a minimum time of 30ms.
Local input commands and I.R. commands have
the same priority.
If a complete I.R. command has been received, the
local inputs are blocked until the command has
been executed and the ”end of transmission code”
generated.
Viceversa an I.R. signal cannot be decoded until
an issued local command has been executed.
MEMORY UP/DOWN
Depressing one of these twocommands, the memory
position is stepped in the UP or DOWN direction.
If the key is kept closed, the channels are stepped
UP/DOWNevery 0.5 second or every5 commands
from the transmitter.
The memory locations 9 to 16 are jumped if pin 31
is at GND level.
BAND SELECTION
The bands can be selected either directly or with a
step-by-step command in the following sequence :
VHF I
CATV
VHF III
UHF
VHF I and so on
Only one band change is performed at each accepted
command.
Disabled bands are automatically skipped. Aband
can be disabled connecting the correspondingoutput
to VSS.
4 modes are available :
a) Automatic search (digiatl AFT)
b) Automatic preset
c) Manual up/down (digital and linear AFT)
d) Manual up/down (linear AFT)
a) AUTOMATIC SEARCH. The search starts from
the actual tuning and band position. During the
search the tuning voltage is always changing from
lower to higher voltage levels. When the end of the
band is reached the search restarts from the beginning
of the next band after a 480 ms interruption
with the sequenceof step-by-step band selection.
Disabled bands are automaticallyskipped.
The search is stopped when the first station is
found or if a channel selection command is given.
Stop of the automatic search is determined by the
STOP/AFTinputs controlledby theTDA4433which
converts the AFC-S-curve into an up/down command.
At the end of the search the up/down command
controls the correct tuning acting on the counter of
the voltage synthesizer (Digital AFT).
It is important to call the attention to the Digital AFT
capturerangewhich is larger than the normallinear
AFT.
Additionally the use of the Digital AFT allows storage
of the tuning information corresponding to the
zero point of the AFC-S-curve. This cannot be
guaranteed using the LinearAFT method only. The
latter is a cheaper system, because it does not
require the use of the TDA4433 but it cannot guarantee
what described above.
As a result of the use of the Digital AFT, the requirements
for stability of the tuner, of the reference
voltage source and of stability of the D/A converter
are less critical.
Tuning speed in automatic search, if no station is
found is :
VHF I 8 second
VHF III 8 second
UHF 32 second
CATV 32 second
The tuning and band information can be stored
using the store/memory addressing command.
The search can be stopped by a memory selection
command.
b) AUTOMATIC PRESET. The search starts from
the lowest memory address, tuning voltage and
VHF I band as described in automatic search
mode.
When an active station is encountered, the corresponding
tuning and band information is automatically
stored in the Non-Volatile Memory.
Afterwards the system starts to search for the next
station. The cycle is repeated until all bands have
been scanned or the tuning information has been
stored into all address locations. After completing
this cycle the system reads out the tuning information
of the lowest address.
c) MANUAL UP/DOWN WITH DIGITAL AND LINEAR
AFT (pin 17 at VDD). Holding one of these
commands pressed, the tuning voltage is increased
or decreased.
During this operation, the Digital AFT is automatically
defeated and can only be reconnected with
the ”AFT on” command or by an Automatic search
or preset command.
The search speed is kept at minimum (there is no
increment with the time).
Band Sweep Timefor the
Complete Band
Number of Tuning
Steps/Second
VHF I
VHF III
UHF
CATV
seconds
128 seconds
128 seconds
512 seconds
512
16
64
64
16
In case of command received from remote control,
the counter is increased/decreased every two received
commands.
No band switching is provided at the upper or lower
tuning positions.
The volume is automaticallymuted 3 second after
the key pressure is immediately restored at the
release of the key.
d)MANUAL UP/DOWN WITHLINEARAFT (pin 17
at VSS). When this control is used the Digital AFT
is disabled.
TheLinearAFToutput goes lowafteranup ordown
command is issued and remains Low for 1 second
after the release of the key.
The volume is automatically muted for 3 seconds
after the key pressure and is immediately restored
at the release of the key.
Tuning speeds are as follows :
- FINE TUNING UP/DOWN
See description of pin 4.
- DIGITALAFT ON
See description of pin 17.
- VOLUMEUP/DOWN
See description of pin 15.
- MAINS ON/OFF
See description of pins 25 and 26.
Band
Number of Tuning Steps Second
Time 0 After 1 s After 2 s After 3 s
VHF I
VHF III
UHF
CATV
64
64
16
16
128
128
32
32
256
256
64
64
512
512
128
128
491B-06.TBL
STORECOMMANDS
2 modes of operations are available.
a)store
b)memory addressing
In order to protect the memory, the store function
is internally disabled after one store cycle.
It is enabled after a program change or a tuning
operation (it is not disabled by the Digital AFT
control).
a) STORE. The tuning information (Tuning D/A,
Fine tuning D/A and band) is stored in a previously
selected memory address when this command is
issued.
b) MEMORY ADDRESSING. The tuning information
can also be stored with this command followed
by the memory position selection.
When this command is accepted all the memory
LEDs are blanked.
Selection of the memory position initiates the store
operations and restores the display.
MUTE ON/OFF
See description of pin 15.
If connected to VSS (GND) the Mains output is
automatically switched on when VDD isappliedand
memory 1 is read.
If it is connected to VDD the circuit goes in stand by
condition.
PIN 26 : MAINS ON/OFF OUTPUT
Switch on of the set is controlled by the Mains on
command issued for more than 0.3 s. The output
transistor is set in the off condition to drive through
an integrated pull-up resistor, an external NPN
transistor.
+5V
491B-17.EPS
Figure 15
At each Mains on command a memory read out
occurs.AVPP (+ 25 V) is required for this operation,
a 1 second delay starts when the mains output is
switched off. For a correct reading of the memory
the VPP supply voltage must reach the value of 25
V within 1 second after a Mains on command.
In case of automatic switch on at power on caused
by pin 25 at GND, the total delay is of 1.13 second
(0.13s for VDD power on reset plus 1 second for
mains on).
TheMains on/off command,if repeated, will switch
the output on (set off).
The last addressinformation is preserved untilVDD
is present.
Next Mains on command will switch the set at the
previously selected memory address and a read
operation will be performed.
PINS 27-28-29-30-33-34-35-36:
MEMORY ADDRESS OUTPUT
These pins operate asoutput only for display of the
selected memory location. Max drive capability is
of 15 mA/1.2V with the exception of pin 36 that is
of 30 mA/1.5 V.
Direct memory selection is only possible by remote
control.Alocalmemory up/downcommand is available
in case of emergency.
Pin 32 must be grounded.
If pin 31 is grounded, the memory position 9 to 16
are skipped in case of memory up/down commands.
For normal operation pin 31 can be left open or,
better, connected to VDD.
PINS 31-32
PINS 37-38-39-40 : BAND INPUT/OUTPUT
These outputs are provided to select up to 4 bands
via external PNPs.
If one or more bands have to be skipped, the
corresponding outputshave to be short-circuited to
VSS.
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